- endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts

- added access to ARM920T vector catch register (via generic register mechanism)
- don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache
- read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands)
- memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes)
- made in_handler independent from in field (makes the handler more flexible)
- added timeout to ft2232 when using D2XX library
- fixed STR7x protection bit handling on second bank (thanks to Bernard)
- added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen)
- fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen)


git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 8 insertions, 5 deletions

diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index 59ed2aa0..dd8bdeb5 100644
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -133,9 +133,10 @@ u32 at91sam7_get_flash_status(flash_bank_t *bank)
 {
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = at91sam7_info->target;
-	long fsr;
+	u32 fsr;
 	
 	target->type->read_memory(target, MC_FSR, 4, 1, (u8 *)&fsr);
+	fsr = target_buffer_get_u32(target, (u8 *)&fsr);
 	
 	return fsr;
 }
@@ -206,7 +207,7 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
 /* Setup the timimg registers for nvbits or normal flash */
 void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
 {
-	u32 fmcn, fmr;
+	u32 fmr, fmcn = 0, fws = 0;
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = at91sam7_info->target;
 	
@@ -220,12 +221,14 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
 			fmcn = (at91sam7_info->mck_freq/666666ul)+1;
 
 		/* Only allow fmcn=0 if clock period is > 30 us. */
-		if (at91sam7_info->mck_freq <= 33333)
+		if (at91sam7_info->mck_freq <= 33333333ul)
 			fmcn = 0;
+		else
+			fws = 1;
 
 		DEBUG("fmcn: %i", fmcn); 
-		fmr = fmcn<<16;
-		target->type->write_memory(target, MC_FSR, 4, 1, (u8 *)&fmr);
+		fmr = fmcn << 16 | fws << 8;
+		target->type->write_memory(target, MC_FMR, 4, 1, (u8 *)&fmr);
 	}
 	at91sam7_info->flashmode = mode;		
 }