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author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:45:47 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:45:47 +0000 |
commit | 6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa (patch) | |
tree | 9f1465d0768f8fde40053f539296f895d7e4e0ac /src/target/arm_disassembler.c | |
parent | fb1a9b2cb2f844a17d26dfeb3d26849364d93e26 (diff) | |
download | openocd+libswd-6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa.tar.gz openocd+libswd-6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa.tar.bz2 openocd+libswd-6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa.tar.xz openocd+libswd-6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa.zip |
- Fixes '[<>]' whitespace
- Replace ')\([<>]\)(' with ') \1 ('.
- Replace ')\([<>]\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\([<>]\)(' with '\1 \2 ('.
- Replace '\(\w\)\([<>]\)\(\w\)' with '\1 \2 \3'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2375 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm_disassembler.c')
-rw-r--r-- | src/target/arm_disassembler.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index e460e468..d290b670 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -891,7 +891,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in int x = (opcode & 0x20) >> 5; int y = (opcode & 0x40) >> 6; - /* SMLA<x><y> */ + /* SMLA < x><y> */ if ((opcode & 0x00600000) == 0x00000000) { uint8_t Rd, Rm, Rs, Rn; @@ -906,7 +906,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in Rd, Rm, Rs, Rn); } - /* SMLAL<x><y> */ + /* SMLAL < x><y> */ if ((opcode & 0x00600000) == 0x00400000) { uint8_t RdLow, RdHi, Rm, Rs; @@ -921,7 +921,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in RdLow, RdHi, Rm, Rs); } - /* SMLAW<y> */ + /* SMLAW < y> */ if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) { uint8_t Rd, Rm, Rs, Rn; @@ -936,7 +936,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in Rd, Rm, Rs, Rn); } - /* SMUL<x><y> */ + /* SMUL < x><y> */ if ((opcode & 0x00600000) == 0x00300000) { uint8_t Rd, Rm, Rs; @@ -950,7 +950,7 @@ int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *in Rd, Rm, Rs); } - /* SMULW<y> */ + /* SMULW < y> */ if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) { uint8_t Rd, Rm, Rs; @@ -1922,7 +1922,7 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in if (reg_list & (1 << i)) reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i); } - if (reg_names_p>reg_names) + if (reg_names_p > reg_names) reg_names_p[-2] = '\0'; else /* invalid op : no registers */ reg_names[0] = '\0'; |