ARM: move opcode macros to <target/arm_opcodes.h>

Move the ARM opcode macros from <target/armv4_5.h>, and a few
Thumb2 ones from <target/armv7m.h>, to more appropriate homes
in a new <target/arm_opcodes.h> file.

Removed duplicate opcodes from that v7m/Thumb2 set.  Protected
a few macro argument references by adding missing parentheses.

Tightening up some of the line lengths turned up a curious artifact:
the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
There's currently no explanation for why it's done that way...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 0 insertions, 79 deletions

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 353860a9..c60ab8cf 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -162,83 +162,4 @@ int armv7m_blank_check_memory(struct target *target,
 
 extern const struct command_registration armv7m_command_handlers[];
 
-/* Thumb mode instructions
- */
-
-/* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
- * Rd: destination register
- * SYSm: source special register
- */
-#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
-
-/* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
- * Rd: source register
- * SYSm: destination special register
- */
-#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
-
-/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
- * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
- * Rd: source register
- * IF:
- */
-#define I_FLAG 2
-#define F_FLAG 1
-#define ARMV7M_T_CPSID(IF)	((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
-#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
-
-/* Breakpoint (Thumb mode) v5 onwards
- * Im: immediate value used by debugger
- */
-#define ARMV7M_T_BKPT(Im)	((0xBE00 | Im) | ((0xBE00 | Im) << 16))
-
-/* Store register (Thumb mode)
- * Rd: source register
- * Rn: base register
- */
-#define ARMV7M_T_STR(Rd, Rn)	((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
-
-/* Load register (Thumb state)
- * Rd: destination register
- * Rn: base register
- */
-#define ARMV7M_T_LDR(Rd, Rn)	((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
-
-/* Load multiple (Thumb state)
- * Rn: base register
- * List: for each bit in list: store register
- */
-#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
-
-/* Load register with PC relative addressing
- * Rd: register to load
- */
-#define ARMV7M_T_LDR_PCREL(Rd)	((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
-
-/* Move hi register (Thumb mode)
- * Rd: destination register
- * Rm: source register
- */
-#define ARMV7M_T_MOV(Rd, Rm)	((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
-
-/* No operation (Thumb mode)
- */
-#define ARMV7M_T_NOP	(0x46c0 | (0x46c0 << 16))
-
-/* Move immediate to register (Thumb state)
- * Rd: destination register
- * Im: 8-bit immediate value
- */
-#define ARMV7M_T_MOV_IM(Rd, Im)	((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
-
-/* Branch and Exchange
- * Rm: register containing branch target
- */
-#define ARMV7M_T_BX(Rm)		((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
-
-/* Branch (Thumb state)
- * Imm: Branch target
- */
-#define ARMV7M_T_B(Imm)	((0xe000 | Imm) | ((0xe000 | Imm) << 16))
-
 #endif /* ARMV7M_H */