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| author | duane <duane@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-30 22:25:43 +0000 |
|---|---|---|
| committer | duane <duane@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-30 22:25:43 +0000 |
| commit | a28eaa85f73759bb189a46308642502c9fa5aa4b (patch) | |
| tree | 93ed39ee8fe48131e227a01a788be91b88203064 /src/target/board/at91rm9200-dk.cfg | |
| parent | 91afc3dc3083a3d4f6a4104a5132d87c8ec03c7f (diff) | |
| download | openocd+libswd-a28eaa85f73759bb189a46308642502c9fa5aa4b.tar.gz openocd+libswd-a28eaa85f73759bb189a46308642502c9fa5aa4b.tar.bz2 openocd+libswd-a28eaa85f73759bb189a46308642502c9fa5aa4b.tar.xz openocd+libswd-a28eaa85f73759bb189a46308642502c9fa5aa4b.zip | |
jtag newtap change & huge manual update
git-svn-id: svn://svn.berlios.de/openocd/trunk@1194 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/board/at91rm9200-dk.cfg')
| -rwxr-xr-x | src/target/board/at91rm9200-dk.cfg | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/src/target/board/at91rm9200-dk.cfg b/src/target/board/at91rm9200-dk.cfg new file mode 100755 index 00000000..900ee351 --- /dev/null +++ b/src/target/board/at91rm9200-dk.cfg @@ -0,0 +1,78 @@ +# +# This is for the "at91rm9200-DK" (not the EK) eval board. +# +# The two are probably very simular.... I have DK... +# +# It has atmel at91rm9200 chip. +source [find target/at91rm9200.cfg] +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { at91rm9200_dk_init } + +#flash bank <driver> <base> <size> <chip_width> <bus_width> +flash_bank cfi 0x10000000 0x00200000 2 2 0 + + +proc at91rm9200_dk_init { } { + # Try to run at 1khz... Yea, that slow! + # Chip is really running @ 32khz + jtag_khz 8 + + mww 0xfffffc64 0xffffffff + ## disable all clocks but system clock + mww 0xfffffc04 0xfffffffe + ## disable all clocks to pioa and piob + mww 0xfffffc14 0xffffffc3 + ## master clock = slow cpu = slow + ## (means the CPU is running at 32khz!) + mww 0xfffffc30 0 + ## main osc enable + mww 0xfffffc20 0x0000ff01 + ## program pllA + mww 0xfffffc28 0x20263e04 + ## program pllB + mww 0xfffffc2c 0x10483e0e + ## let pll settle... sleep 100msec + sleep 100 + ## switch to fast clock + mww 0xfffffc30 0x202 + ## Sleep some - (go read) + sleep 100 + + #======================================== + # CPU now runs at 180mhz + # SYS runs at 60mhz. + jtag_khz 40000 + #======================================== + + + ## set memc for all memories + mww 0xffffff60 0x02 + ## program smc controller + mww 0xffffff70 0x3284 + ## init sdram + mww 0xffffff98 0x7fffffd0 + ## all banks precharge + mww 0xffffff80 0x02 + ## touch sdram chip to make it work + mww 0x20000000 0 + ## sdram controller mode register + mww 0xffffff90 0x04 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + ## sdram controller mode register + ## Refresh, etc.... + mww 0xffffff90 0x03 + mww 0x20000080 0 + mww 0xffffff94 0x1f4 + mww 0x20000080 0 + mww 0xffffff90 0x10 + mww 0x20000000 0 + mww 0xffffff00 0x01 + +} |