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authorduane <duane@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-11-30 22:25:43 +0000
committerduane <duane@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-11-30 22:25:43 +0000
commita28eaa85f73759bb189a46308642502c9fa5aa4b (patch)
tree93ed39ee8fe48131e227a01a788be91b88203064 /src
parent91afc3dc3083a3d4f6a4104a5132d87c8ec03c7f (diff)
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jtag newtap change & huge manual update
git-svn-id: svn://svn.berlios.de/openocd/trunk@1194 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src')
-rw-r--r--src/flash/str9xpec.c194
-rw-r--r--src/flash/str9xpec.h2
-rw-r--r--src/helper/types.h2
-rw-r--r--src/jtag/jtag.c786
-rw-r--r--src/jtag/jtag.h41
-rw-r--r--src/pld/virtex2.c46
-rw-r--r--src/pld/virtex2.h3
-rw-r--r--src/target/Makefile.am33
-rw-r--r--src/target/arm11.c41
-rw-r--r--src/target/arm11_dbgtap.c17
-rw-r--r--src/target/arm720t.c10
-rw-r--r--src/target/arm7_9_common.c5
-rw-r--r--src/target/arm7tdmi.c20
-rw-r--r--src/target/arm7tdmi.h2
-rw-r--r--src/target/arm920t.c30
-rw-r--r--src/target/arm926ejs.c22
-rw-r--r--src/target/arm926ejs.h2
-rw-r--r--src/target/arm966e.c18
-rw-r--r--src/target/arm9tdmi.c30
-rw-r--r--src/target/arm9tdmi.h2
-rw-r--r--src/target/arm_jtag.c13
-rw-r--r--src/target/arm_jtag.h2
-rwxr-xr-xsrc/target/board/arm_evaluator7t.cfg10
-rwxr-xr-xsrc/target/board/at91rm9200-dk.cfg78
-rwxr-xr-x[-rw-r--r--]src/target/board/eir.cfg (renamed from src/target/target/eir-sam7se512.cfg)20
-rwxr-xr-x[-rw-r--r--]src/target/board/hammer.cfg (renamed from src/target/target/hammer.cfg)15
-rwxr-xr-xsrc/target/board/iar_str912_sk.cfg3
-rwxr-xr-xsrc/target/board/logicpd_imx27.cfg12
-rwxr-xr-xsrc/target/board/olimex_sam7_ex256.cfg4
-rwxr-xr-xsrc/target/board/stm3210e_eval.cfg3
-rwxr-xr-xsrc/target/board/stm32f10x_128k_eval.cfg6
-rw-r--r--src/target/cortex_m3.c6
-rw-r--r--src/target/cortex_m3.h2
-rw-r--r--src/target/cortex_swjdp.c12
-rw-r--r--src/target/embeddedice.c30
-rw-r--r--src/target/embeddedice.h6
-rw-r--r--src/target/etb.c43
-rw-r--r--src/target/etb.h2
-rw-r--r--src/target/etm.c12
-rw-r--r--src/target/feroceon.c8
-rw-r--r--src/target/mips32.c4
-rw-r--r--src/target/mips32.h2
-rw-r--r--src/target/mips_ejtag.c24
-rw-r--r--src/target/mips_ejtag.h2
-rw-r--r--src/target/mips_m4k.c6
-rw-r--r--src/target/target.c28
-rw-r--r--src/target/target.h2
-rw-r--r--src/target/target/aduc702x.cfg36
-rw-r--r--src/target/target/at91eb40a.cfg29
-rw-r--r--src/target/target/at91r40008.cfg31
-rwxr-xr-xsrc/target/target/at91rm9200.cfg51
-rw-r--r--src/target/target/at91sam9260.cfg19
-rw-r--r--src/target/target/at91sam9260minimal.cfg29
-rw-r--r--src/target/target/epc9301.cfg25
-rw-r--r--src/target/target/imote2.cfg32
-rw-r--r--src/target/target/imx27.cfg44
-rw-r--r--src/target/target/imx31.cfg66
-rw-r--r--src/target/target/ipx42x.cfg29
-rw-r--r--src/target/target/is5114.cfg43
-rw-r--r--src/target/target/lm3s3748.cfg29
-rw-r--r--src/target/target/lm3s6965.cfg30
-rw-r--r--src/target/target/lm3s811.cfg28
-rw-r--r--src/target/target/lpc2129.cfg34
-rw-r--r--src/target/target/lpc2148.cfg29
-rw-r--r--src/target/target/lpc2148_2mhz.cfg1
-rw-r--r--src/target/target/lpc2148_rclk.cfg1
-rw-r--r--src/target/target/lpc2294.cfg27
-rw-r--r--src/target/target/netx500.cfg32
-rw-r--r--src/target/target/nslu2.cfg24
-rw-r--r--src/target/target/omap5912.cfg35
-rw-r--r--src/target/target/pic32mx.cfg30
-rw-r--r--src/target/target/pxa255.cfg28
-rw-r--r--src/target/target/pxa255_sst.cfg5
-rw-r--r--src/target/target/pxa270.cfg34
-rw-r--r--src/target/target/s3c2440.cfg30
-rwxr-xr-xsrc/target/target/sam7se512.cfg38
-rw-r--r--src/target/target/sam7x256.cfg30
-rwxr-xr-xsrc/target/target/samsung_s2c2410.cfg35
-rwxr-xr-xsrc/target/target/samsung_s3c4510.cfg25
-rwxr-xr-xsrc/target/target/samsung_s3c6410.cfg49
-rwxr-xr-xsrc/target/target/sharp_lh79532.cfg26
-rw-r--r--src/target/target/smdk6410.cfg14
-rw-r--r--src/target/target/stm32.cfg47
-rw-r--r--src/target/target/stm32stick.cfg38
-rw-r--r--src/target/target/str710.cfg33
-rw-r--r--src/target/target/str730.cfg35
-rw-r--r--src/target/target/str750.cfg35
-rw-r--r--src/target/target/str910-eval.cfg41
-rw-r--r--src/target/target/str912.cfg53
-rw-r--r--src/target/target/str9comstick.cfg35
-rw-r--r--src/target/target/test_reset_syntax_error.cfg8
-rw-r--r--src/target/target/wi-9c.cfg32
-rw-r--r--src/target/target/xba_revA3.cfg30
-rw-r--r--src/target/target/zy1000.cfg30
-rw-r--r--src/target/xscale.c79
-rw-r--r--src/target/xscale.h2
-rw-r--r--src/xsvf/xsvf.c27
97 files changed, 2391 insertions, 843 deletions
diff --git a/src/flash/str9xpec.c b/src/flash/str9xpec.c
index c01292d3..662cdc5b 100644
--- a/src/flash/str9xpec.c
+++ b/src/flash/str9xpec.c
@@ -111,20 +111,18 @@ int str9xpec_register_commands(struct command_context_s *cmd_ctx)
return ERROR_OK;
}
-int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state)
+int str9xpec_set_instr(jtag_tap_t *tap, u32 new_instr, enum tap_state end_state)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device == NULL)
- {
+ if( tap == NULL ){
return ERROR_TARGET_INVALID;
}
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
@@ -142,15 +140,15 @@ int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state)
return ERROR_OK;
}
-u8 str9xpec_isc_status(int chain_pos)
+u8 str9xpec_isc_status(jtag_tap_t *tap)
{
scan_field_t field;
u8 status;
- if (str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK)
return ISC_STATUS_ERROR;
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
@@ -174,20 +172,20 @@ u8 str9xpec_isc_status(int chain_pos)
int str9xpec_isc_enable(struct flash_bank_s *bank)
{
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (str9xpec_info->isc_enable)
return ERROR_OK;
/* enter isc mode */
- if (str9xpec_set_instr(chain_pos, ISC_ENABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* check ISC status */
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
if (status & ISC_STATUS_MODE)
{
/* we have entered isc mode */
@@ -201,22 +199,22 @@ int str9xpec_isc_enable(struct flash_bank_s *bank)
int str9xpec_isc_disable(struct flash_bank_s *bank)
{
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable)
return ERROR_OK;
- if (str9xpec_set_instr(chain_pos, ISC_DISABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* delay to handle aborts */
jtag_add_sleep(50);
/* check ISC status */
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
if (!(status & ISC_STATUS_MODE))
{
/* we have left isc mode */
@@ -231,18 +229,18 @@ int str9xpec_read_config(struct flash_bank_s *bank)
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */
- str9xpec_set_instr(chain_pos, ISC_CONFIGURATION, TAP_PI);
+ str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = NULL;
field.out_mask = NULL;
@@ -255,7 +253,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
return status;
}
@@ -352,9 +350,11 @@ int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
arm7_9 = armv4_5->arch_info;
jtag_info = &arm7_9->jtag_info;
- str9xpec_info->chain_pos = (jtag_info->chain_pos - 1);
+
+
+ str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
str9xpec_info->isc_enable = 0;
- str9xpec_info->devarm = NULL;
+
str9xpec_build_block_list(bank);
@@ -368,13 +368,13 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
int i;
u8 *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
@@ -393,9 +393,9 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
}
/* execute ISC_BLANK_CHECK command */
- str9xpec_set_instr(chain_pos, ISC_BLANK_CHECK, TAP_PI);
+ str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = buffer;
field.out_mask = NULL;
@@ -409,7 +409,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
jtag_add_sleep(40000);
/* read blank check result */
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = NULL;
field.out_mask = NULL;
@@ -422,7 +422,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_execute_queue();
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
for (i = first; i <= last; i++)
{
@@ -467,13 +467,13 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
int i;
u8 *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
@@ -509,9 +509,9 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */
- str9xpec_set_instr(chain_pos, ISC_ERASE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ERASE, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = buffer;
field.out_mask = NULL;
@@ -527,7 +527,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
jtag_add_sleep(10);
/* wait for erase completion */
- while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) {
+ while (!((status = str9xpec_isc_status(tap)) & ISC_STATUS_BUSY)) {
alive_sleep(1);
}
@@ -554,11 +554,11 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
@@ -572,12 +572,12 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(chain_pos, ISC_PROGRAM_SECURITY, TAP_RTI);
+ str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
@@ -654,16 +654,16 @@ int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
{
- u32 chain_pos;
+ jtag_tap_t *tap;
scan_field_t field;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
/* set flash controller address */
- str9xpec_set_instr(chain_pos, ISC_ADDRESS_SHIFT, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = &sector;
field.out_mask = NULL;
@@ -686,14 +686,14 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
u32 bytes_written = 0;
u8 status;
u32 check_address = offset;
- u32 chain_pos;
+ jtag_tap_t *tap;
scan_field_t field;
u8 *scanbuf;
int i;
u32 first_sector = 0;
u32 last_sector = 0;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable(bank);
@@ -750,9 +750,9 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (dwords_remaining > 0)
{
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = (buffer + bytes_written);
field.out_mask = NULL;
@@ -767,10 +767,10 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
@@ -810,9 +810,9 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
bytes_written++;
}
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = last_dword;
field.out_mask = NULL;
@@ -827,10 +827,10 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
@@ -871,7 +871,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
flash_bank_t *bank;
scan_field_t field;
u8 *buffer = NULL;
- u32 chain_pos;
+ jtag_tap_t *tap;
u32 idcode;
str9xpec_flash_controller_t *str9xpec_info = NULL;
@@ -888,13 +888,13 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
}
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
buffer = calloc(CEIL(32, 8), 1);
- str9xpec_set_instr(chain_pos, ISC_IDCODE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
@@ -990,11 +990,11 @@ int str9xpec_write_options(struct flash_bank_s *bank)
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
/* erase config options first */
status = str9xpec_erase_area( bank, 0xFE, 0xFE );
@@ -1017,9 +1017,9 @@ int str9xpec_write_options(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = str9xpec_info->options;
field.out_mask = NULL;
@@ -1034,10 +1034,10 @@ int str9xpec_write_options(struct flash_bank_s *bank)
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
@@ -1265,11 +1265,16 @@ int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char
int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
+#if 1
+ command_print( cmd_ctx, "**STR9FLASH is currently broken :-( **");
+ return ERROR_OK;
+#else
int retval;
flash_bank_t *bank;
- u32 chain_pos;
- jtag_device_t* dev0;
- jtag_device_t* dev2;
+ jtag_tap_t *tapX;
+ jtag_tap_t *tap0;
+ jtag_tap_t *tap1;
+ jtag_tap_t *tap2;
str9xpec_flash_controller_t *str9xpec_info = NULL;
if (argc < 1)
@@ -1287,33 +1292,46 @@ int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tapX = str9xpec_info->tap;
/* remove arm core from chain - enter turbo mode */
+ //
+ // At postion +2 in the chain,
+ // I do not think this is right..
+ // I have not tested it...
+ // and it is a bit wacky right now.
+ // -- Duane 25/nov/2008
+ tap0 = tapX;
+ tap1 = tap0->next_tap;
+ if( tap1 == NULL ){
+ // things are *WRONG*
+ command_print(cmd_ctx,"**STR9FLASH** (tap1) invalid chain?");
+ return ERROR_OK;
+ }
+ tap2 = tap1->next_tap;
+ if( tap2 == NULL ){
+ // things are *WRONG*
+ command_print(cmd_ctx,"**STR9FLASH** (tap2) invalid chain?");
+ return ERROR_OK;
+ }
- str9xpec_set_instr(chain_pos+2, 0xD, TAP_RTI);
+ // this instruction disables the arm9 tap
+ str9xpec_set_instr(tap2, 0xD, TAP_RTI);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
/* modify scan chain - str9 core has been removed */
- dev0 = jtag_get_device(chain_pos);
- if (dev0 == NULL)
- return ERROR_FAIL;
- str9xpec_info->devarm = jtag_get_device(chain_pos+1);
- dev2 = jtag_get_device(chain_pos+2);
- if (dev2 == NULL)
- return ERROR_FAIL;
- dev0->next = dev2;
- jtag_num_devices--;
+ str9xpec_info->devarm = tap1;
+ tap1->enabled = 0;
return ERROR_OK;
+#endif
}
int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
flash_bank_t *bank;
- u32 chain_pos;
- jtag_device_t* dev0;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
if (argc < 1)
@@ -1331,22 +1349,18 @@ int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ct
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
- dev0 = jtag_get_device(chain_pos);
- if (dev0 == NULL)
+ if (tap == NULL)
return ERROR_FAIL;
/* exit turbo mode via TLR */
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_TLR);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR);
jtag_execute_queue();
-
/* restore previous scan chain */
- if( str9xpec_info->devarm ) {
- dev0->next = str9xpec_info->devarm;
- jtag_num_devices++;
- str9xpec_info->devarm = NULL;
+ if( tap->next_tap ){
+ tap->next_tap->enabled = 1;
}
return ERROR_OK;
diff --git a/src/flash/str9xpec.h b/src/flash/str9xpec.h
index 4e34f6c7..de19b625 100644
--- a/src/flash/str9xpec.h
+++ b/src/flash/str9xpec.h
@@ -29,10 +29,10 @@
typedef struct str9xpec_flash_controller_s
{
+ jtag_tap_t *tap;
u32 *sector_bits;
int chain_pos;
int isc_enable;
- jtag_device_t* devarm;
u8 options[8];
} str9xpec_flash_controller_t;
diff --git a/src/helper/types.h b/src/helper/types.h
index 6e6d59e4..d87c10a2 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -44,6 +44,8 @@ typedef unsigned long long u64;
#endif
+typedef struct jtag_tap_s jtag_tap_t;
+
/* DANGER!!!! here be dragons! Note that the pointer in
* memory might be unaligned. On some CPU's, i.e. ARM7,
diff --git a/src/jtag/jtag.c b/src/jtag/jtag.c
index 5e29082c..0c74c416 100644
--- a/src/jtag/jtag.c
+++ b/src/jtag/jtag.c
@@ -122,9 +122,8 @@ int jtag_srst = 0;
jtag_command_t *jtag_command_queue = NULL;
jtag_command_t **last_comand_pointer = &jtag_command_queue;
-jtag_device_t *jtag_devices = NULL;
-int jtag_num_devices = 0;
-int jtag_ir_scan_size = 0;
+static jtag_tap_t *jtag_all_taps = NULL;
+
enum reset_types jtag_reset_config = RESET_NONE;
enum tap_state cmd_queue_end_state = TAP_TLR;
enum tap_state cmd_queue_cur_state = TAP_TLR;
@@ -273,6 +272,128 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
int handle_verify_ircapture_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+jtag_tap_t *jtag_AllTaps(void)
+{
+ return jtag_all_taps;
+};
+
+int
+jtag_NumTotalTaps(void)
+{
+ jtag_tap_t *t;
+ int n;
+
+ n = 0;
+ t = jtag_AllTaps();
+ while(t){
+ n++;
+ t = t->next_tap;
+ }
+ return n;
+}
+
+int
+jtag_NumEnabledTaps(void)
+{
+ jtag_tap_t *t;
+ int n;
+
+ n = 0;
+ t = jtag_AllTaps();
+ while(t){
+ if( t->enabled ){
+ n++;
+ }
+ t = t->next_tap;
+ }
+ return n;
+}
+
+jtag_tap_t *
+jtag_NextEnabledTap( jtag_tap_t *p )
+{
+ if( p == NULL ){
+ // start at the head of list
+ p = jtag_AllTaps();
+ } else {
+ // start *after* this one
+ p = p->next_tap;
+ }
+ while( p ){
+ if( p->enabled ){
+ break;
+ } else {
+ p = p->next_tap;
+ }
+ }
+ return p;
+}
+
+jtag_tap_t *jtag_TapByString( const char *s )
+{
+ jtag_tap_t *t;
+ char *cp;
+
+ t = jtag_AllTaps();
+ // try name first
+ while(t){
+ if( 0 == strcmp( t->dotted_name, s ) ){
+ break;
+ } else {
+ t = t->next_tap;
+ }
+ }
+ // backup plan is by number
+ if( t == NULL ){
+ /* ok - is "s" a number? */
+ int n;
+ n = strtol( s, &cp, 0 );
+ if( (s != cp) && (*cp == 0) ){
+ /* Then it is... */
+ t = jtag_TapByAbsPosition(n);
+ }
+ }
+ return t;
+}
+
+jtag_tap_t *
+jtag_TapByJimObj( Jim_Interp *interp, Jim_Obj *o )
+{
+ jtag_tap_t *t;
+ const char *cp;
+
+ cp = Jim_GetString( o, NULL );
+ if(cp == NULL){
+ cp = "(unknown)";
+ t = NULL;
+ } else {
+ t = jtag_TapByString( cp );
+ }
+ if( t == NULL ){
+ Jim_SetResult_sprintf(interp,"Tap: %s is unknown", cp );
+ }
+ return t;
+}
+
+/* returns a pointer to the n-th device in the scan chain */
+jtag_tap_t *
+jtag_TapByAbsPosition( int n )
+{
+ int orig_n;
+ jtag_tap_t *t;
+
+ orig_n = n;
+ t = jtag_AllTaps();
+
+ while( t && (n > 0)) {
+ n--;
+ t = t->next_tap;
+ }
+ return t;
+}
+
+
int jtag_register_event_callback(int (*callback)(enum jtag_event event, void *priv), void *priv)
{
jtag_event_callback_t **callbacks_p = &jtag_event_callbacks;
@@ -354,23 +475,6 @@ jtag_command_t** jtag_get_last_command_p(void)
return last_comand_pointer;
}
-/* returns a pointer to the n-th device in the scan chain */
-jtag_device_t* jtag_get_device(int num)
-{
- jtag_device_t *device = jtag_devices;
- int i = 0;
-
- while (device)
- {
- if (num == i)
- return device;
- device = device->next;
- i++;
- }
-
- LOG_ERROR("jtag device number %d not defined", num);
- return NULL;
-}
void* cmd_queue_alloc(size_t size)
{
@@ -453,8 +557,10 @@ void jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state
int MINIDRIVER(interface_jtag_add_ir_scan)(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
- jtag_device_t *device;
- int i, j;
+ jtag_tap_t *tap;
+ int j;
+ int x;
+ int nth_tap;
int scan_size = 0;
@@ -469,63 +575,67 @@ int MINIDRIVER(interface_jtag_add_ir_scan)(int num_fields, scan_field_t *fields,
/* allocate memory for ir scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
(*last_cmd)->cmd.scan->ir_scan = 1;
- (*last_cmd)->cmd.scan->num_fields = jtag_num_devices; /* one field per device */
- (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(jtag_num_devices * sizeof(scan_field_t));
+ x = jtag_NumEnabledTaps();
+ (*last_cmd)->cmd.scan->num_fields = x; /* one field per device */
+ (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(x * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < jtag_num_devices; i++)
- {
+ nth_tap = -1;
+ tap = NULL;
+ for(;;){
int found = 0;
- device = jtag_get_device(i);
- if (device == NULL)
- {
- exit(-1);
+
+ // do this here so it is not forgotten
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
}
- scan_size = device->ir_length;
- (*last_cmd)->cmd.scan->fields[i].device = i;
- (*last_cmd)->cmd.scan->fields[i].num_bits = scan_size;
- (*last_cmd)->cmd.scan->fields[i].in_value = NULL;
- (*last_cmd)->cmd.scan->fields[i].in_handler = NULL; /* disable verification by default */
+ nth_tap++;
+ scan_size = tap->ir_length;
+ (*last_cmd)->cmd.scan->fields[nth_tap].tap = tap;
+ (*last_cmd)->cmd.scan->fields[nth_tap].num_bits = scan_size;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_value = NULL;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler = NULL; /* disable verification by default */
/* search the list */
for (j = 0; j < num_fields; j++)
{
- if (i == fields[j].device)
+ if (tap == fields[j].tap)
{
found = 1;
- (*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
- (*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[j].out_mask, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_mask = buf_cpy(fields[j].out_mask, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
if (jtag_verify_capture_ir)
{
if (fields[j].in_handler==NULL)
{
- jtag_set_check_value((*last_cmd)->cmd.scan->fields+i, device->expected, device->expected_mask, NULL);
+ jtag_set_check_value((*last_cmd)->cmd.scan->fields+nth_tap, tap->expected, tap->expected_mask, NULL);
} else
{
- (*last_cmd)->cmd.scan->fields[i].in_handler = fields[j].in_handler;
- (*last_cmd)->cmd.scan->fields[i].in_handler_priv = fields[j].in_handler_priv;
- (*last_cmd)->cmd.scan->fields[i].in_check_value = device->expected;
- (*last_cmd)->cmd.scan->fields[i].in_check_mask = device->expected_mask;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler = fields[j].in_handler;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler_priv = fields[j].in_handler_priv;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_check_value = tap->expected;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_check_mask = tap->expected_mask;
}
}
- device->bypass = 0;
+ tap->bypass = 0;
break;
}
}
if (!found)
{
- /* if a device isn't listed, set it to BYPASS */
- (*last_cmd)->cmd.scan->fields[i].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
- (*last_cmd)->cmd.scan->fields[i].out_mask = NULL;
- device->bypass = 1;
+ /* if a tap isn't listed, set it to BYPASS */
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_mask = NULL;
+ tap->bypass = 1;
}
/* update device information */
- buf_cpy((*last_cmd)->cmd.scan->fields[i].out_value, jtag_get_device(i)->cur_instr, scan_size);
+ buf_cpy((*last_cmd)->cmd.scan->fields[nth_tap].out_value, tap->cur_instr, scan_size);
}
return ERROR_OK;
@@ -562,11 +672,10 @@ int MINIDRIVER(interface_jtag_add_plain_ir_scan)(int num_fields, scan_field_t *f
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < num_fields; i++)
- {
+ for( i = 0 ; i < num_fields ; i++ ){
int num_bits = fields[i].num_bits;
int num_bytes = CEIL(fields[i].num_bits, 8);
- (*last_cmd)->cmd.scan->fields[i].device = fields[i].device;
+ (*last_cmd)->cmd.scan->fields[i].tap = fields[i].tap;
(*last_cmd)->cmd.scan->fields[i].num_bits = num_bits;
(*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
(*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[i].out_mask, cmd_queue_alloc(num_bytes), num_bits);
@@ -592,25 +701,26 @@ void jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state
int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields, enum tap_state state)
{
- int i, j;
+ int j;
+ int nth_tap;
int bypass_devices = 0;
int field_count = 0;
int scan_size;
jtag_command_t **last_cmd = jtag_get_last_command_p();
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
/* count devices in bypass */
- while (device)
- {
- if (device->bypass)
+ tap = NULL;
+ bypass_devices = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ if( tap->bypass ){
bypass_devices++;
- device = device->next;
- }
- if (bypass_devices >= jtag_num_devices)
- {
- LOG_ERROR("all devices in bypass");
- return ERROR_JTAG_DEVICE_ERROR;
+ }
}
/* allocate memory for a new list member */
@@ -626,14 +736,20 @@ int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields,
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < jtag_num_devices; i++)
- {
+ tap = NULL;
+ nth_tap = -1;
+ for(;;){
+ nth_tap++;
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
int found = 0;
- (*last_cmd)->cmd.scan->fields[field_count].device = i;
+ (*last_cmd)->cmd.scan->fields[field_count].tap = tap;
for (j = 0; j < num_fields; j++)
{
- if (i == fields[j].device)
+ if (tap == fields[j].tap)
{
found = 1;
scan_size = fields[j].num_bits;
@@ -651,7 +767,7 @@ int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields,
{
#ifdef _DEBUG_JTAG_IO_
/* if a device isn't listed, the BYPASS register should be selected */
- if (!jtag_get_device(i)->bypass)
+ if (! tap->bypass)
{
LOG_ERROR("BUG: no scan data for a device not in BYPASS");
exit(-1);
@@ -671,7 +787,7 @@ int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields,
{
#ifdef _DEBUG_JTAG_IO_
/* if a device is listed, the BYPASS register must not be selected */
- if (jtag_get_device(i)->bypass)
+ if (tap->bypass)
{
LOG_ERROR("BUG: scan data for a device in BYPASS");
exit(-1);
@@ -682,25 +798,31 @@ int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields,
return ERROR_OK;
}
-void MINIDRIVER(interface_jtag_add_dr_out)(int device_num,
+void MINIDRIVER(interface_jtag_add_dr_out)(jtag_tap_t *target_tap,
int num_fields,
const int *num_bits,
const u32 *value,
enum tap_state end_state)
{
- int i;
+ int nth_tap;
int field_count = 0;
int scan_size;
int bypass_devices = 0;
jtag_command_t **last_cmd = jtag_get_last_command_p();
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
+
/* count devices in bypass */
- while (device)
- {
- if (device->bypass)
+ tap = NULL;
+ bypass_devices = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ if( tap->bypass ){
bypass_devices++;
- device = device->next;
+ }
}
/* allocate memory for a new list member */
@@ -716,16 +838,22 @@ void MINIDRIVER(interface_jtag_add_dr_out)(int device_num,
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = end_state;
- for (i = 0; i < jtag_num_devices; i++)
- {
- (*last_cmd)->cmd.scan->fields[field_count].device = i;
+ tap = NULL;
+ nth_tap = -1;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ nth_tap++;
+ (*last_cmd)->cmd.scan->fields[field_count].tap = tap;
- if (i == device_num)
+ if (tap == target_tap)
{
int j;
#ifdef _DEBUG_JTAG_IO_
/* if a device is listed, the BYPASS register must not be selected */
- if (jtag_get_device(i)->bypass)
+ if (tap->bypass)
{
LOG_ERROR("BUG: scan data for a device in BYPASS");
exit(-1);
@@ -749,7 +877,7 @@ void MINIDRIVER(interface_jtag_add_dr_out)(int device_num,
{
#ifdef _DEBUG_JTAG_IO_
/* if a device isn't listed, the BYPASS register should be selected */
- if (!jtag_get_device(i)->bypass)
+ if (! tap->bypass)
{
LOG_ERROR("BUG: no scan data for a device not in BYPASS");
exit(-1);
@@ -801,7 +929,7 @@ int MINIDRIVER(interface_jtag_add_plain_dr_scan)(int num_fields, scan_field_t *f
{
int num_bits = fields[i].num_bits;
int num_bytes = CEIL(fields[i].num_bits, 8);
- (*last_cmd)->cmd.scan->fields[i].device = fields[i].device;
+ (*last_cmd)->cmd.scan->fields[i].tap = fields[i].tap;
(*last_cmd)->cmd.scan->fields[i].num_bits = num_bits;
(*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
(*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[i].out_mask, cmd_queue_alloc(num_bytes), num_bits);
@@ -1203,12 +1331,13 @@ int jtag_check_value(u8 *captured, void *priv, scan_field_t *field)
else
compare_failed = buf_cmp(captured, field->in_check_value, num_bits);
- if (compare_failed)
- {
+ if (compare_failed){
/* An error handler could have caught the failing check
* only report a problem when there wasn't a handler, or if the handler
* acknowledged the error
*/
+ LOG_WARNING("TAP %s:",
+ (field->tap == NULL) ? "(unknown)" : field->tap->dotted_name );
if (compare_failed)
{
char *captured_char = buf_to_str(captured, (num_bits > 64) ? 64 : num_bits, 16);
@@ -1218,7 +1347,9 @@ int jtag_check_value(u8 *captured, void *priv, scan_field_t *field)
{
char *in_check_mask_char;
in_check_mask_char = buf_to_str(field->in_check_mask, (num_bits > 64) ? 64 : num_bits, 16);
- LOG_WARNING("value captured during scan didn't pass the requested check: captured: 0x%s check_value: 0x%s check_mask: 0x%s", captured_char, in_check_value_char, in_check_mask_char);
+ LOG_WARNING("value captured during scan didn't pass the requested check:");
+ LOG_WARNING("captured: 0x%s check_value: 0x%s check_mask: 0x%s",
+ captured_char, in_check_value_char, in_check_mask_char);
free(in_check_mask_char);
}
else
@@ -1300,14 +1431,14 @@ int jtag_execute_queue(void)
int jtag_reset_callback(enum jtag_event event, void *priv)
{
- jtag_device_t *device = priv;
+ jtag_tap_t *tap = priv;
LOG_DEBUG("-");
if (event == JTAG_TRST_ASSERTED)
{
- buf_set_ones(device->cur_instr, device->ir_length);
- device->bypass = 1;
+ buf_set_ones(tap->cur_instr, tap->ir_length);
+ tap->bypass = 1;
}
return ERROR_OK;
@@ -1322,7 +1453,7 @@ void jtag_sleep(u32 us)
*/
int jtag_examine_chain(void)
{
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
scan_field_t field;
u8 idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
int i;
@@ -1331,7 +1462,7 @@ int jtag_examine_chain(void)
u8 zero_check = 0x0;
u8 one_check = 0xff;
- field.device = 0;
+ field.tap = NULL;
field.num_bits = sizeof(idcode_buffer) * 8;
field.out_value = idcode_buffer;
field.out_mask = NULL;
@@ -1362,13 +1493,20 @@ int jtag_examine_chain(void)
return ERROR_JTAG_INIT_FAILED;
}
+ // point at the 1st tap
+ tap = jtag_NextEnabledTap(NULL);
+ if( tap == NULL ){
+ LOG_ERROR("JTAG: No taps enabled?");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
for (bit_count = 0; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;)
{
u32 idcode = buf_get_u32(idcode_buffer, bit_count, 32);
if ((idcode & 1) == 0)
{
/* LSB must not be 0, this indicates a device in bypass */
- LOG_WARNING("Device does not have IDCODE");
+ LOG_WARNING("Tap/Device does not have IDCODE");
idcode=0;
bit_count += 1;
@@ -1406,28 +1544,55 @@ int jtag_examine_chain(void)
break;
}
- manufacturer = (idcode & 0xffe) >> 1;
- part = (idcode & 0xffff000) >> 12;
- version = (idcode & 0xf0000000) >> 28;
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+ manufacturer = EXTRACT_MFG(idcode);
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+ part = EXTRACT_PART(idcode);
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+ version = EXTRACT_VER(idcode);
- LOG_INFO("JTAG device found: 0x%8.8x (Manufacturer: 0x%3.3x, Part: 0x%4.4x, Version: 0x%1.1x)",
+ LOG_INFO("JTAG tap: %s tap/device found: 0x%8.8x (Manufacturer: 0x%3.3x, Part: 0x%4.4x, Version: 0x%1.1x)",
+ ((tap != NULL) ? (tap->dotted_name) : "(not-named)"),
idcode, manufacturer, part, version);
bit_count += 32;
}
- if (device)
+ if (tap)
{
- device->idcode = idcode;
- device = device->next;
+ tap->idcode = idcode;
+ if( tap->expected_id ){
+ if( tap->idcode != tap->expected_id ){
+ LOG_ERROR("ERROR: Tap: %s - Expected id: 0x%08x, Got: 0x%08x",
+ tap->dotted_name,
+ tap->expected_id,
+ idcode );
+ LOG_ERROR("ERROR: expected: mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x",
+ EXTRACT_MFG( tap->expected_id ),
+ EXTRACT_PART( tap->expected_id ),
+ EXTRACT_VER( tap->expected_id ) );
+ LOG_ERROR("ERROR: got: mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x",
+ EXTRACT_MFG( tap->idcode ),
+ EXTRACT_PART( tap->idcode ),
+ EXTRACT_VER( tap->idcode ) );
+ } else {
+ LOG_INFO("JTAG Tap/device matched");
+ }
+ } else {
+#if 0
+ LOG_INFO("JTAG TAP ID: 0x%08x - Unknown - please report (A) chipname and (B) idcode to the openocd project",
+ tap->idcode);
+#endif
+ }
+ tap = jtag_NextEnabledTap(tap);
}
device_count++;
}
/* see if number of discovered devices matches configuration */
- if (device_count != jtag_num_devices)
+ if (device_count != jtag_NumEnabledTaps())
{
- LOG_ERROR("number of discovered devices in JTAG chain (%i) doesn't match configuration (%i)",
- device_count, jtag_num_devices);
+ LOG_ERROR("number of discovered devices in JTAG chain (%i) doesn't match (enabled) configuration (%i), total taps: %d",
+ device_count, jtag_NumEnabledTaps(), jtag_NumTotalTaps());
LOG_ERROR("check the config file and ensure proper JTAG communication (connections, speed, ...)");
return ERROR_JTAG_INIT_FAILED;
}
@@ -1437,23 +1602,27 @@ int jtag_examine_chain(void)
int jtag_validate_chain(void)
{
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
int total_ir_length = 0;
u8 *ir_test = NULL;
scan_field_t field;
int chain_pos = 0;
- while (device)
- {
- total_ir_length += device->ir_length;
- device = device->next;
+ tap = NULL;
+ total_ir_length = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ total_ir_length += tap->ir_length;
}
total_ir_length += 2;
ir_test = malloc(CEIL(total_ir_length, 8));
buf_set_ones(ir_test, total_ir_length);
- field.device = 0;
+ field.tap = NULL;
field.num_bits = total_ir_length;
field.out_value = ir_test;
field.out_mask = NULL;
@@ -1466,9 +1635,15 @@ int jtag_validate_chain(void)
jtag_add_plain_ir_scan(1, &field, TAP_TLR);
jtag_execute_queue();
- device = jtag_devices;
- while (device)
- {
+ tap = NULL;
+ chain_pos = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+
+
if (buf_get_u32(ir_test, chain_pos, 2) != 0x1)
{
char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
@@ -1477,8 +1652,7 @@ int jtag_validate_chain(void)
free(ir_test);
return ERROR_JTAG_INIT_FAILED;
}
- chain_pos += device->ir_length;
- device = device->next;
+ chain_pos += tap->ir_length;
}
if (buf_get_u32(ir_test, chain_pos, 2) != 0x3)
@@ -1497,6 +1671,179 @@ int jtag_validate_chain(void)
static int
+jim_newtap_cmd( Jim_GetOptInfo *goi )
+{
+ jtag_tap_t *pTap;
+ jtag_tap_t **ppTap;
+ jim_wide w;
+ int x;
+ int e;
+ int reqbits;
+ Jim_Nvp *n;
+ char *cp;
+ const Jim_Nvp opts[] = {
+#define NTAP_OPT_IRLEN 0
+ { .name = "-irlen" , .value = NTAP_OPT_IRLEN },
+#define NTAP_OPT_IRMASK 1
+ { .name = "-irmask" , .value = NTAP_OPT_IRMASK },
+#define NTAP_OPT_IRCAPTURE 2
+ { .name = "-ircapture" , .value = NTAP_OPT_IRCAPTURE },
+#define NTAP_OPT_ENABLED 3
+ { .name = "-enable" , .value = NTAP_OPT_ENABLED },
+#define NTAP_OPT_DISABLED 4
+ { .name = "-disable" , .value = NTAP_OPT_DISABLED },
+#define NTAP_OPT_EXPECTED_ID 5
+ { .name = "-expected-id" , .value = NTAP_OPT_EXPECTED_ID },
+ { .name = NULL , .value = -1 },
+ };
+
+
+ pTap = malloc( sizeof(jtag_tap_t) );
+ memset( pTap, 0, sizeof(*pTap) );
+ if( !pTap ){
+ Jim_SetResult_sprintf( goi->interp, "no memory");
+ return JIM_ERR;
+ }
+ //
+ // we expect CHIP + TAP + OPTIONS
+ //
+ if( goi->argc < 3 ){
+ Jim_SetResult_sprintf(goi->interp, "Missing CHIP TAP OPTIONS ....");
+ return JIM_ERR;
+ }
+ Jim_GetOpt_String( goi, &cp, NULL );
+ pTap->chip = strdup(cp);
+
+ Jim_GetOpt_String( goi, &cp, NULL );
+ pTap->tapname = strdup(cp);
+
+ // name + dot + name + null
+ x = strlen(pTap->chip) + 1 + strlen(pTap->tapname) + 1;
+ cp = malloc( x );
+ sprintf( cp, "%s.%s", pTap->chip, pTap->tapname );
+ pTap->dotted_name = cp;
+
+ LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
+ pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc);
+
+
+ // default is enabled
+ pTap->enabled = 1;
+
+ // deal with options
+#define NTREQ_IRLEN 1
+#define NTREQ_IRCAPTURE 2
+#define NTREQ_IRMASK 4
+
+ // clear them as we find them
+ reqbits = (NTREQ_IRLEN | NTREQ_IRCAPTURE | NTREQ_IRMASK);
+
+ while( goi->argc ){
+ e = Jim_GetOpt_Nvp( goi, opts, &n );
+ if( e != JIM_OK ){
+ Jim_GetOpt_NvpUnknown( goi, opts, 0 );
+ return e;
+ }
+ LOG_DEBUG("Processing option: %s", n->name );
+ switch( n->value ){
+ case NTAP_OPT_ENABLED:
+ pTap->enabled = 1;
+ break;
+ case NTAP_OPT_DISABLED:
+ pTap->enabled = 0;
+ break;
+ case NTAP_OPT_EXPECTED_ID:
+ e = Jim_GetOpt_Wide( goi, &w );
+ pTap->expected_id = w;
+ break;
+ case NTAP_OPT_IRLEN:
+ case NTAP_OPT_IRMASK:
+ case NTAP_OPT_IRCAPTURE:
+ e = Jim_GetOpt_Wide( goi, &w );
+ if( e != JIM_OK ){
+ Jim_SetResult_sprintf( goi->interp, "option: %s bad parameter", n->name );
+ return e;
+ }
+ if( (w < 0) || (w > 0xffff) ){
+ // wacky value
+ Jim_SetResult_sprintf( goi->interp, "option: %s - wacky value: %d (0x%x)",
+ n->name, (int)(w), (int)(w));
+ return JIM_ERR;
+ }
+ switch(n->value){
+ case NTAP_OPT_IRLEN:
+ pTap->ir_length = w;
+ reqbits &= (~(NTREQ_IRLEN));
+ break;
+ case NTAP_OPT_IRMASK:
+ pTap->ir_capture_mask = w;
+ reqbits &= (~(NTREQ_IRMASK));
+ break;
+ case NTAP_OPT_IRCAPTURE:
+ pTap->ir_capture_value = w;
+ reqbits &= (~(NTREQ_IRCAPTURE));
+ break;
+ }
+ } // switch(n->value)
+ } // while( goi->argc )
+
+ // Did we get all the options?
+ if( reqbits ){
+ // no
+ Jim_SetResult_sprintf( goi->interp,
+ "newtap: %s missing required parameters",
+ pTap->dotted_name);
+ // fixme: Tell user what is missing :-(
+ // no memory leaks pelase
+ free(((void *)(pTap->chip)));
+ free(((void *)(pTap->tapname)));
+ free(((void *)(pTap->dotted_name)));
+ free(((void *)(pTap)));
+ return JIM_ERR;
+ }
+
+ pTap->expected = malloc( pTap->ir_length );
+ pTap->expected_mask = malloc( pTap->ir_length );
+ pTap->cur_instr = malloc( pTap->ir_length );
+
+ buf_set_u32( pTap->expected,
+ 0,
+ pTap->ir_length,
+ pTap->ir_capture_value );
+ buf_set_u32( pTap->expected_mask,
+ 0,
+ pTap->ir_length,
+ pTap->ir_capture_mask );
+ buf_set_ones( pTap->cur_instr,
+ pTap->ir_length );
+
+ pTap->bypass = 1;
+
+
+ jtag_register_event_callback(jtag_reset_callback, pTap );
+
+ ppTap = &(jtag_all_taps);
+ while( (*ppTap) != NULL ){
+ ppTap = &((*ppTap)->next_tap);
+ }
+ *ppTap = pTap;
+ {
+ static int n_taps = 0;
+ pTap->abs_chain_position = n_taps++;
+ }
+ LOG_DEBUG( "Created Tap: %s @ abs position %d, irlen %d, capture: 0x%x mask: 0x%x",
+ (*ppTap)->dotted_name,
+ (*ppTap)->abs_chain_position,
+ (*ppTap)->ir_length,
+ (*ppTap)->ir_capture_value,
+ (*ppTap)->ir_capture_mask );
+
+
+ return ERROR_OK;
+}
+
+
+static int
jim_jtag_command( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
{
Jim_GetOptInfo goi;
@@ -1507,11 +1854,19 @@ jim_jtag_command( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
enum {
JTAG_CMD_INTERFACE,
JTAG_CMD_INIT_RESET,
+ JTAG_CMD_NEWTAP,
+ JTAG_CMD_TAPENABLE,
+ JTAG_CMD_TAPDISABLE,
+ JTAG_CMD_TAPISENABLED
};
const Jim_Nvp jtag_cmds[] = {
{ .name = "interface" , .value = JTAG_CMD_INTERFACE },
{ .name = "arp_init-reset", .value = JTAG_CMD_INIT_RESET },
+ { .name = "newtap" , .value = JTAG_CMD_NEWTAP },
+ { .name = "tapisenabled" , .value = JTAG_CMD_TAPISENABLED },
+ { .name = "tapenable" , .value = JTAG_CMD_TAPENABLE },
+ { .name = "tapdisable" , .value = JTAG_CMD_TAPDISABLE },
{ .name = NULL, .value = -1 },
};
@@ -1548,6 +1903,39 @@ jim_jtag_command( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
return JIM_ERR;
}
return JIM_OK;
+ case JTAG_CMD_NEWTAP:
+ return jim_newtap_cmd( &goi );
+ break;
+ case JTAG_CMD_TAPISENABLED:
+ case JTAG_CMD_TAPENABLE:
+ case JTAG_CMD_TAPDISABLE:
+ if( goi.argc != 1 ){
+ Jim_SetResultString( goi.interp, "Too many parameters",-1 );
+ return JIM_ERR;
+ }
+
+ {
+ jtag_tap_t *t;
+ t = jtag_TapByJimObj( goi.interp, goi.argv[0] );
+ if( t == NULL ){
+ return JIM_ERR;
+ }
+ switch( n->value ){
+ case JTAG_CMD_TAPISENABLED:
+ // below
+ break;
+ case JTAG_CMD_TAPENABLE:
+ e = 1;
+ t->enabled = e;
+ break;
+ case JTAG_CMD_TAPDISABLE:
+ e = 0;
+ t->enabled = e;
+ break;
+ }
+ Jim_SetResult( goi.interp, Jim_NewIntObj( goi.interp, e ) );
+ return JIM_OK;
+ }
}
@@ -1619,19 +2007,16 @@ int jtag_interface_init(struct command_context_s *cmd_ctx)
static int jtag_init_inner(struct command_context_s *cmd_ctx)
{
- jtag_device_t *device;
+ jtag_tap_t *tap;
int retval;
LOG_DEBUG("Init JTAG chain");
- device = jtag_devices;
- jtag_ir_scan_size = 0;
- jtag_num_devices = 0;
- while (device != NULL)
- {
- jtag_ir_scan_size += device->ir_length;
- jtag_num_devices++;
- device = device->next;
+
+ tap = jtag_NextEnabledTap(NULL);
+ if( tap == NULL ){
+ LOG_ERROR("There are no enabled taps?");
+ return ERROR_JTAG_INIT_FAILED;
}
jtag_add_tlr();
@@ -1798,53 +2183,95 @@ int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char
int handle_jtag_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- jtag_device_t **last_device_p = &jtag_devices;
-
- if (*last_device_p)
- {
- while ((*last_device_p)->next)
- last_device_p = &((*last_device_p)->next);
- last_device_p = &((*last_device_p)->next);
- }
-
- if (argc < 3)
+ int e;
+ char buf[1024];
+ Jim_Obj *newargs[ 10 ];
+ //
+ // CONVERT SYNTAX
+ //
+ // argv[-1] = command
+ // argv[ 0] = ir length
+ // argv[ 1] = ir capture
+ // argv[ 2] = ir mask
+ // argv[ 3] = not actually used by anything but in the docs
+
+ if( argc < 4 ){
+ command_print( cmd_ctx, "OLD DEPRECATED SYNTAX: Please use the NEW syntax");
return ERROR_OK;
-
- *last_device_p = malloc(sizeof(jtag_device_t));
- (*last_device_p)->ir_length = strtoul(args[0], NULL, 0);
-
- (*last_device_p)->expected = malloc((*last_device_p)->ir_length);
- buf_set_u32((*last_device_p)->expected, 0, (*last_device_p)->ir_length, strtoul(args[1], NULL, 0));
- (*last_device_p)->expected_mask = malloc((*last_device_p)->ir_length);
- buf_set_u32((*last_device_p)->expected_mask, 0, (*last_device_p)->ir_length, strtoul(args[2], NULL, 0));
-
- (*last_device_p)->cur_instr = malloc((*last_device_p)->ir_length);
- (*last_device_p)->bypass = 1;
- buf_set_ones((*last_device_p)->cur_instr, (*last_device_p)->ir_length);
-
- (*last_device_p)->next = NULL;
-
- jtag_register_event_callback(jtag_reset_callback, (*last_device_p));
-
- jtag_num_devices++;
-
- return ERROR_OK;
+ }
+ command_print( cmd_ctx, "OLD SYNTAX: DEPRECATED - translating to new syntax");
+ command_print( cmd_ctx, "jtag newtap CHIP TAP -irlen %s -ircapture %s -irvalue %s",
+ args[0],
+ args[1],
+ args[2] );
+ command_print( cmd_ctx, "Example: STM32 has 2 taps, the cortexM3(len4) + boundryscan(len5)");
+ command_print( cmd_ctx, "jtag newtap stm32 cortexm3 ....., thus creating the tap: \"stm32.cortexm3\"");
+ command_print( cmd_ctx, "jtag newtap stm32 boundry ....., and the tap: \"stm32.boundery\"");
+ command_print( cmd_ctx, "And then refer to the taps by the dotted name.");
+
+
+
+ newargs[0] = Jim_NewStringObj( interp, "jtag", -1 );
+ newargs[1] = Jim_NewStringObj( interp, "newtap", -1 );
+ sprintf( buf, "chip%d", jtag_NumTotalTaps() );
+ newargs[2] = Jim_NewStringObj( interp, buf, -1 );
+ sprintf( buf, "tap%d", jtag_NumTotalTaps() );
+ newargs[3] = Jim_NewStringObj( interp, buf, -1 );
+ newargs[4] = Jim_NewStringObj( interp, "-irlen", -1 );
+ newargs[5] = Jim_NewStringObj( interp, args[0], -1 );
+ newargs[6] = Jim_NewStringObj( interp, "-ircapture", -1 );
+ newargs[7] = Jim_NewStringObj( interp, args[1], -1 );
+ newargs[8] = Jim_NewStringObj( interp, "-irmask", -1 );
+ newargs[9] = Jim_NewStringObj( interp, args[2], -1 );
+
+ command_print( cmd_ctx, "NEW COMMAND:");
+ sprintf( buf, "%s %s %s %s %s %s %s %s %s %s",
+ Jim_GetString( newargs[0], NULL ),
+ Jim_GetString( newargs[1], NULL ),
+ Jim_GetString( newargs[2], NULL ),
+ Jim_GetString( newargs[3], NULL ),
+ Jim_GetString( newargs[4], NULL ),
+ Jim_GetString( newargs[5], NULL ),
+ Jim_GetString( newargs[6], NULL ),
+ Jim_GetString( newargs[7], NULL ),
+ Jim_GetString( newargs[8], NULL ),
+ Jim_GetString( newargs[9], NULL ) );
+
+
+
+ e = jim_jtag_command( interp, 10, newargs );
+ if( e != JIM_OK ){
+ command_print( cmd_ctx, "%s", Jim_GetString( Jim_GetResult(interp), NULL ) );
+ }
+ return e;
}
+
int handle_scan_chain_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- jtag_device_t *device = jtag_devices;
- int device_count = 0;
+ jtag_tap_t *tap;
- while (device)
- {
+ tap = jtag_all_taps;
+ command_print(cmd_ctx, " TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr ");
+ command_print(cmd_ctx, "---|--------------------|---------|------------|------------|------|------|------|---------");
+
+ while( tap ){
u32 expected, expected_mask, cur_instr;
- expected = buf_get_u32(device->expected, 0, device->ir_length);
- expected_mask = buf_get_u32(device->expected_mask, 0, device->ir_length);
- cur_instr = buf_get_u32(device->cur_instr, 0, device->ir_length);
- command_print(cmd_ctx, "%i: idcode: 0x%8.8x ir length %i, ir capture 0x%x, ir mask 0x%x, current instruction 0x%x", device_count, device->idcode, device->ir_length, expected, expected_mask, cur_instr);
- device = device->next;
- device_count++;
+ expected = buf_get_u32(tap->expected, 0, tap->ir_length);
+ expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length);
+ cur_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length);
+ command_print(cmd_ctx,
+ "%2d | %-18s | %c | 0x%08x | 0x%08x | 0x%02x | 0x%02x | 0x%02x | 0x%02x",
+ tap->abs_chain_position,
+ tap->dotted_name,
+ tap->enabled ? 'Y' : 'n',
+ tap->idcode,
+ tap->expected_id,
+ tap->ir_length,
+ expected,
+ expected_mask,
+ cur_instr);
+ tap = tap->next_tap;
}
return ERROR_OK;
@@ -1867,7 +2294,7 @@ int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, ch
jtag_reset_config = RESET_TRST_AND_SRST;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(1) invalid reset_config argument (%s), defaulting to none", args[0]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
@@ -1888,7 +2315,7 @@ int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, ch
jtag_reset_config |= RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(2) invalid reset_config argument (%s), defaulting to none", args[1]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
@@ -1903,7 +2330,7 @@ int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, ch
jtag_reset_config &= ~RESET_TRST_OPEN_DRAIN;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(3) invalid reset_config argument (%s) defaulting to none", args[2] );
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
@@ -1917,7 +2344,7 @@ int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, ch
jtag_reset_config &= ~RESET_SRST_PUSH_PULL;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(4) invalid reset_config argument (%s), defaulting to none", args[3]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
@@ -2113,6 +2540,7 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
{
int i;
scan_field_t *fields;
+ jtag_tap_t *tap;
if ((argc < 2) || (argc % 2))
{
@@ -2123,14 +2551,14 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
for (i = 0; i < argc / 2; i++)
{
- int device = strtoul(args[i*2], NULL, 0);
- jtag_device_t *device_ptr=jtag_get_device(device);
- if (device_ptr==NULL)
+ tap = jtag_TapByString( args[i*2] );
+ if (tap==NULL)
{
+ command_print( cmd_ctx, "Tap: %s unknown", args[i*2] );
return ERROR_FAIL;
}
- int field_size = device_ptr->ir_length;
- fields[i].device = device;
+ int field_size = tap->ir_length;
+ fields[i].tap = tap;
fields[i].out_value = malloc(CEIL(field_size, 8));
buf_set_u32(fields[i].out_value, 0, field_size, strtoul(args[i*2+1], NULL, 0));
fields[i].out_mask = NULL;
@@ -2158,7 +2586,7 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
int num_fields;
int field_count = 0;
int i, e;
- long device;
+ jtag_tap_t *tap;
/* args[1] = device
* args[2] = num_bits
@@ -2180,9 +2608,10 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
return e;
}
- e = Jim_GetLong(interp, args[1], &device);
- if (e != JIM_OK)
- return e;
+ tap = jtag_TapByJimObj( interp, args[1] );
+ if( tap == NULL ){
+ return JIM_ERR;
+ }
num_fields=(argc-2)/2;
fields = malloc(sizeof(scan_field_t) * num_fields);
@@ -2195,7 +2624,8 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
Jim_GetLong(interp, args[i], &bits);
str = Jim_GetString(args[i+1], &len);
- fields[field_count].device = device;
+
+ fields[field_count].tap = tap;
fields[field_count].num_bits = bits;
fields[field_count].out_value = malloc(CEIL(bits, 8));
str_to_buf(str, len, fields[field_count].out_value, bits, 0);
@@ -2211,8 +2641,7 @@ int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
{
- Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
- Jim_AppendStrings(interp, Jim_GetResult(interp), "drscan: jtag execute failed", NULL);
+ Jim_SetResultString(interp, "drscan: jtag execute failed",-1);
return JIM_ERR;
}
@@ -2274,3 +2703,4 @@ int jtag_srst_asserted(int *srst_asserted)
{
return jtag->srst_asserted(srst_asserted);
}
+
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 68f52dde..cff2a662 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -75,7 +75,7 @@ typedef int (*in_handler_t)(u8 *in_value, void *priv, struct scan_field_s *field
typedef struct scan_field_s
{
- int device; /* ordinal device number this instruction refers to */
+ jtag_tap_t *tap; /* tap pointer this instruction refers to */
int num_bits; /* number of bits this field specifies (up to 32) */
u8 *out_value; /* value to be scanned into the device */
u8 *out_mask; /* only masked bits care */
@@ -163,20 +163,39 @@ typedef struct jtag_command_s
extern jtag_command_t *jtag_command_queue;
-typedef struct jtag_device_s
+// this is really: typedef jtag_tap_t
+// But - the typedef is done in "types.h"
+// due to "forward decloration reasons"
+struct jtag_tap_s
{
+ const char *chip;
+ const char *tapname;
+ const char *dotted_name;
+ int abs_chain_position;
+ int enabled;
int ir_length; /* size of instruction register */
+ u32 ir_capture_value;
u8 *expected; /* Capture-IR expected value */
+ u32 ir_capture_mask;
u8 *expected_mask; /* Capture-IR expected mask */
u32 idcode; /* device identification code */
+ u32 expected_id;
u8 *cur_instr; /* current instruction */
int bypass; /* bypass register selected */
- struct jtag_device_s *next;
-} jtag_device_t;
+ jtag_tap_t *next_tap;
+};
+extern jtag_tap_t *jtag_AllTaps(void);
+extern jtag_tap_t *jtag_TapByPosition(int n);
+extern jtag_tap_t *jtag_NextEnabledTap( jtag_tap_t * );
+extern jtag_tap_t *jtag_TapByPosition( int n );
+extern jtag_tap_t *jtag_TapByString( const char *dotted_name );
+extern jtag_tap_t *jtag_TapByJimObj( Jim_Interp *interp, Jim_Obj *obj );
+extern jtag_tap_t *jtag_TapByAbsPosition( int abs_position );
+extern int jtag_NumEnabledTaps(void);
+extern int jtag_NumTotalTaps(void);
+
+
-extern jtag_device_t *jtag_devices;
-extern int jtag_num_devices;
-extern int jtag_ir_scan_size;
enum reset_line_mode
{
@@ -420,7 +439,7 @@ extern enum scan_type jtag_scan_type(scan_command_t *cmd);
extern int jtag_scan_size(scan_command_t *cmd);
extern int jtag_read_buffer(u8 *buffer, scan_command_t *cmd);
extern int jtag_build_buffer(scan_command_t *cmd, u8 **buffer);
-extern jtag_device_t* jtag_get_device(int num);
+
extern void jtag_sleep(u32 us);
extern int jtag_call_event_callbacks(enum jtag_event event);
extern int jtag_register_event_callback(int (*callback)(enum jtag_event event, void *priv), void *priv);
@@ -463,7 +482,7 @@ extern int jtag_verify_capture_ir;
*
* Note that this jtag_add_dr_out can be defined as an inline function.
*/
-extern void interface_jtag_add_dr_out(int device,
+extern void interface_jtag_add_dr_out(jtag_tap_t *tap,
int num_fields,
const int *num_bits,
const u32 *value,
@@ -473,7 +492,7 @@ extern void interface_jtag_add_dr_out(int device,
-static __inline__ void jtag_add_dr_out(int device,
+static __inline__ void jtag_add_dr_out(jtag_tap_t *tap,
int num_fields,
const int *num_bits,
const u32 *value,
@@ -482,7 +501,7 @@ static __inline__ void jtag_add_dr_out(int device,
if (end_state != -1)
cmd_queue_end_state=end_state;
cmd_queue_cur_state=cmd_queue_end_state;
- interface_jtag_add_dr_out(device, num_fields, num_bits, value, cmd_queue_end_state);
+ interface_jtag_add_dr_out(tap, num_fields, num_bits, value, cmd_queue_end_state);
}
diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index 9ddd1f66..2d86e3e5 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -43,18 +43,17 @@ pld_driver_t virtex2_pld =
.load = virtex2_load,
};
-int virtex2_set_instr(int chain_pos, u32 new_instr)
+int virtex2_set_instr(jtag_tap_t *tap, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
@@ -81,7 +80,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
values = malloc(num_words * 4);
- scan_field.device = virtex2_info->chain_pos;
+ scan_field.tap = virtex2_info->tap;
scan_field.num_bits = num_words * 32;
scan_field.out_value = values;
scan_field.out_mask = NULL;
@@ -94,7 +93,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
for (i = 0; i < num_words; i++)
buf_set_u32(values + 4 * i, 0, 32, flip_u32(*words++, 32));
- virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
+ virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD);
@@ -115,7 +114,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
virtex2_pld_device_t *virtex2_info = pld_device->driver_priv;
scan_field_t scan_field;
- scan_field.device = virtex2_info->chain_pos;
+ scan_field.tap = virtex2_info->tap;
scan_field.num_bits = 32;
scan_field.out_value = NULL;
scan_field.out_mask = NULL;
@@ -124,7 +123,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
scan_field.in_check_mask = NULL;
scan_field.in_handler = virtex2_jtag_buf_to_u32;
- virtex2_set_instr(virtex2_info->chain_pos, 0x4); /* CFG_OUT */
+ virtex2_set_instr(virtex2_info->tap, 0x4); /* CFG_OUT */
while (num_words--)
{
@@ -166,7 +165,7 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
scan_field_t field;
- field.device = virtex2_info->chain_pos;
+ field.tap = virtex2_info->tap;
field.out_mask = NULL;
field.in_value = NULL;
field.in_check_value = NULL;
@@ -178,11 +177,11 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
return retval;
jtag_add_end_state(TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0xb); /* JPROG_B */
+ virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
jtag_execute_queue();
jtag_add_sleep(1000);
- virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
+ virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_execute_queue();
for (i = 0; i < bit_file.length; i++)
@@ -197,13 +196,13 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
jtag_add_tlr();
jtag_add_end_state(TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0xc); /* JSTART */
+ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
- virtex2_set_instr(virtex2_info->chain_pos, 0xc); /* JSTART */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
jtag_execute_queue();
return ERROR_OK;
@@ -249,6 +248,8 @@ int virtex2_register_commands(struct command_context_s *cmd_ctx)
int virtex2_pld_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct pld_device_s *pld_device)
{
+ jtag_tap_t *tap;
+
virtex2_pld_device_t *virtex2_info;
if (argc < 2)
@@ -257,10 +258,15 @@ int virtex2_pld_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
return ERROR_PLD_DEVICE_INVALID;
}
+ tap = jtag_TapByString( args[1] );
+ if( tap == NULL ){
+ command_print( cmd_ctx, "Tap: %s does not exist", args[1] );
+ return ERROR_OK;
+ }
+
virtex2_info = malloc(sizeof(virtex2_pld_device_t));
pld_device->driver_priv = virtex2_info;
-
- virtex2_info->chain_pos = strtoul(args[1], NULL, 0);
+ virtex2_info->tap = tap;
return ERROR_OK;
}
diff --git a/src/pld/virtex2.h b/src/pld/virtex2.h
index 1b5865dd..7bc6c5eb 100644
--- a/src/pld/virtex2.h
+++ b/src/pld/virtex2.h
@@ -20,12 +20,13 @@
#ifndef VIRTEX2_H
#define VIRTEX2_H
+#include "types.h"
#include "pld.h"
#include "xilinx_bit.h"
typedef struct virtex2_pld_device_s
{
- int chain_pos;
+ jtag_tap_t *tap;
} virtex2_pld_device_t;
#endif /* VIRTEX2_H */
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 6a9465b8..fd55a04b 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -19,27 +19,12 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
-nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
- target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg \
- target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
- target/pxa255.cfg target/zy1000.cfg target/at91sam9260.cfg \
- target/wi-9c.cfg target/stm32.cfg target/xba_revA3.cfg \
- ecos/at91eb40a.elf target/lm3s6965.cfg interface/parport.cfg \
- interface/jtagkey-tiny.cfg interface/jtagkey.cfg interface/str9-comstick.cfg \
- target/epc9301.cfg target/ipx42x.cfg target/lpc2129.cfg target/netx500.cfg \
- target/omap5912.cfg target/pxa270.cfg target/str750.cfg target/str9comstick.cfg \
- target/str730.cfg target/stm32stick.cfg \
- target/lm3s811.cfg interface/luminary.cfg interface/luminary-libftdi.cfg interface/luminary-lm3s811.cfg \
- target/imx31.cfg target/lm3s3748.cfg \
- interface/stm32-stick.cfg interface/calao-usb-a9260-c01.cfg interface/calao-usb-a9260-c02.cfg \
- interface/calao-usb-a9260.cfg target/at91sam9260minimal.cfg \
- interface/chameleon.cfg interface/at91rm9200.cfg interface/jlink.cfg interface/arm-usb-ocd.cfg \
- interface/signalyzer.cfg target/eir-sam7se512.cfg \
- interface/flyswatter.cfg target/hammer.cfg \
- interface/olimex-jtag-tiny-a.cfg \
- target/pic32mx.cfg target/aduc702x.cfg interface/dummy.cfg interface/olimex-arm-usb-ocd.cfg target/s3c2440.cfg \
- interface/openocd-usb.cfg target/test_syntax_error.cfg target/test_reset_syntax_error.cfg \
- target/imx27.cfg
-
-
-
+nobase_dist_pkglib_DATA =
+nobase_dist_pkglib_DATA += xscale/debug_handler.bin
+nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
+# Various chip targets
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/target/*.cfg)
+# Various jtag interfaces
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/interface/*.cfg)
+# Various preconfigured boards
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/board/*.cfg)
diff --git a/src/target/arm11.c b/src/target/arm11.c
index e53f0233..38961bd7 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1526,7 +1526,7 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp)
arm11->target = target;
/* prepare JTAG information for the new target */
- arm11->jtag_info.chain_pos = target->chain_position;
+ arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
@@ -1534,13 +1534,12 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp)
return retval;
}
- jtag_device_t *device = jtag_get_device(target->chain_position);
- if (device==NULL)
+ if (target->tap==NULL)
return ERROR_FAIL;
- if (device->ir_length != 5)
+ if (target->tap->ir_length != 5)
{
- LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
+ LOG_ERROR("'target arm11' expects IR LENGTH = 5");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1831,22 +1830,22 @@ const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode
arm11_common_t * arm11_find_target(const char * arg)
{
- size_t jtag_target = strtoul(arg, NULL, 0);
-
- {target_t * t;
- for (t = all_targets; t; t = t->next)
- {
- if (strcmp(t->type->name,"arm11"))
- continue;
-
- arm11_common_t * arm11 = t->arch_info;
-
- if (arm11->jtag_info.chain_pos != jtag_target)
- continue;
-
- return arm11;
- }}
-
+ jtag_tap_t *tap;
+ target_t * t;
+
+ tap = jtag_TapByString( arg );
+ if( !tap ){
+ return NULL;
+ }
+
+ for (t = all_targets; t; t = t->next){
+ if( t->tap == tap ){
+ if( 0 == strcmp(t->type->name,"arm11")){
+ arm11_common_t * arm11 = t->arch_info;
+ return arm11;
+ }
+ }
+ }
return 0;
}
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 09e8b78c..a6660cdd 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -78,7 +78,7 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
{
- field->device = arm11->jtag_info.chain_pos;
+ field->tap = arm11->jtag_info.tap;
field->num_bits = num_bits;
field->out_mask = NULL;
field->in_check_mask = NULL;
@@ -101,16 +101,17 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
*/
void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
{
- jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos);
- if (device==NULL)
- {
+ jtag_tap_t *tap;
+ tap = arm11->jtag_info.tap;
+ if( tap == NULL ){
/* FIX!!!! error is logged, but not propagated back up the call stack... */
+ LOG_ERROR( "tap is null here! This is bad!");
+ return;
}
- if (buf_get_u32(device->cur_instr, 0, 5) == instr)
- {
- JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
- return;
+ if (buf_get_u32(tap->cur_instr, 0, 5) == instr){
+ JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
+ return;
}
JTAG_DEBUG("IR <= 0x%02x", instr);
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index e95f2676..1d9efc04 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -109,7 +109,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
return retval;
}
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
fields[0].out_mask = NULL;
@@ -119,7 +119,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = out_buf;
fields[1].out_mask = NULL;
@@ -456,12 +456,12 @@ int arm720t_quit(void)
return ERROR_OK;
}
-int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, const char *variant)
+int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
- arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
+ arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
arm7tdmi->arch_info = arm720t;
arm720t->common_magic = ARM720T_COMMON_MAGIC;
@@ -485,7 +485,7 @@ int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
- arm720t_init_arch_info(target, arm720t, target->chain_position, target->variant);
+ arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3dec458e..edadcb2b 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2349,9 +2349,10 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
- int chain_pos = ice_reg->jtag_info->chain_pos;
+ jtag_tap_t *tap;
+ tap = ice_reg->jtag_info->tap;
- embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
+ embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
buffer += (count-2)*4;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 4528a83f..2e9d28d8 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -112,7 +112,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
jtag_add_end_state(TAP_PD);
- fields[0].device = arm7_9->jtag_info.chain_pos;
+ fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -122,7 +122,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = arm7_9->jtag_info.chain_pos;
+ fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -165,7 +165,7 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
{
u32 values[2]={breakpoint, flip_u32(out, 32)};
- jtag_add_dr_out(jtag_info->chain_pos,
+ jtag_add_dr_out(jtag_info->tap,
2,
arm7tdmi_num_bits,
values,
@@ -199,7 +199,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -209,7 +209,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -260,7 +260,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -270,7 +270,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -784,7 +784,7 @@ int arm7tdmi_quit(void)
return ERROR_OK;
}
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, const char *variant)
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -793,7 +793,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c
armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */
- arm7_9->jtag_info.chain_pos = chain_pos;
+ arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 4;
/* register arch-specific functions */
@@ -860,7 +860,7 @@ int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
- arm7tdmi_init_arch_info(target, arm7tdmi, target->chain_position, target->variant);
+ arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h
index 1389244e..ab078e28 100644
--- a/src/target/arm7tdmi.h
+++ b/src/target/arm7tdmi.h
@@ -41,7 +41,7 @@ typedef struct arm7tdmi_common_s
} arm7tdmi_common_t;
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, const char *variant);
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant);
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm7tdmi_examine(struct target_s *target);
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index b22a8c2b..76e54f72 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -110,7 +110,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
@@ -120,7 +120,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -130,7 +130,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].out_mask = NULL;
@@ -140,7 +140,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
@@ -182,7 +182,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
@@ -192,7 +192,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = value_buf;
fields[1].out_mask = NULL;
@@ -202,7 +202,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].out_mask = NULL;
@@ -212,7 +212,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
@@ -249,7 +249,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
@@ -259,7 +259,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = cp15_opcode_buf;
fields[1].out_mask = NULL;
@@ -269,7 +269,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].out_mask = NULL;
@@ -279,7 +279,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
@@ -712,14 +712,14 @@ int arm920t_quit(void)
return ERROR_OK;
}
-int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, const char *variant)
+int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm920t;
arm920t->common_magic = ARM920T_COMMON_MAGIC;
@@ -752,7 +752,7 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
- arm920t_init_arch_info(target, arm920t, target->chain_position, target->variant);
+ arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 2a3ba307..b812e984 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -139,7 +139,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -149,7 +149,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].out_mask = NULL;
@@ -159,7 +159,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].out_mask = NULL;
@@ -169,7 +169,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
@@ -229,7 +229,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].out_mask = NULL;
@@ -239,7 +239,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].out_mask = NULL;
@@ -249,7 +249,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].out_mask = NULL;
@@ -259,7 +259,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
@@ -714,14 +714,14 @@ int arm926ejs_quit(void)
return ERROR_OK;
}
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm926ejs;
arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
@@ -755,7 +755,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
{
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
- arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h
index f40120c0..1b280de7 100644
--- a/src/target/arm926ejs.h
+++ b/src/target/arm926ejs.h
@@ -43,7 +43,7 @@ typedef struct arm926ejs_common_s
u32 d_far;
} arm926ejs_common_t;
-extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant);
+extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant);
extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
extern int arm926ejs_arch_state(struct target_s *target);
extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index a441acbf..576be2e1 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -102,12 +102,12 @@ int arm966e_quit(void)
return ERROR_OK;
}
-int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, const char *variant)
+int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC;
@@ -125,7 +125,7 @@ int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
- arm966e_init_arch_info(target, arm966e, target->chain_position, target->variant);
+ arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
return ERROR_OK;
}
@@ -185,7 +185,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -195,7 +195,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].out_mask = NULL;
@@ -205,7 +205,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].out_mask = NULL;
@@ -253,7 +253,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].out_mask = NULL;
@@ -263,7 +263,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].out_mask = NULL;
@@ -273,7 +273,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].out_mask = NULL;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 89842d50..70ee6239 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -127,7 +127,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
jtag_add_end_state(TAP_PD);
- fields[0].device = arm7_9->jtag_info.chain_pos;
+ fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -137,7 +137,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = arm7_9->jtag_info.chain_pos;
+ fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -147,7 +147,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = arm7_9->jtag_info.chain_pos;
+ fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
@@ -215,7 +215,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].out_mask = NULL;
@@ -233,7 +233,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].out_mask = NULL;
@@ -243,7 +243,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].out_mask = NULL;
@@ -290,7 +290,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -300,7 +300,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -310,7 +310,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
@@ -362,7 +362,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -383,7 +383,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -393,7 +393,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
@@ -941,7 +941,7 @@ int arm9tdmi_quit(void)
return ERROR_OK;
}
-int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant)
+int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -950,7 +950,7 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int c
armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */
- arm7_9->jtag_info.chain_pos = chain_pos;
+ arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
/* register arch-specific functions */
@@ -1051,7 +1051,7 @@ int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
{
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
- arm9tdmi_init_arch_info(target, arm9tdmi, target->chain_position, target->variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h
index e52bf78c..3cb3786b 100644
--- a/src/target/arm9tdmi.h
+++ b/src/target/arm9tdmi.h
@@ -60,7 +60,7 @@ enum arm9tdmi_vector
extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_examine(struct target_s *target);
-extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant);
+extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant);
extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed);
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 2967f088..888d0f7f 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -38,17 +38,18 @@
int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, in_handler_t handler)
{
- jtag_device_t *device = jtag_get_device(jtag_info->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+ tap = jtag_info->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
u8 t[4];
- field.device = jtag_info->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
@@ -79,7 +80,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, u32 new_scan_chain)
return retval;
}
- jtag_add_dr_out(jtag_info->chain_pos,
+ jtag_add_dr_out(jtag_info->tap,
1,
num_bits,
values,
diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h
index c5677429..11f6bd61 100644
--- a/src/target/arm_jtag.h
+++ b/src/target/arm_jtag.h
@@ -28,7 +28,7 @@
typedef struct arm_jtag_s
{
- int chain_pos;
+ jtag_tap_t *tap;
int scann_size;
u32 scann_instr;
diff --git a/src/target/board/arm_evaluator7t.cfg b/src/target/board/arm_evaluator7t.cfg
new file mode 100755
index 00000000..9cca2391
--- /dev/null
+++ b/src/target/board/arm_evaluator7t.cfg
@@ -0,0 +1,10 @@
+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+# Add (A) sdram configuration
+# Add (B) flash cfi programing configuration
+#
+
diff --git a/src/target/board/at91rm9200-dk.cfg b/src/target/board/at91rm9200-dk.cfg
new file mode 100755
index 00000000..900ee351
--- /dev/null
+++ b/src/target/board/at91rm9200-dk.cfg
@@ -0,0 +1,78 @@
+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash_bank cfi 0x10000000 0x00200000 2 2 0
+
+
+proc at91rm9200_dk_init { } {
+ # Try to run at 1khz... Yea, that slow!
+ # Chip is really running @ 32khz
+ jtag_khz 8
+
+ mww 0xfffffc64 0xffffffff
+ ## disable all clocks but system clock
+ mww 0xfffffc04 0xfffffffe
+ ## disable all clocks to pioa and piob
+ mww 0xfffffc14 0xffffffc3
+ ## master clock = slow cpu = slow
+ ## (means the CPU is running at 32khz!)
+ mww 0xfffffc30 0
+ ## main osc enable
+ mww 0xfffffc20 0x0000ff01
+ ## program pllA
+ mww 0xfffffc28 0x20263e04
+ ## program pllB
+ mww 0xfffffc2c 0x10483e0e
+ ## let pll settle... sleep 100msec
+ sleep 100
+ ## switch to fast clock
+ mww 0xfffffc30 0x202
+ ## Sleep some - (go read)
+ sleep 100
+
+ #========================================
+ # CPU now runs at 180mhz
+ # SYS runs at 60mhz.
+ jtag_khz 40000
+ #========================================
+
+
+ ## set memc for all memories
+ mww 0xffffff60 0x02
+ ## program smc controller
+ mww 0xffffff70 0x3284
+ ## init sdram
+ mww 0xffffff98 0x7fffffd0
+ ## all banks precharge
+ mww 0xffffff80 0x02
+ ## touch sdram chip to make it work
+ mww 0x20000000 0
+ ## sdram controller mode register
+ mww 0xffffff90 0x04
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ ## sdram controller mode register
+ ## Refresh, etc....
+ mww 0xffffff90 0x03
+ mww 0x20000080 0
+ mww 0xffffff94 0x1f4
+ mww 0x20000080 0
+ mww 0xffffff90 0x10
+ mww 0x20000000 0
+ mww 0xffffff00 0x01
+
+}
diff --git a/src/target/target/eir-sam7se512.cfg b/src/target/board/eir.cfg
index bf53be1f..08765658 100644..100755
--- a/src/target/target/eir-sam7se512.cfg
+++ b/src/target/board/eir.cfg
@@ -1,14 +1,9 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+source [find target/sam7se512.cfg]
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-
-
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# WDT_MR, disable watchdog
mww 0xFFFFFD44 0x00008000
@@ -97,10 +92,3 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
mww 0xfffffd08 0xa5000001
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank at91sam7 0 0 0 0 0
-
-# For more information about the configuration files, take a
-# look at the "Open On-Chip Debugger (openocd)" documentation.
diff --git a/src/target/target/hammer.cfg b/src/target/board/hammer.cfg
index 441f7abf..f9d116b6 100644..100755
--- a/src/target/target/hammer.cfg
+++ b/src/target/board/hammer.cfg
@@ -1,17 +1,9 @@
# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
# http://www.tincantools.com
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
+source [target/samsung_s3c2410.cfg]
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-
-target create target0 arm920t -endian little -chain-position 0 -variant arm920t
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# Reset Script for the TinCanTools S3C2410 Based Hammer Module
# http://www.tincantools.com
#
@@ -38,9 +30,6 @@ target create target0 arm920t -endian little -chain-position 0 -variant arm920t
flash probe 0
}
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
diff --git a/src/target/board/iar_str912_sk.cfg b/src/target/board/iar_str912_sk.cfg
new file mode 100755
index 00000000..ba060a04
--- /dev/null
+++ b/src/target/board/iar_str912_sk.cfg
@@ -0,0 +1,3 @@
+# The IAR str912-sk evaluation kick start board has an str912
+
+source [find target/str912.cfg] \ No newline at end of file
diff --git a/src/target/board/logicpd_imx27.cfg b/src/target/board/logicpd_imx27.cfg
new file mode 100755
index 00000000..b068f1a1
--- /dev/null
+++ b/src/target/board/logicpd_imx27.cfg
@@ -0,0 +1,12 @@
+# The LogicPD Eval IMX27 eval board has a single IMX27 chip
+source [find target/imx27.cfg]
+
+# The Logic PD board has a NOR flash on CS0
+flash_bank cfi 0xc0000000 0x00200000 2 2 0
+
+#
+# FIX ME, Add support to
+#
+# (A) hard reset the board.
+# (B) Initialize the SDRAM on the board
+#
diff --git a/src/target/board/olimex_sam7_ex256.cfg b/src/target/board/olimex_sam7_ex256.cfg
new file mode 100755
index 00000000..5f83629d
--- /dev/null
+++ b/src/target/board/olimex_sam7_ex256.cfg
@@ -0,0 +1,4 @@
+# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
+
+source [find target/sam7x256.cfg]
+
diff --git a/src/target/board/stm3210e_eval.cfg b/src/target/board/stm3210e_eval.cfg
new file mode 100755
index 00000000..ab2f64f0
--- /dev/null
+++ b/src/target/board/stm3210e_eval.cfg
@@ -0,0 +1,3 @@
+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+source [find target/stm32.cfg]
diff --git a/src/target/board/stm32f10x_128k_eval.cfg b/src/target/board/stm32f10x_128k_eval.cfg
new file mode 100755
index 00000000..6835ece3
--- /dev/null
+++ b/src/target/board/stm32f10x_128k_eval.cfg
@@ -0,0 +1,6 @@
+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+# My test board has a "Rev1" tap id.
+set BSTAPID 0x16410041
+source [find target/stm32.cfg]
+
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 5816981c..7125e5af 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1510,13 +1510,13 @@ int cortex_m3_handle_target_request(void *priv)
return ERROR_OK;
}
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant)
{
armv7m_common_t *armv7m;
armv7m = &cortex_m3->armv7m;
/* prepare JTAG information for the new target */
- cortex_m3->jtag_info.chain_pos = chain_pos;
+ cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
cortex_m3->swjdp_info.dp_select_value = -1;
@@ -1561,7 +1561,7 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
{
cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
- cortex_m3_init_arch_info(target, cortex_m3, target->chain_position, target->variant);
+ cortex_m3_init_arch_info(target, cortex_m3, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 56a74901..4b2c235c 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -189,6 +189,6 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant);
+extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant);
#endif /* CORTEX_M3_H */
diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c
index 4363dfdd..02cbe004 100644
--- a/src/target/cortex_swjdp.c
+++ b/src/target/cortex_swjdp.c
@@ -24,8 +24,8 @@
* *
* CoreSight (Light?) SerialWireJtagDebugPort *
* *
- * CoreSightâ„¢ DAP-Lite TRM, ARM DDI 0316A *
- * Cortex-M3â„¢ TRM, ARM DDI 0337C *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
* *
***************************************************************************/
#ifdef HAVE_CONFIG_H
@@ -67,7 +67,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
jtag_add_end_state(TAP_RTI);
arm_jtag_set_instr(jtag_info, instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
@@ -78,7 +78,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = outvalue;
fields[1].out_mask = NULL;
@@ -103,7 +103,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
jtag_add_end_state(TAP_RTI);
arm_jtag_set_instr(jtag_info, instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
@@ -114,7 +114,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
buf_set_u32(out_value_buf, 0, 32, outvalue);
fields[1].out_value = out_value_buf;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 19021cab..8a1b3987 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -251,7 +251,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
- fields[0].device = ice_reg->jtag_info->chain_pos;
+ fields[0].tap = ice_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
@@ -261,7 +261,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = ice_reg->jtag_info->chain_pos;
+ fields[1].tap = ice_reg->jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
@@ -272,7 +272,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = ice_reg->jtag_info->chain_pos;
+ fields[2].tap = ice_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -313,7 +313,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -323,7 +323,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
@@ -334,7 +334,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -406,7 +406,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value)
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
u8 reg_addr = ice_reg->addr & 0x1f;
- embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
+ embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
}
@@ -430,7 +430,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
fields[0].out_mask = NULL;
@@ -440,7 +440,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
@@ -451,7 +451,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 1);
@@ -499,7 +499,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -509,7 +509,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
@@ -520,7 +520,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -550,12 +550,12 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
}
/* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
+void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
{
int i;
for (i = 0; i < count; i++)
{
- embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
buffer += 4;
}
}
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index 92aee2b3..9e7f47ca 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -112,7 +112,7 @@ extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
* embeddedice_write_reg
*/
static const int embeddedice_num_bits[]={32,5,1};
-static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr, u32 value)
+static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, u32 value)
{
u32 values[3];
@@ -120,14 +120,14 @@ static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr,
values[1]=reg_addr;
values[2]=1;
- jtag_add_dr_out(chain_pos,
+ jtag_add_dr_out( tap,
3,
embeddedice_num_bits,
values,
-1);
}
-void embeddedice_write_dcc(int chain_pos, int reg_addr, u8 *buffer, int little, int count);
+void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
#endif /* EMBEDDED_ICE_H */
diff --git a/src/target/etb.c b/src/target/etb.c
index 05d970d5..c536773d 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -62,16 +62,17 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
int etb_set_instr(etb_t *etb, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(etb->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+ tap = etb->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = etb->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
@@ -95,7 +96,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
{
scan_field_t field;
- field.device = etb->chain_pos;
+ field.tap = etb->tap;
field.num_bits = 5;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
@@ -187,7 +188,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
- fields[0].device = etb->chain_pos;
+ fields[0].tap = etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
@@ -197,7 +198,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb->chain_pos;
+ fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, 4);
@@ -208,7 +209,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb->chain_pos;
+ fields[2].tap = etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -258,7 +259,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
@@ -268,7 +269,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -279,7 +280,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -354,7 +355,7 @@ int etb_write_reg(reg_t *reg, u32 value)
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
@@ -365,7 +366,7 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -376,7 +377,7 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);
@@ -415,7 +416,7 @@ int etb_register_commands(struct command_context_s *cmd_ctx)
int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target;
- jtag_device_t *jtag_device;
+ jtag_tap_t *tap;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
@@ -438,20 +439,20 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
return ERROR_FAIL;
}
- jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
-
- if (!jtag_device)
- {
+ tap = jtag_TapByString( args[1] );
+ if( tap == NULL ){
+ command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
return ERROR_FAIL;
}
+
if (arm7_9->etm_ctx)
{
etb_t *etb = malloc(sizeof(etb_t));
arm7_9->etm_ctx->capture_driver_priv = etb;
- etb->chain_pos = strtoul(args[1], NULL, 0);
+ etb->tap = tap;
etb->cur_scan_chain = -1;
etb->reg_cache = NULL;
etb->ram_width = 0;
diff --git a/src/target/etb.h b/src/target/etb.h
index e3dcb1d7..260a0220 100644
--- a/src/target/etb.h
+++ b/src/target/etb.h
@@ -45,7 +45,7 @@ enum
typedef struct etb_s
{
etm_context_t *etm_ctx;
- int chain_pos;
+ jtag_tap_t *tap;
int cur_scan_chain;
reg_cache_t *reg_cache;
diff --git a/src/target/etm.c b/src/target/etm.c
index c3750557..e2846ad0 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -339,7 +339,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
- fields[0].device = etm_reg->jtag_info->chain_pos;
+ fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
@@ -349,7 +349,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etm_reg->jtag_info->chain_pos;
+ fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -360,7 +360,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etm_reg->jtag_info->chain_pos;
+ fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -430,7 +430,7 @@ int etm_write_reg(reg_t *reg, u32 value)
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
- fields[0].device = etm_reg->jtag_info->chain_pos;
+ fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
@@ -441,7 +441,7 @@ int etm_write_reg(reg_t *reg, u32 value)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etm_reg->jtag_info->chain_pos;
+ fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -452,7 +452,7 @@ int etm_write_reg(reg_t *reg, u32 value)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etm_reg->jtag_info->chain_pos;
+ fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index e199a081..407ac52b 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -132,7 +132,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].out_mask = NULL;
@@ -142,7 +142,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].out_mask = NULL;
@@ -152,7 +152,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].out_mask = NULL;
@@ -645,7 +645,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
arm7_9_common_t *arm7_9;
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
- arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
armv4_5 = target->arch_info;
arm7_9 = armv4_5->arch_info;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index bcf96147..8a260a28 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -320,7 +320,7 @@ reg_cache_t *mips32_build_reg_cache(target_t *target)
return cache;
}
-int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant)
+int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant)
{
target->arch_info = mips32;
mips32->common_magic = MIPS32_COMMON_MAGIC;
@@ -329,7 +329,7 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_p
mips32->bp_scanned = 0;
mips32->data_break_list = NULL;
- mips32->ejtag_info.chain_pos = chain_pos;
+ mips32->ejtag_info.tap = tap;
mips32->read_core_reg = mips32_read_core_reg;
mips32->write_core_reg = mips32_write_core_reg;
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 8a484487..02f88b0a 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -119,7 +119,7 @@ typedef struct mips32_core_reg_s
#define MIPS32_DRET 0x4200001F
extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant);
extern int mips32_restore_context(target_t *target);
extern int mips32_save_context(target_t *target);
extern reg_cache_t *mips32_build_reg_cache(target_t *target);
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 43250046..729b1a23 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -34,17 +34,19 @@
int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler)
{
- jtag_device_t *device = jtag_get_device(ejtag_info->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+
+ tap = ejtag_info->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
u8 t[4];
- field.device = ejtag_info->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
@@ -67,7 +69,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
- field.device = ejtag_info->chain_pos;
+ field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
@@ -94,7 +96,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
- field.device = ejtag_info->chain_pos;
+ field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
@@ -115,16 +117,16 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t
int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
{
- jtag_device_t *device;
- device = jtag_get_device(ejtag_info->chain_pos);
+ jtag_tap_t *tap;
+ tap = ejtag_info->tap;
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
scan_field_t field;
u8 t[4];
int retval;
- field.device = ejtag_info->chain_pos;
+ field.tap = tap;
field.num_bits = 32;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, *data);
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 4125dfc4..74ba2071 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -100,7 +100,7 @@
typedef struct mips_ejtag_s
{
- int chain_pos;
+ jtag_tap_t *tap;
u32 impcode;
/*int use_dma;*/
u32 ejtag_ctrl;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d9b823e6..e1fd8dc8 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -735,7 +735,7 @@ int mips_m4k_quit(void)
return ERROR_OK;
}
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
@@ -751,7 +751,7 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int c
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
/* initialize mips4k specific info */
- mips32_init_arch_info(target, mips32, chain_pos, variant);
+ mips32_init_arch_info(target, mips32, tap, variant);
mips32->arch_info = mips_m4k;
return ERROR_OK;
@@ -761,7 +761,7 @@ int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
- mips_m4k_init_arch_info(target, mips_m4k, target->chain_position, target->variant);
+ mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
return ERROR_OK;
}
diff --git a/src/target/target.c b/src/target/target.c
index 96a414da..560ee78c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -198,7 +198,7 @@ const Jim_Nvp nvp_target_event[] = {
{ .value = TARGET_EVENT_EXAMINE_START, .name = "examine-start" },
- { .value = TARGET_EVENT_EXAMINE_START, .name = "examine-end" },
+ { .value = TARGET_EVENT_EXAMINE_END, .name = "examine-end" },
{ .value = TARGET_EVENT_DEBUG_HALTED, .name = "debug-halted" },
@@ -1387,18 +1387,19 @@ int handle_targets_command(struct command_context_s *cmd_ctx, char *cmd, char **
}
DumpTargets:
- target = all_targets;
- command_print(cmd_ctx, " CmdName Type Endian ChainPos State ");
- command_print(cmd_ctx, "-- ---------- ---------- ---------- -------- ----------");
+ target = all_targets;
+ command_print(cmd_ctx, " CmdName Type Endian AbsChainPos Name State ");
+ command_print(cmd_ctx, "-- ---------- ---------- ---------- ----------- ------------- ----------");
while (target)
{
/* XX: abcdefghij abcdefghij abcdefghij abcdefghij */
- command_print(cmd_ctx, "%2d: %-10s %-10s %-10s %8d %s",
+ command_print(cmd_ctx, "%2d: %-10s %-10s %-10s %10d %14s %s",
target->target_number,
target->cmd_name,
target->type->name,
Jim_Nvp_value2name_simple( nvp_target_endian, target->endianness )->name,
- target->chain_position,
+ target->tap->abs_chain_position,
+ target->tap->dotted_name,
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
target = target->next;
}
@@ -1417,7 +1418,7 @@ static int runPowerDropout;
static int runSrstAsserted;
static int runSrstDeasserted;
-static int sense_handler()
+static int sense_handler(void)
{
static int prevSrstAsserted = 0;
static int prevPowerdropout = 0;
@@ -3349,22 +3350,25 @@ target_configure( Jim_GetOptInfo *goi,
break;
case TCFG_CHAIN_POSITION:
if( goi->isconfigure ){
+ Jim_Obj *o;
+ jtag_tap_t *tap;
target_free_all_working_areas(target);
- e = Jim_GetOpt_Wide( goi, &w );
+ e = Jim_GetOpt_Obj( goi, &o );
if( e != JIM_OK ){
return e;
}
- if (jtag_get_device(w)==NULL)
+ tap = jtag_TapByJimObj( goi->interp, o );
+ if( tap == NULL ){
return JIM_ERR;
-
+ }
/* make this exactly 1 or 0 */
- target->chain_position = w;
+ target->tap = tap;
} else {
if( goi->argc != 0 ){
goto no_params;
}
}
- Jim_SetResult( interp, Jim_NewIntObj( goi->interp, target->chain_position ) );
+ Jim_SetResultString( interp, target->tap->dotted_name, -1 );
/* loop for more e*/
break;
}
diff --git a/src/target/target.h b/src/target/target.h
index c2ca2572..cbd3e2b2 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -245,7 +245,7 @@ typedef struct target_s
target_type_t *type; /* target type definition (name, access functions) */
const char *cmd_name; /* tcl Name of target */
int target_number; /* generaly, target index but may not be in order */
- int chain_position; /* where on the jtag chain is this */
+ jtag_tap_t *tap; /* where on the jtag chain is this */
const char *variant; /* what varient of this chip is it? */
target_event_action_t *event_action;
diff --git a/src/target/target/aduc702x.cfg b/src/target/target/aduc702x.cfg
index c9ef92cd..35f5ff32 100644
--- a/src/target/target/aduc702x.cfg
+++ b/src/target/target/aduc702x.cfg
@@ -1,6 +1,27 @@
## -*- tcl -*-
##
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
@@ -10,18 +31,13 @@ reset_config none
## JTAG scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
##
## Target configuration
##
-target create target0 arm7tdmi -endian little -chain-position 0
-
-## software initiated reset (if your SRST isn't wired)
-#proc target_0_reset {} { mwb 0x0ffff0230 04 }
-
-# use top 1k of SRAM for as temporary JTAG memory
-#[new_target_name] configure -work-area-virt 0 -work-area-phys 0x11C00 -work-area-size 0x400 -work-area-backup 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
## flash configuration
flash bank aduc702x 0x80000 0x10000 2 2 0
@@ -37,5 +53,5 @@ proc watchdog_service {} {
set watchdog_hdl [after 500 watchdog_service]
}
-[new_target_name] configure -event reset-halt-post { watchdog_service }
-[new_target_name] configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
+$_TARGETNAME configure -event reset-halt-post { watchdog_service }
+$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
diff --git a/src/target/target/at91eb40a.cfg b/src/target/target/at91eb40a.cfg
index b2b91dbc..c552dc5b 100644
--- a/src/target/target/at91eb40a.cfg
+++ b/src/target/target/at91eb40a.cfg
@@ -1,5 +1,25 @@
#Script for AT91EB40a
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
#Atmel ties SRST & TRST together, at which point it makes
#no sense to use TRST, but use TMS instead.
#
@@ -11,10 +31,11 @@ reset_config srst_only srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
#target configuration
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# speed up memory downloads
arm7_9 fast_memory_access enable
@@ -25,9 +46,9 @@ flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
# required for usable performance. Used for lots of
# other things than flash programming.
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
puts "Running reset init script for AT91EB40A"
# Reset script for AT91EB40a
reg cpsr 0x000000D3
diff --git a/src/target/target/at91r40008.cfg b/src/target/target/at91r40008.cfg
index 0d323af5..48317c86 100644
--- a/src/target/target/at91r40008.cfg
+++ b/src/target/target/at91r40008.cfg
@@ -1,3 +1,24 @@
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at9r40008
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
@@ -6,12 +27,12 @@ reset_config srst_only srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGENAME -variant arm7tdmi
-[new_target_name] configure -event gdb-flash-erase-start {
+$_TARGETNAME configure -event gdb-flash-erase-start {
wait_halt
sleep 10
poll
@@ -21,7 +42,7 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
mww 0xffe00020 0x00000001
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
flash bank cfi 0x10000000 0x400000 2 2 0
diff --git a/src/target/target/at91rm9200.cfg b/src/target/target/at91rm9200.cfg
new file mode 100755
index 00000000..58c7318e
--- /dev/null
+++ b/src/target/target/at91rm9200.cfg
@@ -0,0 +1,51 @@
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91rm9200
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x05b0203f
+}
+
+# Never allow the following!
+if { $_CPUTAPID == 0x15b0203f } {
+ puts "-------------------------------------------------------"
+ puts "- ERROR: -"
+ puts "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -"
+ puts "- ERROR: The chip/board has a JTAG select pin/jumper -"
+ puts "- ERROR: -"
+ puts "- ERROR: In one position (0x05b0203f) it selects the -"
+ puts "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
+ puts "- ERROR: it selects boundry-scan not the ARM -"
+ puts "- ERROR: -"
+ puts "-------------------------------------------------------"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+# AT91RM9200 has a 16K block of sram @ 0x0020.0000
+$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
+
+
+
+
+
diff --git a/src/target/target/at91sam9260.cfg b/src/target/target/at91sam9260.cfg
index b3e1d215..d7c8833c 100644
--- a/src/target/target/at91sam9260.cfg
+++ b/src/target/target/at91sam9260.cfg
@@ -2,21 +2,16 @@
# Target: Atmel AT91SAM9260
######################################
-reset_config trst_and_srst
-
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
+# We add to the minimal configuration.
+source [find target/at91sam9260minimal.cfg]
######################
# Target configuration
######################
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
-
-[new_target_name] configure -event reset-init {
+$_TARGET_NAME configure -event reset-init {
+ # at reset chip runs at 32khz
+ jtag_khz 8
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
@@ -31,7 +26,8 @@ target create target0 arm926ejs -endian little -chain-position 0 -variant arm926
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
sleep 10 # wait 10 ms
- jtag_speed 0 # Increase JTAG Speed to 6 MHz
+ # Now run at anything fast... ie: 10mhz!
+ jtag_khz 10000 # Increase JTAG Speed to 6 MHz
arm7_9 dcc_downloads enable # Enable faster DCC downloads
mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
@@ -76,7 +72,6 @@ target create target0 arm926ejs -endian little -chain-position 0 -variant arm926
mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
#####################
# Flash configuration
diff --git a/src/target/target/at91sam9260minimal.cfg b/src/target/target/at91sam9260minimal.cfg
index ca6edd9b..93114d80 100644
--- a/src/target/target/at91sam9260minimal.cfg
+++ b/src/target/target/at91sam9260minimal.cfg
@@ -2,10 +2,29 @@
# Target: Atmel AT91SAM9260
######################################
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
reset_config trst_and_srst
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 200
jtag_ntrst_delay 200
@@ -14,6 +33,10 @@ jtag_ntrst_delay 200
# Target configuration
######################
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGET_NAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
diff --git a/src/target/target/epc9301.cfg b/src/target/target/epc9301.cfg
index 31ff3320..6dbb91b3 100644
--- a/src/target/target/epc9301.cfg
+++ b/src/target/target/epc9301.cfg
@@ -1,9 +1,30 @@
# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
-jtag_device 4 0x1 0xf 0xe
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ep9301
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-target create target0 arm920t -endian little -chain-position 0 -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
diff --git a/src/target/target/imote2.cfg b/src/target/target/imote2.cfg
index a02a8d3c..beb539b6 100644
--- a/src/target/target/imote2.cfg
+++ b/src/target/target/imote2.cfg
@@ -1,5 +1,24 @@
# iMote2
#
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imote2
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
#
# Marvell/Intel PXA270 Script
@@ -9,15 +28,18 @@ jtag_nsrst_delay 800
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target xscale little 0 pxa27x
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -varient pxa27x
+$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
# maps to PXA internal RAM. If you are using a PXA255
# you must initialize SDRAM or leave this option off
-working_area 0 0x5c000000 0x10000 nobackup
+
#flash bank <driver> <base> <size> <chip_width> <bus_width>
# works for P30 flash
diff --git a/src/target/target/imx27.cfg b/src/target/target/imx27.cfg
index c6fdf41c..240a8498 100644
--- a/src/target/target/imx27.cfg
+++ b/src/target/target/imx27.cfg
@@ -1,12 +1,42 @@
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-# There are 2 taps on the chip:
-# The ETM
-jtag_device 4 0x1 0xf 0xe
-# The ARM926EJS
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imx27
+}
-# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
-target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Note above there are 2 taps
+
+# The bs tap
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable
diff --git a/src/target/target/imx31.cfg b/src/target/target/imx31.cfg
index 34b35d8b..83a4abc4 100644
--- a/src/target/target/imx31.cfg
+++ b/src/target/target/imx31.cfg
@@ -2,18 +2,64 @@
#
# NB! Does not work yet. Work in progress
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-# 4 devices otherwise openocd complains, the last one returns 0x0 for all bytes
-jtag_device 4 0x1 0x0 0xe
-jtag_device 5 0x1 0x1f 0x1e
-#jtag_device 4 0x0 0x0 0xe
-# The device below does not have an IDCODE, so lsb is 1
-jtag_device 4 0x0 0x0 0xf
-jtag_device 5 0x1 0x0 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#========================================
+# The "system jtag controller"
+# IMX31 reference manual, page 6-28 - figure 6-14
+if { [info exists SJCTAPID ] } {
+ set _SJCTAPID $SJCTAPID
+} else {
+ set _SJCTAPID 0xffffffff
+}
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 00 irmask 0x0 -expected-id $_SJCTAPID
+
+# The "SDMA" - <S>mart <DMA> controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+# SIGNAL NAME:
+# SJC_MOD - controls multiplexer - disables ARM1136
+# SDMA_BYPASS - disables SDMA -
+#
+if { [info exists SDMATAPID ] } {
+ set _SDMATAPID $SDMATAPID
+} else {
+ set _SDMATAPID 0xffffffff
+}
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SJCTAPID
+
+# The ARM11 core tap
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e irmask 0x1f -expected-id $_SJCTAPID
+
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm11 -endian little -chain-position 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/src/target/target/ipx42x.cfg b/src/target/target/ipx42x.cfg
index f2185f80..961a5c93 100644
--- a/src/target/target/ipx42x.cfg
+++ b/src/target/target/ipx42x.cfg
@@ -1,9 +1,32 @@
#xscale ixp42x CPU
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ipx42x
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can?t set TRST/SRST separately
reset_config srst_only srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target create target0 xscale -endian big -chain-position 0 -variant IXP42x
+
+jtag newtap $_CPUNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ipxP42x
diff --git a/src/target/target/is5114.cfg b/src/target/target/is5114.cfg
index 56c8685c..95736c29 100644
--- a/src/target/target/is5114.cfg
+++ b/src/target/target/is5114.cfg
@@ -1,20 +1,49 @@
# script for Insilica IS-5114
+# AKA: Atmel AT76C114 - an ARM946 chip
+# ATMEL sold his product line to Insilica...
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME is5114
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
# jtag speed. We need to stick to 16kHz until we've finished reset.
jtag_rclk 16
reset_config trst_and_srst
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+# Do not specify a tap id here...
+#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
+#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe
+# This is the "arm946" chip.
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
+#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e
+jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
+
#arm946e-s and
-target arm966e little 1 arm966e
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm966e
-[new_target_name] configure -event reset-start { jtag_rclk 16 }
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
jtag_rclk 3000
}
-working_area 0 0x50000000 16384 nobackup
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/src/target/target/lm3s3748.cfg b/src/target/target/lm3s3748.cfg
index bb35181c..f3ed12e2 100644
--- a/src/target/target/lm3s3748.cfg
+++ b/src/target/target/lm3s3748.cfg
@@ -3,6 +3,26 @@
# NB! work in progress! Duplicated from lm3s811.cfg, but does
# it need modification??
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s3748
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# RCLK
jtag_khz 500
@@ -13,16 +33,17 @@ jtag_ntrst_delay 100
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 8k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lm3s6965.cfg b/src/target/target/lm3s6965.cfg
index e1d38227..8fdc9c89 100644
--- a/src/target/target/lm3s6965.cfg
+++ b/src/target/target/lm3s6965.cfg
@@ -1,5 +1,26 @@
# script for luminary lm3s6965
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s6965
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 500
@@ -10,16 +31,17 @@ jtag_ntrst_delay 100
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 4k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lm3s811.cfg b/src/target/target/lm3s811.cfg
index 90543334..e6a7d05f 100644
--- a/src/target/target/lm3s811.cfg
+++ b/src/target/target/lm3s811.cfg
@@ -1,5 +1,25 @@
# Script for luminary lm3s811
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s811
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 500
@@ -10,16 +30,16 @@ jtag_ntrst_delay 100
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 8k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
diff --git a/src/target/target/lpc2129.cfg b/src/target/target/lpc2129.cfg
index d94f8228..a93d4992 100644
--- a/src/target/target/lpc2129.cfg
+++ b/src/target/target/lpc2129.cfg
@@ -1,12 +1,36 @@
#LPC-2129 CPU
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2129
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
diff --git a/src/target/target/lpc2148.cfg b/src/target/target/lpc2148.cfg
index 24ec05ed..7b701ab6 100644
--- a/src/target/target/lpc2148.cfg
+++ b/src/target/target/lpc2148.cfg
@@ -1,3 +1,23 @@
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2148
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#delays on reset lines
jtag_nsrst_delay 200
jtag_ntrst_delay 200
@@ -11,10 +31,12 @@ jtag_ntrst_delay 200
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -event reset-init {
# Force target into ARM state
soft_reset_halt
#do not remap 0x0000-0x0020 to anything but the flash
@@ -22,7 +44,6 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
diff --git a/src/target/target/lpc2148_2mhz.cfg b/src/target/target/lpc2148_2mhz.cfg
index 7e43f33d..0ed87ca4 100644
--- a/src/target/target/lpc2148_2mhz.cfg
+++ b/src/target/target/lpc2148_2mhz.cfg
@@ -1,3 +1,4 @@
# 2MHz
jtag_khz 2000
script target/lpc2148.cfg
+
diff --git a/src/target/target/lpc2148_rclk.cfg b/src/target/target/lpc2148_rclk.cfg
index 4a3fb3ef..dd7330f7 100644
--- a/src/target/target/lpc2148_rclk.cfg
+++ b/src/target/target/lpc2148_rclk.cfg
@@ -1,3 +1,4 @@
# RCLK
jtag_khz 0
script target/lpc2148.cfg
+
diff --git a/src/target/target/lpc2294.cfg b/src/target/target/lpc2294.cfg
index bd282eba..01ac5854 100644
--- a/src/target/target/lpc2294.cfg
+++ b/src/target/target/lpc2294.cfg
@@ -1,12 +1,31 @@
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2294
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
diff --git a/src/target/target/netx500.cfg b/src/target/target/netx500.cfg
index e7b5e51a..c639017b 100644
--- a/src/target/target/netx500.cfg
+++ b/src/target/target/netx500.cfg
@@ -1,10 +1,34 @@
#Hilscher netX 500 CPU
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME netx500
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
diff --git a/src/target/target/nslu2.cfg b/src/target/target/nslu2.cfg
index c545e01f..2ad71174 100644
--- a/src/target/target/nslu2.cfg
+++ b/src/target/target/nslu2.cfg
@@ -1,22 +1,8 @@
-# use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
-
-# jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-
-# target configuration
-target create target0 xscale -endian big -chain-position 0 -variant ixp42x
-
-
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-#flash bank cfi 0x50000000 0x1000000 2 4 0
-
-
+# This is for the LinkSys (CYSCO) LSLU2 board
+# It is an Intel XSCALE IPX420 CPU.
+source [find target/ipx42x.cfg]
+# The _TARGETNAME is set by the above.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/src/target/target/omap5912.cfg b/src/target/target/omap5912.cfg
index a18f8b71..5277593f 100644
--- a/src/target/target/omap5912.cfg
+++ b/src/target/target/omap5912.cfg
@@ -1,17 +1,38 @@
#TI OMAP5912 dual core processor - http://www.ti.com
#on a OMAP5912 OSK board http://www.spectrumdigital.com.
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME omap5912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 38 0x0 0x0 0x0
-jtag_device 4 0x1 0x0 0xe
-jtag_device 8 0x0 0x0 0x0
+jtag newtap $_CHIPNAME unknown1 -irlen 38 -ircapture 0x0 -irmask 0x0
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown2 irlen 8 -ircapture 0x0 -irmask 0x0
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-target create target0 arm926ejs -endian little -chain-position 1 -variant arm926ejs
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
#
# halt target
#
@@ -36,7 +57,7 @@ target create target0 arm926ejs -endian little -chain-position 1 -variant arm926
}
# omap5912 lcd frame buffer as working area
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
+$_TARGENAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank cfi 0x00000000 0x1000000 2 2 0
diff --git a/src/target/target/pic32mx.cfg b/src/target/target/pic32mx.cfg
index 1d23ff2a..2ade5550 100644
--- a/src/target/target/pic32mx.cfg
+++ b/src/target/target/pic32mx.cfg
@@ -1,3 +1,23 @@
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pic32mx
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
jtag_nsrst_delay 100
jtag_ntrst_delay 100
@@ -6,13 +26,13 @@ reset_config srst_only
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 5 0x1 0x1 0x1e
+jtag newtap $_CPUNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
-target create target0 mips_m4k -endian little -chain-position 0
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
-#flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg
index de491f6d..c79ea4c9 100644
--- a/src/target/target/pxa255.cfg
+++ b/src/target/target/pxa255.cfg
@@ -1,9 +1,29 @@
-jtag_device 5 0x1 0x1f 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
-
-target create target0 xscale -endian little -chain-position 0 -variant pxa255
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
+$_TARGETNAME configure -event reset-init {
xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
#
# setup GPIO
diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg
index 49ebd2b3..37ff1a8b 100644
--- a/src/target/target/pxa255_sst.cfg
+++ b/src/target/target/pxa255_sst.cfg
@@ -7,8 +7,9 @@
# RAM at 0x4000000
# Flash at 0x00000000
#
-script target/pxa255.cfg
+source [find target/pxa255.cfg]
+# Target name is set by above
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg
index dcf5fa2b..c745feb1 100644
--- a/src/target/target/pxa270.cfg
+++ b/src/target/target/pxa270.cfg
@@ -1,19 +1,43 @@
#Marvell/Intel PXA270 Script
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pxa270
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
# set jtag_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
jtag_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target create target0 xscale -endian little -chain-position 0 -variant pxa27x
+
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_TARGETNAME -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
# maps to PXA internal RAM. If you are using a PXA255
# you must initialize SDRAM or leave this option off
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
# works for P30 flash
diff --git a/src/target/target/s3c2440.cfg b/src/target/target/s3c2440.cfg
index 6227107b..eba1a816 100644
--- a/src/target/target/s3c2440.cfg
+++ b/src/target/target/s3c2440.cfg
@@ -2,14 +2,36 @@
# Tested on a S3C2440 Evaluation board
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xFFFFFFFF
+}
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-target create target0 arm920t -endian little -chain-position 0 -variant arm920t
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
reset_config trst_and_srst
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/src/target/target/sam7se512.cfg b/src/target/target/sam7se512.cfg
new file mode 100755
index 00000000..a3104058
--- /dev/null
+++ b/src/target/target/sam7se512.cfg
@@ -0,0 +1,38 @@
+
+# ATMEL sam7se512
+# Example: the "Elektor Internet Radio" - EIR
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME sam7se512
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+flash bank at91sam7 0 0 0 0 0
+
diff --git a/src/target/target/sam7x256.cfg b/src/target/target/sam7x256.cfg
index d7e11ff3..8e8cc97a 100644
--- a/src/target/target/sam7x256.cfg
+++ b/src/target/target/sam7x256.cfg
@@ -1,12 +1,30 @@
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME sam7x256
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-init {
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init {
# disable watchdog
mww 0xfffffd44 0x00008000
# enable user reset
@@ -25,7 +43,7 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
sleep 100
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank at91sam7 0 0 0 0 0
diff --git a/src/target/target/samsung_s2c2410.cfg b/src/target/target/samsung_s2c2410.cfg
new file mode 100755
index 00000000..3c0768bc
--- /dev/null
+++ b/src/target/target/samsung_s2c2410.cfg
@@ -0,0 +1,35 @@
+# Found on the 'TinCanTools' Hammer board.
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that cannot set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
diff --git a/src/target/target/samsung_s3c4510.cfg b/src/target/target/samsung_s3c4510.cfg
new file mode 100755
index 00000000..65e7fd84
--- /dev/null
+++ b/src/target/target/samsung_s3c4510.cfg
@@ -0,0 +1,25 @@
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c4510
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
+# This appears to be a "Version 1" arm7tdmi.
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
diff --git a/src/target/target/samsung_s3c6410.cfg b/src/target/target/samsung_s3c6410.cfg
new file mode 100755
index 00000000..34078df9
--- /dev/null
+++ b/src/target/target/samsung_s3c6410.cfg
@@ -0,0 +1,49 @@
+# -*- tcl -*-
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor : ARM1176
+# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c6410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # force an error till we get a good number
+ set _BSTAPID 0xffffffff
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#jtag scan chain
+
+# I think the "unknown" is the boundry scan tap
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm1176
+
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+#reset configuration
+reset_config trst_and_srst
diff --git a/src/target/target/sharp_lh79532.cfg b/src/target/target/sharp_lh79532.cfg
new file mode 100755
index 00000000..a239e3c5
--- /dev/null
+++ b/src/target/target/sharp_lh79532.cfg
@@ -0,0 +1,26 @@
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lh79532
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # sharp changed the number!
+ set _CPUTAPID 0x00002061
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
diff --git a/src/target/target/smdk6410.cfg b/src/target/target/smdk6410.cfg
index 0dd71742..6ce07cae 100644
--- a/src/target/target/smdk6410.cfg
+++ b/src/target/target/smdk6410.cfg
@@ -3,18 +3,6 @@
# Processor : ARM1176
# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1f 0xe
-
-#target create target0 arm11 -endian little -chain-position 0 -variant arm1176
-target arm11 little reset_halt 1
-
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
-
-#reset configuration
-reset_config trst_and_srst
+source [find target/samsung_s3c6410.cfg]
flash bank cfi 0x00000000 0x00100000 2 2 0 jedec_probe \ No newline at end of file
diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
index 1c80679e..c9581d49 100644
--- a/src/target/target/stm32.cfg
+++ b/src/target/target/stm32.cfg
@@ -1,5 +1,18 @@
# script for stm32
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
# jtag speed
jtag_khz 500
@@ -10,15 +23,35 @@ jtag_ntrst_delay 100
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-
-target create target0 cortex_m3 -endian little -chain-position 0
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.2
+ # Medium Density RevA
+ set _BSTAPID 0x06410041
+ # Rev B and Rev Z
+ set _BSTAPID 0x16410041
+ # High Density Devices, Rev A
+ set _BSTAPID 0x06414041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
diff --git a/src/target/target/stm32stick.cfg b/src/target/target/stm32stick.cfg
index 00964ab5..bb297dd7 100644
--- a/src/target/target/stm32stick.cfg
+++ b/src/target/target/stm32stick.cfg
@@ -1,5 +1,17 @@
# Hitex stm32 performance stick
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32_hitex
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
# set jtag speed
jtag_khz 500
@@ -10,16 +22,28 @@ jtag_ntrst_delay 100
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-jtag_device 4 0x1 0xf 0xe
+# The CPU
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+
+# The boundery scan register, leave the "expected-id" undefined.
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e
+
+# What is this? It must be some extra chip on the stm32stick...
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-target create target0 cortex_m3 -endian little -chain-position 0
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
+#
flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
diff --git a/src/target/target/str710.cfg b/src/target/target/str710.cfg
index b2e03f3d..de3b0b9e 100644
--- a/src/target/target/str710.cfg
+++ b/src/target/target/str710.cfg
@@ -1,23 +1,42 @@
#start slow, speed up after reset
jtag_khz 10
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str710
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 6000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
flash protect 1 0 1 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
diff --git a/src/target/target/str730.cfg b/src/target/target/str730.cfg
index 8c0f59c4..c0dfcdd1 100644
--- a/src/target/target/str730.cfg
+++ b/src/target/target/str730.cfg
@@ -1,29 +1,46 @@
#STR730 CPU
-
jtag_khz 3000
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str730
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 3000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
diff --git a/src/target/target/str750.cfg b/src/target/target/str750.cfg
index 6d0c47d3..806bbfa1 100644
--- a/src/target/target/str750.cfg
+++ b/src/target/target/str750.cfg
@@ -1,31 +1,50 @@
#STR750 CPU
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str750
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 10
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 3000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
flash protect 1 0 1 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
diff --git a/src/target/target/str910-eval.cfg b/src/target/target/str910-eval.cfg
index 276bb48a..44edeaa4 100644
--- a/src/target/target/str910-eval.cfg
+++ b/src/target/target/str910-eval.cfg
@@ -3,13 +3,44 @@
# Need reset scripts
reset_config trst_and_srst
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
-target arm966e little reset_halt 1 arm966e
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
-working_area 0 0x50000000 16384 nobackup
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ # Fixme with a correct number!
+ set _FLASHTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
flash bank str9xpec 0x00000000 0x00080000 0 0 0
diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
index 6f605b06..3b7d7ff1 100644
--- a/src/target/target/str912.cfg
+++ b/src/target/target/str912.cfg
@@ -1,29 +1,58 @@
# script for str9
-# jtag speed. We need to stick to 16kHz until we've finished reset.
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
-jtag_rclk 16
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+jtag_rclk 16
+
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID
-target create target0 arm966e -endian little -chain-position 1 -variant arm966e
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-[new_target_name] configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- jtag_rclk 3000
+ #jtag_rclk 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
@@ -33,7 +62,7 @@ target create target0 arm966e -endian little -chain-position 1 -variant arm966e
flash protect 0 0 7 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank str9x <base> <size> 0 0 <target#> <variant>
flash bank str9x 0x00000000 0x00080000 0 0 0
diff --git a/src/target/target/str9comstick.cfg b/src/target/target/str9comstick.cfg
index b9b5fc75..0696c121 100644
--- a/src/target/target/str9comstick.cfg
+++ b/src/target/target/str9comstick.cfg
@@ -5,15 +5,38 @@ jtag_khz 3000
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-#use combined on interfaces or targets that can’t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-target create target0 arm966e -endian little -chain-position 1 -variant arm966e
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str9x 0x00000000 0x00080000 0 0 0
diff --git a/src/target/target/test_reset_syntax_error.cfg b/src/target/target/test_reset_syntax_error.cfg
index b720ca9d..e573c1c0 100644
--- a/src/target/target/test_reset_syntax_error.cfg
+++ b/src/target/target/test_reset_syntax_error.cfg
@@ -4,12 +4,14 @@
# at91eb40a target
#jtag scan chain
-jtag_device 4 0x1 0xf 0xe
+set _CHIPNAME syntaxtest
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
#target configuration
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
syntax error
}
diff --git a/src/target/target/wi-9c.cfg b/src/target/target/wi-9c.cfg
index a966f54c..3606d0d5 100644
--- a/src/target/target/wi-9c.cfg
+++ b/src/target/target/wi-9c.cfg
@@ -1,15 +1,37 @@
+# FIXME: THIS IS A *BOARD* not a CHIP configuration.
######################################
# Target: DIGI ConnectCore Wi-9C
######################################
reset_config trst_and_srst
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN big
+}
+
+
# What's a good fallback frequency for this board if RCLK is
# not available??
jtag_rclk 1000
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xFFFFFFFF
+}
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap_device $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 200
jtag_ntrst_delay 0
@@ -19,8 +41,8 @@ jtag_ntrst_delay 0
# Target configuration
######################
-target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
-[new_target_name] configure -event reset-init {
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 # Enable the memory controller.
mww 0xA0700024 0x00000006 # Set the refresh counter 6
@@ -92,7 +114,7 @@ target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
reg cpsr 0xd3
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
#####################
# Flash configuration
diff --git a/src/target/target/xba_revA3.cfg b/src/target/target/xba_revA3.cfg
index 30d119a8..007cb9e1 100644
--- a/src/target/target/xba_revA3.cfg
+++ b/src/target/target/xba_revA3.cfg
@@ -1,16 +1,36 @@
#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xba_reva3
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # default to big endian
+ set _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
reset_config trst_and_srst separate
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-target create target0 xscale -endian big -chain-position 0 -variant ixp42x
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+$_TARGETNAME configure -event reset-init {
#############################################################################
# setup expansion bus CS, disable external wdt
#############################################################################
@@ -55,7 +75,7 @@ target create target0 xscale -endian big -chain-position 0 -variant ixp42x
flash probe 0
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
flash bank cfi 0x50000000 0x400000 2 2 0
diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg
index 2fb2db32..56bf0c46 100644
--- a/src/target/target/zy1000.cfg
+++ b/src/target/target/zy1000.cfg
@@ -8,19 +8,39 @@
#SRST reset, which means that the CPU will run a number
#of cycles before it can be halted(as much as milliseconds).
reset_config srst_only srst_pulls_trst
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME zy1000
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # sharp changed the number!
+ set _CPUTAPID 0x3f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# at CPU CLK <32kHz this must be disabled
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# Set up chip selects & timings
mww 0xFFE00000 0x0100273D
mww 0xFFE00004 0x08002125
@@ -44,7 +64,7 @@ flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
# required for usable performance. Used for lots of
# other things than flash programming.
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
jtag_khz 16000
diff --git a/src/target/xscale.c b/src/target/xscale.c
index ce40c685..36d41fd5 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -212,23 +212,22 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc
return ERROR_OK;
}
-int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
+int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
field.in_value = NULL;
- jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
+ jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
jtag_add_ir_scan(1, &field, -1);
@@ -254,19 +253,19 @@ int xscale_read_dcsr(target_t *target)
u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_PD);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -276,7 +275,7 @@ int xscale_read_dcsr(target_t *target)
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
@@ -337,14 +336,14 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
path[1] = TAP_CD;
path[2] = TAP_SD;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -356,7 +355,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
@@ -364,7 +363,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
/* repeat until all words have been collected */
@@ -445,7 +444,7 @@ int xscale_read_tx(target_t *target, int consume)
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
path[0] = TAP_SDS;
path[1] = TAP_CD;
@@ -458,14 +457,14 @@ int xscale_read_tx(target_t *target, int consume)
noconsume_path[4] = TAP_E2D;
noconsume_path[5] = TAP_SD;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
@@ -477,7 +476,7 @@ int xscale_read_tx(target_t *target, int consume)
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
@@ -554,16 +553,16 @@ int xscale_write_rx(target_t *target)
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[1].out_mask = NULL;
@@ -575,7 +574,7 @@ int xscale_write_rx(target_t *target)
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
@@ -643,7 +642,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
bits[0]=3;
t[0]=0;
@@ -680,7 +679,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
LOG_ERROR("BUG: size neither 4, 2 nor 1");
exit(-1);
}
- jtag_add_dr_out(xscale->jtag_info.chain_pos,
+ jtag_add_dr_out(xscale->jtag_info.tap,
3,
bits,
t,
@@ -728,19 +727,19 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
xscale->external_debug_break = ext_dbg_brk;
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].out_mask = NULL;
@@ -752,7 +751,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
@@ -798,7 +797,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
if (mini)
@@ -811,7 +810,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].out_mask = NULL;
@@ -821,7 +820,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].out_mask = NULL;
@@ -861,7 +860,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
scan_field_t fields[2];
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
@@ -869,7 +868,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].out_mask = NULL;
@@ -879,7 +878,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].out_mask = NULL;
@@ -1599,7 +1598,7 @@ int xscale_assert_reset(target_t *target)
* end up in T-L-R, which would reset JTAG
*/
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
@@ -1607,7 +1606,7 @@ int xscale_assert_reset(target_t *target)
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
jtag_execute_queue();
/* assert reset */
@@ -3045,7 +3044,7 @@ int xscale_quit(void)
return ERROR_OK;
}
-int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, const char *variant)
+int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
u32 high_reset_branch, low_reset_branch;
@@ -3061,7 +3060,7 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p
xscale->variant = strdup(variant);
/* prepare JTAG information for the new target */
- xscale->jtag_info.chain_pos = chain_pos;
+ xscale->jtag_info.tap = tap;
xscale->jtag_info.dbgrx = 0x02;
xscale->jtag_info.dbgtx = 0x10;
@@ -3158,7 +3157,7 @@ int xscale_target_create(struct target_s *target, Jim_Interp *interp)
{
xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
- xscale_init_arch_info(target, xscale, target->chain_position, target->variant);
+ xscale_init_arch_info(target, xscale, target->tap, target->variant);
xscale_build_reg_cache(target);
return ERROR_OK;
diff --git a/src/target/xscale.h b/src/target/xscale.h
index e3bfcec6..2eacb060 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -35,7 +35,7 @@
typedef struct xscale_jtag_s
{
/* position in JTAG scan chain */
- int chain_pos;
+ jtag_tap_t *tap;
/* IR length and instructions */
int ir_length;
diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c
index e86afbb8..e7ca5596 100644
--- a/src/xsvf/xsvf.c
+++ b/src/xsvf/xsvf.c
@@ -169,7 +169,10 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
int runtest_requires_tck = 0;
- int device = -1; /* use -1 to indicate a "plain" xsvf file which accounts for additional devices in the scan chain, otherwise the device that should be affected */
+ jtag_tap_t *tap = NULL;
+ /* use NULL to indicate a "plain" xsvf file which accounts for
+ additional devices in the scan chain, otherwise the device
+ that should be affected */
if (argc < 2)
{
@@ -179,7 +182,11 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
if (strcmp(args[0], "plain") != 0)
{
- device = strtoul(args[0], NULL, 0);
+ tap = jtag_TapByString( args[0] );
+ if( !tap ){
+ command_print( cmd_ctx, "Tap: %s unknown", args[0] );
+ return ERROR_OK;
+ }
}
if ((xsvf_fd = open(args[1], O_RDONLY)) < 0)
@@ -222,7 +229,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = c;
field.out_value = ir_buf;
field.out_mask = NULL;
@@ -231,7 +238,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, TAP_PI);
else
jtag_add_ir_scan(1, &field, TAP_PI);
@@ -265,13 +272,13 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = xsdrsize;
field.out_value = dr_out_buf;
field.out_mask = NULL;
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD);
@@ -339,13 +346,13 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = xsdrsize;
field.out_value = dr_out_buf;
field.out_mask = NULL;
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD);
@@ -482,7 +489,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = us;
field.out_value = ir_buf;
field.out_mask = NULL;
@@ -491,7 +498,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, xsvf_to_tap[xendir]);
else
jtag_add_ir_scan(1, &field, xsvf_to_tap[xendir]);