Submitted by David Brownell <david-b@pacbell.net>:

Improve support for the DM355 EVM board, and eventually other boards based
on DaVinci chips:

 - Provide generic "davinci.cfg" to hold utilities that can be reused by
   different chips in this family.  Start with PINMUX, PSC, and PLL setup.

 - DM355 chip support updates:  provide a dictionary with chip-specific
   symbols, load those utilities.

 - Create a new dm355evm board file, with a reset-init event handler
   which uses those utilities to set up PLLs and clocks, configure the
   pins, and improve the JTAG speed limit.

Also a minor tweak:  provide a virtual address for the work area, matching
what the very latest kernels do.  It's probably unwise to use OpenOCD while
the MMU is active though.

The DRAM isn't yet accessible, but NAND access is mostly ready.


git-svn-id: svn://svn.berlios.de/openocd/trunk@1881 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 111 insertions, 0 deletions

diff --git a/src/target/board/dm355evm.cfg b/src/target/board/dm355evm.cfg
new file mode 100644
index 00000000..6b633b88
--- /dev/null
+++ b/src/target/board/dm355evm.cfg
@@ -0,0 +1,111 @@
+#
+# DM355 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
+#   http://c6000.spectrumdigital.com/evmdm355/
+
+source [find target/ti_dm355.cfg]
+
+reset_config trst_and_srst separate
+
+# NOTE:  disable or replace this call to dm355evm_init if you're
+# debugging new UBL code from SRAM.
+$_TARGETNAME configure -event reset-init { dm355evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm355evm_init {} {
+	global dm355
+
+	puts "Initialize DM355 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	jtag_khz 1500
+
+	########################
+	# PLL1		= 432 MHz (/8, x144)
+	# ...SYSCLK1	= 216 MHz (/2)  ... ARM, MJCP
+	# ...SYSCLK2	= 108 MHz (/4)  ... Peripherals
+	# ...SYSCLK3	= 27  MHz (/16) ... VPBE, DAC
+	# ...SYSCLK4	= 108 MHz (/4)  ... VPSS
+	#	pll1.{prediv,div1,div2} are fixed
+	#	pll1.postdiv set in MISC (for *this* speed grade)
+
+	set addr [dict get $dm355 pllc1]
+	set pll_divs [dict create]
+	dict set pll_divs div3 16
+	dict set pll_divs div4 8
+	pll_setup $addr 144 $pll_divs
+
+	# ARM is now running at 216 MHz, so JTAG can go faster
+	jtag_khz 20000
+
+	########################
+	# PLL2		= 342 MHz (/8, x114)
+	# ....SYSCLK1	= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
+	#	pll2.{postdiv,div1} are fixed
+
+	set addr [dict get $dm355 pllc2]
+	set pll_divs [dict create]
+	dict set pll_divs prediv 8
+	pll_setup $addr 114 $pll_divs
+
+	########################
+	# PINMUX
+
+	# All Video Inputs
+	davinci_pinmux $dm355 0 0x00007f55
+	# All Video Outputs
+	davinci_pinmux $dm355 1 0x00145555
+	# EMIFA (NOTE: more could be set up for use as GPIOs)
+	davinci_pinmux $dm355 2 0x00000c08
+	# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+	davinci_pinmux $dm355 3 0x1bff55ff
+	# MMC/SD0 instead of MS; SPI0
+	davinci_pinmux $dm355 4 0x00000000
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	########################
+	# DDR2 EMIF
+
+	# FIXME setup
+
+	########################
+	# ASYNC EMIF
+
+	set addr [dict get $dm355 a_emif]
+
+	# slow/pessimistic timings
+	set nand_timings 0x40400204
+	# fast (25% faster page reads)
+	#set nand_timings 0x0400008c
+
+	# AWCCR
+	mww [expr $addr + 0x04] 0xff
+	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
+	mww [expr $addr + 0x10] $nand_timings
+	# CS1 == dm9000 Ethernet
+	mww [expr $addr + 0x14] 0x00a00505
+	# NANDFCR -- only CS0 has NAND
+	mww [expr $addr + 0x60] 0x01
+
+	########################
+	# UART0
+
+	# FIXME setup
+}
+
+# FIXME
+#  - declare the NAND flash; use the 4-bit ECC
+#  - support writing UBL with its header (new layout only with new ROMs)
+#  - support writing ABL/U-Boot with its header (both layouts)