Cortex-M3: expose most DWT registers

Expose most DWT registers via Tcl; there are a few more, but
those are mostly for profiling along with the ITM.  Having
this set available enables operations which aren't possible
with just the standard watchpoint operations.

The cycle counter may be interesting.  Turn it on after reset
by setting the LSB of the dwt_ctrl register, and it counts
CPU clocks.  You can program the comparator 0 watchpoint to
trigger on a given cycle count, rather than a data address.

Likewise, comparator 1 may be able to match data values given
address matches from one or two other comparators.  (Not all
hardware supports this capability though; try it.  That is
something the standard watchpoint methods should eventually
handle, for the single address case.)

Minor cleanup:  remove needless functional indirection for
exposing the v7m architctural registers.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index a7074d36..1dd724c8 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -45,6 +45,7 @@
 #define DCRSR_WnR	(1 << 16)
 
 #define DWT_CTRL	0xE0001000
+#define DWT_CYCCNT	0xE0001004
 #define DWT_COMP0	0xE0001020
 #define DWT_MASK0	0xE0001024
 #define DWT_FUNCTION0	0xE0001028
@@ -157,6 +158,7 @@ typedef struct cortex_m3_common_s
 	int dwt_num_comp;
 	int dwt_comp_available;
 	cortex_m3_dwt_comparator_t *dwt_comparator_list;
+	struct reg_cache_s *dwt_cache;
 
 	armv7m_common_t armv7m;
 	void *arch_info;