diff options
| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-09 07:31:24 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-09 07:31:24 +0000 |
| commit | 23939e4fc3400aa6f781ac364d9fd8c2cf66449a (patch) | |
| tree | 42d9f512cb70205d17719d87d1a1128867e2b238 /src/target/event/str912_reset.script | |
| parent | 2585fc34200938fb3fa55a450ea37f68012aafa7 (diff) | |
| download | openocd+libswd-23939e4fc3400aa6f781ac364d9fd8c2cf66449a.tar.gz openocd+libswd-23939e4fc3400aa6f781ac364d9fd8c2cf66449a.tar.bz2 openocd+libswd-23939e4fc3400aa6f781ac364d9fd8c2cf66449a.tar.xz openocd+libswd-23939e4fc3400aa6f781ac364d9fd8c2cf66449a.zip | |
- add missing svn props
git-svn-id: svn://svn.berlios.de/openocd/trunk@554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/event/str912_reset.script')
| -rw-r--r-- | src/target/event/str912_reset.script | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script index bbec5976..c3d68104 100644 --- a/src/target/event/str912_reset.script +++ b/src/target/event/str912_reset.script @@ -1,22 +1,22 @@ -mww 0xFFFFFD44, 0x00008000 #Disable watchdog
-mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
-sleep 20
-mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
-sleep 20
-
-
-# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
-# when the bank 0 is the boot bank, then enable the Bank 1. */
-
-mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
-mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
-mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
-mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
-mww 0x54000018, 0x18 #Enable CS on both banks
-
-# -- Enable 96K RAM */
-mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
-arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
-
-str9x flash_config 0 4 2 0 0x80000
-flash protect 0 0 7 off
+mww 0xFFFFFD44, 0x00008000 #Disable watchdog +mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator +sleep 20 +mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR +sleep 20 + + +# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, +# when the bank 0 is the boot bank, then enable the Bank 1. */ + +mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB +mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB +mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0 +mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000 +mww 0x54000018, 0x18 #Enable CS on both banks + +# -- Enable 96K RAM */ +mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled +arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register + +str9x flash_config 0 4 2 0 0x80000 +flash protect 0 0 7 off |