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authorntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-10 11:43:48 +0000
committerntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-10 11:43:48 +0000
commit9c3dec377eb6eb822b85fa107ade2a62c9e1cfd1 (patch)
tree528bc639688200b05ae27df46046c3544399d121 /src/target/xscale/build.sh
parent1ade331ba925c506ed4254f31dba5e6f9cf782b4 (diff)
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- single core context used, removed debug context as thought unnecessary.
- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon. - now checks for User Thread Mode and Thread mode when halted. - removed repeated function declarations from command.c - cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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