Uwe Hermann tightned up comments, etc. to follow OpenOCD policy

git-svn-id: svn://svn.berlios.de/openocd/trunk@431 b42882b7-edfa-0310-969c-e2dbd0fdcd60

8 files changed, 37 insertions, 30 deletions

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 85068a11..f117a480 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -404,14 +404,15 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
 
     arm11_write_DSCR(arm11, new_dscr);
 
-//    jtag_execute_queue();
+    /* jtag_execute_queue(); */
 
 
+/*
+    DEBUG("SAVE DSCR %08x", R(DSCR));
 
-//    DEBUG("SAVE DSCR %08x", R(DSCR));
-
-//    if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
-//	DEBUG("SAVE wDTR %08x", R(WDTR));
+    if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
+	DEBUG("SAVE wDTR %08x", R(WDTR));
+*/
 
 
     /* From the spec:
@@ -424,7 +425,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
     while (1)
     {
 	/* MRC p14,0,R0,c5,c10,0 */
-//	arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
+	/* arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); */
 
 	/* mcr     15, 0, r0, cr7, cr10, {4} */
 	arm11_run_instr_no_data1(arm11, 0xee070f9a);
@@ -501,7 +502,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
 	arm11->reg_values[ARM11_RC_PC] -= 8;
     }
 
-//    DEBUG("SAVE PC   %08x", R(PC));
+    /* DEBUG("SAVE PC   %08x", R(PC)); */
 
     arm11_run_instr_data_finish(arm11);
 
@@ -557,7 +558,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
 	/* MRC p14,0,r?,c0,c5,0 */
 	arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 
-//	DEBUG("RESTORE R%d %08x", i, R(RX + i));
+	/* DEBUG("RESTORE R%d %08x", i, R(RX + i)); */
     }}
 
     arm11_run_instr_data_finish(arm11);
@@ -762,8 +763,10 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 {
     FNC_INFO;
 
-//    DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
-//	current, address, handle_breakpoints, debug_execution);
+/*
+    DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
+	current, address, handle_breakpoints, debug_execution);
+*/
 
     arm11_common_t * arm11 = target->arch_info;
 
@@ -948,7 +951,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 	arm11_on_enter_debug_state(arm11);
     }
 
-//    target->state		= TARGET_HALTED;
+    /* target->state		= TARGET_HALTED; */
     target->debug_reason	= DBG_REASON_SINGLESTEP;
 
     target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1447,7 +1450,7 @@ int arm11_set_reg(reg_t *reg, u8 *buf)
 
     target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
     arm11_common_t *arm11 = target->arch_info;
-//    const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+    /* const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; */
 
     arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
     reg->valid	= 1;
@@ -1479,8 +1482,8 @@ void arm11_build_reg_cache(target_t *target)
     reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
     (*cache_p) = cache;
 
-//    armv7m->core_cache = cache;
-//    armv7m->process_context = cache;
+    /* armv7m->core_cache = cache; */
+    /* armv7m->process_context = cache; */
 
     size_t i;
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 2528f107..3bd50cd6 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -217,7 +217,7 @@ int armv4_5_get_core_reg(reg_t *reg)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
-	//retval = armv4_5->armv4_5_common->full_context(target);
+	/* retval = armv4_5->armv4_5_common->full_context(target); */
 	retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
 	
 	return retval;
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 2f82a6f1..6a8119a0 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -63,7 +63,7 @@ char* armv7m_core_reg_list[] =
 	"sp", "lr", "pc",
 	"xPSR", "msp", "psp",
 	/* Registers accessed through MSR instructions */
-//	"apsr", "iapsr", "ipsr", "epsr",
+	/* "apsr", "iapsr", "ipsr", "epsr", */
 	"primask", "basepri", "faultmask", "control"
 };
 
@@ -74,7 +74,7 @@ char* armv7m_core_dbgreg_list[] =
 	"sp", "lr", "pc",
 	"xPSR", "msp", "psp",
 	/* Registers accessed through MSR instructions */
-//	"dbg_apsr", "iapsr", "ipsr", "epsr",
+	/* "dbg_apsr", "iapsr", "ipsr", "epsr", */
 	"primask", "basepri", "faultmask", "dbg_control"
 };
 
@@ -110,10 +110,12 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
 	{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 
 	/*  CORE_SP are accesible using MSR and MRS instructions */
+#if 0
 //	{0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
 //	{0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
 //	{0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
 //	{0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
+#endif
 
 	{0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 	{0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
@@ -332,7 +334,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 	{
 		if (i < ARMV7NUMCOREREGS)
 			(*reg_list)[i] = &armv7m->process_context->reg_list[i];
-			//(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+			/* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
 		else
 			(*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 	}
@@ -344,7 +346,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 
 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 {
-	// get pointers to arch-specific information
+	/* get pointers to arch-specific information */
 	armv7m_common_t *armv7m = target->arch_info;
 	armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 	enum armv7m_state core_state = armv7m->core_state;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 946264c4..e897fc44 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -104,9 +104,11 @@ typedef struct armv7m_common_s
 	
 	void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
 	
-//	void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
-//	void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
-//	void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+/*
+	void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
+	void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
+	void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+*/
 
 /*
 	void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3a567aba..91911f9e 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -639,7 +639,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
 	return ERROR_OK;
 }
 
-//int irqstepcount=0;
+/* int irqstepcount=0; */
 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 {
 	/* get pointers to arch-specific information */
@@ -1134,7 +1134,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
 			ERROR("JTAG failure %i",retval);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		//DEBUG("load from core reg %i  value 0x%x",num,*value);
+		/* DEBUG("load from core reg %i  value 0x%x",num,*value); */
 	}
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
@@ -1468,7 +1468,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
 	armv7m->arch_info = cortex_m3;
 	armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
 	armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-//	armv7m->full_context = cortex_m3_full_context;
+	/* armv7m->full_context = cortex_m3_full_context; */
 	
 	target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
 	
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index d04923f9..236911f5 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -134,7 +134,7 @@ typedef struct  cortex_m3_dwt_comparator_s
 typedef struct cortex_m3_common_s
 {
 	int common_magic;
-//	int (*full_context)(struct target_s *target);
+	/* int (*full_context)(struct target_s *target); */
 
 	arm_jtag_t jtag_info;
 	
diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c
index 81ff6f99..6f267907 100644
--- a/src/target/cortex_swjdp.c
+++ b/src/target/cortex_swjdp.c
@@ -327,13 +327,13 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
 	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 	if (csw != swjdp->ap_csw_value)
 	{
-		//DEBUG("swjdp : Set CSW %x",csw);
+		/* DEBUG("swjdp : Set CSW %x",csw); */
 		ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw ); 
 		swjdp->ap_csw_value = csw;
 	}
 	if (tar != swjdp->ap_tar_value)
 	{
-		//DEBUG("swjdp : Set TAR %x",tar);
+		/* DEBUG("swjdp : Set TAR %x",tar); */
 		ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
 		swjdp->ap_tar_value = tar;
 	}
diff --git a/src/target/cortex_swjdp.h b/src/target/cortex_swjdp.h
index ad6c69a6..99dae691 100644
--- a/src/target/cortex_swjdp.h
+++ b/src/target/cortex_swjdp.h
@@ -98,9 +98,9 @@ typedef struct swjdp_common_s
 
 /* Internal functions used in the module, partial transactions, use with caution */
 extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
-//extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
+/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
 extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
-//extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
+/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
 extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
 extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);