TCL: fix non TCL comments

End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>

3 files changed, 109 insertions, 109 deletions

diff --git a/tcl/chip/st/spear/spear310.tcl b/tcl/chip/st/spear/spear310.tcl
index b2c3676e..95df51d4 100644
--- a/tcl/chip/st/spear/spear310.tcl
+++ b/tcl/chip/st/spear/spear310.tcl
@@ -6,11 +6,11 @@
 
 
 proc sp310_init {} {
-	mww 0xfca80034 0x0000ffff	# enable all RAS clocks
-	mww 0xfca80040 0x00000000	# remove all RAS resets
-	mww 0xb4000008 0x00002ff4	# RAS function enable
+	mww 0xfca80034 0x0000ffff	;# enable all RAS clocks
+	mww 0xfca80040 0x00000000	;# remove all RAS resets
+	mww 0xb4000008 0x00002ff4	;# RAS function enable
 
-	mww 0xfca8013c 0x2f7bc210	# plgpio_pad_drv
+	mww 0xfca8013c 0x2f7bc210	;# plgpio_pad_drv
 	mww 0xfca80140 0x017bdef6
 }
 
@@ -21,20 +21,20 @@ proc sp310_emi_init {} {
 	mmw 0xfca8013c 0x00039ce7 0x00000000
 
 	# set safe EMI timing as in BootROM
-	#mww 0x4f000000 0x0000000f	# tAP_0_reg
-	#mww 0x4f000004 0x00000000	# tSDP_0_reg
-	#mww 0x4f000008 0x000000ff	# tDPw_0_reg
-	#mww 0x4f00000c 0x00000111	# tDPr_0_reg
-	#mww 0x4f000010 0x00000002	# tDCS_0_reg
+	#mww 0x4f000000 0x0000000f	;# tAP_0_reg
+	#mww 0x4f000004 0x00000000	;# tSDP_0_reg
+	#mww 0x4f000008 0x000000ff	;# tDPw_0_reg
+	#mww 0x4f00000c 0x00000111	;# tDPr_0_reg
+	#mww 0x4f000010 0x00000002	;# tDCS_0_reg
 
 	# set fast EMI timing as in Linux
-	mww 0x4f000000 0x00000010	# tAP_0_reg
-	mww 0x4f000004 0x00000005	# tSDP_0_reg
-	mww 0x4f000008 0x0000000a	# tDPw_0_reg
-	mww 0x4f00000c 0x0000000a	# tDPr_0_reg
-	mww 0x4f000010 0x00000005	# tDCS_0_re
+	mww 0x4f000000 0x00000010	;# tAP_0_reg
+	mww 0x4f000004 0x00000005	;# tSDP_0_reg
+	mww 0x4f000008 0x0000000a	;# tDPw_0_reg
+	mww 0x4f00000c 0x0000000a	;# tDPr_0_reg
+	mww 0x4f000010 0x00000005	;# tDCS_0_re
 
 	# 32bit wide, 8/16/32bit access
-	mww 0x4f000014 0x0000000e	# control_0_reg
-	mww 0x4f000094 0x0000003f	# ack_reg
+	mww 0x4f000014 0x0000000e	;# control_0_reg
+	mww 0x4f000094 0x0000003f	;# ack_reg
 }
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index ea85d295..660dab3b 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -15,34 +15,34 @@
 # - HCLK    = 166 MHz
 # - PCLK    =  83 MHz
 proc sp3xx_clock_default {} {
-	mww 0xfca00000 0x00000002	# set sysclk slow
-	mww 0xfca00014 0x0ffffff8	# set pll timeout to minimum (100us ?!?)
+	mww 0xfca00000 0x00000002	;# set sysclk slow
+	mww 0xfca00014 0x0ffffff8	;# set pll timeout to minimum (100us ?!?)
 
 	# DDRCORE disable to change frequency
 	set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
 	mww 0xfca8002c $val
-	mww 0xfca8002c $val # Yes, write twice!
+	mww 0xfca8002c $val ;# Yes, write twice!
 
 	# programming PLL1
-	mww 0xfca8000c 0xa600010c	# M=166 P=1 N=12
-	mww 0xfca80008 0x00001c0a	# power down
-	mww 0xfca80008 0x00001c0e	# enable
-	mww 0xfca80008 0x00001c06	# strobe
+	mww 0xfca8000c 0xa600010c	;# M=166 P=1 N=12
+	mww 0xfca80008 0x00001c0a	;# power down
+	mww 0xfca80008 0x00001c0e	;# enable
+	mww 0xfca80008 0x00001c06	;# strobe
 	mww 0xfca80008 0x00001c0e
 	while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
 
 	# programming PLL2
-	mww 0xfca80018 0xa600010c	# M=166, P=1, N=12
-	mww 0xfca80014 0x00001c0a	# power down
-	mww 0xfca80014 0x00001c0e	# enable
-	mww 0xfca80014 0x00001c06	# strobe
+	mww 0xfca80018 0xa600010c	;# M=166, P=1, N=12
+	mww 0xfca80014 0x00001c0a	;# power down
+	mww 0xfca80014 0x00001c0e	;# enable
+	mww 0xfca80014 0x00001c06	;# strobe
 	mww 0xfca80014 0x00001c0e
 	while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
 
-	mww 0xfca80028 0x00000082	# enable plltimeen
-	mww 0xfca80024 0x00000511	# set hclkdiv="/2" & pclkdiv="/2"
+	mww 0xfca80028 0x00000082	;# enable plltimeen
+	mww 0xfca80024 0x00000511	;# set hclkdiv="/2" & pclkdiv="/2"
 
-	mww 0xfca00000 0x00000004	# setting SYSCTL to NORMAL mode
+	mww 0xfca00000 0x00000004	;# setting SYSCTL to NORMAL mode
 	while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
 
 	# Select source of DDR clock
@@ -54,15 +54,15 @@ proc sp3xx_clock_default {} {
 }
 
 proc sp3xx_common_init {} {
-	mww 0xfca8002c 0xfffffff8	# enable clock of all peripherals
-	mww 0xfca80038 0x00000000	# remove reset of all peripherals
+	mww 0xfca8002c 0xfffffff8	;# enable clock of all peripherals
+	mww 0xfca80038 0x00000000	;# remove reset of all peripherals
 
-	mww 0xfca800e4 0x78000008	# COMP1V8_REG
-	mww 0xfca800ec 0x78000008	# COMP3V3_REG
+	mww 0xfca800e4 0x78000008	;# COMP1V8_REG
+	mww 0xfca800ec 0x78000008	;# COMP3V3_REG
 
-	mww 0xfca80050 0x00000001	# Enable clk mem port 1
+	mww 0xfca80050 0x00000001	;# Enable clk mem port 1
 
-	mww 0xfc000000 0x10000f5f	# init SMI and set HW mode
+	mww 0xfc000000 0x10000f5f	;# init SMI and set HW mode
 	mww 0xfc000000 0x00000f5f
 
 	# Initialize Bus Interconnection Matrix
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index a804cdc4..14b5dfe0 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -41,80 +41,80 @@ proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
 
 	# Use "1:2 sync" only when DDR clock source is PLL1 and
 	# HCLK is half of PLL1
-	mww 0xfc600000 0x00000001	# MEMCTL_AHB_SET_00 # This is async
-	mww 0xfc600004 0x00000000	# MEMCTL_AHB_SET_01
-#	mww 0xfc600000 0x02020201	# MEMCTL_AHB_SET_00 # This is 1:2 sync
-#	mww 0xfc600004 0x02020202	# MEMCTL_AHB_SET_01
+	mww 0xfc600000 0x00000001	;# MEMCTL_AHB_SET_00 # This is async
+	mww 0xfc600004 0x00000000	;# MEMCTL_AHB_SET_01
+#	mww 0xfc600000 0x02020201	;# MEMCTL_AHB_SET_00 # This is 1:2 sync
+#	mww 0xfc600004 0x02020202	;# MEMCTL_AHB_SET_01
 
-	mww 0xfc600008 0x01000000	# MEMCTL_RFSH_SET_00
-	mww 0xfc60000c 0x00000101	# MEMCTL_DLL_SET_00
-	mww 0xfc600010 0x00000101	# MEMCTL_GP_00
-	mww 0xfc600014 0x01000000	# MEMCTL_GP_01
-	mww 0xfc600018 0x00010001	# MEMCTL_GP_02
-	mww 0xfc60001c 0x00000100	# MEMCTL_GP_03
-	mww 0xfc600020 0x00010001	# MEMCTL_GP_04
-	mww 0xfc600024 0x01020203	# MEMCTL_GP_05
-	mww 0xfc600028 0x01000102	# MEMCTL_GP_06
-	mww 0xfc60002c 0x02000202	# MEMCTL_AHB_SET_02
-	mww 0xfc600030 0x04040105	# MEMCTL_AHB_SET_03
-	mww 0xfc600034 0x03030302	# MEMCTL_AHB_SET_04
-	mww 0xfc600038 0x02040101	# MEMCTL_AHB_SET_05
-	mww 0xfc60003c 0x00000002	# MEMCTL_AHB_SET_06
-	mww 0xfc600044 0x03000405	# MEMCTL_DQS_SET_0
-	mww 0xfc600048 0x03040002	# MEMCTL_TIME_SET_01
-	mww 0xfc60004c 0x04000305	# MEMCTL_TIME_SET_02
-	mww 0xfc600050 0x0505053f	# MEMCTL_AHB_RELPR_00
-	mww 0xfc600054 0x05050505	# MEMCTL_AHB_RELPR_01
-	mww 0xfc600058 0x04040405	# MEMCTL_AHB_RELPR_02
-	mww 0xfc60005c 0x04040404	# MEMCTL_AHB_RELPR_03
-	mww 0xfc600060 0x03030304	# MEMCTL_AHB_RELPR_04
-	mww 0xfc600064 0x03030303	# MEMCTL_AHB_RELPR_05
-	mww 0xfc600068 0x02020203	# MEMCTL_AHB_RELPR_06
-	mww 0xfc60006c 0x02020202	# MEMCTL_AHB_RELPR_07
-	mww 0xfc600070 0x01010102	# MEMCTL_AHB_RELPR_08
-	mww 0xfc600074 0x01010101	# MEMCTL_AHB_RELPR_09
-	mww 0xfc600078 0x00000001	# MEMCTL_AHB_RELPR_10
-	mww 0xfc600088 0x0a0c0a00	# MEMCTL_DQS_SET_1
-	mww 0xfc60008c 0x0000023f	# MEMCTL_GP_07
-	mww 0xfc600090 0x00050a00	# MEMCTL_GP_08
-	mww 0xfc600094 0x11000000	# MEMCTL_GP_09
-	mww 0xfc600098 0x00001302	# MEMCTL_GP_10
-	mww 0xfc60009c 0x00001c1c	# MEMCTL_DLL_SET_01
-	mww 0xfc6000a0 0x7c000000	# MEMCTL_DQS_OUT_SHIFT
-	mww 0xfc6000a4 0x005c0000	# MEMCTL_WR_DQS_SHIFT
-	mww 0xfc6000a8 0x2b050e00	# MEMCTL_TIME_SET_03
-	mww 0xfc6000ac 0x00640064	# MEMCTL_AHB_PRRLX_00
-	mww 0xfc6000b0 0x00640064	# MEMCTL_AHB_PRRLX_01
-	mww 0xfc6000b4 0x00000064	# MEMCTL_AHB_PRRLX_02
-	mww 0xfc6000b8 0x00000000	# MEMCTL_OUTRANGE_LGTH
-	mww 0xfc6000bc 0x00200020	# MEMCTL_AHB_RW_SET_00
-	mww 0xfc6000c0 0x00200020	# MEMCTL_AHB_RW_SET_01
-	mww 0xfc6000c4 0x00200020	# MEMCTL_AHB_RW_SET_02
-	mww 0xfc6000c8 0x00200020	# MEMCTL_AHB_RW_SET_03
-	mww 0xfc6000cc 0x00200020	# MEMCTL_AHB_RW_SET_04
-	mww 0xfc6000d8 0x00000a24	# MEMCTL_TREF
-	mww 0xfc6000dc 0x00000000	# MEMCTL_EMRS3_DATA
-	mww 0xfc6000e0 0x5b1c00c8	# MEMCTL_TIME_SET_04
-	mww 0xfc6000e4 0x00c8002e	# MEMCTL_TIME_SET_05
-	mww 0xfc6000e8 0x00000000	# MEMCTL_VERSION
-	mww 0xfc6000ec 0x0001046b	# MEMCTL_TINIT
-	mww 0xfc6000f0 0x00000000	# MEMCTL_OUTRANGE_ADDR_01
-	mww 0xfc6000f4 0x00000000	# MEMCTL_OUTRANGE_ADDR_02
-	mww 0xfc600104 0x001c0000	# MEMCTL_DLL_DQS_DELAY_BYPASS_0
-	mww 0xfc600108 0x0019001c	# MEMCTL_DLL_SET_02
-	mww 0xfc60010c 0x00100000	# MEMCTL_DLL_SET_03
-	mww 0xfc600110 0x001e007a	# MEMCTL_DQS_SET_2
-	mww 0xfc600188 0x00000000	# MEMCTL_USER_DEF_REG_0
-	mww 0xfc60018c 0x00000000	# MEMCTL_USER_DEF_REG_1
-	mww 0xfc600190 0x01010001	# MEMCTL_GP_11
-	mww 0xfc600194 0x01000000	# MEMCTL_GP_12
-	mww 0xfc600198 0x00000001	# MEMCTL_GP_13
-	mww 0xfc60019c 0x00400000	# MEMCTL_GP_14
-	mww 0xfc6001a0 0x00000000	# MEMCTL_EMRS2_DATA_X
-	mww 0xfc6001a4 0x00000000	# MEMCTL_LWPWR_CNT
-	mww 0xfc6001a8 0x00000000	# MEMCTL_LWPWR_REG
-	mww 0xfc6001ac 0x00860000	# MEMCTL_GP_15
-	mww 0xfc6001b0 0x00000002	# MEMCTL_TPDEX
+	mww 0xfc600008 0x01000000	;# MEMCTL_RFSH_SET_00
+	mww 0xfc60000c 0x00000101	;# MEMCTL_DLL_SET_00
+	mww 0xfc600010 0x00000101	;# MEMCTL_GP_00
+	mww 0xfc600014 0x01000000	;# MEMCTL_GP_01
+	mww 0xfc600018 0x00010001	;# MEMCTL_GP_02
+	mww 0xfc60001c 0x00000100	;# MEMCTL_GP_03
+	mww 0xfc600020 0x00010001	;# MEMCTL_GP_04
+	mww 0xfc600024 0x01020203	;# MEMCTL_GP_05
+	mww 0xfc600028 0x01000102	;# MEMCTL_GP_06
+	mww 0xfc60002c 0x02000202	;# MEMCTL_AHB_SET_02
+	mww 0xfc600030 0x04040105	;# MEMCTL_AHB_SET_03
+	mww 0xfc600034 0x03030302	;# MEMCTL_AHB_SET_04
+	mww 0xfc600038 0x02040101	;# MEMCTL_AHB_SET_05
+	mww 0xfc60003c 0x00000002	;# MEMCTL_AHB_SET_06
+	mww 0xfc600044 0x03000405	;# MEMCTL_DQS_SET_0
+	mww 0xfc600048 0x03040002	;# MEMCTL_TIME_SET_01
+	mww 0xfc60004c 0x04000305	;# MEMCTL_TIME_SET_02
+	mww 0xfc600050 0x0505053f	;# MEMCTL_AHB_RELPR_00
+	mww 0xfc600054 0x05050505	;# MEMCTL_AHB_RELPR_01
+	mww 0xfc600058 0x04040405	;# MEMCTL_AHB_RELPR_02
+	mww 0xfc60005c 0x04040404	;# MEMCTL_AHB_RELPR_03
+	mww 0xfc600060 0x03030304	;# MEMCTL_AHB_RELPR_04
+	mww 0xfc600064 0x03030303	;# MEMCTL_AHB_RELPR_05
+	mww 0xfc600068 0x02020203	;# MEMCTL_AHB_RELPR_06
+	mww 0xfc60006c 0x02020202	;# MEMCTL_AHB_RELPR_07
+	mww 0xfc600070 0x01010102	;# MEMCTL_AHB_RELPR_08
+	mww 0xfc600074 0x01010101	;# MEMCTL_AHB_RELPR_09
+	mww 0xfc600078 0x00000001	;# MEMCTL_AHB_RELPR_10
+	mww 0xfc600088 0x0a0c0a00	;# MEMCTL_DQS_SET_1
+	mww 0xfc60008c 0x0000023f	;# MEMCTL_GP_07
+	mww 0xfc600090 0x00050a00	;# MEMCTL_GP_08
+	mww 0xfc600094 0x11000000	;# MEMCTL_GP_09
+	mww 0xfc600098 0x00001302	;# MEMCTL_GP_10
+	mww 0xfc60009c 0x00001c1c	;# MEMCTL_DLL_SET_01
+	mww 0xfc6000a0 0x7c000000	;# MEMCTL_DQS_OUT_SHIFT
+	mww 0xfc6000a4 0x005c0000	;# MEMCTL_WR_DQS_SHIFT
+	mww 0xfc6000a8 0x2b050e00	;# MEMCTL_TIME_SET_03
+	mww 0xfc6000ac 0x00640064	;# MEMCTL_AHB_PRRLX_00
+	mww 0xfc6000b0 0x00640064	;# MEMCTL_AHB_PRRLX_01
+	mww 0xfc6000b4 0x00000064	;# MEMCTL_AHB_PRRLX_02
+	mww 0xfc6000b8 0x00000000	;# MEMCTL_OUTRANGE_LGTH
+	mww 0xfc6000bc 0x00200020	;# MEMCTL_AHB_RW_SET_00
+	mww 0xfc6000c0 0x00200020	;# MEMCTL_AHB_RW_SET_01
+	mww 0xfc6000c4 0x00200020	;# MEMCTL_AHB_RW_SET_02
+	mww 0xfc6000c8 0x00200020	;# MEMCTL_AHB_RW_SET_03
+	mww 0xfc6000cc 0x00200020	;# MEMCTL_AHB_RW_SET_04
+	mww 0xfc6000d8 0x00000a24	;# MEMCTL_TREF
+	mww 0xfc6000dc 0x00000000	;# MEMCTL_EMRS3_DATA
+	mww 0xfc6000e0 0x5b1c00c8	;# MEMCTL_TIME_SET_04
+	mww 0xfc6000e4 0x00c8002e	;# MEMCTL_TIME_SET_05
+	mww 0xfc6000e8 0x00000000	;# MEMCTL_VERSION
+	mww 0xfc6000ec 0x0001046b	;# MEMCTL_TINIT
+	mww 0xfc6000f0 0x00000000	;# MEMCTL_OUTRANGE_ADDR_01
+	mww 0xfc6000f4 0x00000000	;# MEMCTL_OUTRANGE_ADDR_02
+	mww 0xfc600104 0x001c0000	;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
+	mww 0xfc600108 0x0019001c	;# MEMCTL_DLL_SET_02
+	mww 0xfc60010c 0x00100000	;# MEMCTL_DLL_SET_03
+	mww 0xfc600110 0x001e007a	;# MEMCTL_DQS_SET_2
+	mww 0xfc600188 0x00000000	;# MEMCTL_USER_DEF_REG_0
+	mww 0xfc60018c 0x00000000	;# MEMCTL_USER_DEF_REG_1
+	mww 0xfc600190 0x01010001	;# MEMCTL_GP_11
+	mww 0xfc600194 0x01000000	;# MEMCTL_GP_12
+	mww 0xfc600198 0x00000001	;# MEMCTL_GP_13
+	mww 0xfc60019c 0x00400000	;# MEMCTL_GP_14
+	mww 0xfc6001a0 0x00000000	;# MEMCTL_EMRS2_DATA_X
+	mww 0xfc6001a4 0x00000000	;# MEMCTL_LWPWR_CNT
+	mww 0xfc6001a8 0x00000000	;# MEMCTL_LWPWR_REG
+	mww 0xfc6001ac 0x00860000	;# MEMCTL_GP_15
+	mww 0xfc6001b0 0x00000002	;# MEMCTL_TPDEX
 	# MPMC START
 	mww 0xfc60001c 0x01000100
 }