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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2010-12-19 01:22:53 +0800 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-12-18 21:04:22 +0100 |
| commit | 30da7c67cec8b315972377b5389735ff11f6042c (patch) | |
| tree | f5735bd53edf0b43ef27c5058fdab817d2034462 /tcl/target/ar71xx.cfg | |
| parent | af3f77a1777e4f28ec1a14122f4800ca3467e4c7 (diff) | |
| download | openocd+libswd-30da7c67cec8b315972377b5389735ff11f6042c.tar.gz openocd+libswd-30da7c67cec8b315972377b5389735ff11f6042c.tar.bz2 openocd+libswd-30da7c67cec8b315972377b5389735ff11f6042c.tar.xz openocd+libswd-30da7c67cec8b315972377b5389735ff11f6042c.zip | |
TCL: fix non TCL comments
End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target/ar71xx.cfg')
| -rw-r--r-- | tcl/target/ar71xx.cfg | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 126efe4d..3ac61d94 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -15,35 +15,35 @@ target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME $TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting - mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0 - mww 0xb8050000 0x800f40a3 # send to PLL + mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 + mww 0xb8050000 0x800f40a3 ;# send to PLL #next command will reset for PLL changes to take effect - mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC) + mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) } $TARGETNAME configure -event reset-init { #complete pll initialization - mww 0xb8050000 0x800f0080 # set sw_update bit - mww 0xb8050008 0 # clear reset_switch bit - mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass - mww 0xb8050008 1 # set clock_switch bit - sleep 1 # wait for lock + mww 0xb8050000 0x800f0080 ;# set sw_update bit + mww 0xb8050008 0 ;# clear reset_switch bit + mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass + mww 0xb8050008 1 ;# set clock_switch bit + sleep 1 ;# wait for lock # Setup DDR config and flash mapping - mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0) - mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8) - - mww 0xb8000010 8 # force precharge all banks - mww 0xb8000010 1 # force EMRS update cycle - mww 0xb800000c 0 # clr ext. mode register - mww 0xb8000010 2 # force auto refresh all banks - mww 0xb8000010 8 # force precharge all banks - mww 0xb8000008 0x31 # set DDR mode value CAS=3 - mww 0xb8000010 1 # force EMRS update cycle - mww 0xb8000014 0x461b # DDR refresh value - mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff) - mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7) + mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) + mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8) + + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb800000c 0 ;# clr ext. mode register + mww 0xb8000010 2 ;# force auto refresh all banks + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb8000014 0x461b ;# DDR refresh value + mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) + mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) mww 0xb8000020 0 mww 0xb8000024 0 mww 0xb8000028 0 |