summaryrefslogtreecommitdiff
path: root/tcl/target
diff options
context:
space:
mode:
authorThomas Koeller <thomas.koeller@baslerweb.com>2010-08-10 14:56:43 +0200
committerØyvind Harboe <oyvind.harboe@zylin.com>2010-08-12 08:59:03 +0200
commit4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136 (patch)
treef27154d8e9d75fa823a7bc82bd4e3e4fa475bdb3 /tcl/target
parent98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db (diff)
downloadopenocd+libswd-4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136.tar.gz
openocd+libswd-4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136.tar.bz2
openocd+libswd-4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136.tar.xz
openocd+libswd-4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136.zip
DM36x: Disable unused SYSCLKs
Clear the enable bits for all clocks that are not set explicitly. This is done to increase robustness by removing pre-existing state. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Diffstat (limited to 'tcl/target')
-rw-r--r--tcl/target/davinci.cfg21
1 files changed, 20 insertions, 1 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index b736c6ef..11ae093f 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -197,63 +197,82 @@ proc pll_v03_setup {pll_addr mult config} {
# 11 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
- # - ALNCTL has everything set
set aln 0
if { [dict exists $config div1] } {
set div [dict get $config div1]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0118] $div
set aln [expr $aln | 0x1]
+ } else {
+ mww [expr $pll_addr + 0x0118] 0
}
if { [dict exists $config div2] } {
set div [dict get $config div2]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x011c] $div
set aln [expr $aln | 0x2]
+ } else {
+ mww [expr $pll_addr + 0x011c] 0
}
if { [dict exists $config div3] } {
set div [dict get $config div3]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0120] $div
set aln [expr $aln | 0x4]
+ } else {
+ mww [expr $pll_addr + 0x0120] 0
}
if { [dict exists $config div4] } {
set div [dict get $config div4]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0160] $div
set aln [expr $aln | 0x8]
+ } else {
+ mww [expr $pll_addr + 0x0160] 0
}
if { [dict exists $config div5] } {
set div [dict get $config div5]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0164] $div
set aln [expr $aln | 0x10]
+ } else {
+ mww [expr $pll_addr + 0x0164] 0
}
if { [dict exists $config div6] } {
set div [dict get $config div6]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0168] $div
set aln [expr $aln | 0x20]
+ } else {
+ mww [expr $pll_addr + 0x0168] 0
}
if { [dict exists $config div7] } {
set div [dict get $config div7]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x016c] $div
set aln [expr $aln | 0x40]
+ } else {
+ mww [expr $pll_addr + 0x016c] 0
}
if { [dict exists $config div8] } {
set div [dict get $config div8]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0170] $div
set aln [expr $aln | 0x80]
+ } else {
+ mww [expr $pll_addr + 0x0170] 0
}
if { [dict exists $config div9] } {
set div [dict get $config div9]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0174] $div
set aln [expr $aln | 0x100]
+ } else {
+ mww [expr $pll_addr + 0x0174] 0
}
if {$aln != 0} {
+ # clear pllcmd.GO
+ mww [expr $pll_addr + 0x0138] 0x00
# write alingment flags
mww [expr $pll_addr + 0x0140] $aln
# write pllcmd.GO; poll pllstat.GO