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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-21 20:19:47 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-21 22:25:33 +0200 |
| commit | fcf1301e5269fdf734946ccf03177511f2eda851 (patch) | |
| tree | 10dd493cacbc966e6bbe210163c00fa09fa229e2 /tcl/target | |
| parent | e996452089fd5ffba34094958e87d51c1fcf8619 (diff) | |
| download | openocd+libswd-fcf1301e5269fdf734946ccf03177511f2eda851.tar.gz openocd+libswd-fcf1301e5269fdf734946ccf03177511f2eda851.tar.bz2 openocd+libswd-fcf1301e5269fdf734946ccf03177511f2eda851.tar.xz openocd+libswd-fcf1301e5269fdf734946ccf03177511f2eda851.zip | |
mww_phys retired. Replaced by generic mww phys in target.c
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/davinci.cfg | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index e1eb48f5..c14c98ea 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -204,34 +204,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000 + arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - arm926ejs mww_phys [expr $timer2_phys + 0x20] 0 + arm926ejs mww phys [expr $timer2_phys + 0x20] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - arm926ejs mww_phys [expr $timer2_phys + 0x24] 0 - arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b + arm926ejs mww phys [expr $timer2_phys + 0x24] 0 + arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - arm926ejs mww_phys [expr $timer2_phys + 0x10] 0 - arm926ejs mww_phys [expr $timer2_phys + 0x14] 0 - arm926ejs mww_phys [expr $timer2_phys + 0x18] 0 - arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0 + arm926ejs mww phys [expr $timer2_phys + 0x10] 0 + arm926ejs mww phys [expr $timer2_phys + 0x14] 0 + arm926ejs mww phys [expr $timer2_phys + 0x18] 0 + arm926ejs mww phys [expr $timer2_phys + 0x1c] 0 # WDTCR: put into pre-active state, then active - arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000 - arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000 + arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000 + arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000 + arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000 } |