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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-11-23 18:23:10 +0100 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-11-23 18:23:10 +0100 |
| commit | 828d006a9d05b24b6dcdf1c552912e04586d6f7d (patch) | |
| tree | 19872647219be432af3f2a6150151124e1889184 /tcl | |
| parent | eeb4276deb5c3ba6621b8121d460bc50857c8d53 (diff) | |
| download | openocd+libswd-828d006a9d05b24b6dcdf1c552912e04586d6f7d.tar.gz openocd+libswd-828d006a9d05b24b6dcdf1c552912e04586d6f7d.tar.bz2 openocd+libswd-828d006a9d05b24b6dcdf1c552912e04586d6f7d.tar.xz openocd+libswd-828d006a9d05b24b6dcdf1c552912e04586d6f7d.zip | |
arm926ejs: fix gaffe when converting from arm926ejs cp15 to mcr
the first arg is the register number 15 = cp15.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/dm355evm.cfg | 2 | ||||
| -rw-r--r-- | tcl/board/openrd.cfg | 2 | ||||
| -rw-r--r-- | tcl/board/sheevaplug.cfg | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 2e298b7e..2c8bea82 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -182,7 +182,7 @@ proc dm355evm_init {} { ######################## # turn on icache - set I bit in cp15 register c1 - mcr 0 0 1 0 0x00051078 + mcr 15 0 0 1 0 0x00051078 } # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one. diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg index 4bc708da..12cc79e4 100644 --- a/tcl/board/openrd.cfg +++ b/tcl/board/openrd.cfg @@ -29,7 +29,7 @@ proc openrd_init { } { jtag_reset 0 0 wait_halt - mcr 0 0 1 0 0x00052078 + mcr 15 0 0 1 0 0x00052078 mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register mww 0xD0001404 0x37543000 # Dunit Control Low Register diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg index 8e8396d7..9267eb95 100644 --- a/tcl/board/sheevaplug.cfg +++ b/tcl/board/sheevaplug.cfg @@ -29,7 +29,7 @@ proc sheevaplug_init { } { jtag_reset 0 0 wait_halt - mcr 0 0 1 0 0x00052078 + mcr 15 0 0 1 0 0x00052078 mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register mww 0xD0001404 0x39543000 # Dunit Control Low Register |