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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-28 06:28:39 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-28 06:28:39 +0000 |
| commit | adbe3ac8179db30c10619b2b682cd549e84fa6a4 (patch) | |
| tree | d9d08a0a9e634be00729ce2956605a91dbeacd4d /testing/examples/SAM7X256Test/prj/sam7x256_reset.script | |
| parent | b2a13907a86eb23b96452c27729d16f658cbad53 (diff) | |
| download | openocd+libswd-adbe3ac8179db30c10619b2b682cd549e84fa6a4.tar.gz openocd+libswd-adbe3ac8179db30c10619b2b682cd549e84fa6a4.tar.bz2 openocd+libswd-adbe3ac8179db30c10619b2b682cd549e84fa6a4.tar.xz openocd+libswd-adbe3ac8179db30c10619b2b682cd549e84fa6a4.zip | |
eol-style native
git-svn-id: svn://svn.berlios.de/openocd/trunk@1549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'testing/examples/SAM7X256Test/prj/sam7x256_reset.script')
| -rw-r--r-- | testing/examples/SAM7X256Test/prj/sam7x256_reset.script | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/testing/examples/SAM7X256Test/prj/sam7x256_reset.script b/testing/examples/SAM7X256Test/prj/sam7x256_reset.script index ff609b01..456341d6 100644 --- a/testing/examples/SAM7X256Test/prj/sam7x256_reset.script +++ b/testing/examples/SAM7X256Test/prj/sam7x256_reset.script @@ -1,17 +1,17 @@ -#
-# Init - taken form the script openocd_at91sam7_ecr.script
-#
-# I take this script from the following page:
-#
-# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
-#
-mww 0xfffffd44 0x00008000 # disable watchdog
-mww 0xfffffd08 0xa5000001 # enable user reset
-mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator
-sleep 10
-mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz
-sleep 10
-mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-sleep 10
-mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60)
-sleep 100
+# +# Init - taken form the script openocd_at91sam7_ecr.script +# +# I take this script from the following page: +# +# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html +# +mww 0xfffffd44 0x00008000 # disable watchdog +mww 0xfffffd08 0xa5000001 # enable user reset +mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +sleep 10 +mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz +sleep 10 +mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +sleep 10 +mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +sleep 100 |