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Diffstat (limited to 'testing/examples/SAM7X256Test/prj/sam7x256_reset.script')
-rw-r--r--testing/examples/SAM7X256Test/prj/sam7x256_reset.script34
1 files changed, 17 insertions, 17 deletions
diff --git a/testing/examples/SAM7X256Test/prj/sam7x256_reset.script b/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
index ff609b01..456341d6 100644
--- a/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
+++ b/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
@@ -1,17 +1,17 @@
-#
-# Init - taken form the script openocd_at91sam7_ecr.script
-#
-# I take this script from the following page:
-#
-# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
-#
-mww 0xfffffd44 0x00008000 # disable watchdog
-mww 0xfffffd08 0xa5000001 # enable user reset
-mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator
-sleep 10
-mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz
-sleep 10
-mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-sleep 10
-mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60)
-sleep 100
+#
+# Init - taken form the script openocd_at91sam7_ecr.script
+#
+# I take this script from the following page:
+#
+# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
+#
+mww 0xfffffd44 0x00008000 # disable watchdog
+mww 0xfffffd08 0xa5000001 # enable user reset
+mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator
+sleep 10
+mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz
+sleep 10
+mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+sleep 10
+mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60)
+sleep 100