summaryrefslogtreecommitdiff
path: root/src/target/event/str912_reset.script
diff options
context:
space:
mode:
Diffstat (limited to 'src/target/event/str912_reset.script')
-rw-r--r--src/target/event/str912_reset.script1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script
index 8178c82c..bbec5976 100644
--- a/src/target/event/str912_reset.script
+++ b/src/target/event/str912_reset.script
@@ -18,4 +18,5 @@ mww 0x54000018, 0x18 #Enable CS on both banks
mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
+str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off