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-rw-r--r--src/target/arm11.c9
-rw-r--r--src/target/arm11.h1
-rw-r--r--src/target/arm720t.c1
-rw-r--r--src/target/arm7_9_common.c62
-rw-r--r--src/target/arm7tdmi.c1
-rw-r--r--src/target/arm920t.c1
-rw-r--r--src/target/arm926ejs.c1
-rw-r--r--src/target/arm966e.c1
-rw-r--r--src/target/arm9tdmi.c1
-rw-r--r--src/target/armv4_5.c1
-rw-r--r--src/target/cortex_m3.c26
-rw-r--r--src/target/event/str912_reset.script1
-rw-r--r--src/target/feroceon.c1
-rw-r--r--src/target/target.c51
-rw-r--r--src/target/target.h26
-rw-r--r--src/target/target/readme.txt18
-rw-r--r--src/target/target/stm32.cfg2
-rw-r--r--src/target/xscale.c10
18 files changed, 116 insertions, 98 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c
index d459dbb0..adcbe749 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -72,7 +72,6 @@ target_type_t arm11_target =
ARM11_HANDLER(assert_reset),
ARM11_HANDLER(deassert_reset),
ARM11_HANDLER(soft_reset_halt),
- ARM11_HANDLER(prepare_reset_halt),
ARM11_HANDLER(get_gdb_reg_list),
@@ -1025,12 +1024,6 @@ int arm11_soft_reset_halt(struct target_s *target)
return ERROR_OK;
}
-int arm11_prepare_reset_halt(struct target_s *target)
-{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
-}
/* target register access for gdb */
@@ -1707,7 +1700,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (values[i] > arm11_coproc_instruction_limits[i])
{
- LOG_ERROR("Parameter %d out of bounds (%d max). %s",
+ LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
i + 2, arm11_coproc_instruction_limits[i],
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 818db766..faa93f58 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -193,7 +193,6 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
int arm11_assert_reset(struct target_s *target);
int arm11_deassert_reset(struct target_s *target);
int arm11_soft_reset_halt(struct target_s *target);
-int arm11_prepare_reset_halt(struct target_s *target);
/* target register access for gdb */
int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 118fff45..d364437a 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -63,7 +63,6 @@ target_type_t arm720t_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm720t_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 5c91e9c3..63767ae3 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -742,20 +742,18 @@ int arm7_9_assert_reset(target_t *target)
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
+
+ /* we can't know what state the target is in as we might e.g.
+ * be resetting after a power dropout, so we need to issue a tms/srst
+ */
- if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
- {
- /* if the target wasn't running, there might be working areas allocated */
- target_free_all_working_areas(target);
-
- /* assert SRST and TRST */
- /* system would get ouf sync if we didn't reset test-logic, too */
- jtag_add_reset(1, 1);
-
- jtag_add_sleep(5000);
-
- }
+ /* assert SRST and TRST */
+ /* system would get ouf sync if we didn't reset test-logic, too */
+ jtag_add_reset(1, 1);
+ jtag_add_sleep(5000);
+
+ /* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
@@ -764,8 +762,13 @@ int arm7_9_assert_reset(target_t *target)
jtag_add_reset(0, 1);
}
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
+
+ /* at this point we TRST *may* be deasserted */
+ arm7_9_prepare_reset_halt(target);
+
armv4_5_invalidate_core_regs(target);
@@ -908,31 +911,11 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int arm7_9_prepare_reset_halt(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
- /* poll the target, and resume if it was currently halted */
- arm7_9_poll(target);
- if (target->state == TARGET_HALTED)
+ if ((target->reset_mode!=RESET_HALT)&&(target->reset_mode!=RESET_INIT))
{
- arm7_9_resume(target, 1, 0x0, 0, 1);
- }
-
- if (arm7_9->has_vector_catch)
- {
- /* program vector catch register to catch reset vector */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
- }
- else
- {
- /* program watchpoint unit to match on reset vector address */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+ return ERROR_OK;
}
-
- return ERROR_OK;
+ return arm7_9_halt(target);
}
int arm7_9_halt(target_t *target)
@@ -961,15 +944,6 @@ int arm7_9_halt(target_t *target)
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
- else
- {
- /* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in arm7_9_prepare_reset_halt()
- */
- target->debug_reason = DBG_REASON_DBGRQ;
-
- return ERROR_OK;
- }
}
if (arm7_9->use_dbgrq)
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index d0cebfe4..35902ba6 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -68,7 +68,6 @@ target_type_t arm7tdmi_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 2468202f..ae8814e5 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -72,7 +72,6 @@ target_type_t arm920t_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 46360230..14cd674a 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -72,7 +72,6 @@ target_type_t arm926ejs_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 0201ca56..84c55cf4 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -63,7 +63,6 @@ target_type_t arm966e_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 9811aeda..4a4b9a1c 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -66,7 +66,6 @@ target_type_t arm9tdmi_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index dfd38ebe..0b6b3457 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -504,6 +504,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
int exit_breakpoint_size = 0;
int i;
int retval = ERROR_OK;
+ LOG_DEBUG("Running algorithm");
if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
{
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index aa674745..406a00af 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -70,7 +70,6 @@ target_type_t cortexm3_target =
.assert_reset = cortex_m3_assert_reset,
.deassert_reset = cortex_m3_deassert_reset,
.soft_reset_halt = cortex_m3_soft_reset_halt,
- .prepare_reset_halt = cortex_m3_prepare_reset_halt,
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
@@ -202,9 +201,6 @@ int cortex_m3_endreset_event(target_t *target)
}
swjdp_transaction_endcheck(swjdp);
- /* Make sure working_areas are all free */
- target_free_all_working_areas(target);
-
/* We are in process context */
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
armv7m_invalidate_core_regs(target);
@@ -704,6 +700,7 @@ int cortex_m3_assert_reset(target_t *target)
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int retval;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
@@ -712,7 +709,10 @@ int cortex_m3_assert_reset(target_t *target)
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
-
+ /* FIX!!! should this be removed as we're asserting trst anyway? */
+ if ((retval=cortex_m3_prepare_reset_halt(target))!=ERROR_OK)
+ return retval;
+
ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
if (target->reset_mode == RESET_RUN)
@@ -720,7 +720,7 @@ int cortex_m3_assert_reset(target_t *target)
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT );
-
+
cortex_m3_clear_halt(target);
/* Enter debug state on reset, cf. end_reset_event() */
@@ -730,10 +730,10 @@ int cortex_m3_assert_reset(target_t *target)
if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
{
- /* assert SRST and TRST */
- /* system would get ouf sync if we didn't reset test-logic, too */
- jtag_add_reset(1, 1);
- jtag_add_sleep(5000);
+ /* assert SRST and TRST */
+ /* system would get ouf sync if we didn't reset test-logic, too */
+ jtag_add_reset(1, 1);
+ jtag_add_sleep(5000);
}
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -747,6 +747,12 @@ int cortex_m3_assert_reset(target_t *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
+ #if 0
+ if ((target->reset_mode==RESET_HALT)||(target->reset_mode==RESET_INIT))
+ {
+ cortex_m3_halt(target);
+ }
+ #endif
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
armv7m_invalidate_core_regs(target);
diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script
index 8178c82c..bbec5976 100644
--- a/src/target/event/str912_reset.script
+++ b/src/target/event/str912_reset.script
@@ -18,4 +18,5 @@ mww 0x54000018, 0x18 #Enable CS on both banks
mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
+str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index bad110e0..0c1d46da 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -76,7 +76,6 @@ target_type_t feroceon_target =
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
diff --git a/src/target/target.c b/src/target/target.c
index f098ef34..f90834d1 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -284,21 +284,16 @@ int target_process_reset(struct command_context_s *cmd_ctx)
break;
}
}
- switch (target->reset_mode)
- {
- case RESET_HALT:
- case RESET_INIT:
- target->type->prepare_reset_halt(target);
- break;
- default:
- break;
- }
target = target->next;
}
target = targets;
while (target)
{
+ /* we have no idea what state the target is in, so we
+ * have to drop working areas
+ */
+ target_free_all_working_areas_restore(target, 0);
target->type->assert_reset(target);
target = target->next;
}
@@ -343,6 +338,8 @@ int target_process_reset(struct command_context_s *cmd_ctx)
}
jtag_execute_queue();
+ LOG_DEBUG("Waiting for halted stated as approperiate");
+
/* Wait for reset to complete, maximum 5 seconds. */
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 5, 0);
@@ -355,14 +352,18 @@ int target_process_reset(struct command_context_s *cmd_ctx)
target = targets;
while (target)
{
+ LOG_DEBUG("Polling target");
target->type->poll(target);
- if ((target->reset_mode == RESET_RUN_AND_INIT) || (target->reset_mode == RESET_RUN_AND_HALT))
+ if ((target->reset_mode == RESET_RUN_AND_INIT) ||
+ (target->reset_mode == RESET_RUN_AND_HALT) ||
+ (target->reset_mode == RESET_HALT) ||
+ (target->reset_mode == RESET_INIT))
{
if (target->state != TARGET_HALTED)
{
if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec)))
{
- LOG_USER("Timed out waiting for reset");
+ LOG_USER("Timed out waiting for halt after reset");
goto done;
}
/* this will send alive messages on e.g. GDB remote protocol. */
@@ -384,6 +385,16 @@ int target_process_reset(struct command_context_s *cmd_ctx)
/* We want any events to be processed before the prompt */
target_call_timer_callbacks_now();
+ /* if we timed out we need to unregister these handlers */
+ target = targets;
+ while (target)
+ {
+ target_unregister_timer_callback(target_run_and_halt_handler, target);
+ target = target->next;
+ }
+ target_unregister_event_callback(target_init_handler, cmd_ctx);
+
+
jtag->speed(jtag_speed_post_reset);
return retval;
@@ -722,12 +733,12 @@ int target_alloc_working_area(struct target_s *target, u32 size, working_area_t
return ERROR_OK;
}
-int target_free_working_area(struct target_s *target, working_area_t *area)
+int target_free_working_area_restore(struct target_s *target, working_area_t *area, int restore)
{
if (area->free)
return ERROR_OK;
- if (target->backup_working_area)
+ if (restore&&target->backup_working_area)
target->type->write_memory(target, area->address, 4, area->size / 4, area->backup);
area->free = 1;
@@ -739,14 +750,19 @@ int target_free_working_area(struct target_s *target, working_area_t *area)
return ERROR_OK;
}
-int target_free_all_working_areas(struct target_s *target)
+int target_free_working_area(struct target_s *target, working_area_t *area)
+{
+ return target_free_working_area_restore(target, area, 1);
+}
+
+int target_free_all_working_areas_restore(struct target_s *target, int restore)
{
working_area_t *c = target->working_areas;
while (c)
{
working_area_t *next = c->next;
- target_free_working_area(target, c);
+ target_free_working_area_restore(target, c, restore);
if (c->backup)
free(c->backup);
@@ -761,6 +777,11 @@ int target_free_all_working_areas(struct target_s *target)
return ERROR_OK;
}
+int target_free_all_working_areas(struct target_s *target)
+{
+ return target_free_all_working_areas_restore(target, 1);
+}
+
int target_register_commands(struct command_context_s *cmd_ctx)
{
register_command(cmd_ctx, NULL, "target", handle_target_command, COMMAND_CONFIG, NULL);
diff --git a/src/target/target.h b/src/target/target.h
index fa83949b..6ce8fee9 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -121,11 +121,19 @@ typedef struct target_type_s
int (*resume)(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int (*step)(struct target_s *target, int current, u32 address, int handle_breakpoints);
- /* target reset control */
+ /* target reset control. assert reset can be invoked when OpenOCD and
+ * the target is out of sync.
+ *
+ * A typical example is that the target was power cycled while OpenOCD
+ * thought the target was halted or running.
+ *
+ * assert_reset() can therefore make no assumptions whatsoever about the
+ * state of the target
+ *
+ */
int (*assert_reset)(struct target_s *target);
int (*deassert_reset)(struct target_s *target);
int (*soft_reset_halt)(struct target_s *target);
- int (*prepare_reset_halt)(struct target_s *target);
/* target register access for gdb.
*
@@ -258,9 +266,23 @@ extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u
extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_checksum_memory(struct target_s *target, u32 address, u32 size, u32* crc);
+/* DANGER!!!!!
+ *
+ * if "area" passed in to target_alloc_working_area() points to a memory
+ * location that goes out of scope (e.g. a pointer on the stack), then
+ * the caller of target_alloc_working_area() is responsible for invoking
+ * target_free_working_area() before "area" goes out of scope.
+ *
+ * target_free_all_working_areas() will NULL out the "area" pointer
+ * upon resuming or resetting the CPU.
+ *
+ */
extern int target_alloc_working_area(struct target_s *target, u32 size, working_area_t **area);
extern int target_free_working_area(struct target_s *target, working_area_t *area);
+extern int target_free_working_area_restore(struct target_s *target, working_area_t *area, int restore);
extern int target_free_all_working_areas(struct target_s *target);
+extern int target_free_all_working_areas_restore(struct target_s *target, int restore);
+
extern target_t *targets;
diff --git a/src/target/target/readme.txt b/src/target/target/readme.txt
new file mode 100644
index 00000000..b8bf5dcf
--- /dev/null
+++ b/src/target/target/readme.txt
@@ -0,0 +1,18 @@
+Prerequisites:
+The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
+do the same thing across all the targets.
+
+Rules to follow when writing scripts:
+
+1. The configuration script should be defined such as , for example, the following sequences are working:
+ reset
+ flash info <bank>
+and
+ reset
+ flash erase_address <start> <len>
+
+In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
+in the configuration file).
+
+2. If the target is correctly configured, flash must be writable without any other helper commands. It is
+assumed that all write-protect mechanisms should be disabled.
diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
index 68c42e5b..0cffeb1d 100644
--- a/src/target/target/stm32.cfg
+++ b/src/target/target/stm32.cfg
@@ -11,7 +11,7 @@ jtag_device 5 0x1 0x1 0x1e
#target <type> <startup mode>
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
-target cortex_m3 little reset_halt 0
+target cortex_m3 little reset_init 0
run_and_halt_time 0 30
working_area 0 0x20000000 16384 nobackup
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 89ecc265..1d379f59 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -64,7 +64,6 @@ int xscale_restore_context(target_t *target);
int xscale_assert_reset(target_t *target);
int xscale_deassert_reset(target_t *target);
int xscale_soft_reset_halt(struct target_s *target);
-int xscale_prepare_reset_halt(struct target_s *target);
int xscale_set_reg_u32(reg_t *reg, u32 value);
@@ -105,7 +104,6 @@ target_type_t xscale_target =
.assert_reset = xscale_assert_reset,
.deassert_reset = xscale_deassert_reset,
.soft_reset_halt = xscale_soft_reset_halt,
- .prepare_reset_halt = xscale_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
@@ -1780,14 +1778,6 @@ int xscale_soft_reset_halt(struct target_s *target)
return ERROR_OK;
}
-int xscale_prepare_reset_halt(struct target_s *target)
-{
- /* nothing to be done for reset_halt on XScale targets
- * we always halt after a reset to upload the debug handler
- */
- return ERROR_OK;
-}
-
int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
{
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-27 14:37:51 +0000