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path: root/src/target/arm920t.c
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* Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixesFreddie Chopin2011-06-041-10/+0
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* types: write memory now uses constØyvind Harboe2011-04-011-2/+2
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add missing error reportingØyvind Harboe2010-08-111-0/+12
| | | | | | | when an unknown core mode is read from the target, report error. Can be communication failure. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_jtag_scann error propagation fixesØyvind Harboe2010-07-201-3/+9
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: error propagation of arm_jtag_set_instrØyvind Harboe2010-07-191-3/+11
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug: debug entry error propagationØyvind Harboe2010-07-191-12/+36
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation for enable/disable mmu cachesØyvind Harboe2010-07-191-8/+20
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation to generic get_ttb fnØyvind Harboe2010-07-191-2/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm920t: -Wshadow warning fixesØyvind Harboe2010-06-151-11/+12
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* TARGET: removed unused parametersAntonio Borneo2010-06-121-6/+2
| | | | | | | Parameters "domain" and "ap" of function armv4_5_mmu_translate_va() are not used. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET: removed unsed parameterAntonio Borneo2010-06-121-4/+2
| | | | | | | | Parameter "type" of function armv4_5_mmu_translate_va() is now not used. Remove the parameter and the "enum" listing its values. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET: fix handling return code of MMU translationAntonio Borneo2010-06-121-6/+0
| | | | | | | | | Function armv4_5_mmu_translate_va() now properly signals errors in the return value. Remove former error handling by setting variable "type" to value "-1". Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET/ARM920T: fix return valueAntonio Borneo2010-06-121-1/+1
| | | | | | | | | Function arm920t_write_memory() default return value should be ERROR_OK. All cases of local errors are handled immediately and not further propagated. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET/ARM920T: fix compile warningAntonio Borneo2010-06-121-1/+1
| | | | | | | | | Commit 0538081246fafbfb74d554bb1b758412534aa254 introduces a compile time warning: arm920t.c: In function ‘arm920t_write_memory’: arm920t.c:567: warning: ‘retval’ may be used uninitialized in this function Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* arm mmu: error propagation added for address translationØyvind Harboe2010-06-111-4/+9
| | | | | | | The return value for MMU translation was a mess, either error or value. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM920T: review scope of functionsAntonio Borneo2010-04-101-1/+1
| | | | | | Add "static" qualifier to private functions. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* arm breakpoints: amended fix commentØyvind Harboe2010-03-211-1/+5
| | | | | | | | the handling of caches, should be moved into the breakpoint specific callbacks rather than being plonked into generic memory write fn's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire jtag_get/set_end_state()Øyvind Harboe2010-03-191-3/+0
| | | | | | | Voila! This get rids of mysteries about what what state the TAP is in. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire one instance of jtag_get_end_state() usageØyvind Harboe2010-03-181-6/+6
| | | | | | Less global variables.... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: cut down on usage of unintended modification of global end stateØyvind Harboe2010-03-181-4/+4
| | | | | | | | | | | | | jtag_get/set_end_state() is now deprecated. There were lots of places in the code where the end state was unintentionally modified. The big Q is whether there were any places where the intention was to modify the end state. 0.5 is a long way off, so we'll get a fair amount of testing. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire tap fieldØyvind Harboe2010-03-081-16/+4
| | | | | | | | | | | | | | | | | jtag_add_dr/ir_scan() now takes the tap as the first argument, rather than for each of the fields passed in. The code never exercised the path where there was more than one tap being scanned, who knows if it even worked. This simplifies the implementation and reduces clutter in the calling code. use jtag_add_ir/dr_plain_scan() for more fancy situations. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: keep a handle to the PCDavid Brownell2010-02-211-3/+3
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm920t line length cleanupDavid Brownell2010-02-201-115/+247
| | | | | | | | | | | | The recent patch to fixbreakpoints and dcache handling added a bunch of overlong lines (80+ chars) ... shrink them, and do the same to a few lines which were already overlong. Also add a few FIXME comments to nudge (a) replacement of some magic numbers with opcode macros, which will be much better at showing what's actually going on, and (b) correct return codes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* atm920t : fix breakpoints and data cache handlingMarc Pignat2010-02-191-17/+103
| | | | | | | | | Breakpoints did not work because the data cache was not flushed properly. As a bonus add capability to write to memory marked as read only by the MMU, which allows software breakpoints in such memory regions.
* ARM920T scanchain 15 comments/cleanupDavid Brownell2010-02-161-51/+112
| | | | | | | | | | | | | | | | | For folk who don't know the ARM920 JTAG interface very well, the two modes of scan chain 15 access to CP15 are confusing. Make those parts of the ARM920 code less opaque, by: - Adding comments referencing the relevant parts of the TRM, catching up to similar updates in the User's Guide. - Replacing magic numbers in physical access clients with symbolic equivalents. No functional change. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm920: add virt2phys fnMarc Pignat2010-02-121-3/+13
| | | | | | | Copy of the 926ejs function. I have tested it only using my rtems application (where virtual address mapping == physical). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: enable check that DCC downloads have been enabledØyvind Harboe2010-01-131-0/+1
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM720: help/usage updatesDavid Brownell2010-01-071-10/+14
| | | | | | | | | | | | | Deprecate the "pass an instruction opcode" flavor of cp15 access in favor of the "arm mcr ..." and "arm mrc ..." commands, which offer fewer ways to break things. Use the same EBNF syntax in the code as for the user's guide. Update User's Guide to say where to find those magic values (which table in the ARM920 TRM). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: don't clone arm_arch_state() codeDavid Brownell2009-12-071-8/+2
| | | | | | | | | | | Have various ARM cores delegate to arm_arch_state() to display basic information, instead of duplicating that logic. This shrinks the code, makes them all report when semihosting is active, and highlights which data are specific to this core. (Like ARM720 not having separate instruction and data caches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-071-1/+1
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-0/+1
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell2009-12-071-4/+16
| | | | | | | | | | | | Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: switch target_to_armv4_5() to target_to_arm()David Brownell2009-12-041-2/+2
| | | | | | And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_state_* as arm_state_*David Brownell2009-12-041-1/+1
| | | | | | And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* change #include "time_support.h" to <helper/time_support.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-011-2/+13
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-9/+5
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* arm920t: use register_commands()Zachary T Welch2009-11-241-27/+47
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-6/+6
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* ARM: use arm_reg_current()David Brownell2009-11-221-26/+40
| | | | | | | | | | Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-6/+6
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-221-1/+0
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-5/+7
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-4/+4
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add is_arm_mode()David Brownell2009-11-171-4/+4
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-1/+1
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-28/+28
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-10/+10
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-9/+9
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* ARM9TDMI: remove now-needless "struct arm9tdmi"David Brownell2009-11-171-9/+7
| | | | | | | And move the rest of the vector_catch stuff into the C file; it's not part of the module interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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