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* ARM: simplify CPSR handlingDavid Brownell2009-11-221-1/+1
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't include "log.h" from "armv4_5.h"David Brownell2009-11-161-0/+1
| | | | | | | No point in multiple includes, and that file doesn't use its functions any more. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "command.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target_t -> struct targetZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct target.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-8/+8
| | | | Remove misleading typedef and just use struct arm.
* arm_instruction_t -> struct arm_instructionZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct arm_instruction.
* ARM: minor simulator cleanupDavid Brownell2009-11-081-25/+49
| | | | | | | | Make several functions be static. Shrink some of the overlong lines. Use pure tab indents in some places that mixed in spaces. This gives a minor object code shrink (about 2% on amd64). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: other code uses the new inheritance/nesting schemeDavid Brownell2009-11-051-12/+10
| | | | | | | Remove most remaining uses of target->arch_info from ARM infrastructure, where it hasn't already been updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix single-step of Thumb unconditional branchNicolas Pitre2009-10-271-2/+2
| | | | | | | | | Only type 1 branch instruction has a condition code, not type 2. Currently they're both tagged with ARM_B which doesn't allow for the distinction. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix Thumb mode handling when single-stepping register based branch insnsNicolas Pitre2009-10-261-22/+33
| | | | | | | | | | | | | | | | | | | Currently, OpenOCD is always caching the PC value without the T bit. This means that assignment to the PC register must clear that bit and set the processor state to Thumb when it is set. And when the PC register value is transferred to another register or stored into memory then the T bit must be restored. Discussion: It is arguable if OpenOCd should have preserved the original PC value which would have greatly simplified this code. The processor state could then be obtained simply by getting at bit 0 of the PC. This however would require special handling elsewhere instead since the T bit is not always relevant (like when PC is used with ALU insns or as an index with some addressing modes). It is unclear which way would be simpler in the end. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: allow proper single stepping of Thumb BL and BLX instructionsNicolas Pitre2009-10-261-0/+12
| | | | | | | | | | | | | | Whenever an unconditional branch with the H bits set to 0b10 is met, the offset must be combined with the offset from the following opcode and not ignored like it is now. A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder would be a simpler solution. That might be true when single-stepping of Thumb2 code is implemented. But for now this appears to be the simplest solution to fix Thumb1 support. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: call thumb_pass_branch_condition() only for actual branch opcodesNicolas Pitre2009-10-261-8/+6
| | | | | | | | | | | | | | Calling it first with every opcodes and then testing if the opcode was indeed a branch instruction is wasteful and rather strange. If ever thumb_pass_branch_condition() has side effects (say, like printing a debugging traces) then the result would be garbage for most Thumb instructions which have no condition code. While at it, let's make the nearby code more readable by reducing some of the redundant brace noise and reworking the error handling construct. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix single step of bx instruction going into Thumb modeNicolas Pitre2009-10-191-1/+1
| | | | | | | | Without this fix, the following code cannot be single stepped: add ip, pc, #1 bx ip [thumb code here]
* fix pass_condition() LE condition code checkLennert Buytenhek2009-10-131-3/+3
| | | | | | | | The LE check is obviously buggy (as easily triggered during some testing), but I didn't audit the rest of the cases. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe2009-08-271-48/+129
| | | | | | changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace at end of lines, step 1.zwelch2009-06-231-57/+57
| | | | | | | - Replace '\s*$' with ''. git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Replace 'if(' with 'if ('.zwelch2009-06-231-8/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2357 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u32' to 'uint32_t' in src/target/arm*zwelch2009-06-181-24/+24
| | | | | | | | - Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2278 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u16' to 'uint16_t'zwelch2009-06-181-2/+2
| | | | | | | | - Replace '\([^_]\)u16' with '\1uint16_t'. - Replace '^u16' with 'uint16_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2277 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u8' to 'uint8_t' in src/targetzwelch2009-06-181-7/+7
| | | | | | | | - Replace '\([^_]\)u8' with '\1uint8_t'. - Replace '^u8' with 'uint8_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2274 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audit and eliminate redundant #include directives in arm target files.zwelch2009-05-111-2/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1714 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Solve problem with single stepping.mlu2009-04-141-1/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1455 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Hongtao Zheng - fix a simulation error for "BX PC"oharboe2008-10-281-0/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1109 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* hontor <hontor@126.com> - fix simulation step errorsoharboe2008-10-231-3/+9
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1097 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Laurentiu Cocanu - add error handlingoharboe2008-10-141-5/+21
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1057 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - rename log functions to stop conflicts under win32 (wingdi)ntfreak2008-03-251-5/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - removed warnings "xxxxx" might be used uninitialized in this function ↵mifi2008-03-011-2/+2
| | | | | | | | (arm_simulator.c) - some cosmetic changes git-svn-id: svn://svn.berlios.de/openocd/trunk@423 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - debug handler file not closed - (thanks to oyvind harboe for the patch)ntfreak2008-01-111-3/+6
| | | | | | - arm_simulate_step called incorrect arm_evaluate_opcode when in thumb mode git-svn-id: svn://svn.berlios.de/openocd/trunk@254 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - split fileio handling into fileio part and image handlingdrath2007-05-291-14/+36
| | | | | | | | | | | - reworked etm/etb into a generic etm part with trace capture drivers (currently only etb supported) - added XScale debug handler binary to repository - added Thumb disassembling (thanks to Vincent Palatin for this patch) - added support for non-CFI compatible flashes to cfi driver (currently only SST39VFxxx devices supported) This checkin is experimental, not suitable for general use git-svn-id: svn://svn.berlios.de/openocd/trunk@155 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - merged XScale branch back into trunkdrath2007-03-281-0/+684
- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c - free working area and register stuff if str7x block write algorithm failed - check PC after exiting a target algorithm in armv4_5.c git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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