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* Remove srst_pulls_trst from LPC1768 targetPeter Stuge2010-10-251-3/+0
| | | | | | | srst_pulls_trst may be true on some (broken) LPC1768 boards but is not true in general for the LPC1768. Signed-off-by: Peter Stuge <peter@stuge.se>
* swj-dp.tcl (SWD infrastructure #1)David Brownell2010-10-101-1/+6
| | | | | | | | | | | | | | | | | | | | Provide new helper proc that can set up either an SWD or JTAG DAP based on the transport which is in use -- mostly for SWJ-DP. Also update some SWJ-DP based chips/targets to use it. The goal is making SWD-vs-JTAG transparent in most places. SWJ-DP based chips really need this flexible configuration to cope with debug adapters that support different transports, without needing new target configs for each transport or adapter. For JTAG-DP, callers will use "jtag newtap" directly, as today; only one chip-level transport option exists. For SW-DP (e.g. LPC1[13]xx or EFM32, they'll use "swd newdap" directly (part of an upcoming SWD transport patch). Again, only one transport option exists, so hard-wiring is appropriate there. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* mcb1700: Keil MCB1700 w/1768 config scriptØyvind Harboe2010-08-171-12/+4
| | | | | | Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* lpc1768: turn down the jtag clockØyvind Harboe2010-08-131-7/+9
| | | | | | | Tests should that it needs to be as low as 100kHz to be stable. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* lpc1768: even if rclk "works", it isn't necessarily the correct clkØyvind Harboe2010-08-021-2/+6
| | | | | | rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* lpc7168: make flash available upon reset initØyvind Harboe2010-07-301-0/+19
| | | | | | | set user mode to avoid ROM being mapped at address 0 rather than flash. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Update "flash bank" helper comments for LPC2xxx chipsFreddie Chopin2010-05-241-0/+1
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* rename jtag_nsrst_delay as adapter_nsrst_delayDavid Brownell2010-03-151-1/+1
| | | | | | | | | | | Globally rename "jtag_nsrst_delay" as "adapter_nsrst_delay", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC1768 updates, IAR board supportDavid Brownell2010-03-021-25/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC1768.cfg -- partial fixes for bogus reset-init handlerDavid Brownell2010-02-151-4/+4
| | | | | | | | | Cortex-M targets don't support ARM instructions. Leave the NVIC.VTOR setup alone, but comment how the whole routine looks like one big bug... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* update 'flash bank' usage in scriptsZachary T Welch2009-11-191-1/+2
| | | | | Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-161-1/+1
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: remove "-work-area-virt 0"David Brownell2009-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: use $_TARGETNAME for flashFreddie Chopin2009-10-311-1/+1
| | | | | | | | | This gets rid of runtime warnings from the use of numbers. STM32 and LPC2103 were tested. Other LPC updates are the same, and so are safe. The CFI updates match other tested changes now in the tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use "armv4_5 core_state arm" instead of soft_reset_halt, fewer side effectsoharboe2009-09-041-1/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2672 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> "set _TARGETNAME ..." cleanupoharboe2009-09-041-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2665 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audrius Urmanavičius [didele.deze@gmail.com]:ntfreak2009-08-131-0/+49
Add flash programming support for NXP LPC1700 cortex_m3 based family git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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