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* TCL scripts: fix ocd_mem2array/mem2arrayAntonio Borneo2010-09-281-1/+1
| | | | | | | | In previous patch, I have introduced again the symbol "ocd_mem2array", now replaced by "mem2array". Fix the error. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* Fix omap3_dbginit to write to physical memory.Zachary T Welch2010-09-261-1/+1
| | | | | Setting the OMAP3530 DBGEN bit must be done in physical memory, so update omap3_dbginit callback to use the new 'mww phys' command syntax.
* TCL scripts: collect duplicated proceduresAntonio Borneo2010-09-214-35/+25
| | | | | | | | TCL procedures mrw and mmw, originally in DaVinci target code, are duplicated in other TCL scripts. Moved in a common helper file, and added help/usage description. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* tcl: remove incomplete unused tcl fileØyvind Harboe2010-09-201-24/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* AM/DM37x: Unify configuration scripts and add support for TI Beagleboard xM.Karl Kurbjun2010-09-203-82/+221
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* board scripts: Marvell PXA270M processor has a new TAPID: 0x89265013Takács Áron2010-09-142-1/+20
| | | | | | | | | | the new Marvell PXA270M processor has a new TAPID: 0x89265013. Attached you will find a patch for target/pxa270.cfg that will handle this. I have also attached a board/colibri.cfg file to support the Colibri PXA270 module by Toradex. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex m3: add cortex_m3 reset_config cmdSpencer Oliver2010-08-311-6/+37
| | | | | | | | | | | | This new cmd adds the ability to choose the Cortex-M3 reset method used. It defaults to using SRST for reset if available otherwise it falls back to using NVIC VECTRESET. This is known to work on all cores. Move any luminary specific reset handling to the stellaris cfg file. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* cfg: update Luminary config filesSpencer Oliver2010-08-319-105/+36
| | | | | | | | - Update all Luminary config's to use a common target/stellaris.cfg. - Add Luminary ek-lm3s6965 config. - Increase working area for boards with more ram. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* imx35pdk: fix clock and reset delaysØyvind Harboe2010-08-192-0/+5
| | | | | | Use rclk and 100ms delay on ntrst Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mcb1700: Keil MCB1700 w/1768 config scriptØyvind Harboe2010-08-172-12/+79
| | | | | | Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* update more Stellaris EK board commentsDavid Brownell2010-08-162-0/+4
| | | | | | | Using the bundled JTAG/SWD debug support in JTAG mode is optional on *all* of the EK boards. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Update comments for some Stellaris EK boards.David Brownell2010-08-162-1/+3
| | | | | | | These don't need to use the on-board debuggers in JTAG mode. Off-board is OK, as would be SWD mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* avr32: basic target scriptOleksandr Tymoshenko2010-08-151-0/+18
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* at32ap7000 config fileDavid Brownell2010-08-151-0/+16
| | | | nice board to play with.
* lpc1768: turn down the jtag clockØyvind Harboe2010-08-131-7/+9
| | | | | | | Tests should that it needs to be as low as 100kHz to be stable. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Added Lisa/L script as a target board.Piotr Esden-Tempski2010-08-131-0/+7
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* Added support for Lisa/L builtin JTAG interface.Piotr Esden-Tempski2010-08-131-0/+11
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* at91cap7a-stk-sdram.cfg: faster resetØyvind Harboe2010-08-121-5/+5
| | | | | | crank up JTAG speed as soon as clocks are set up. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* DM36x: Set OSCDIV dividerThomas Koeller2010-08-121-0/+7
| | | | | | The ability to set up the OSCDIV divider was missing. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
* DM36x: Disable unused SYSCLKsThomas Koeller2010-08-121-1/+20
| | | | | | | | Clear the enable bits for all clocks that are not set explicitly. This is done to increase robustness by removing pre-existing state. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
* DM36x: Use enable bit for PLL pre-dividerThomas Koeller2010-08-121-1/+1
| | | | | | | The PLL pre- and postdividers seem to have enable bits, although these are not mentioned in the chip documentation. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
* tcl: remove silly ocd_ prefix to array2mem and mem2arrayØyvind Harboe2010-08-116-15/+15
| | | | | | | | ocd_ prefix is used internally in OpenOCD as a kludge more or less to deal with the two kinds of commands that OpenOCD has. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* board: added at91cap7a stk w/sdram config scriptsØyvind Harboe2010-08-111-0/+165
| | | | | | | The strange thing here with this board is that 16MHz kinda works, but only 2MHz is really stable. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* config scripts: remove useless reference to OpenOCD docsØyvind Harboe2010-08-1110-30/+0
| | | | | | clutters config scripts. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: add omapl138 support and da850evm preliminary supportBen Gardiner2010-08-102-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the omapl138 target and preliminary support for the da850evm. The target cfg file is based on the icepick routing done by the target/ti_dm6446.cfg file. I have performed limited testing with this setup. I am posting this patch in the interest of sharing cfg files and in the hopes that the experts on this list can correct errors I have made or point out enhancements. The testing I have performed is debugging uboot with gdb where I also use the following local.cfg and gdbinit files. Debugging appears to work in so much as 'ni' works. local.cfg: gdb_memory_map disable gdbinit: target remote localhost:3333 set remote hardware-breakpoint-limit 2 set remote hardware-watchpoint-limit 2 monitor poll on Comments welcome. Best Regards, Ben Gardiner
* Luminary-icdi comment updateDavid Brownell2010-08-031-0/+4
| | | | | | | Clarify that ICDI is the generic logic, but this config is for the JTAG-only (no-SWD) mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* lpc1768: even if rclk "works", it isn't necessarily the correct clkØyvind Harboe2010-08-021-2/+6
| | | | | | rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Support NGX Technologies product NGX ARM USB JTAGPeter Stuge2010-08-011-0/+6
| | | | | This is a standard FT2232 device. More info at their web page: http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
* Remove srst_pulls_trst from LPC2148 targetPeter Stuge2010-08-011-1/+1
| | | | | | | | | srst_pulls_trst is only true on some (broken) LPC2148 boards, a fact which is already documented in doc/openocd.texi, so it shouldn't be set unconditionally in the target tcl. This patch was needed to reflash when an Abort exception occured very early after reset, before OpenOCD tried to halt the CPU.
* lpc7168: make flash available upon reset initØyvind Harboe2010-07-301-0/+19
| | | | | | | set user mode to avoid ROM being mapped at address 0 rather than flash. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: add Amontec JTAGkey2p interface config (Issue #26)Spencer Oliver2010-07-191-0/+11
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* flash: add nuc910 nand driverSpencer Oliver2010-07-191-0/+3
| | | | | | | | This adds a nand driver support for the nuc910 target. Note that ECC is not currently supported by this driver, although it is supported by the peripheral. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* cfg: update rsc-w910 scriptSpencer Oliver2010-07-191-1/+2
| | | | | | | - Only enable the FMI (NAND) and DMA clocks. - Select NAND interface on the MFSEL. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* lm3s811-ek uses generic stellaris target configDavid Brownell2010-07-172-32/+4
| | | | | | | There's no point in an lm3s811-specific target file, so remove it in favor of the generic "stellaris.cfg". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* cfg: add Avalue RSC-W910 configSpencer Oliver2010-07-132-0/+89
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* at91sam3s* supportOlaf Lüke2010-06-254-36/+76
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* am3517 evm: use physical write to memory while target is runningØyvind Harboe2010-06-221-3/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* board: add alpha am3517evm ti board config fileØyvind Harboe2010-06-221-0/+97
| | | | | | | Signs of life: reset(kinda), halt, resume and memory display/modify. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* DM36x: pll & clock setupThomas Koeller2010-06-151-0/+127
| | | | | | | | Added a function 'pll_v03_setup' to set up PLLs and clock dividers on DM365 and DM368. Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm1136 scriptsmichal smulski2010-06-151-1/+2
| | | | | | | | | Here is a patch to fix a startup in C100 (arm1136). Basically make sure that UART is configured before using it. Michal Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: add pic32 virtual banksSpencer Oliver2010-05-261-0/+7
| | | | | | make use of the new virtual bank flash driver. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* There are no variants of arm7tdmi targetFreddie Chopin2010-05-247-7/+7
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* All LPC2xxx chips are little endian and that cannot be changed - update ↵Freddie Chopin2010-05-247-53/+8
| | | | | | config scripts Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* add correct CPUTAPID value for LPC2129Freddie Chopin2010-05-241-6/+2
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Update "flash bank" helper comments for LPC2xxx chipsFreddie Chopin2010-05-248-7/+8
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* LPC23xx and LPC24xx after reset run on internal 4MHz RC oscillator, so ↵Freddie Chopin2010-05-241-1/+1
| | | | | | "flash bank" parameter should be 4000 (not 12000) Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* at91sam9260: use RCLKØyvind Harboe2010-05-211-19/+12
| | | | | | | | | | | | | It might be possible to get this target going without RCLK, but it would require more careful analysis and usage of the reset events. Enable fast memory accesses. Tested on an at91sam9260 custom board w/external DRAM and flash. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: update stm32 performance stick configSpencer Oliver2010-05-211-1/+8
| | | | | | | | | - As this is a complete unit, including jtag we might as welli nclude the jtag cfg. - Add missing id for the str750 that is also in the jtag chain. - Reduce jtag startup speed to 500kHz. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* board: dm355evm.cfg SDTIMR0/1 minor naming fixJon Povey2010-05-211-1/+1
| | | | | | | Register name fix; ref. TI document sprueh7d Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* reset: fix reset halt bugGary Carlson2010-05-191-23/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was finally able to figure out the cause of this problem. There are two parts to the patch. The first patch modifies the configuration file I originally generated for the Atmel AT91SAM9G20 board and achieves the following: +++ Splits the reset-init handler into a reset-start handler for some of the initial configuration activities and keeps the remainder in the reset-init handler as was the case before. This was the real issue that was causing the timing problems I identified before. This solution was confirmed with an o-scope on actual target hardware. +++ Adds a new instruction in the reset-start handler to disable fast memory accesses in the reset-start handler. When the target jtag clock is started out at 2 kHz during system clock initialization, memory writes (i.e. register write to enable external reset pin -- basically to RSTC_MR) are naturally slow and cause GDB keep-alive issues (refer to PATCH 2/2 for additional fixes). +++ Modifies the configuration file to use srst_only reset action. The reset-start/reset-init handler split also now allows the correct behavior to be used in the configuration file (previously had to use both SRST and TRST even though only SRST is actually used and connected on the evaluation board). +++ Adds external NandFlash configuration support to take advantage of flash driver added earlier. Doesn't fix any bugs but adds functionality that was marked as TBD before and thrown in when I did other work on the configuration file. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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