| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch finally adds support for i.MX51 based Genesi USA EfikaMX smarttop
board.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.
i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acassis@gmail.com>.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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measure_clk indicates ca. 3-4MHz, so 1MHz should be safe.
Added self_test proc used to test that rclk worked.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Peter Stuge <peter@stuge.se>
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srst_pulls_trst may be true on some (broken) LPC1768 boards but is
not true in general for the LPC1768.
Signed-off-by: Peter Stuge <peter@stuge.se>
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Provide new helper proc that can set up either an SWD or JTAG DAP
based on the transport which is in use -- mostly for SWJ-DP.
Also update some SWJ-DP based chips/targets to use it. The goal
is making SWD-vs-JTAG transparent in most places. SWJ-DP based chips
really need this flexible configuration to cope with debug adapters
that support different transports, without needing new target configs
for each transport or adapter.
For JTAG-DP, callers will use "jtag newtap" directly, as today; only
one chip-level transport option exists.
For SW-DP (e.g. LPC1[13]xx or EFM32, they'll use "swd newdap" directly
(part of an upcoming SWD transport patch). Again, only one transport
option exists, so hard-wiring is appropriate there.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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In previous patch, I have introduced again the symbol
"ocd_mem2array", now replaced by "mem2array".
Fix the error.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Setting the OMAP3530 DBGEN bit must be done in physical memory, so
update omap3_dbginit callback to use the new 'mww phys' command syntax.
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TCL procedures mrw and mmw, originally in DaVinci target code,
are duplicated in other TCL scripts.
Moved in a common helper file, and added help/usage description.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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the new Marvell PXA270M processor has a new TAPID: 0x89265013.
Attached you will find a patch for target/pxa270.cfg that will handle this.
I have also attached a board/colibri.cfg file to support the Colibri
PXA270 module by Toradex.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This new cmd adds the ability to choose the Cortex-M3
reset method used.
It defaults to using SRST for reset if available otherwise
it falls back to using NVIC VECTRESET. This is known to work
on all cores.
Move any luminary specific reset handling to the stellaris cfg file.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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- Update all Luminary config's to use a common target/stellaris.cfg.
- Add Luminary ek-lm3s6965 config.
- Increase working area for boards with more ram.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Use rclk and 100ms delay on ntrst
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Using the bundled JTAG/SWD debug support in JTAG mode
is optional on *all* of the EK boards.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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These don't need to use the on-board debuggers in JTAG mode.
Off-board is OK, as would be SWD mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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nice board to play with.
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Tests should that it needs to be as low as 100kHz to be
stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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crank up JTAG speed as soon as clocks are set up.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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The ability to set up the OSCDIV divider was missing.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
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Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
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The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
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ocd_ prefix is used internally in OpenOCD as a kludge more
or less to deal with the two kinds of commands that OpenOCD
has.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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The strange thing here with this board is that 16MHz kinda
works, but only 2MHz is really stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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clutters config scripts.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This patch adds support for the omapl138 target and preliminary support for the da850evm. The
target cfg file is based on the icepick routing done by the target/ti_dm6446.cfg file.
I have performed limited testing with this setup. I am posting this patch in the interest of
sharing cfg files and in the hopes that the experts on this list can correct errors I have made or
point out enhancements.
The testing I have performed is debugging uboot with gdb where I also use the following local.cfg
and gdbinit files. Debugging appears to work in so much as 'ni' works.
local.cfg:
gdb_memory_map disable
gdbinit:
target remote localhost:3333
set remote hardware-breakpoint-limit 2
set remote hardware-watchpoint-limit 2
monitor poll on
Comments welcome.
Best Regards,
Ben Gardiner
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Clarify that ICDI is the generic logic, but this config is
for the JTAG-only (no-SWD) mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This is a standard FT2232 device. More info at their web page:
http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
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srst_pulls_trst is only true on some (broken) LPC2148 boards, a fact
which is already documented in doc/openocd.texi, so it shouldn't be
set unconditionally in the target tcl.
This patch was needed to reflash when an Abort exception occured very
early after reset, before OpenOCD tried to halt the CPU.
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set user mode to avoid ROM being mapped at address
0 rather than flash.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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This adds a nand driver support for the nuc910 target.
Note that ECC is not currently supported by this driver, although
it is supported by the peripheral.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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- Only enable the FMI (NAND) and DMA clocks.
- Select NAND interface on the MFSEL.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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There's no point in an lm3s811-specific target file,
so remove it in favor of the generic "stellaris.cfg".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signs of life: reset(kinda), halt, resume and memory
display/modify.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Added a function 'pll_v03_setup' to set up PLLs and clock
dividers on DM365 and DM368.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Here is a patch to fix a startup in C100 (arm1136). Basically make sure
that UART is configured before using it.
Michal
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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make use of the new virtual bank flash driver.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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config scripts
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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