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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2010-04-20 12:15:49 +0800 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-05-16 13:39:47 +0200 |
| commit | 61bb0d3d235c659eb407a7032aa9ec70a914dc03 (patch) | |
| tree | 3b57db977bb18b70ba8305064b9807528374c1e3 /src/flash/nand/core.c | |
| parent | 89747f81f22084b255f35d92f709facd3b4553a1 (diff) | |
| download | openocd_libswd-61bb0d3d235c659eb407a7032aa9ec70a914dc03.tar.gz openocd_libswd-61bb0d3d235c659eb407a7032aa9ec70a914dc03.tar.bz2 openocd_libswd-61bb0d3d235c659eb407a7032aa9ec70a914dc03.tar.xz openocd_libswd-61bb0d3d235c659eb407a7032aa9ec70a914dc03.zip | |
NOR/CFI: identify memory accesses not using "bus_width".
Since NOR flash devices does not handle "byte enable lanes",
each read/write access involves the whole "chip_width".
When multiple devices are in parallel, usually all chips are
enabled during each access.
All such cases are compatible with flash accesses at
"bus_width" size.
Access at "bus_width" size is mandatory for write access to
avoid transferring of garbage values to flash.
During read access the flash controller should take care,
and discard unneeded bytes. Anyway, it is good practice to
use "bus_width" size also for read.
Every memory access that does not respect "bus_width" size
is marked with a "FIXME" comment.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/flash/nand/core.c')
0 files changed, 0 insertions, 0 deletions