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| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:48:22 +0000 |
| commit | 71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch) | |
| tree | 9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/target/ar71xx.cfg | |
| parent | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff) | |
| download | openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.gz openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.bz2 openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.tar.xz openocd_libswd-71af49ca7fb11b0bd0c1ba9578826f49288b68ef.zip | |
Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/target/ar71xx.cfg')
| -rw-r--r-- | tcl/target/ar71xx.cfg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 213048ae..47bab1e3 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -29,11 +29,11 @@ $TARGETNAME configure -event reset-init { mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass mww 0xb8050008 1 # set clock_switch bit sleep 1 # wait for lock - + # Setup DDR config and flash mapping mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0) mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8) - + mww 0xb8000010 8 # force precharge all banks mww 0xb8000010 1 # force EMRS update cycle mww 0xb800000c 0 # clr ext. mode register @@ -47,7 +47,7 @@ $TARGETNAME configure -event reset-init { mww 0xb8000020 0 mww 0xb8000024 0 mww 0xb8000028 0 -} +} # setup working area somewhere in RAM $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 |