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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-10-26 22:59:46 -0700
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-10-26 22:59:46 -0700
commit4a26390eec5b969c07684ab5d4b7e957011d71bd (patch)
tree3e4b10eeeb6ab93f4d9d3773881e00f5ceab4aa0 /tcl
parent4a91b070ffd7890c5a0b6381997787136d797bd5 (diff)
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PXA255: force reset config
These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG.
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/pxa255.cfg4
1 files changed, 4 insertions, 0 deletions
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 7137621a..44efdaa4 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -31,6 +31,10 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
jtag_khz 300
$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
# reset processing that works with PXA
proc init_reset {mode} {
# assert both resets; equivalent to power-on reset