diff options
| -rw-r--r-- | tcl/target/omap4430.cfg | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index 13ed80c3..fc3db5d0 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -82,7 +82,20 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" # second core. # set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -coreid 0 + +# APB DBGBASE reads 0x80040000, but this points to an empty ROM table. +# 0x80000000 is cpu0 coresight region +# +# +# CORTEX_A8_PADDRDBG_CPU_SHIFT 13 +# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) + +set _coreid 0 +set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +echo "Using dbgbase = [format 0x%x $_dbgbase]" + +target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \ + -coreid 0 -dbgbase $_dbgbase # SRAM: 56KiB at 0x4030.0000 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 |