diff options
Diffstat (limited to 'tcl/board/at91sam9g20-ek.cfg')
| -rw-r--r-- | tcl/board/at91sam9g20-ek.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index fb6068cc..f24f1a13 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -77,7 +77,7 @@ proc at91sam9g20_init { } { # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. - jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow. + adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow. halt # Make sure processor is halted, or error will result in following steps. mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog. @@ -112,7 +112,7 @@ proc at91sam9g20_init { } { # Switch over to adaptive clocking. - jtag_khz 0 + adapter_khz 0 # Enable faster DCC downloads. |