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* ARM: define two register utilitiesDavid Brownell2009-11-221-6/+1
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-7/+5
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-24/+23
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: better context restoreDavid Brownell2009-11-191-13/+67
| | | | | | | The previous version never wrote dirty registers for non-current CPU modes ... fix that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: mode supportDavid Brownell2009-11-191-30/+116
| | | | | | | | | | | | | | | | We *should* be able to read and write registers in any core mode, instead of being stuck with whatever mode the core was when we entered debug state. This patch makes them work. Note that the current restore_context() only handles the current mode; writing to other-mode registers is a NOP without a followup patch fixing that. Also, that SPSR access needed some bugfixes; it was confused with CPSR. Secure monitor mode also seems dubious; there's probably more to be done before that's sufficiently understood by the debugger. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-2/+3
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: parts of examine() run just onceDavid Brownell2009-11-191-4/+15
| | | | | | | | | The examine() method has some conceptual breakage. Cope with it by manually splitting out the run-once parts from the after-each-reset parts ... this gets rid of memory leaks and speeds up resets after the first one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-12/+38
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: xPSR handling updatesDavid Brownell2009-11-181-17/+20
| | | | | | | | | | When we read the CPSR on debug entry, update the CPSR cache in all cases, not just when the current processor state is User or System. Plus minor cleanup of how the (too-many) other registers' cache entries get updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add a default full_context() methodDavid Brownell2009-11-181-9/+3
| | | | | | | | | | | | If the core doesn't provide an optimized version of this method, provide one without core-specific optimizations. Use this to make Cortex-A8 support the "arm reg" command. Related: make the two register access methods properly static, have the "set" log a "not halted" error too, and make sure that the "valid" flag is set on successful reads. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify ARMv7-A register handlingDavid Brownell2009-11-181-33/+45
| | | | | | | | | | | | | | | | | | | ARMv7-A doesn't need to duplicate all the standard ARM code for register handling. - Switch Cortex-A8 to use the standard register code - Remove duplicated infrastructure from ARMv7-A - Have ARMv7-A arch_state() show CPSR, like other ARMs Add comments to show where the Cortex-A8 isn't actually doing the right thing for register reads/writes, unless core happens to be in the right mode to start with. (Looks like maybe there may be generic confusion between saved/current PSR values in all the ARM code ...) Make related ARMv7-A and Cortex-A8 symbols properly static. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-0/+2
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-3/+3
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* target: remove some more duplicate includesDavid Brownell2009-11-171-1/+0
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: no exit() calls, add missing v7-A initDavid Brownell2009-11-161-31/+16
| | | | | | | Eventually there should be a v7a init routine, but for now all that is inlined here. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-2/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-2/+3
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: make "examined" flag be per-targetDavid Brownell2009-11-151-3/+3
| | | | | | | | | | | | | | | | | | Previously this flag was stored in "target_type", so that for example if there were two ARM7TDMI targets in a scan chain, both would claim to have been examined although only the first one actually had its examine() method called. Move this state to where it should have been in the first place, and hide a method that didn't need exposure ... the flag is write-once. Provide some doxygen. The examine() method is confusing, since it isn't separating one-time setup from the after-each-reset stuff. And the ARM7/ARM9 version is, somewhat undesirably, not leaving the debug state alone after reset ... probably more of an issue for trace setup than for watchpoints and breakpoints. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-47/+47
| | | | Remove misleading typedef and redundant suffix from struct target.
* target_type_t -> struct target_typeZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct target_type.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and just use struct arm.
* cortex_a8_wrp_t -> struct cortex_a8_wrpZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct cortex_a8_wrp.
* cortex_a8_brp_t -> struct cortex_a8_brpZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct cortex_a8_brp.
* breakpoint_t -> struct breakpointZachary T Welch2009-11-131-9/+9
| | | | Remove misleading typedef and redundant suffix from struct breakpoint.
* working_area_t -> struct working_areaZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct working_area.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* cortex_a8_common_t -> struct cortex_a8_commonZachary T Welch2009-11-131-11/+11
| | | | Remove misleading typedef and redundant suffix from struct cortex_a8_common.
* armv7a_common_t -> struct armv7a_commonZachary T Welch2009-11-131-23/+23
| | | | Remove misleading typedef and redundant suffix from struct armv7a_common.
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-18/+18
| | | | Remove misleading typedef and redundant suffix from struct swjdp_common.
* jtag_tap_t -> struct jtag_tapZachary T Welch2009-11-131-1/+1
| | | | | Search and destroy the jtag_tap_t typedef. This also cleans up a layering violation, removing the declaration from types.h.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-4/+2
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* Cortex-A8: fix indentDavid Brownell2009-11-131-28/+28
| | | | | | | The "remove (forward) declarations" patch goofed indentation on the "cortexa8_target" struct; fix. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* cortex_a8: remove declarations, use static keywordZachary T Welch2009-11-111-106/+82
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* Cortex-A8: use the new inheritance/nesting schemeDavid Brownell2009-11-051-105/+41
| | | | | | | Use target_to_armv7a() etc, replacing needless pointer traversals. Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* cortex_a8: add mrc mcr interface.Øyvind Harboe2009-11-051-0/+29
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: remove unused interface fn that clutters codeØyvind Harboe2009-11-051-1/+0
| | | | | | | | | The quit entry point was not being invoked. Just a source of confusion at this point. XScale ran 100x reset upon quit, but that code made no sense, wasn't commented and never invoke. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug interface: get rid of unused pre_debug fnØyvind Harboe2009-11-051-4/+0
| | | | | | Removing unused code makes it much less mysterius. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Cleanup: nuke trailling whitespacesYauheni Kaliuta2009-10-131-10/+10
| | | | Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
* It is not possible to invalidate I-Cache on memory writes while the target ↵mlu2009-10-021-0/+3
| | | | | | is running git-svn-id: svn://svn.berlios.de/openocd/trunk@2795 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Make sure that DSCR_DTR_RX is not full before writingmlu2009-10-021-0/+27
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2794 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More error reporting in Cortex_a8 execute_opcodemlu2009-10-021-0/+6
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2793 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2792 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Added asser_reset and deassert_reset for cortex_a8mlu2009-10-021-22/+56
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2791 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove annoying end-of-line whitespace from most src/*dbrownell2009-09-211-4/+4
| | | | | | | files; omitted src/httpd git-svn-id: svn://svn.berlios.de/openocd/trunk@2742 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Avoid cache invalidation when writing to hardware debug registersmlu2009-09-191-4/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2733 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu2009-09-181-28/+39
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2728 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASEmlu2009-09-161-28/+31
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2716 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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