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* fileio: fileio_size() can now failØyvind Harboe2010-09-293-6/+37
| | | | | | Part of making the fileio API more robust. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* fileio: refactor struct fileio to be an opaque structureØyvind Harboe2010-09-293-6/+6
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* image: fix spelling mistakeØyvind Harboe2010-09-272-13/+13
| | | | | | struct imageection => struct imagesection Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtagdp: remove #if 0'd kludges and explain why the code is correctØyvind Harboe2010-09-211-16/+24
| | | | | | | | | short story: if the JTAG clock is too high, then the behavior will be flaky and kludging the code may seem to make things beter, but really it's just a red herring. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embeddedice: fix error handlingØyvind Harboe2010-09-211-0/+4
| | | | | | error is now reported at failure site. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* warnings: fix alignment warningsØyvind Harboe2010-09-208-15/+15
| | | | | | | These warnings are for architectures that do not support non-aligned word access. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* xscale: check that wp length does not exceed addressMike Dunn2010-09-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, A while back I sent in a patch that adds support for watchpoint lengths greater than four on xscale. It's been working well, until the other day, when it caused an unexpected debug exception. Looking into this I realized there is a case where it breaks: when the length arg is greater than the base address. This is a consequence of the way the hardware works. Don't see a work-around, so I added code to xscale_add_watchpoint() to check for and disallow this combination. Some more detail... xscale watchpoint hardware does not support a length directly. Instead, a mask value can be specified (not to be confused with the optional mask arg to the wp command, which xscale does not support). Any bits set in the mask are ignored when the watchpoint hardware compares the access address to the watchpoint address. So as long as the length is a power of two, setting the mask to length-1 effectively specifies the length. Or so I thought, until I realized that if the length exceeds the base address, *all* bits of the base address are ignored by the comaparator, and the watchpoint range effectively becomes 0 .. length. Questions, comments, criticisms gratefully received. Thanks, Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
* xscale: bp/wp: additional LOG_ERROR on failureMike Dunn2010-09-201-6/+10
| | | | | | | | | | | | | | | | | | | | | Hi everyone, Added more LOG_ERROR messsages to watchpoint and breakpoint code, given that the infrastructure no longer interprets returned error codes. Also changed existing LOG_INFO and LOG_WARNING to LOG_ERROR for cases where an error is returned. Note that the check of the target state is superflous, since the infrastruture code currently checks this before calling target code. Is this being reconsidered as well? Also, should we stop returning anything other than ERROR_OK and ERROR_FAIL? Comments gratefully received. Thanks, Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
* breakpoints: fix error handlingØyvind Harboe2010-09-141-29/+7
| | | | | | | | do not try to interpret "retval" into a string, just amend a bit about the context of the already reported error. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* xscale: fix sw breakpoints for thumb; set bp immediatelyMike Dunn2010-09-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, Version 2 of this patch. Code added to breakpoints.c was removed from previous patch, and item 3 added, per discussion with Øyvind regarding error reporting. Item 4 added, which I just noticed. I tried to use a software breakpoint in thumb code on the xscale for the first time recently, and was surprised to find that it didn't work. The result was this patch, which does four things: 1): fix trivial cut-n-paste error that caused thumb breakpoints to not work 2): call xscale_set_breakpoint() from xscale_add_breakpoint() 3): log error on data abort in xscale_write_memory() 4): fixed incorrect error code returned by xscale_set_breakpoint() when no breakpoint register is available; added comment Item 2 not only makes the xscale breakpoint code consistent with other targets, but also alerts the user immediately if an error occurs when writing the breakpoint instruction to target memory (previously, xscale_set_breakpoint() was not called until execution resumed). Also, calling xscale_breakpoint_set() as part of the call chain starting with handle_bp_command() and propagating the return status back up the chain avoids the situation where OpenOCD "thinks" the breakpoint is set when in reality an error ocurred. Item 3 provides a helpful message for a common reason for failure to set sw breakpoint. This was thoroughly tested, mindful of the fact that breakpoint management is somewhat dicey during single-stepping. Comments and criticisms of course gratefully received. Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* propagate return status of set_breakpoint() up call chainMike Dunn2010-09-133-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, I figured since I was poking around in the breakpoint code on other arches, I'd add this change to those arches that don't do it already. This patch propagates the return code of <arch>_set_breakpoint() up the call stack. This ensures that the higher layer breakpoint infrastructure is aware that an error ocurred, in which case the breakpoint is not recorded. Normally I wouldn't touch code that I can't test, but the code is very uniform across architectures, and the change is rather benign, so I figured after careful inspection that it is safe. If the maintainers or others think this is imprudent, the patch can be dropped. Also changed the error code to something more appropriate in two cases where hardware resources are unavailable. Comments and criticisms of course gratefully received. Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* xscale: mark xscale registers invalid on debug entryMike Dunn2010-09-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, This simple patch fixes a problem I noticed on the xscale where incorrect values are sometimes reported by the reg command. The problem can occur when requesting the value of registers in the xscale-specific register cache. With a couple of exceptions, none of the registers in the xscale register cache are automatically retrieved on debug entry. This is probably fine, as they are unlikely to be needed on a regular basis during a typical debug session, and they can be retrieved when explicitly requested by name using the reg command. The problem is that once this is done, the register remains marked as valid for the remainder of the OpenOCD session, and the reg command will henceforth always report the same value because it is obtained from the cache and is never again retrieved from the debug handler on the target. The fix is to mark all registers in the xscale register cache as invalid on debug entry (before the two exceptions are retrieved), thus forcing retrieval (when requested) from the target across resumptions in execution, and avoiding the reporting of stale values. Small addition change by Øyvind: change 'i' to unsigned to fix compiler warning for xscale_debug_entry() fn. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex m3: add cortex_m3 reset_config cmdSpencer Oliver2010-08-312-51/+84
| | | | | | | | | | | | This new cmd adds the ability to choose the Cortex-M3 reset method used. It defaults to using SRST for reset if available otherwise it falls back to using NVIC VECTRESET. This is known to work on all cores. Move any luminary specific reset handling to the stellaris cfg file. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* avr32: work-in-progressOleksandr Tymoshenko2010-08-1510-0/+1769
| | | | | | | | | | | | | committed so as to ease cooperation and to let it be improved over time. So far it supports: - halt/resume - registers inspection - memory inspection/modification I'm still getting up to speed with OpenOCD internals and AVR32 so code is a little bit messy and I'd appreciate any feedback.
* tcl: remove silly ocd_ prefix to array2mem and mem2arrayØyvind Harboe2010-08-111-2/+2
| | | | | | | | ocd_ prefix is used internally in OpenOCD as a kludge more or less to deal with the two kinds of commands that OpenOCD has. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug: use assert's when approperiateØyvind Harboe2010-08-112-4/+2
| | | | | | error was returned instead of using assert. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add missing error reportingØyvind Harboe2010-08-113-1/+28
| | | | | | | when an unknown core mode is read from the target, report error. Can be communication failure. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: fix "reset run + halt"Øyvind Harboe2010-08-092-11/+27
| | | | | | | | | | | | | | | | if polling is off, then "reset run + halt" would fail since halt incorrectly assumed the target was in the reset state as it is the internal poll implementation that moves the sw tracking of the target state out of the reset state. To reproduce: > reset run; halt JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1) BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset() Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: if polling fails, back offØyvind Harboe2010-08-091-8/+29
| | | | | | | | | | | | back-off algorithm for polling. Double polling interval up to 5000ms when it fails. when polling succeeds, reset backoff. This avoids flooding logs(as much) when working with conditions where the target polling will fail. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* verify_image: print out a statement that there are no further errorsØyvind Harboe2010-08-021-1/+10
| | | | | | | | | It is useful to know that the printed errors are *all* the errors there were. Added missing error handling(found by inspection). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips32: exit_point optional for mips32_run_algorithmSpencer Oliver2010-07-201-1/+1
| | | | | | | | | As the mips32 uses instruction breakpoints for algorithms we do not really need to check the pc on exit. This now matches the behaviour of the arm codebase. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* armv7m: exit_point optional for armv7m_run_algorithmSpencer Oliver2010-07-201-1/+1
| | | | | | | | | As the armv7m uses instruction breakpoints for algorithms we do not really need to check the pc on exit. This now matches the behaviour of the arm4_5 codebase. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* armv4_5: add algorithms instruction breakpoint supportSpencer Oliver2010-07-201-6/+16
| | | | | | | Update the arm_checksum_memory and arm_blank_check_memory algorithms to use a breakpoint instruction on v5 arch. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* arm11 error propagation fixesØyvind Harboe2010-07-203-29/+32
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_jtag_scann error propagation fixesØyvind Harboe2010-07-205-12/+34
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_dpm: error propagation fixesØyvind Harboe2010-07-191-2/+26
| | | | | | found by inspection Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* adi_jtag_ error propagationØyvind Harboe2010-07-191-4/+12
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: error propagation of arm_jtag_set_instrØyvind Harboe2010-07-1910-32/+108
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: dap_run() error propagationØyvind Harboe2010-07-191-15/+28
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: mem_ap_write error propagationØyvind Harboe2010-07-192-25/+78
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: error propagation of mem_ap_read_atomic_u32 failureØyvind Harboe2010-07-192-26/+73
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mem_ap_read_u32 error propagationØyvind Harboe2010-07-192-16/+48
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm_adi_v5: add error propagation for dap_setup_accessportØyvind Harboe2010-07-192-15/+45
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug: debug entry error propagationØyvind Harboe2010-07-1911-41/+116
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: added timeout handlingØyvind Harboe2010-07-191-5/+28
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation for enable/disable mmu cachesØyvind Harboe2010-07-198-65/+162
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation to generic get_ttb fnØyvind Harboe2010-07-198-18/+46
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: lots of error propagation fixesØyvind Harboe2010-07-191-18/+53
| | | | | | found by code inspection Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: mem_ap_read_buf_u32() error handlingØyvind Harboe2010-07-191-1/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for ↵Øyvind Harboe2010-07-191-3/+9
| | | | | | cortex_a8_dap_write/read_coreregister_u32() Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling from cortex_a8_exec_opcode()Øyvind Harboe2010-07-191-13/+52
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for mem_ap_atomic_write_u32()Øyvind Harboe2010-07-191-1/+5
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for mem_ap_read_atomic_u32()Øyvind Harboe2010-07-191-0/+11
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* spelling fixes in commentsØyvind Harboe2010-07-181-5/+5
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM ADI-V5: cleanup CID/PID addressingDavid Brownell2010-07-161-21/+23
| | | | | | | | | | | Use addition for offsetting, not masking. Shorten some lines. Make "component_start" print-only (unused otherwise; don't save). Still doesn't resolve the issue where multiple components are wrongly displaying as NVICs on some Cortex-M3 parts because many PIDs appear to be zeroes ... maybe adapter related?? Signed-off-by: David Brownell <db@helium.(none)>
* ARM ADI-V5: PIDs and CIDs are 8 bitsDavid Brownell2010-07-131-21/+41
| | | | | | | | | Mask the upper bits after 32-bit reads. Alsoo revert the ugly changes to use PRIx32; just cast to unsized integers when printing (two chars not eight). Signed-off-by: David Brownell <db@helium.(none)>
* arm9: revert change arm9tdmi cmd group name to arm9Spencer Oliver2010-07-121-2/+2
| | | | | | | | | This reverts the incorrect change made to the arm9 cmd group in commit d1eca9a74c7c57ba6a3210c51b2a10cc5adb22e1. The code now matches the docs and the release notes. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* arm11: fix gaffe in no-ack transfersØyvind Harboe2010-06-231-1/+1
| | | | | | | | | | | The code did not transfer the last word in no-ack transfers. The strange thing is that this did not lead to any observable errors. This gaffe was introduced in commit 1f5883ea56cb058221f Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* error number: reviewAntonio Borneo2010-06-232-3/+3
| | | | | | | | | Review allocation of error numbers in openocd to avoid overlap. Put brackets around negative numbers to avoid issues during macro expansion. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* cortex a8: only physical read/write's are available when target is runningØyvind Harboe2010-06-221-2/+9
| | | | | | | | | Memory read/writes to virtual memory, requires that the CPU is halted. Use 'phys' option to write to memory while target is running. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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