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authorTrygve Laugstøl <trygvis@inamo.no>2013-02-10 22:00:43 +0100
committerTrygve Laugstøl <trygvis@inamo.no>2013-02-10 22:00:43 +0100
commit2be1fada10bddbbabe4da448a76f1208aed53c5e (patch)
tree585434eb2bd6d44d62f4899919d7563774fbcf50
parent6c56d89c8db4830418bdd27d5c775a77d0ab462b (diff)
downloadrom-emulator-2be1fada10bddbbabe4da448a76f1208aed53c5e.tar.gz
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rom-emulator-2be1fada10bddbbabe4da448a76f1208aed53c5e.tar.xz
rom-emulator-2be1fada10bddbbabe4da448a76f1208aed53c5e.zip
wip
-rw-r--r--README.txt6
-rw-r--r--hardware-v1/.gitignore4
-rw-r--r--hardware-v1/eagle.epf352
-rw-r--r--hardware-v1/ram-ice.brd814
-rw-r--r--hardware-v1/ram-ice.sch1228
-rw-r--r--hardware-v1/untitled.pro25
-rw-r--r--hardware/.gitignore4
-rw-r--r--vhdl/.gitignore26
-rw-r--r--vhdl/ice.vhd80
-rw-r--r--vhdl/ice_tb.vhd66
-rw-r--r--vhdl/ieee_proposed/std_logic_1164_additions.vhdl1680
-rw-r--r--vhdl/mcu_interface.vhd104
-rw-r--r--vhdl/mcu_interface_tb.vhd120
-rw-r--r--vhdl/ram-ice.xise134
14 files changed, 4497 insertions, 146 deletions
diff --git a/README.txt b/README.txt
new file mode 100644
index 0000000..fa9a7a9
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,6 @@
+The file vhdl/ieee_proposed/std_logic_1164_additions.vhd came from [1].
+
+The files in vhdl/fmf came from [2].
+
+[1]: http://www.vhdl.org/fphdl/std_logic_1164_additions.vhdl
+[2]: http://freemodelfoundry.com
diff --git a/hardware-v1/.gitignore b/hardware-v1/.gitignore
new file mode 100644
index 0000000..ba66ed2
--- /dev/null
+++ b/hardware-v1/.gitignore
@@ -0,0 +1,4 @@
+*.b#*
+*.s#*
+*.pro
+eagle.epf
diff --git a/hardware-v1/eagle.epf b/hardware-v1/eagle.epf
new file mode 100644
index 0000000..ff48142
--- /dev/null
+++ b/hardware-v1/eagle.epf
@@ -0,0 +1,352 @@
+[Eagle]
+Version="06 04 00"
+Platform="Linux"
+Serial="62191E841E-LSR-WLM-1EL"
+Globals="Globals"
+Desktop="Desktop"
+
+[Globals]
+AutoSaveProject=1
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/19inch.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/40xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/41xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/45xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ac-logic.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ttl-din.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-eu.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-de.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-us.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-us.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/751xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/advanced-test-technologies.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/agilent-technologies.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/allegro.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-II.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-III.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-stratix-iv.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/am29-memory.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/amd-mach.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/amd.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/amis.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/analog-devices.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ase.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/atmel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/austriamicrosystems.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/axis.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/battery.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/belton-engineering.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/burr-brown.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/busbar.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/buzzer.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/capacitor-wima.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/chipcard-siemens.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-4ucon.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-amp-micromatch.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-amp-mt.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-amp-mt6.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-amp-quick.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/con-amp.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-micron.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-motorola-dram.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-nec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-samsung.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-sram.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/mems.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micrel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-cyrod.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-fujitsu.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-harris.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-hitachi.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-infineon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-intel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-mc68000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-motorola.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-philips.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-renesas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-samsung.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microchip.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micron.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micronas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microphon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microwave.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/midori-sensor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/minicircuits.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/mitsubishi-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/motorola-sensor-driver.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/murata-filter.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/murata-sensor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nanotec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/national-instruments.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/national-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nec-lqfp100-pack.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nrj-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/omnivision.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/on-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell-3000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell-4000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-micro-linear.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-trans-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-transmittter-hp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-vishay.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/optocoupler.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pal.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/philips-semiconductors.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/photo-elements.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/piher.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pinhead.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/plcc-socket.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pld-intel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/plxtech.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot-vitrohm.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot-xicor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ptc-ntc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/quantum-research-group.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rcl.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/recom-international.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rectifier.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ref-packages-longpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ref-packages.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/relay.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/renesas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-bourns.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-dil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-net.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-power.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-ruf.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-shunt.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-sil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rf-micro-devices.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rf-solutions.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rohm.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/semicon-smd-ipc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-comus-group.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-heraeus.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-infratec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sharp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/silabs.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sim-technology.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sipex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/smd-ipc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/smd-special.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/solomon-systech.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/solpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/special-drill.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/special.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/st-microelectronics.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supertex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supply1.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supply2.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-alps.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-coto.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-dil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-misc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-omron.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-raychem.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-reed.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telcom.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telecontrolli.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telefunken.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/testpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/texas-sn55-sn75.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/texas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/toshiba.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/traco-electronic.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-bei.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-hammondmfg.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-xicon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transformer-pulse.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-fet.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-neu-to92.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-npn.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-pnp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-power.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-small-signal.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/triac.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trimble.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/tripas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/u-blox.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/uln-udn.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/v-reg-micrel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/v-reg.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/varistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/wafer-scale-psd.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/wirepad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xicor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-virtex-v5.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xc18v.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xc9.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xcv.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/zetex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/zilog.lbr"
+
+[Win_1]
+Type="Control Panel"
+Loc="0 0 1917 1197"
+State=2
+Number=0
+
+[Desktop]
+Screen="1920 1200"
+Window="Win_1"
diff --git a/hardware-v1/ram-ice.brd b/hardware-v1/ram-ice.brd
new file mode 100644
index 0000000..0d74c93
--- /dev/null
+++ b/hardware-v1/ram-ice.brd
@@ -0,0 +1,814 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.025" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="0" x2="100" y2="0" width="0" layer="20"/>
+<wire x1="100" y1="0" x2="100" y2="80" width="0" layer="20"/>
+<wire x1="100" y1="80" x2="0" y2="80" width="0" layer="20"/>
+<wire x1="0" y1="80" x2="0" y2="0" width="0" layer="20"/>
+</plain>
+<libraries>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="SO16">
+<description>&lt;b&gt;Small Outline package&lt;/b&gt; 150 mil</description>
+<wire x1="4.699" y1="1.9558" x2="-4.699" y2="1.9558" width="0.1524" layer="51"/>
+<wire x1="4.699" y1="-1.9558" x2="5.08" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.5748" x2="-4.699" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="1.9558" x2="5.08" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.5748" x2="-4.699" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="-1.9558" x2="4.699" y2="-1.9558" width="0.1524" layer="51"/>
+<wire x1="5.08" y1="-1.5748" x2="5.08" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.5748" x2="-5.08" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.508" x2="-5.08" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-5.08" y1="-1.6002" x2="5.08" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-4.445" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="16" x="-4.445" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="2" x="-3.175" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<smd name="9" x="4.445" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<text x="-3.81" y="-0.762" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-5.461" y="-1.905" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/>
+<rectangle x1="-4.699" y1="-3.0988" x2="-4.191" y2="-1.9558" layer="51"/>
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+<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/>
+<rectangle x1="2.921" y1="-3.0988" x2="3.429" y2="-1.9558" layer="51"/>
+<rectangle x1="4.191" y1="-3.0988" x2="4.699" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/>
+<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/>
+<rectangle x1="2.921" y1="1.9558" x2="3.429" y2="3.0988" layer="51"/>
+<rectangle x1="4.191" y1="1.9558" x2="4.699" y2="3.0988" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="memory-idt">
+<description>&lt;b&gt;IDT Memories&lt;/b&gt;&lt;p&gt;
+Integrated Device Technology, Inc.&lt;p&gt;
+http://www.idt.com&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL28-6">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.6 inch</description>
+<wire x1="-17.653" y1="-1.27" x2="-17.653" y2="-6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="1.27" x2="-17.653" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
+<wire x1="17.653" y1="-6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="-17.653" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="-6.604" x2="17.653" y2="-6.604" width="0.1524" layer="21"/>
+<pad name="1" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="13" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-17.78" y="-6.35" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-14.605" y="-0.9398" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO28-3">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt;</description>
+<wire x1="-8.814" y1="-4.248" x2="8.839" y2="-4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="-4.248" x2="8.839" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="4.248" x2="-8.814" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="-8.814" y1="4.248" x2="-8.814" y2="-4.248" width="0.1524" layer="21"/>
+<circle x="-7.874" y="-3.0988" radius="0.5334" width="0.1524" layer="21"/>
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+<rectangle x1="-8.509" y1="4.2735" x2="-8.001" y2="5.7975" layer="51"/>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="default">
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.
+</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="8mil"/>
+<param name="mdWirePad" value="8mil"/>
+<param name="mdWireVia" value="8mil"/>
+<param name="mdPadPad" value="8mil"/>
+<param name="mdPadVia" value="8mil"/>
+<param name="mdViaVia" value="8mil"/>
+<param name="mdSmdPad" value="8mil"/>
+<param name="mdSmdVia" value="8mil"/>
+<param name="mdSmdSmd" value="8mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="40mil"/>
+<param name="mdDrill" value="8mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="10mil"/>
+<param name="msDrill" value="0.6mm"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="999999"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="|"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="-"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
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+<via x="53.34" y="53.975" extent="1-16" drill="0.6" shape="square"/>
+</signal>
+<signal name="D3">
+<contactref element="IC1" pad="14"/>
+<contactref element="IC2" pad="3"/>
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+</signal>
+<signal name="D4">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC2" pad="4"/>
+<wire x1="27.2034" y1="62.23" x2="34.29" y2="62.23" width="0.4064" layer="1"/>
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+<via x="34.29" y="53.975" extent="1-16" drill="0.6" shape="square"/>
+<contactref element="IC5" pad="16"/>
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+</signal>
+<signal name="D5">
+<contactref element="IC1" pad="4"/>
+<contactref element="IC2" pad="5"/>
+<contactref element="IC5" pad="17"/>
+<wire x1="27.2034" y1="63.5" x2="33.02" y2="63.5" width="0.4064" layer="1"/>
+<via x="33.02" y="63.5" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="33.02" y1="63.5" x2="33.02" y2="52.705" width="0.4064" layer="16"/>
+<via x="33.02" y="52.705" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="33.02" y1="52.705" x2="39.135" y2="52.705" width="0.4064" layer="1"/>
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+<wire x1="41.275" y1="60.96" x2="61.6966" y2="60.96" width="0.4064" layer="1"/>
+</signal>
+<signal name="D6">
+<contactref element="IC1" pad="5"/>
+<contactref element="IC2" pad="6"/>
+<contactref element="IC5" pad="18"/>
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+<via x="31.75" y="51.435" extent="1-16" drill="0.6" shape="square"/>
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+<wire x1="41.275" y1="59.055" x2="41.91" y2="59.69" width="0.4064" layer="1"/>
+</signal>
+<signal name="D7">
+<contactref element="IC1" pad="6"/>
+<contactref element="IC2" pad="7"/>
+<contactref element="IC5" pad="19"/>
+<wire x1="27.2034" y1="66.04" x2="30.48" y2="66.04" width="0.4064" layer="1"/>
+<via x="30.48" y="66.04" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="30.48" y1="66.04" x2="30.48" y2="50.165" width="0.4064" layer="16"/>
+<via x="30.48" y="50.165" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="30.48" y1="50.165" x2="39.135" y2="50.165" width="0.4064" layer="1"/>
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+<wire x1="41.91" y1="57.785" x2="42.545" y2="58.42" width="0.4064" layer="1"/>
+<wire x1="42.545" y1="58.42" x2="61.6966" y2="58.42" width="0.4064" layer="1"/>
+</signal>
+<signal name="N$2">
+<contactref element="IC4" pad="9"/>
+<contactref element="IC2" pad="14"/>
+<wire x1="21.0566" y1="60.96" x2="19.05" y2="60.96" width="0.4064" layer="1"/>
+<via x="19.05" y="60.96" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="19.05" y1="60.96" x2="19.05" y2="43.815" width="0.4064" layer="16"/>
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+<wire x1="19.05" y1="43.815" x2="21.0566" y2="43.815" width="0.4064" layer="1"/>
+</signal>
+<signal name="N$3">
+<contactref element="IC2" pad="9"/>
+<contactref element="IC1" pad="10"/>
+<wire x1="21.0566" y1="67.31" x2="22.86" y2="67.31" width="0.4064" layer="1"/>
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+<via x="69.85" y="57.15" extent="1-16" drill="0.6" shape="square"/>
+<wire x1="69.85" y1="57.15" x2="67.8434" y2="57.15" width="0.4064" layer="1"/>
+</signal>
+<signal name="D_IN">
+<contactref element="IC3" pad="14"/>
+</signal>
+<signal name="D_CLK">
+<contactref element="IC3" pad="11"/>
+<contactref element="IC4" pad="11"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="IC1" pad="2"/>
+<wire x1="67.8434" y1="42.545" x2="61.6966" y2="63.5" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="64.77" x2="61.6966" y2="63.5" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="41.275" x2="21.0566" y2="64.77" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$5">
+<contactref element="IC2" pad="12"/>
+<contactref element="IC4" pad="12"/>
+<contactref element="IC3" pad="12"/>
+<contactref element="IC1" pad="1"/>
+<wire x1="67.8434" y1="43.815" x2="61.6966" y2="64.77" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="63.5" x2="61.6966" y2="64.77" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="40.005" x2="21.0566" y2="63.5" width="0" layer="19" extent="1-1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>
diff --git a/hardware-v1/ram-ice.sch b/hardware-v1/ram-ice.sch
new file mode 100644
index 0000000..e06ad85
--- /dev/null
+++ b/hardware-v1/ram-ice.sch
@@ -0,0 +1,1228 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="yes" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="yes" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="yes" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL16">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="10.16" y1="2.921" x2="-10.16" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="2.921" x2="-10.16" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="-10.16" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="1.016" x2="-10.16" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-10.541" y="-2.921" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.493" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO16">
+<description>&lt;b&gt;Small Outline package&lt;/b&gt; 150 mil</description>
+<wire x1="4.699" y1="1.9558" x2="-4.699" y2="1.9558" width="0.1524" layer="51"/>
+<wire x1="4.699" y1="-1.9558" x2="5.08" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.5748" x2="-4.699" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="1.9558" x2="5.08" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.5748" x2="-4.699" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="-1.9558" x2="4.699" y2="-1.9558" width="0.1524" layer="51"/>
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+<wire x1="-5.08" y1="1.5748" x2="-5.08" y2="0.508" width="0.1524" layer="21"/>
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+<wire x1="-5.08" y1="-1.6002" x2="5.08" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-4.445" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<description>8-bit parallel load &lt;b&gt;SHIFT REGISTER&lt;/b&gt;</description>
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+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
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+<connect gate="A" pin="B" pad="12"/>
+<connect gate="A" pin="C" pad="13"/>
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+<connect gate="A" pin="SH/!LD" pad="1"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
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+</device>
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+<connect gate="A" pin="A" pad="11"/>
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+<connect gate="A" pin="C" pad="13"/>
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+<connect gate="A" pin="C" pad="17"/>
+<connect gate="A" pin="CLK" pad="3"/>
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+<connect gate="A" pin="SH/!LD" pad="2"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
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+</technologies>
+</device>
+</devices>
+</deviceset>
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+<description>8-bit &lt;b&gt;SHIFT REGISTER&lt;/b&gt;, output latch</description>
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+</gates>
+<devices>
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+<connects>
+<connect gate="A" pin="G" pad="13"/>
+<connect gate="A" pin="QA" pad="15"/>
+<connect gate="A" pin="QB" pad="1"/>
+<connect gate="A" pin="QC" pad="2"/>
+<connect gate="A" pin="QD" pad="3"/>
+<connect gate="A" pin="QE" pad="4"/>
+<connect gate="A" pin="QF" pad="5"/>
+<connect gate="A" pin="QG" pad="6"/>
+<connect gate="A" pin="QH" pad="7"/>
+<connect gate="A" pin="QH*" pad="9"/>
+<connect gate="A" pin="RCK" pad="12"/>
+<connect gate="A" pin="SCK" pad="11"/>
+<connect gate="A" pin="SCL" pad="10"/>
+<connect gate="A" pin="SER" pad="14"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="D" package="SO16">
+<connects>
+<connect gate="A" pin="G" pad="13"/>
+<connect gate="A" pin="QA" pad="15"/>
+<connect gate="A" pin="QB" pad="1"/>
+<connect gate="A" pin="QC" pad="2"/>
+<connect gate="A" pin="QD" pad="3"/>
+<connect gate="A" pin="QE" pad="4"/>
+<connect gate="A" pin="QF" pad="5"/>
+<connect gate="A" pin="QG" pad="6"/>
+<connect gate="A" pin="QH" pad="7"/>
+<connect gate="A" pin="QH*" pad="9"/>
+<connect gate="A" pin="RCK" pad="12"/>
+<connect gate="A" pin="SCK" pad="11"/>
+<connect gate="A" pin="SCL" pad="10"/>
+<connect gate="A" pin="SER" pad="14"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="G" pad="17"/>
+<connect gate="A" pin="QA" pad="19"/>
+<connect gate="A" pin="QB" pad="2"/>
+<connect gate="A" pin="QC" pad="3"/>
+<connect gate="A" pin="QD" pad="4"/>
+<connect gate="A" pin="QE" pad="5"/>
+<connect gate="A" pin="QF" pad="7"/>
+<connect gate="A" pin="QG" pad="8"/>
+<connect gate="A" pin="QH" pad="9"/>
+<connect gate="A" pin="QH*" pad="12"/>
+<connect gate="A" pin="RCK" pad="15"/>
+<connect gate="A" pin="SCK" pad="14"/>
+<connect gate="A" pin="SCL" pad="13"/>
+<connect gate="A" pin="SER" pad="18"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="memory-idt">
+<description>&lt;b&gt;IDT Memories&lt;/b&gt;&lt;p&gt;
+Integrated Device Technology, Inc.&lt;p&gt;
+http://www.idt.com&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL28-6">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.6 inch</description>
+<wire x1="-17.653" y1="-1.27" x2="-17.653" y2="-6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="1.27" x2="-17.653" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
+<wire x1="17.653" y1="-6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="-17.653" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="-6.604" x2="17.653" y2="-6.604" width="0.1524" layer="21"/>
+<pad name="1" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-17.78" y="-6.35" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-14.605" y="-0.9398" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO28-3">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt;</description>
+<wire x1="-8.814" y1="-4.248" x2="8.839" y2="-4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="-4.248" x2="8.839" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="4.248" x2="-8.814" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="-8.814" y1="4.248" x2="-8.814" y2="-4.248" width="0.1524" layer="21"/>
+<circle x="-7.874" y="-3.0988" radius="0.5334" width="0.1524" layer="21"/>
+<smd name="1" x="-8.255" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="2" x="-6.985" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="3" x="-5.715" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="4" x="-4.445" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="5" x="-3.175" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="6" x="-1.905" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="7" x="-0.635" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="8" x="0.635" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="9" x="1.905" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="10" x="3.175" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="20" x="1.905" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="19" x="3.175" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="18" x="4.445" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="17" x="5.715" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="16" x="6.985" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="15" x="8.255" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="14" x="8.255" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="13" x="6.985" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="12" x="5.715" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="11" x="4.445" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="21" x="0.635" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="22" x="-0.635" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="23" x="-1.905" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="24" x="-3.175" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="25" x="-4.445" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="26" x="-5.715" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="27" x="-6.985" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="28" x="-8.255" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<text x="-9.144" y="-4.318" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.874" y="-1.524" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-8.509" y1="-5.7976" x2="-8.001" y2="-4.2736" layer="51"/>
+<rectangle x1="-7.239" y1="-5.7976" x2="-6.731" y2="-4.2736" layer="51"/>
+<rectangle x1="-5.969" y1="-5.7976" x2="-5.461" y2="-4.2736" layer="51"/>
+<rectangle x1="-4.699" y1="-5.7976" x2="-4.191" y2="-4.2736" layer="51"/>
+<rectangle x1="-3.429" y1="-5.7976" x2="-2.921" y2="-4.2736" layer="51"/>
+<rectangle x1="-2.159" y1="-5.7976" x2="-1.651" y2="-4.2736" layer="51"/>
+<rectangle x1="-0.889" y1="-5.7976" x2="-0.381" y2="-4.2736" layer="51"/>
+<rectangle x1="0.381" y1="-5.7976" x2="0.889" y2="-4.2736" layer="51"/>
+<rectangle x1="1.651" y1="-5.7976" x2="2.159" y2="-4.2736" layer="51"/>
+<rectangle x1="2.921" y1="-5.7976" x2="3.429" y2="-4.2736" layer="51"/>
+<rectangle x1="4.191" y1="-5.7976" x2="4.699" y2="-4.2736" layer="51"/>
+<rectangle x1="5.461" y1="-5.7976" x2="5.969" y2="-4.2736" layer="51"/>
+<rectangle x1="6.731" y1="-5.7976" x2="7.239" y2="-4.2736" layer="51"/>
+<rectangle x1="8.001" y1="-5.7976" x2="8.509" y2="-4.2736" layer="51"/>
+<rectangle x1="8.001" y1="4.2735" x2="8.509" y2="5.7975" layer="51"/>
+<rectangle x1="6.731" y1="4.2735" x2="7.239" y2="5.7975" layer="51"/>
+<rectangle x1="5.461" y1="4.2735" x2="5.969" y2="5.7975" layer="51"/>
+<rectangle x1="4.191" y1="4.2735" x2="4.699" y2="5.7975" layer="51"/>
+<rectangle x1="2.921" y1="4.2735" x2="3.429" y2="5.7975" layer="51"/>
+<rectangle x1="1.651" y1="4.2735" x2="2.159" y2="5.7975" layer="51"/>
+<rectangle x1="0.381" y1="4.2735" x2="0.889" y2="5.7975" layer="51"/>
+<rectangle x1="-0.889" y1="4.2735" x2="-0.381" y2="5.7975" layer="51"/>
+<rectangle x1="-2.159" y1="4.2735" x2="-1.651" y2="5.7975" layer="51"/>
+<rectangle x1="-3.429" y1="4.2735" x2="-2.921" y2="5.7975" layer="51"/>
+<rectangle x1="-4.699" y1="4.2735" x2="-4.191" y2="5.7975" layer="51"/>
+<rectangle x1="-5.969" y1="4.2735" x2="-5.461" y2="5.7975" layer="51"/>
+<rectangle x1="-7.239" y1="4.2735" x2="-6.731" y2="5.7975" layer="51"/>
+<rectangle x1="-8.509" y1="4.2735" x2="-8.001" y2="5.7975" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="71256">
+<wire x1="-7.62" y1="-25.4" x2="7.62" y2="-25.4" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-25.4" x2="7.62" y2="25.4" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="25.4" x2="-7.62" y2="25.4" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="25.4" x2="-7.62" y2="-25.4" width="0.4064" layer="94"/>
+<text x="-7.62" y="26.035" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-27.94" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="A0" x="-12.7" y="22.86" length="middle" direction="in"/>
+<pin name="A1" x="-12.7" y="20.32" length="middle" direction="in"/>
+<pin name="A2" x="-12.7" y="17.78" length="middle" direction="in"/>
+<pin name="A3" x="-12.7" y="15.24" length="middle" direction="in"/>
+<pin name="A4" x="-12.7" y="12.7" length="middle" direction="in"/>
+<pin name="A5" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="A6" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="A7" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="A8" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="A9" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="A10" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="!OE" x="-12.7" y="-17.78" length="middle" direction="in"/>
+<pin name="I/O5" x="12.7" y="12.7" length="middle" rot="R180"/>
+<pin name="I/O6" x="12.7" y="10.16" length="middle" rot="R180"/>
+<pin name="I/O7" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="I/O8" x="12.7" y="5.08" length="middle" rot="R180"/>
+<pin name="!WE" x="-12.7" y="-20.32" length="middle" direction="in"/>
+<pin name="!CS" x="-12.7" y="-22.86" length="middle" direction="in"/>
+<pin name="I/O1" x="12.7" y="22.86" length="middle" rot="R180"/>
+<pin name="I/O2" x="12.7" y="20.32" length="middle" rot="R180"/>
+<pin name="I/O3" x="12.7" y="17.78" length="middle" rot="R180"/>
+<pin name="I/O4" x="12.7" y="15.24" length="middle" rot="R180"/>
+<pin name="A11" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="A12" x="-12.7" y="-7.62" length="middle" direction="in"/>
+<pin name="A13" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="A14" x="-12.7" y="-12.7" length="middle" direction="in"/>
+</symbol>
+<symbol name="VCCGND">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="71256P" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;MEMORY&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="71256" x="0" y="0"/>
+<gate name="P" symbol="VCCGND" x="-25.4" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="DIL28-6">
+<connects>
+<connect gate="G$1" pin="!CS" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="I/O1" pad="11"/>
+<connect gate="G$1" pin="I/O2" pad="12"/>
+<connect gate="G$1" pin="I/O3" pad="13"/>
+<connect gate="G$1" pin="I/O4" pad="15"/>
+<connect gate="G$1" pin="I/O5" pad="16"/>
+<connect gate="G$1" pin="I/O6" pad="17"/>
+<connect gate="G$1" pin="I/O7" pad="18"/>
+<connect gate="G$1" pin="I/O8" pad="19"/>
+<connect gate="P" pin="GND" pad="14"/>
+<connect gate="P" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="71256S" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;MEMORY&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="71256" x="0" y="0"/>
+<gate name="P" symbol="VCCGND" x="-22.86" y="2.54" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="SO28-3">
+<connects>
+<connect gate="G$1" pin="!CS" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="I/O1" pad="11"/>
+<connect gate="G$1" pin="I/O2" pad="12"/>
+<connect gate="G$1" pin="I/O3" pad="13"/>
+<connect gate="G$1" pin="I/O4" pad="15"/>
+<connect gate="G$1" pin="I/O5" pad="16"/>
+<connect gate="G$1" pin="I/O6" pad="17"/>
+<connect gate="G$1" pin="I/O7" pad="18"/>
+<connect gate="G$1" pin="I/O8" pad="19"/>
+<connect gate="P" pin="GND" pad="14"/>
+<connect gate="P" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="IDT71256SA20YG" constant="no"/>
+<attribute name="OC_FARNELL" value="1218010" constant="no"/>
+<attribute name="OC_NEWARK" value="34M6449" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply1">
+<description>&lt;b&gt;Supply Symbols&lt;/b&gt;&lt;p&gt;
+ GND, VCC, 0V, +5V, -5V, etc.&lt;p&gt;
+ Please keep in mind, that these devices are necessary for the
+ automatic wiring of the supply signals.&lt;p&gt;
+ The pin name defined in the symbol is identical to the net which is to be wired automatically.&lt;p&gt;
+ In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.&lt;p&gt;
+ &lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="VCC">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="VCC" prefix="P+">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="VCC" symbol="VCC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC1" library="74xx-eu" deviceset="74*165" device="D" technology="AC"/>
+<part name="IC2" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC3" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC4" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC5" library="memory-idt" deviceset="71256S" device=""/>
+<part name="P+1" library="supply1" deviceset="VCC" device=""/>
+<part name="IC6" library="memory-idt" deviceset="71256P" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+</plain>
+<instances>
+<instance part="IC1" gate="A" x="162.56" y="83.82"/>
+<instance part="IC2" gate="A" x="162.56" y="40.64" rot="R180"/>
+<instance part="IC3" gate="A" x="45.72" y="88.9"/>
+<instance part="IC4" gate="A" x="45.72" y="45.72"/>
+<instance part="IC5" gate="G$1" x="101.6" y="55.88"/>
+<instance part="P+1" gate="VCC" x="27.94" y="109.22"/>
+<instance part="IC6" gate="G$1" x="233.68" y="58.42"/>
+</instances>
+<busses>
+<bus name="A[0..7]">
+<segment>
+<wire x1="63.5" y1="99.06" x2="63.5" y2="81.28" width="0.762" layer="92"/>
+<wire x1="63.5" y1="81.28" x2="81.28" y2="81.28" width="0.762" layer="92"/>
+<wire x1="81.28" y1="81.28" x2="81.28" y2="60.96" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="A[8..14]">
+<segment>
+<wire x1="81.28" y1="58.42" x2="81.28" y2="35.56" width="0.762" layer="92"/>
+<wire x1="81.28" y1="35.56" x2="63.5" y2="35.56" width="0.762" layer="92"/>
+<wire x1="63.5" y1="35.56" x2="63.5" y2="55.88" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="D[0..7]">
+<segment>
+<wire x1="134.62" y1="96.52" x2="134.62" y2="78.74" width="0.762" layer="92"/>
+<wire x1="134.62" y1="78.74" x2="134.62" y2="30.48" width="0.762" layer="92"/>
+<wire x1="134.62" y1="78.74" x2="121.92" y2="78.74" width="0.762" layer="92"/>
+<wire x1="121.92" y1="78.74" x2="121.92" y2="60.96" width="0.762" layer="92"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="A1" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QB"/>
+<wire x1="58.42" y1="96.52" x2="63.5" y2="96.52" width="0.1524" layer="91"/>
+<label x="58.42" y="96.52" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A1"/>
+<wire x1="81.28" y1="76.2" x2="88.9" y2="76.2" width="0.1524" layer="91"/>
+<label x="88.9" y="76.2" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A0" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QA"/>
+<wire x1="58.42" y1="99.06" x2="63.5" y2="99.06" width="0.1524" layer="91"/>
+<label x="58.42" y="99.06" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A0"/>
+<wire x1="81.28" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/>
+<label x="88.9" y="78.74" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A3" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QD"/>
+<wire x1="63.5" y1="91.44" x2="58.42" y2="91.44" width="0.1524" layer="91"/>
+<label x="58.42" y="91.44" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A3"/>
+<wire x1="81.28" y1="71.12" x2="88.9" y2="71.12" width="0.1524" layer="91"/>
+<label x="88.9" y="71.12" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A2" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QC"/>
+<wire x1="63.5" y1="93.98" x2="58.42" y2="93.98" width="0.1524" layer="91"/>
+<label x="58.42" y="93.98" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A2"/>
+<wire x1="81.28" y1="73.66" x2="88.9" y2="73.66" width="0.1524" layer="91"/>
+<label x="88.9" y="73.66" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A4" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QE"/>
+<wire x1="63.5" y1="88.9" x2="58.42" y2="88.9" width="0.1524" layer="91"/>
+<label x="58.42" y="88.9" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A4"/>
+<wire x1="88.9" y1="68.58" x2="81.28" y2="68.58" width="0.1524" layer="91"/>
+<label x="88.9" y="68.58" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A5" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QF"/>
+<wire x1="63.5" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/>
+<label x="58.42" y="86.36" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A5"/>
+<wire x1="88.9" y1="66.04" x2="81.28" y2="66.04" width="0.1524" layer="91"/>
+<label x="88.9" y="66.04" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A6" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QG"/>
+<wire x1="63.5" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/>
+<label x="58.42" y="83.82" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A6"/>
+<wire x1="88.9" y1="63.5" x2="81.28" y2="63.5" width="0.1524" layer="91"/>
+<label x="88.9" y="63.5" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A7" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QH"/>
+<wire x1="63.5" y1="81.28" x2="58.42" y2="81.28" width="0.1524" layer="91"/>
+<label x="58.42" y="81.28" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A7"/>
+<wire x1="88.9" y1="60.96" x2="81.28" y2="60.96" width="0.1524" layer="91"/>
+<label x="88.9" y="60.96" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A8" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QA"/>
+<wire x1="58.42" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/>
+<label x="58.42" y="55.88" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A8"/>
+<wire x1="88.9" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/>
+<label x="88.9" y="58.42" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A9" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QB"/>
+<wire x1="58.42" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/>
+<label x="58.42" y="53.34" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A9"/>
+<wire x1="88.9" y1="55.88" x2="81.28" y2="55.88" width="0.1524" layer="91"/>
+<label x="88.9" y="55.88" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A10" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QC"/>
+<wire x1="58.42" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/>
+<label x="58.42" y="50.8" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A10"/>
+<wire x1="88.9" y1="53.34" x2="81.28" y2="53.34" width="0.1524" layer="91"/>
+<label x="88.9" y="53.34" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A11" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QD"/>
+<wire x1="58.42" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/>
+<label x="58.42" y="48.26" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A11"/>
+<wire x1="88.9" y1="50.8" x2="81.28" y2="50.8" width="0.1524" layer="91"/>
+<label x="88.9" y="50.8" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A12" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QE"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="58.42" y="45.72" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A12"/>
+<wire x1="88.9" y1="48.26" x2="81.28" y2="48.26" width="0.1524" layer="91"/>
+<label x="88.9" y="48.26" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A13" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QF"/>
+<wire x1="58.42" y1="43.18" x2="63.5" y2="43.18" width="0.1524" layer="91"/>
+<label x="58.42" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A13"/>
+<wire x1="81.28" y1="45.72" x2="88.9" y2="45.72" width="0.1524" layer="91"/>
+<label x="88.9" y="45.72" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A14" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QG"/>
+<wire x1="58.42" y1="40.64" x2="63.5" y2="40.64" width="0.1524" layer="91"/>
+<label x="58.42" y="40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A14"/>
+<wire x1="88.9" y1="43.18" x2="81.28" y2="43.18" width="0.1524" layer="91"/>
+<label x="88.9" y="43.18" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QH*"/>
+<wire x1="58.42" y1="76.2" x2="58.42" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="66.04" x2="30.48" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="66.04" x2="30.48" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="SER"/>
+<wire x1="30.48" y1="55.88" x2="33.02" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A_EN" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="G"/>
+<wire x1="33.02" y1="76.2" x2="22.86" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="76.2" x2="22.86" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="G"/>
+<wire x1="22.86" y1="33.02" x2="22.86" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="33.02" x2="22.86" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="25.4" x2="5.08" y2="25.4" width="0.1524" layer="91"/>
+<label x="5.08" y="27.94" size="1.778" layer="95"/>
+<junction x="22.86" y="33.02"/>
+</segment>
+</net>
+<net name="D0" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A"/>
+<wire x1="134.62" y1="96.52" x2="149.86" y2="96.52" width="0.1524" layer="91"/>
+<label x="137.16" y="96.52" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QA"/>
+<wire x1="134.62" y1="30.48" x2="149.86" y2="30.48" width="0.1524" layer="91"/>
+<label x="137.16" y="30.48" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O1"/>
+<wire x1="114.3" y1="78.74" x2="121.92" y2="78.74" width="0.1524" layer="91"/>
+<label x="116.84" y="78.74" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D1" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="B"/>
+<wire x1="134.62" y1="93.98" x2="149.86" y2="93.98" width="0.1524" layer="91"/>
+<label x="137.16" y="93.98" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QB"/>
+<wire x1="134.62" y1="33.02" x2="149.86" y2="33.02" width="0.1524" layer="91"/>
+<label x="137.16" y="33.02" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O2"/>
+<wire x1="114.3" y1="76.2" x2="121.92" y2="76.2" width="0.1524" layer="91"/>
+<label x="116.84" y="76.2" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D2" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="C"/>
+<wire x1="134.62" y1="91.44" x2="149.86" y2="91.44" width="0.1524" layer="91"/>
+<label x="137.16" y="91.44" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QC"/>
+<wire x1="134.62" y1="35.56" x2="149.86" y2="35.56" width="0.1524" layer="91"/>
+<label x="137.16" y="35.56" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O3"/>
+<wire x1="114.3" y1="73.66" x2="121.92" y2="73.66" width="0.1524" layer="91"/>
+<label x="116.84" y="73.66" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D3" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="D"/>
+<wire x1="134.62" y1="88.9" x2="149.86" y2="88.9" width="0.1524" layer="91"/>
+<label x="137.16" y="88.9" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QD"/>
+<wire x1="134.62" y1="38.1" x2="149.86" y2="38.1" width="0.1524" layer="91"/>
+<label x="137.16" y="38.1" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O4"/>
+<wire x1="121.92" y1="71.12" x2="114.3" y2="71.12" width="0.1524" layer="91"/>
+<label x="116.84" y="71.12" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D4" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="E"/>
+<wire x1="134.62" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/>
+<label x="137.16" y="86.36" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QE"/>
+<wire x1="134.62" y1="40.64" x2="149.86" y2="40.64" width="0.1524" layer="91"/>
+<label x="137.16" y="40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O5"/>
+<wire x1="121.92" y1="68.58" x2="114.3" y2="68.58" width="0.1524" layer="91"/>
+<label x="116.84" y="68.58" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D5" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="F"/>
+<wire x1="134.62" y1="83.82" x2="149.86" y2="83.82" width="0.1524" layer="91"/>
+<label x="137.16" y="83.82" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QF"/>
+<wire x1="134.62" y1="43.18" x2="149.86" y2="43.18" width="0.1524" layer="91"/>
+<label x="137.16" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O6"/>
+<wire x1="114.3" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/>
+<label x="116.84" y="66.04" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D6" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="G"/>
+<wire x1="134.62" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/>
+<label x="137.16" y="81.28" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QG"/>
+<wire x1="134.62" y1="45.72" x2="149.86" y2="45.72" width="0.1524" layer="91"/>
+<label x="137.16" y="45.72" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O7"/>
+<wire x1="114.3" y1="63.5" x2="121.92" y2="63.5" width="0.1524" layer="91"/>
+<label x="116.84" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D7" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="H"/>
+<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.1524" layer="91"/>
+<label x="137.16" y="78.74" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QH"/>
+<wire x1="134.62" y1="48.26" x2="149.86" y2="48.26" width="0.1524" layer="91"/>
+<label x="137.16" y="48.26" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O8"/>
+<wire x1="114.3" y1="60.96" x2="121.92" y2="60.96" width="0.1524" layer="91"/>
+<label x="116.84" y="60.96" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QH*"/>
+<wire x1="58.42" y1="33.02" x2="60.96" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="33.02" x2="60.96" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="15.24" x2="180.34" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="15.24" x2="180.34" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="SER"/>
+<wire x1="180.34" y1="30.48" x2="175.26" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="IC2" gate="A" pin="QH*"/>
+<wire x1="149.86" y1="53.34" x2="142.24" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="53.34" x2="142.24" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="SER"/>
+<wire x1="142.24" y1="99.06" x2="149.86" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="D_IN" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="SER"/>
+<wire x1="33.02" y1="99.06" x2="20.32" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="99.06" x2="20.32" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="33.02" x2="5.08" y2="33.02" width="0.1524" layer="91"/>
+<label x="5.08" y="35.56" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D_CLK" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="SCK"/>
+<wire x1="33.02" y1="93.98" x2="17.78" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="93.98" x2="17.78" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="SCK"/>
+<wire x1="17.78" y1="50.8" x2="33.02" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="50.8" x2="17.78" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="40.64" x2="5.08" y2="40.64" width="0.1524" layer="91"/>
+<label x="5.08" y="43.18" size="1.778" layer="95"/>
+<wire x1="17.78" y1="40.64" x2="17.78" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="7.62" x2="187.96" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="7.62" x2="187.96" y2="35.56" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="SCK"/>
+<wire x1="175.26" y1="35.56" x2="187.96" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="35.56" x2="187.96" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="60.96" x2="144.78" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="CLK"/>
+<wire x1="149.86" y1="73.66" x2="144.78" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="73.66" x2="144.78" y2="60.96" width="0.1524" layer="91"/>
+<junction x="17.78" y="40.64"/>
+<junction x="187.96" y="35.56"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="IC2" gate="A" pin="RCK"/>
+<wire x1="175.26" y1="43.18" x2="185.42" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="43.18" x2="185.42" y2="10.16" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="10.16" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="RCK"/>
+<wire x1="33.02" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="RCK"/>
+<wire x1="33.02" y1="86.36" x2="25.4" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="86.36" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="SH/!LD"/>
+<wire x1="149.86" y1="68.58" x2="147.32" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="68.58" x2="147.32" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="63.5" x2="185.42" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="63.5" x2="185.42" y2="43.18" width="0.1524" layer="91"/>
+<junction x="25.4" y="43.18"/>
+<junction x="185.42" y="43.18"/>
+</segment>
+</net>
+<net name="VCC" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="SCL"/>
+<wire x1="33.02" y1="48.26" x2="27.94" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="48.26" x2="27.94" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="SCL"/>
+<wire x1="27.94" y1="91.44" x2="27.94" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="91.44" x2="27.94" y2="91.44" width="0.1524" layer="91"/>
+<junction x="27.94" y="91.44"/>
+<pinref part="P+1" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+</eagle>
diff --git a/hardware-v1/untitled.pro b/hardware-v1/untitled.pro
new file mode 100644
index 0000000..d77689b
--- /dev/null
+++ b/hardware-v1/untitled.pro
@@ -0,0 +1,25 @@
+EAGLE AutoRouter Statistics:
+
+Job : /home/trygvis/dev/io.trygvis/2013/02/ram-ice/untitled.brd
+
+Start at : 01:56:21 (2/10/13)
+End at : 01:56:21 (2/10/13)
+Elapsed time : 00:00:00
+
+Signals : 30 RoutingGrid: 50 mil Layers: 2
+Connections : 43 predefined: 0 ( 0 Vias )
+
+Router memory : 24708
+
+Passname : Busses Route Optimize1 Optimize2 Optimize3 Optimize4
+
+Time per pass : 00:00:00 00:00:00 00:00:00 00:00:00 00:00:00 00:00:00
+Number of Ripups : 0 0 0 0 0 0
+max. Level : 0 0 0 0 0 0
+max. Total : 0 0 0 0 0 0
+
+Routed : 0 0 0 0 0 0
+Vias : 0 0 0 0 0 0
+Resolution : 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 %
+
+Final : 0.0% finished
diff --git a/hardware/.gitignore b/hardware/.gitignore
new file mode 100644
index 0000000..ba66ed2
--- /dev/null
+++ b/hardware/.gitignore
@@ -0,0 +1,4 @@
+*.b#*
+*.s#*
+*.pro
+eagle.epf
diff --git a/vhdl/.gitignore b/vhdl/.gitignore
new file mode 100644
index 0000000..d6863ac
--- /dev/null
+++ b/vhdl/.gitignore
@@ -0,0 +1,26 @@
+ghdl
+
+# Xilix ISE excludes
+fuse.*
+iseconfig
+isim
+webtalk_pn.xml
+xilinxsim.ini
+xst
+_xmsgs
+.lso
+*.cmd
+*.cmd_log
+*_envsettings.html
+*.exe
+*.gise
+*.log
+*.lso
+*.prj
+*.stx
+*_summary.html
+*.syr
+*.wcfg
+*.wdb
+*.xrpt
+*.xst
diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd
deleted file mode 100644
index 22e1f51..0000000
--- a/vhdl/ice.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-library fmf;
-use fmf.std595;
-
-use work.all;
-
-entity ice is
- port (
- bit_in : in std_logic;
- bit_out : out std_logic;
- bit_clk : in std_logic;
- byte_clk : in std_logic;
- a_oe : in std_logic;
- d_oe : in std_logic;
-
- ah : out std_logic_vector(7 downto 0);
- al : out std_logic_vector(7 downto 0);
- d_out : out std_logic_vector(7 downto 0)
- );
-end;
-
-architecture behave of ice is
- signal ah_out : std_logic;
- signal al_out : std_logic;
- signal d_out_out : std_logic;
-begin
- ah_buf : entity fmf.std595(vhdl_behavioral) port map(
- ser => bit_in,
- qhser => ah_out,
- sck => bit_clk,
- rck => byte_clk,
- gneg => a_oe,
- qa => ah(0),
- qb => ah(1),
- qc => ah(2),
- qd => ah(3),
- qe => ah(4),
- qf => ah(5),
- qg => ah(6),
- qh => ah(7),
- SCLRNeg => '1'
- );
-
- al_buf : entity fmf.std595(vhdl_behavioral) port map(
- ser => ah_out,
- qhser => al_out,
- sck => bit_clk,
- rck => byte_clk,
- gneg => a_oe,
- qa => al(0),
- qb => al(1),
- qc => al(2),
- qd => al(3),
- qe => al(4),
- qf => al(5),
- qg => al(6),
- qh => al(7),
- SCLRNeg => '1'
- );
-
- d_out_buf : entity fmf.std595(vhdl_behavioral) port map(
- ser => al_out,
- qhser => d_out_out,
- sck => bit_clk,
- rck => byte_clk,
- gneg => d_oe,
- qa => d_out(0),
- qb => d_out(1),
- qc => d_out(2),
- qd => d_out(3),
- qe => d_out(4),
- qf => d_out(5),
- qg => d_out(6),
- qh => d_out(7),
- SCLRNeg => '1'
- );
-end;
diff --git a/vhdl/ice_tb.vhd b/vhdl/ice_tb.vhd
deleted file mode 100644
index 24916cd..0000000
--- a/vhdl/ice_tb.vhd
+++ /dev/null
@@ -1,66 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use work.all;
-
-entity ice_tb is
-end ice_tb;
-
-architecture ice_tb_arch of ice_tb is
- signal bit_in : std_logic;
- signal bit_out : std_logic;
- signal bit_clk : std_logic := '0';
- signal byte_clk : std_logic := '0';
- signal a_oe : std_logic := '1';
- signal d_oe : std_logic := '1';
-
- signal ah : std_logic_vector(7 downto 0);
- signal al : std_logic_vector(7 downto 0);
- signal d_out : std_logic_vector(7 downto 0);
-
- constant tClk : time := 1 ns;
-begin
- ice : entity work.ice port map(bit_in, bit_out, bit_clk, byte_clk, a_oe, d_oe, ah, al, d_out);
-
- stimulus : process
- procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
- begin
- for i in byte'range loop
- bit_in <= byte(i);
- bit_clk <= '1';
- wait for tClk;
-
- bit_clk <= '0';
- wait for tClk;
- end loop;
-
- byte_clk <= '1';
- wait for tClk;
-
- byte_clk <= '0';
- wait for tClk;
- end;
-
- procedure write_ram(
- data : in std_logic_vector(7 downto 0);
- address : in std_logic_vector(15 downto 0)) is
- begin
- -- TODO: busreq + wait for busack
- byte_out(data);
- byte_out(address(7 downto 0));
- byte_out(address(15 downto 8));
- end;
-
- begin
- write_ram("10100101", "0000000000000001");
- d_oe <= '0';
- a_oe <= '0';
-
- wait for tClk;
- assert ah = "00000000" report "ah failed";
- assert al = "00000001" report "al failed";
- assert d_out = "10100101" report "d_out failed";
-
- assert false report "end of test" severity note;
- wait;
- end process;
-end;
diff --git a/vhdl/ieee_proposed/std_logic_1164_additions.vhdl b/vhdl/ieee_proposed/std_logic_1164_additions.vhdl
new file mode 100644
index 0000000..15f1341
--- /dev/null
+++ b/vhdl/ieee_proposed/std_logic_1164_additions.vhdl
@@ -0,0 +1,1680 @@
+------------------------------------------------------------------------------
+-- "std_logic_1164_additions" package contains the additions to the standard
+-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
+-- This package should be compiled into "ieee_proposed" and used as follows:
+-- use ieee.std_logic_1164.all;
+-- use ieee_proposed.std_logic_1164_additions.all;
+-- Last Modified: $Date: 2010/09/22 18:32:33 $
+-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
+--
+-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+package std_logic_1164_additions is
+
+ -- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
+ -- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
+ -- take inputs in STD_LOGIC_VECTOR.
+ -- For compatability with VHDL-2002, I have replicated all of these funcitons
+ -- here for STD_LOGIC_VECTOR.
+ -- new aliases
+ alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
+ alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
+ alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
+ alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
+ alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
+ alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+ alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
+ alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+ alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
+ alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
+ alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
+ alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
+
+ function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC_VECTOR;
+ function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC;
+ function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC_VECTOR;
+ function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC;
+
+ -------------------------------------------------------------------
+ -- overloaded shift operators
+ -------------------------------------------------------------------
+
+ function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
+ function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+
+ function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
+ function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+
+ function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
+ function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+
+ function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
+ function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+ -------------------------------------------------------------------
+ -- vector/scalar overloaded logical operators
+ -------------------------------------------------------------------
+ function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
+ function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+ function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+ -------------------------------------------------------------------
+ -- vector-reduction functions.
+ -- "and" functions default to "1", or defaults to "0"
+ -------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- %%% Replace the "_reduce" functions with the ones commented out below.
+ -----------------------------------------------------------------------------
+ -- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ -- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ -- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ -- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ -- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ -- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
+ -- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
+ function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ -------------------------------------------------------------------
+ -- ?= operators, same functionality as 1076.3 1994 std_match
+ -------------------------------------------------------------------
+-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
+-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
+-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
+-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
+-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
+-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
+-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
+-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
+-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
+-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
+
+ function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
+ function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+ function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
+
+
+ -- "??" operator, converts a std_ulogic to a boolean.
+ --%%% Uncomment the following operators
+ -- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
+ --%%% REMOVE the following funciton (for testing only)
+ function \??\ (S : STD_ULOGIC) return BOOLEAN;
+
+ -- rtl_synthesis off
+-- pragma synthesis_off
+ function to_string (value : STD_ULOGIC) return STRING;
+ function to_string (value : STD_ULOGIC_VECTOR) return STRING;
+ function to_string (value : STD_LOGIC_VECTOR) return STRING;
+
+ -- explicitly defined operations
+
+ alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+ alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+ function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+ alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
+ function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+ alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+
+ alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+ alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
+ alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+ alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+ alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+ alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+ alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+ alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
+
+ alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+ alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+ procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+ alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+ procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+ alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+ alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
+ alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
+ function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
+ alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
+ function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
+ alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
+
+ procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+
+ alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
+ alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
+ alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
+ alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
+ alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
+ alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
+ procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
+ alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
+ alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
+
+ alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
+ alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
+
+ procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+ alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
+
+ procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
+ alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
+ -- rtl_synthesis on
+-- pragma synthesis_on
+ function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
+ function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+ function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+ function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
+end package std_logic_1164_additions;
+
+package body std_logic_1164_additions is
+ type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
+ -----------------------------------------------------------------------------
+ -- New/updated funcitons for VHDL-200X fast track
+ -----------------------------------------------------------------------------
+ -- to_01
+ -------------------------------------------------------------------
+ function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC_VECTOR is
+ variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
+ variable BAD_ELEMENT : BOOLEAN := false;
+ alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
+ begin
+ for I in RESULT'range loop
+ case XS(I) is
+ when '0' | 'L' => RESULT(I) := '0';
+ when '1' | 'H' => RESULT(I) := '1';
+ when others => BAD_ELEMENT := true;
+ end case;
+ end loop;
+ if BAD_ELEMENT then
+ for I in RESULT'range loop
+ RESULT(I) := XMAP; -- standard fixup
+ end loop;
+ end if;
+ return RESULT;
+ end function TO_01;
+ -------------------------------------------------------------------
+ function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC is
+ begin
+ case s is
+ when '0' | 'L' => RETURN '0';
+ when '1' | 'H' => RETURN '1';
+ when others => return xmap;
+ end case;
+ end function TO_01;
+ -------------------------------------------------------------------
+ function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC_VECTOR is
+ variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
+ alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
+ begin
+ for I in RESULT'range loop
+ case XS(I) is
+ when '0' => RESULT(I) := '0';
+ when '1' => RESULT(I) := '1';
+ end case;
+ end loop;
+ return RESULT;
+ end function TO_01;
+ -------------------------------------------------------------------
+ function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
+ return STD_ULOGIC is
+ begin
+ case s is
+ when '0' => RETURN '0';
+ when '1' => RETURN '1';
+ end case;
+ end function TO_01;
+-- end Bugzilla issue #148
+ -------------------------------------------------------------------
+
+ -------------------------------------------------------------------
+ -- overloaded shift operators
+ -------------------------------------------------------------------
+
+ -------------------------------------------------------------------
+ -- sll
+ -------------------------------------------------------------------
+ function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
+ begin
+ if r >= 0 then
+ result(1 to l'length - r) := lv(r + 1 to l'length);
+ else
+ result := l srl -r;
+ end if;
+ return result;
+ end function "sll";
+ -------------------------------------------------------------------
+ function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
+ begin
+ if r >= 0 then
+ result(1 to l'length - r) := lv(r + 1 to l'length);
+ else
+ result := l srl -r;
+ end if;
+ return result;
+ end function "sll";
+
+ -------------------------------------------------------------------
+ -- srl
+ -------------------------------------------------------------------
+ function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
+ begin
+ if r >= 0 then
+ result(r + 1 to l'length) := lv(1 to l'length - r);
+ else
+ result := l sll -r;
+ end if;
+ return result;
+ end function "srl";
+ -------------------------------------------------------------------
+ function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
+ begin
+ if r >= 0 then
+ result(r + 1 to l'length) := lv(1 to l'length - r);
+ else
+ result := l sll -r;
+ end if;
+ return result;
+ end function "srl";
+
+ -------------------------------------------------------------------
+ -- rol
+ -------------------------------------------------------------------
+ function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ constant rm : INTEGER := r mod l'length;
+ begin
+ if r >= 0 then
+ result(1 to l'length - rm) := lv(rm + 1 to l'length);
+ result(l'length - rm + 1 to l'length) := lv(1 to rm);
+ else
+ result := l ror -r;
+ end if;
+ return result;
+ end function "rol";
+ -------------------------------------------------------------------
+ function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ constant rm : INTEGER := r mod l'length;
+ begin
+ if r >= 0 then
+ result(1 to l'length - rm) := lv(rm + 1 to l'length);
+ result(l'length - rm + 1 to l'length) := lv(1 to rm);
+ else
+ result := l ror -r;
+ end if;
+ return result;
+ end function "rol";
+
+ -------------------------------------------------------------------
+ -- ror
+ -------------------------------------------------------------------
+ function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
+ constant rm : INTEGER := r mod l'length;
+ begin
+ if r >= 0 then
+ result(rm + 1 to l'length) := lv(1 to l'length - rm);
+ result(1 to rm) := lv(l'length - rm + 1 to l'length);
+ else
+ result := l rol -r;
+ end if;
+ return result;
+ end function "ror";
+ -------------------------------------------------------------------
+ function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
+ constant rm : INTEGER := r mod l'length;
+ begin
+ if r >= 0 then
+ result(rm + 1 to l'length) := lv(1 to l'length - rm);
+ result(1 to rm) := lv(l'length - rm + 1 to l'length);
+ else
+ result := l rol -r;
+ end if;
+ return result;
+ end function "ror";
+ -------------------------------------------------------------------
+ -- vector/scalar overloaded logical operators
+ -------------------------------------------------------------------
+
+ -------------------------------------------------------------------
+ -- and
+ -------------------------------------------------------------------
+ function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "and" (lv(i), r);
+ end loop;
+ return result;
+ end function "and";
+ -------------------------------------------------------------------
+ function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "and" (lv(i), r);
+ end loop;
+ return result;
+ end function "and";
+ -------------------------------------------------------------------
+ function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "and" (l, rv(i));
+ end loop;
+ return result;
+ end function "and";
+ -------------------------------------------------------------------
+ function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "and" (l, rv(i));
+ end loop;
+ return result;
+ end function "and";
+
+ -------------------------------------------------------------------
+ -- nand
+ -------------------------------------------------------------------
+ function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("and" (lv(i), r));
+ end loop;
+ return result;
+ end function "nand";
+ -------------------------------------------------------------------
+ function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("and" (lv(i), r));
+ end loop;
+ return result;
+ end function "nand";
+ -------------------------------------------------------------------
+ function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("and" (l, rv(i)));
+ end loop;
+ return result;
+ end function "nand";
+ -------------------------------------------------------------------
+ function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("and" (l, rv(i)));
+ end loop;
+ return result;
+ end function "nand";
+
+ -------------------------------------------------------------------
+ -- or
+ -------------------------------------------------------------------
+ function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "or" (lv(i), r);
+ end loop;
+ return result;
+ end function "or";
+ -------------------------------------------------------------------
+ function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "or" (lv(i), r);
+ end loop;
+ return result;
+ end function "or";
+ -------------------------------------------------------------------
+ function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "or" (l, rv(i));
+ end loop;
+ return result;
+ end function "or";
+ -------------------------------------------------------------------
+ function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "or" (l, rv(i));
+ end loop;
+ return result;
+ end function "or";
+
+ -------------------------------------------------------------------
+ -- nor
+ -------------------------------------------------------------------
+ function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("or" (lv(i), r));
+ end loop;
+ return result;
+ end function "nor";
+ -------------------------------------------------------------------
+ function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("or" (lv(i), r));
+ end loop;
+ return result;
+ end function "nor";
+ -------------------------------------------------------------------
+ function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("or" (l, rv(i)));
+ end loop;
+ return result;
+ end function "nor";
+ -------------------------------------------------------------------
+ function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("or" (l, rv(i)));
+ end loop;
+ return result;
+ end function "nor";
+
+ -------------------------------------------------------------------
+ -- xor
+ -------------------------------------------------------------------
+ function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "xor" (lv(i), r);
+ end loop;
+ return result;
+ end function "xor";
+ -------------------------------------------------------------------
+ function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "xor" (lv(i), r);
+ end loop;
+ return result;
+ end function "xor";
+ -------------------------------------------------------------------
+ function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "xor" (l, rv(i));
+ end loop;
+ return result;
+ end function "xor";
+ -------------------------------------------------------------------
+ function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "xor" (l, rv(i));
+ end loop;
+ return result;
+ end function "xor";
+
+ -------------------------------------------------------------------
+ -- xnor
+ -------------------------------------------------------------------
+ function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
+ alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_LOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("xor" (lv(i), r));
+ end loop;
+ return result;
+ end function "xnor";
+ -------------------------------------------------------------------
+ function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+ alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
+ variable result : STD_ULOGIC_VECTOR (1 to l'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("xor" (lv(i), r));
+ end loop;
+ return result;
+ end function "xnor";
+ -------------------------------------------------------------------
+ function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_LOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("xor" (l, rv(i)));
+ end loop;
+ return result;
+ end function "xnor";
+ -------------------------------------------------------------------
+ function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
+ variable result : STD_ULOGIC_VECTOR (1 to r'length);
+ begin
+ for i in result'range loop
+ result(i) := "not"("xor" (l, rv(i)));
+ end loop;
+ return result;
+ end function "xnor";
+
+ -------------------------------------------------------------------
+ -- vector-reduction functions
+ -------------------------------------------------------------------
+
+ -------------------------------------------------------------------
+ -- and
+ -------------------------------------------------------------------
+ function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return and_reduce (to_StdULogicVector (l));
+ end function and_reduce;
+ -------------------------------------------------------------------
+ function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ variable result : STD_ULOGIC := '1';
+ begin
+ for i in l'reverse_range loop
+ result := (l(i) and result);
+ end loop;
+ return result;
+ end function and_reduce;
+
+ -------------------------------------------------------------------
+ -- nand
+ -------------------------------------------------------------------
+ function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return not (and_reduce(to_StdULogicVector(l)));
+ end function nand_reduce;
+ -------------------------------------------------------------------
+ function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return not (and_reduce(l));
+ end function nand_reduce;
+
+ -------------------------------------------------------------------
+ -- or
+ -------------------------------------------------------------------
+ function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return or_reduce (to_StdULogicVector (l));
+ end function or_reduce;
+ -------------------------------------------------------------------
+ function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ variable result : STD_ULOGIC := '0';
+ begin
+ for i in l'reverse_range loop
+ result := (l(i) or result);
+ end loop;
+ return result;
+ end function or_reduce;
+
+ -------------------------------------------------------------------
+ -- nor
+ -------------------------------------------------------------------
+ function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return "not"(or_reduce(To_StdULogicVector(l)));
+ end function nor_reduce;
+ -------------------------------------------------------------------
+ function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return "not"(or_reduce(l));
+ end function nor_reduce;
+
+ -------------------------------------------------------------------
+ -- xor
+ -------------------------------------------------------------------
+ function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return xor_reduce (to_StdULogicVector (l));
+ end function xor_reduce;
+ -------------------------------------------------------------------
+ function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ variable result : STD_ULOGIC := '0';
+ begin
+ for i in l'reverse_range loop
+ result := (l(i) xor result);
+ end loop;
+ return result;
+ end function xor_reduce;
+
+ -------------------------------------------------------------------
+ -- xnor
+ -------------------------------------------------------------------
+ function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return "not"(xor_reduce(To_StdULogicVector(l)));
+ end function xnor_reduce;
+ -------------------------------------------------------------------
+ function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return "not"(xor_reduce(l));
+ end function xnor_reduce;
+ -- %%% End "remove the following functions"
+
+ constant match_logic_table : stdlogic_table := (
+ -----------------------------------------------------
+ -- U X 0 1 Z W L H - | |
+ -----------------------------------------------------
+ ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
+ ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
+ );
+
+ -------------------------------------------------------------------
+ -- ?= functions, Similar to "std_match", but returns "std_ulogic".
+ -------------------------------------------------------------------
+ -- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
+ function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return match_logic_table (l, r);
+ end function \?=\;
+ -- %%% END FUNCTION "?=";
+ -------------------------------------------------------------------
+ -- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
+ function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
+ alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
+ variable result, result1 : STD_ULOGIC; -- result
+ begin
+ -- Logically identical to an "=" operator.
+ if ((l'length < 1) and (r'length < 1)) then
+ -- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
+ return '1';
+ elsif lv'length /= rv'length then
+ -- Two arrays of different lengths are false
+ return '0';
+ else
+ result := '1';
+ for i in lv'low to lv'high loop
+ result1 := match_logic_table(lv(i), rv(i));
+ result := result and result1;
+ end loop;
+ return result;
+ end if;
+ end function \?=\;
+ -- %%% END FUNCTION "?=";
+ -------------------------------------------------------------------
+ -- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
+ function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
+ alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
+ variable result, result1 : STD_ULOGIC;
+ begin
+ -- Logically identical to an "=" operator.
+ if ((l'length < 1) and (r'length < 1)) then
+ -- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
+ return '1';
+ elsif lv'length /= rv'length then
+ -- Two arrays of different lengths are false
+ return '0';
+ else
+ result := '1';
+ for i in lv'low to lv'high loop
+ result1 := match_logic_table(lv(i), rv(i));
+ result := result and result1;
+ end loop;
+ return result;
+ end if;
+ end function \?=\;
+ -- %%% END FUNCTION "?=";
+ -- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return not \?=\ (l, r);
+ end function \?/=\;
+ -- %%% END FUNCTION "?/=";
+ -- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
+ function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return not \?=\ (l, r);
+ end function \?/=\;
+ -- %%% END FUNCTION "?/=";
+ -- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
+ function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
+ begin
+ return not \?=\ (l, r);
+ end function \?/=\;
+ -- %%% END FUNCTION "?/=";
+
+ -- Table for the ?< function (Section 9.2.3)
+ constant qlt : stdlogic_table := (
+ -----------------------------------------------------
+ -- U X 0 1 Z W L H - | |
+ -----------------------------------------------------
+ ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
+ ('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
+ ('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
+ ('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
+ );
+
+ -- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return not (qlt (l, r) or match_logic_table (l,r));
+ end function \?>\;
+ -- %%% END FUNCTION "?>";
+
+ -- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return not qlt (l, r);
+ end function \?>=\;
+ -- %%% END FUNCTION "?>=";
+
+ -- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return qlt (l, r);
+ end function \?<\;
+ -- %%% END FUNCTION "?<";
+
+ -- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return qlt (l, r) or match_logic_table (l,r);
+ end function \?<=\;
+ -- %%% END FUNCTION "?<=";
+
+ -- "??" operator, converts a std_ulogic to a boolean.
+-- %%% FUNCTION "??"
+ function \??\ (S : STD_ULOGIC) return BOOLEAN is
+ begin
+ return S = '1' or S = 'H';
+ end function \??\;
+-- %%% END FUNCTION "??";
+
+ -- rtl_synthesis off
+-- pragma synthesis_off
+ -----------------------------------------------------------------------------
+ -- This section copied from "std_logic_textio"
+ -----------------------------------------------------------------------------
+ -- Type and constant definitions used to map STD_ULOGIC values
+ -- into/from character values.
+ type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
+ type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
+ type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
+ type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
+ constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
+ constant char_to_MVL9 : MVL9_indexed_by_char :=
+ ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+ 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
+ constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
+ ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+ 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
+
+ constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
+ constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
+
+ -- purpose: Skips white space
+ procedure skip_whitespace (
+ L : inout LINE) is
+ variable readOk : BOOLEAN;
+ variable c : CHARACTER;
+ begin
+ while L /= null and L.all'length /= 0 loop
+ if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
+ read (l, c, readOk);
+ else
+ exit;
+ end if;
+ end loop;
+ end procedure skip_whitespace;
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
+ GOOD : out BOOLEAN) is
+ variable c : CHARACTER;
+ variable readOk : BOOLEAN;
+ begin
+ VALUE := 'U'; -- initialize to a "U"
+ Skip_whitespace (L);
+ read (l, c, readOk);
+ if not readOk then
+ good := false;
+ else
+ if char_to_MVL9plus(c) = error then
+ good := false;
+ else
+ VALUE := char_to_MVL9(c);
+ good := true;
+ end if;
+ end if;
+ end procedure READ;
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable m : STD_ULOGIC;
+ variable c : CHARACTER;
+ variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
+ variable readOk : BOOLEAN;
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then
+ read (l, c, readOk);
+ i := 0;
+ good := false;
+ while i < VALUE'length loop
+ if not readOk then -- Bail out if there was a bad read
+ return;
+ elsif c = '_' then
+ if i = 0 then -- Begins with an "_"
+ return;
+ elsif lastu then -- "__" detected
+ return;
+ else
+ lastu := true;
+ end if;
+ elsif (char_to_MVL9plus(c) = error) then -- Illegal character
+ return;
+ else
+ mv(i) := char_to_MVL9(c);
+ i := i + 1;
+ if i > mv'high then -- reading done
+ good := true;
+ VALUE := mv;
+ return;
+ end if;
+ lastu := false;
+ end if;
+ read(L, c, readOk);
+ end loop;
+ else
+ good := true; -- read into a null array
+ end if;
+ end procedure READ;
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
+ variable c : CHARACTER;
+ variable readOk : BOOLEAN;
+ begin
+ VALUE := 'U'; -- initialize to a "U"
+ Skip_whitespace (L);
+ read (l, c, readOk);
+ if not readOk then
+ report "STD_LOGIC_1164.READ(STD_ULOGIC) "
+ & "End of string encountered"
+ severity error;
+ return;
+ elsif char_to_MVL9plus(c) = error then
+ report
+ "STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
+ c & "' read, expected STD_ULOGIC literal."
+ severity error;
+ else
+ VALUE := char_to_MVL9(c);
+ end if;
+ end procedure READ;
+
+ procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
+ variable m : STD_ULOGIC;
+ variable c : CHARACTER;
+ variable readOk : BOOLEAN;
+ variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then -- non Null input string
+ read (l, c, readOk);
+ i := 0;
+ while i < VALUE'length loop
+ if readOk = false then -- Bail out if there was a bad read
+ report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
+ & "End of string encountered"
+ severity error;
+ return;
+ elsif c = '_' then
+ if i = 0 then
+ report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
+ & "String begins with an ""_""" severity error;
+ return;
+ elsif lastu then
+ report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
+ & "Two underscores detected in input string ""__"""
+ severity error;
+ return;
+ else
+ lastu := true;
+ end if;
+ elsif c = ' ' or c = NBSP or c = HT then -- reading done.
+ report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
+ & "Short read, Space encounted in input string"
+ severity error;
+ return;
+ elsif char_to_MVL9plus(c) = error then
+ report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
+ & "Error: Character '" &
+ c & "' read, expected STD_ULOGIC literal."
+ severity error;
+ return;
+ else
+ mv(i) := char_to_MVL9(c);
+ i := i + 1;
+ if i > mv'high then
+ VALUE := mv;
+ return;
+ end if;
+ lastu := false;
+ end if;
+ read(L, c, readOk);
+ end loop;
+ end if;
+ end procedure READ;
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ begin
+ write(l, MVL9_to_char(VALUE), justified, field);
+ end procedure WRITE;
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ variable s : STRING(1 to VALUE'length);
+ variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
+ begin
+ for i in 1 to VALUE'length loop
+ s(i) := MVL9_to_char(m(i));
+ end loop;
+ write(l, s, justified, field);
+ end procedure WRITE;
+
+ -- Read and Write procedures for STD_LOGIC_VECTOR
+
+ procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ READ (L => L, VALUE => ivalue, GOOD => GOOD);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure READ;
+
+ procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ READ (L => L, VALUE => ivalue);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure READ;
+
+ procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ variable s : STRING(1 to VALUE'length);
+ variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
+ begin
+ for i in 1 to VALUE'length loop
+ s(i) := MVL9_to_char(m(i));
+ end loop;
+ write(L, s, justified, field);
+ end procedure WRITE;
+
+ -----------------------------------------------------------------------
+ -- Alias for bread and bwrite are provided with call out the read and
+ -- write functions.
+ -----------------------------------------------------------------------
+
+ -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
+ -- Modified from the original to be more forgiving.
+
+ procedure Char2QuadBits (C : CHARACTER;
+ RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
+ GOOD : out BOOLEAN;
+ ISSUE_ERROR : in BOOLEAN) is
+ begin
+ case c is
+ when '0' => result := x"0"; good := true;
+ when '1' => result := x"1"; good := true;
+ when '2' => result := x"2"; good := true;
+ when '3' => result := x"3"; good := true;
+ when '4' => result := x"4"; good := true;
+ when '5' => result := x"5"; good := true;
+ when '6' => result := x"6"; good := true;
+ when '7' => result := x"7"; good := true;
+ when '8' => result := x"8"; good := true;
+ when '9' => result := x"9"; good := true;
+ when 'A' | 'a' => result := x"A"; good := true;
+ when 'B' | 'b' => result := x"B"; good := true;
+ when 'C' | 'c' => result := x"C"; good := true;
+ when 'D' | 'd' => result := x"D"; good := true;
+ when 'E' | 'e' => result := x"E"; good := true;
+ when 'F' | 'f' => result := x"F"; good := true;
+ when 'Z' => result := "ZZZZ"; good := true;
+ when 'X' => result := "XXXX"; good := true;
+ when others =>
+ assert not ISSUE_ERROR
+ report
+ "STD_LOGIC_1164.HREAD Read a '" & c &
+ "', expected a Hex character (0-F)."
+ severity error;
+ good := false;
+ end case;
+ end procedure Char2QuadBits;
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable ok : BOOLEAN;
+ variable c : CHARACTER;
+ constant ne : INTEGER := (VALUE'length+3)/4;
+ constant pad : INTEGER := ne*4 - VALUE'length;
+ variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then
+ read (l, c, ok);
+ i := 0;
+ while i < ne loop
+ -- Bail out if there was a bad read
+ if not ok then
+ good := false;
+ return;
+ elsif c = '_' then
+ if i = 0 then
+ good := false; -- Begins with an "_"
+ return;
+ elsif lastu then
+ good := false; -- "__" detected
+ return;
+ else
+ lastu := true;
+ end if;
+ else
+ Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
+ if not ok then
+ good := false;
+ return;
+ end if;
+ i := i + 1;
+ lastu := false;
+ end if;
+ if i < ne then
+ read(L, c, ok);
+ end if;
+ end loop;
+ if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
+ good := false; -- vector was truncated.
+ else
+ good := true;
+ VALUE := sv (pad to sv'high);
+ end if;
+ else
+ good := true; -- Null input string, skips whitespace
+ end if;
+ end procedure HREAD;
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
+ variable ok : BOOLEAN;
+ variable c : CHARACTER;
+ constant ne : INTEGER := (VALUE'length+3)/4;
+ constant pad : INTEGER := ne*4 - VALUE'length;
+ variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then -- non Null input string
+ read (l, c, ok);
+ i := 0;
+ while i < ne loop
+ -- Bail out if there was a bad read
+ if not ok then
+ report "STD_LOGIC_1164.HREAD "
+ & "End of string encountered"
+ severity error;
+ return;
+ end if;
+ if c = '_' then
+ if i = 0 then
+ report "STD_LOGIC_1164.HREAD "
+ & "String begins with an ""_""" severity error;
+ return;
+ elsif lastu then
+ report "STD_LOGIC_1164.HREAD "
+ & "Two underscores detected in input string ""__"""
+ severity error;
+ return;
+ else
+ lastu := true;
+ end if;
+ else
+ Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
+ if not ok then
+ return;
+ end if;
+ i := i + 1;
+ lastu := false;
+ end if;
+ if i < ne then
+ read(L, c, ok);
+ end if;
+ end loop;
+ if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
+ report "STD_LOGIC_1164.HREAD Vector truncated"
+ severity error;
+ else
+ VALUE := sv (pad to sv'high);
+ end if;
+ end if;
+ end procedure HREAD;
+
+ procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ begin
+ write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
+ end procedure HWRITE;
+
+
+ -- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
+ -- Modified from the original to be more forgiving.
+
+ procedure Char2TriBits (C : CHARACTER;
+ RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
+ GOOD : out BOOLEAN;
+ ISSUE_ERROR : in BOOLEAN) is
+ begin
+ case c is
+ when '0' => result := o"0"; good := true;
+ when '1' => result := o"1"; good := true;
+ when '2' => result := o"2"; good := true;
+ when '3' => result := o"3"; good := true;
+ when '4' => result := o"4"; good := true;
+ when '5' => result := o"5"; good := true;
+ when '6' => result := o"6"; good := true;
+ when '7' => result := o"7"; good := true;
+ when 'Z' => result := "ZZZ"; good := true;
+ when 'X' => result := "XXX"; good := true;
+ when others =>
+ assert not ISSUE_ERROR
+ report
+ "STD_LOGIC_1164.OREAD Error: Read a '" & c &
+ "', expected an Octal character (0-7)."
+ severity error;
+ good := false;
+ end case;
+ end procedure Char2TriBits;
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable ok : BOOLEAN;
+ variable c : CHARACTER;
+ constant ne : INTEGER := (VALUE'length+2)/3;
+ constant pad : INTEGER := ne*3 - VALUE'length;
+ variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then
+ read (l, c, ok);
+ i := 0;
+ while i < ne loop
+ -- Bail out if there was a bad read
+ if not ok then
+ good := false;
+ return;
+ elsif c = '_' then
+ if i = 0 then
+ good := false; -- Begins with an "_"
+ return;
+ elsif lastu then
+ good := false; -- "__" detected
+ return;
+ else
+ lastu := true;
+ end if;
+ else
+ Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
+ if not ok then
+ good := false;
+ return;
+ end if;
+ i := i + 1;
+ lastu := false;
+ end if;
+ if i < ne then
+ read(L, c, ok);
+ end if;
+ end loop;
+ if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
+ good := false; -- vector was truncated.
+ else
+ good := true;
+ VALUE := sv (pad to sv'high);
+ end if;
+ else
+ good := true; -- read into a null array
+ end if;
+ end procedure OREAD;
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
+ variable c : CHARACTER;
+ variable ok : BOOLEAN;
+ constant ne : INTEGER := (VALUE'length+2)/3;
+ constant pad : INTEGER := ne*3 - VALUE'length;
+ variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
+ variable i : INTEGER;
+ variable lastu : BOOLEAN := false; -- last character was an "_"
+ begin
+ VALUE := (VALUE'range => 'U'); -- initialize to a "U"
+ Skip_whitespace (L);
+ if VALUE'length > 0 then
+ read (l, c, ok);
+ i := 0;
+ while i < ne loop
+ -- Bail out if there was a bad read
+ if not ok then
+ report "STD_LOGIC_1164.OREAD "
+ & "End of string encountered"
+ severity error;
+ return;
+ elsif c = '_' then
+ if i = 0 then
+ report "STD_LOGIC_1164.OREAD "
+ & "String begins with an ""_""" severity error;
+ return;
+ elsif lastu then
+ report "STD_LOGIC_1164.OREAD "
+ & "Two underscores detected in input string ""__"""
+ severity error;
+ return;
+ else
+ lastu := true;
+ end if;
+ else
+ Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
+ if not ok then
+ return;
+ end if;
+ i := i + 1;
+ lastu := false;
+ end if;
+ if i < ne then
+ read(L, c, ok);
+ end if;
+ end loop;
+ if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
+ report "STD_LOGIC_1164.OREAD Vector truncated"
+ severity error;
+ else
+ VALUE := sv (pad to sv'high);
+ end if;
+ end if;
+ end procedure OREAD;
+
+ procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ begin
+ write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
+ end procedure OWRITE;
+
+ -- Hex Read and Write procedures for STD_LOGIC_VECTOR
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure HREAD;
+
+ procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ HREAD (L => L, VALUE => ivalue);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure HREAD;
+
+ procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ begin
+ write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
+ end procedure HWRITE;
+
+ -- Octal Read and Write procedures for STD_LOGIC_VECTOR
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
+ GOOD : out BOOLEAN) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure OREAD;
+
+ procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
+ variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
+ begin
+ OREAD (L => L, VALUE => ivalue);
+ VALUE := to_stdlogicvector (ivalue);
+ end procedure OREAD;
+
+ procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
+ JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
+ begin
+ write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
+ end procedure OWRITE;
+
+ -----------------------------------------------------------------------------
+ -- New string functions for vhdl-200x fast track
+ -----------------------------------------------------------------------------
+ function to_string (value : STD_ULOGIC) return STRING is
+ variable result : STRING (1 to 1);
+ begin
+ result (1) := MVL9_to_char (value);
+ return result;
+ end function to_string;
+ -------------------------------------------------------------------
+ -- TO_STRING (an alias called "to_bstring" is provide)
+ -------------------------------------------------------------------
+ function to_string (value : STD_ULOGIC_VECTOR) return STRING is
+ alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
+ variable result : STRING(1 to value'length);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ for i in ivalue'range loop
+ result(i) := MVL9_to_char(iValue(i));
+ end loop;
+ return result;
+ end if;
+ end function to_string;
+
+ -------------------------------------------------------------------
+ -- TO_HSTRING
+ -------------------------------------------------------------------
+ function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
+ constant ne : INTEGER := (value'length+3)/4;
+ variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+ variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
+ variable result : STRING(1 to ne);
+ variable quad : STD_ULOGIC_VECTOR(0 to 3);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value (value'left) = 'Z' then
+ pad := (others => 'Z');
+ else
+ pad := (others => '0');
+ end if;
+ ivalue := pad & value;
+ for i in 0 to ne-1 loop
+ quad := To_X01Z(ivalue(4*i to 4*i+3));
+ case quad is
+ when x"0" => result(i+1) := '0';
+ when x"1" => result(i+1) := '1';
+ when x"2" => result(i+1) := '2';
+ when x"3" => result(i+1) := '3';
+ when x"4" => result(i+1) := '4';
+ when x"5" => result(i+1) := '5';
+ when x"6" => result(i+1) := '6';
+ when x"7" => result(i+1) := '7';
+ when x"8" => result(i+1) := '8';
+ when x"9" => result(i+1) := '9';
+ when x"A" => result(i+1) := 'A';
+ when x"B" => result(i+1) := 'B';
+ when x"C" => result(i+1) := 'C';
+ when x"D" => result(i+1) := 'D';
+ when x"E" => result(i+1) := 'E';
+ when x"F" => result(i+1) := 'F';
+ when "ZZZZ" => result(i+1) := 'Z';
+ when others => result(i+1) := 'X';
+ end case;
+ end loop;
+ return result;
+ end if;
+ end function to_hstring;
+
+ -------------------------------------------------------------------
+ -- TO_OSTRING
+ -------------------------------------------------------------------
+ function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
+ constant ne : INTEGER := (value'length+2)/3;
+ variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
+ variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
+ variable result : STRING(1 to ne);
+ variable tri : STD_ULOGIC_VECTOR(0 to 2);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value (value'left) = 'Z' then
+ pad := (others => 'Z');
+ else
+ pad := (others => '0');
+ end if;
+ ivalue := pad & value;
+ for i in 0 to ne-1 loop
+ tri := To_X01Z(ivalue(3*i to 3*i+2));
+ case tri is
+ when o"0" => result(i+1) := '0';
+ when o"1" => result(i+1) := '1';
+ when o"2" => result(i+1) := '2';
+ when o"3" => result(i+1) := '3';
+ when o"4" => result(i+1) := '4';
+ when o"5" => result(i+1) := '5';
+ when o"6" => result(i+1) := '6';
+ when o"7" => result(i+1) := '7';
+ when "ZZZ" => result(i+1) := 'Z';
+ when others => result(i+1) := 'X';
+ end case;
+ end loop;
+ return result;
+ end if;
+ end function to_ostring;
+
+ function to_string (value : STD_LOGIC_VECTOR) return STRING is
+ begin
+ return to_string (to_stdulogicvector (value));
+ end function to_string;
+
+ function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
+ begin
+ return to_hstring (to_stdulogicvector (value));
+ end function to_hstring;
+
+ function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
+ begin
+ return to_ostring (to_stdulogicvector (value));
+ end function to_ostring;
+
+ -- rtl_synthesis on
+-- pragma synthesis_on
+ function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ begin -- function maximum
+ if L > R then return L;
+ else return R;
+ end if;
+ end function maximum;
+
+ -- std_logic_vector output
+ function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+ begin -- function minimum
+ if L > R then return R;
+ else return L;
+ end if;
+ end function minimum;
+
+ function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ begin -- function maximum
+ if L > R then return L;
+ else return R;
+ end if;
+ end function maximum;
+
+ -- std_logic_vector output
+ function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+ begin -- function minimum
+ if L > R then return R;
+ else return L;
+ end if;
+ end function minimum;
+
+ function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
+ begin -- function maximum
+ if L > R then return L;
+ else return R;
+ end if;
+ end function maximum;
+
+ -- std_logic_vector output
+ function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
+ begin -- function minimum
+ if L > R then return R;
+ else return L;
+ end if;
+ end function minimum;
+end package body std_logic_1164_additions;
diff --git a/vhdl/mcu_interface.vhd b/vhdl/mcu_interface.vhd
new file mode 100644
index 0000000..d8d2b56
--- /dev/null
+++ b/vhdl/mcu_interface.vhd
@@ -0,0 +1,104 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library fmf;
+use fmf.std595;
+
+use work.all;
+
+entity mcu_interface is
+ port (
+ -- SPI interface
+ bit_in : in std_logic;
+ bit_out : out std_logic;
+ bit_clk : in std_logic;
+
+ -- Strobed to latch data from SPI buffer to AH, AL and Dout
+ byte_out_clk : in std_logic;
+ -- Store to latch data from D bus to Din
+ byte_in_clk : in std_logic;
+ -- Enable AH and AL, active low
+ a_oe : in std_logic;
+ -- Enable Dout, active low
+ d_oe : in std_logic;
+
+ ah : out std_logic_vector(7 downto 0);
+ al : out std_logic_vector(7 downto 0);
+ d_out : out std_logic_vector(7 downto 0);
+ d_in : in std_logic_vector(7 downto 0)
+ );
+end;
+
+architecture behaviour of mcu_interface is
+ -- Internal SPI bus signals
+ signal ah_out : std_logic;
+ signal al_out : std_logic;
+begin
+ ah_buf : entity fmf.std595(vhdl_behavioral) port map(
+ ser => bit_in,
+ qhser => ah_out,
+ sck => bit_clk,
+ rck => byte_out_clk,
+ gneg => a_oe,
+ qa => ah(0),
+ qb => ah(1),
+ qc => ah(2),
+ qd => ah(3),
+ qe => ah(4),
+ qf => ah(5),
+ qg => ah(6),
+ qh => ah(7),
+ SCLRNeg => '1'
+ );
+
+ al_buf : entity fmf.std595(vhdl_behavioral) port map(
+ ser => ah_out,
+ qhser => al_out,
+ sck => bit_clk,
+ rck => byte_out_clk,
+ gneg => a_oe,
+ qa => al(0),
+ qb => al(1),
+ qc => al(2),
+ qd => al(3),
+ qe => al(4),
+ qf => al(5),
+ qg => al(6),
+ qh => al(7),
+ SCLRNeg => '1'
+ );
+
+ d_out_buf : entity fmf.std595(vhdl_behavioral) port map(
+ ser => al_out,
+-- qhser => Not connected
+ sck => bit_clk,
+ rck => byte_out_clk,
+ gneg => d_oe,
+ qa => d_out(0),
+ qb => d_out(1),
+ qc => d_out(2),
+ qd => d_out(3),
+ qe => d_out(4),
+ qf => d_out(5),
+ qg => d_out(6),
+ qh => d_out(7),
+ SCLRNeg => '1'
+ );
+
+ d_in_buf : entity fmf.std165(vhdl_behavioral) port map(
+ ser => '0',
+ q => bit_out,
+ clk => bit_clk,
+ clkinh => '0',
+ sh => byte_in_clk,
+ da => d_in(0),
+ db => d_in(1),
+ dc => d_in(2),
+ dd => d_in(3),
+ de => d_in(4),
+ df => d_in(5),
+ dg => d_in(6),
+ dh => d_in(7)
+ );
+end;
diff --git a/vhdl/mcu_interface_tb.vhd b/vhdl/mcu_interface_tb.vhd
new file mode 100644
index 0000000..d46df95
--- /dev/null
+++ b/vhdl/mcu_interface_tb.vhd
@@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.all;
+
+-- library std;
+-- use std.textio.all;
+
+-- use ieee.std_logic_textio.all;
+library ieee_proposed;
+use ieee_proposed.std_logic_1164_additions.all;
+
+entity mcu_interface_tb is
+end mcu_interface_tb;
+
+-- The MCU has to initialize its output to these values.
+architecture behaviour of mcu_interface_tb is
+ signal bit_in : std_logic;
+ signal bit_out : std_logic;
+ signal bit_clk : std_logic := '0';
+ signal byte_out_clk : std_logic := '0';
+ signal byte_in_clk : std_logic := '1'; -- active low
+ signal a_oe : std_logic := '1';
+ signal d_oe : std_logic := '1';
+
+ signal ah : std_logic_vector(7 downto 0);
+ signal al : std_logic_vector(7 downto 0);
+ signal d_out : std_logic_vector(7 downto 0);
+ signal d_in : std_logic_vector(7 downto 0) := "11110000";
+
+ signal byte_in_s : std_logic_vector(7 downto 0) := "UUUUUUUU";
+
+ constant tClk : time := 1 ns;
+begin
+ mcu_interface : entity work.mcu_interface port map(
+ bit_in,
+ bit_out,
+ bit_clk,
+ byte_out_clk,
+ byte_in_clk,
+ a_oe,
+ d_oe,
+ ah,
+ al,
+ d_out,
+ d_in);
+
+ stimulus : process
+ variable byte_in_v : std_logic_vector(7 downto 0) := "UUUUUUUU";
+
+ -- The MCU will implement these function in software
+ procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
+ begin
+ for i in byte'range loop
+ bit_in <= byte(i);
+ bit_clk <= '1';
+ wait for tClk;
+
+ bit_clk <= '0';
+ wait for tClk;
+ end loop;
+
+ byte_out_clk <= '1';
+ wait for tClk;
+
+ byte_out_clk <= '0';
+ wait for tClk;
+ end;
+
+ procedure byte_in(byte : out std_logic_vector(7 downto 0)) is
+ begin
+ byte_in_clk <= '0';
+ wait for tClk;
+
+ byte_in_clk <= '1';
+ wait for tClk;
+
+ for i in byte'range loop
+ byte(i) := bit_out;
+ bit_clk <= '1';
+ wait for tClk;
+
+ bit_clk <= '0';
+ wait for tClk;
+ end loop;
+ end;
+
+ procedure write_ram(
+ data : in std_logic_vector(7 downto 0);
+ address : in std_logic_vector(15 downto 0)) is
+ begin
+ report "write_ram: " & to_string(data);
+
+ -- TODO: busreq + wait for busack
+ byte_out(data);
+ byte_out(address(7 downto 0));
+ byte_out(address(15 downto 8));
+ end;
+
+ begin
+ write_ram("10100101", "0000000000000001");
+ d_oe <= '0';
+ a_oe <= '0';
+
+ wait for tClk;
+ assert ah = "00000000" report "ah failed";
+ assert al = "00000001" report "al failed";
+ assert d_out = "10100101" report "d_out failed";
+
+ wait for tClk;
+ d_in <= "01011010";
+ wait for 2 * tClk;
+ byte_in(byte_in_v);
+ byte_in_s <= byte_in_v;
+ wait for tClk;
+ assert byte_in_v = "01011010" report "byte_in failed";
+
+ assert false report "end of test" severity note;
+ wait;
+ end process;
+end;
diff --git a/vhdl/ram-ice.xise b/vhdl/ram-ice.xise
new file mode 100644
index 0000000..a5bd50b
--- /dev/null
+++ b/vhdl/ram-ice.xise
@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="ice_tb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="ice.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="fmf/conversions.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/ecl_package.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/ecl_utils.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/ff_package.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/gen_utils.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/memory.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/state_tab_package.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/std165.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="fmf/std595.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <library xil_pn:name="fmf"/>
+ </file>
+ <file xil_pn:name="mcu_interface_tb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="37"/>
+ </file>
+ <file xil_pn:name="mcu_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="ieee_proposed/std_logic_1164_additions.vhdl" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+ <library xil_pn:name="ieee_proposed"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Device" xil_pn:value="xc95*xl" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mcu_interface|behaviour" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="mcu_interface.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mcu_interface" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="*" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mcu_interface_tb" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.mcu_interface_tb" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-*" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mcu_interface_tb|behaviour" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="ram-ice" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-10T14:06:24" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CC41C5D21C862F16AE667C80E5797D8C" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries>
+ <library xil_pn:name="fmf"/>
+ <library xil_pn:name="ieee"/>
+ <library xil_pn:name="ieee_proposed"/>
+ </libraries>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>