diff options
| author | Trygve Laugstøl <trygvis@inamo.no> | 2013-02-10 16:26:03 +0100 |
|---|---|---|
| committer | Trygve Laugstøl <trygvis@inamo.no> | 2013-02-10 16:26:03 +0100 |
| commit | 6c56d89c8db4830418bdd27d5c775a77d0ab462b (patch) | |
| tree | b4baba1a3374ca0c8bc139fa1c545cbd113ee795 | |
| download | rom-emulator-6c56d89c8db4830418bdd27d5c775a77d0ab462b.tar.gz rom-emulator-6c56d89c8db4830418bdd27d5c775a77d0ab462b.tar.bz2 rom-emulator-6c56d89c8db4830418bdd27d5c775a77d0ab462b.tar.xz rom-emulator-6c56d89c8db4830418bdd27d5c775a77d0ab462b.zip | |
wip
| -rw-r--r-- | hardware/ram-ice.brd | 875 | ||||
| -rw-r--r-- | hardware/ram-ice.sch | 1348 | ||||
| -rw-r--r-- | vhdl/AS7C256A.vhd | 383 | ||||
| -rw-r--r-- | vhdl/TEST_AS7C256A.vhd | 264 | ||||
| -rw-r--r-- | vhdl/fmf/conversions.vhd | 1178 | ||||
| -rw-r--r-- | vhdl/fmf/ecl_package.vhd | 116 | ||||
| -rw-r--r-- | vhdl/fmf/ecl_utils.vhd | 160 | ||||
| -rw-r--r-- | vhdl/fmf/ff_package.vhd | 926 | ||||
| -rw-r--r-- | vhdl/fmf/gen_utils.vhd | 186 | ||||
| -rw-r--r-- | vhdl/fmf/memory.vhd | 714 | ||||
| -rw-r--r-- | vhdl/fmf/state_tab_package.vhd | 156 | ||||
| -rw-r--r-- | vhdl/fmf/std165.vhd | 576 | ||||
| -rw-r--r-- | vhdl/fmf/std595.vhd | 610 | ||||
| -rw-r--r-- | vhdl/ice.vhd | 80 | ||||
| -rw-r--r-- | vhdl/ice_tb.vhd | 66 |
15 files changed, 7638 insertions, 0 deletions
diff --git a/hardware/ram-ice.brd b/hardware/ram-ice.brd new file mode 100644 index 0000000..81f55db --- /dev/null +++ b/hardware/ram-ice.brd @@ -0,0 +1,875 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.4"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.025" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/> +<layer number="20" name="Dimension" color="15" fill="1" visible="yes" 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Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name. +</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="40mil"/> +<param name="mdDrill" value="8mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="10mil"/> +<param name="msDrill" value="0.6mm"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="999999"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" 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distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/> +<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/> +<layer number="25" name="tNames" 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pin="SER" pad="14"/> +<connect gate="P" pin="GND" pad="8"/> +<connect gate="P" pin="VCC" pad="16"/> +</connects> +<technologies> +<technology name="HC"/> +<technology name="HCT"/> +</technologies> +</device> +<device name="FK" package="LCC20"> +<connects> +<connect gate="A" pin="G" pad="17"/> +<connect gate="A" pin="QA" pad="19"/> +<connect gate="A" pin="QB" pad="2"/> +<connect gate="A" pin="QC" pad="3"/> +<connect gate="A" pin="QD" pad="4"/> +<connect gate="A" pin="QE" pad="5"/> +<connect gate="A" pin="QF" pad="7"/> +<connect gate="A" pin="QG" pad="8"/> +<connect gate="A" pin="QH" pad="9"/> +<connect gate="A" pin="QH*" pad="12"/> +<connect gate="A" pin="RCK" pad="15"/> +<connect gate="A" pin="SCK" pad="14"/> +<connect gate="A" pin="SCL" pad="13"/> +<connect gate="A" pin="SER" pad="18"/> +<connect gate="P" pin="GND" pad="10"/> +<connect gate="P" pin="VCC" pad="20"/> +</connects> +<technologies> +<technology name="HC"/> +<technology name="HCT"/> +<technology name="LS"/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="memory-idt"> +<description><b>IDT Memories</b><p> +Integrated Device Technology, Inc.<p> +http://www.idt.com<p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="DIL28-6"> +<description><b>Dual In Line Package</b> 0.6 inch</description> +<wire x1="-17.653" y1="-1.27" x2="-17.653" y2="-6.604" width="0.1524" layer="21"/> +<wire x1="-17.653" y1="1.27" x2="-17.653" y2="-1.27" width="0.1524" layer="21" curve="-180"/> +<wire x1="17.653" y1="-6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/> +<wire x1="-17.653" y1="6.604" x2="-17.653" y2="1.27" width="0.1524" layer="21"/> +<wire x1="-17.653" y1="6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/> +<wire x1="-17.653" y1="-6.604" x2="17.653" y2="-6.604" width="0.1524" layer="21"/> +<pad name="1" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/> +<pad name="2" x="-13.97" y="-7.62" drill="0.8128" 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x="-17.78" y="-6.35" size="1.778" layer="25" ratio="10" rot="R90">>NAME</text> +<text x="-14.605" y="-0.9398" size="1.778" layer="27" ratio="10">>VALUE</text> +</package> +<package name="SO28-3"> +<description><b>Small Outline Package</b></description> +<wire x1="-8.814" y1="-4.248" x2="8.839" y2="-4.248" width="0.1524" layer="21"/> +<wire x1="8.839" y1="-4.248" x2="8.839" y2="4.248" width="0.1524" layer="21"/> +<wire x1="8.839" y1="4.248" x2="-8.814" y2="4.248" width="0.1524" layer="21"/> +<wire x1="-8.814" y1="4.248" x2="-8.814" y2="-4.248" width="0.1524" layer="21"/> +<circle x="-7.874" y="-3.0988" radius="0.5334" width="0.1524" layer="21"/> +<smd name="1" x="-8.255" y="-5.315" dx="0.762" dy="1.524" layer="1"/> +<smd name="2" x="-6.985" y="-5.315" dx="0.762" dy="1.524" layer="1"/> +<smd name="3" x="-5.715" y="-5.315" dx="0.762" dy="1.524" layer="1"/> +<smd name="4" x="-4.445" y="-5.315" dx="0.762" dy="1.524" layer="1"/> +<smd name="5" x="-3.175" y="-5.315" dx="0.762" dy="1.524" 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layer="94"/> +<wire x1="7.62" y1="-25.4" x2="7.62" y2="25.4" width="0.4064" layer="94"/> +<wire x1="7.62" y1="25.4" x2="-7.62" y2="25.4" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="25.4" x2="-7.62" y2="-25.4" width="0.4064" layer="94"/> +<text x="-7.62" y="26.035" size="1.778" layer="95">>NAME</text> +<text x="-7.62" y="-27.94" size="1.778" layer="96">>VALUE</text> +<pin name="A0" x="-12.7" y="22.86" length="middle" direction="in"/> +<pin name="A1" x="-12.7" y="20.32" length="middle" direction="in"/> +<pin name="A2" x="-12.7" y="17.78" length="middle" direction="in"/> +<pin name="A3" x="-12.7" y="15.24" length="middle" direction="in"/> +<pin name="A4" x="-12.7" y="12.7" length="middle" direction="in"/> +<pin name="A5" x="-12.7" y="10.16" length="middle" direction="in"/> +<pin name="A6" x="-12.7" y="7.62" length="middle" direction="in"/> +<pin name="A7" x="-12.7" y="5.08" length="middle" direction="in"/> +<pin name="A8" x="-12.7" y="2.54" length="middle" direction="in"/> +<pin name="A9" x="-12.7" y="0" length="middle" direction="in"/> +<pin name="A10" x="-12.7" y="-2.54" length="middle" direction="in"/> +<pin name="!OE" x="-12.7" y="-17.78" length="middle" direction="in"/> +<pin name="I/O5" x="12.7" y="12.7" length="middle" rot="R180"/> +<pin name="I/O6" x="12.7" y="10.16" length="middle" rot="R180"/> +<pin name="I/O7" x="12.7" y="7.62" length="middle" rot="R180"/> +<pin name="I/O8" x="12.7" y="5.08" length="middle" rot="R180"/> +<pin name="!WE" x="-12.7" y="-20.32" length="middle" direction="in"/> +<pin name="!CS" x="-12.7" y="-22.86" length="middle" direction="in"/> +<pin name="I/O1" x="12.7" y="22.86" length="middle" rot="R180"/> +<pin name="I/O2" x="12.7" y="20.32" length="middle" rot="R180"/> +<pin name="I/O3" x="12.7" y="17.78" length="middle" rot="R180"/> +<pin name="I/O4" x="12.7" y="15.24" length="middle" rot="R180"/> +<pin name="A11" x="-12.7" y="-5.08" length="middle" direction="in"/> +<pin name="A12" x="-12.7" y="-7.62" length="middle" direction="in"/> +<pin name="A13" x="-12.7" y="-10.16" length="middle" direction="in"/> +<pin name="A14" x="-12.7" y="-12.7" length="middle" direction="in"/> +</symbol> +<symbol name="VCCGND"> +<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text> +<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text> +<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text> +<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/> +<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="71256P" prefix="IC" uservalue="yes"> +<description><b>MEMORY</b></description> +<gates> +<gate name="G$1" symbol="71256" x="0" y="0"/> +<gate name="P" symbol="VCCGND" x="-25.4" y="0" addlevel="request"/> +</gates> +<devices> +<device name="" package="DIL28-6"> +<connects> +<connect gate="G$1" pin="!CS" pad="20"/> +<connect gate="G$1" pin="!OE" pad="22"/> +<connect gate="G$1" pin="!WE" pad="27"/> +<connect gate="G$1" pin="A0" pad="10"/> +<connect gate="G$1" pin="A1" pad="9"/> +<connect gate="G$1" pin="A10" pad="21"/> +<connect gate="G$1" pin="A11" pad="23"/> +<connect gate="G$1" pin="A12" pad="2"/> +<connect gate="G$1" pin="A13" pad="26"/> +<connect gate="G$1" pin="A14" pad="1"/> +<connect gate="G$1" pin="A2" pad="8"/> +<connect gate="G$1" pin="A3" pad="7"/> +<connect gate="G$1" pin="A4" pad="6"/> +<connect gate="G$1" pin="A5" pad="5"/> +<connect gate="G$1" pin="A6" pad="4"/> +<connect gate="G$1" pin="A7" pad="3"/> +<connect gate="G$1" pin="A8" pad="25"/> +<connect gate="G$1" pin="A9" pad="24"/> +<connect gate="G$1" pin="I/O1" pad="11"/> +<connect gate="G$1" pin="I/O2" pad="12"/> +<connect gate="G$1" pin="I/O3" pad="13"/> +<connect gate="G$1" pin="I/O4" pad="15"/> +<connect gate="G$1" pin="I/O5" pad="16"/> +<connect gate="G$1" pin="I/O6" pad="17"/> +<connect gate="G$1" pin="I/O7" pad="18"/> +<connect gate="G$1" pin="I/O8" pad="19"/> +<connect gate="P" pin="GND" pad="14"/> +<connect gate="P" pin="VCC" pad="28"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="" constant="no"/> +<attribute name="OC_FARNELL" value="unknown" constant="no"/> +<attribute name="OC_NEWARK" value="unknown" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="71256S" prefix="IC" uservalue="yes"> +<description><b>MEMORY</b></description> +<gates> +<gate name="G$1" symbol="71256" x="0" y="0"/> +<gate name="P" symbol="VCCGND" x="-22.86" y="2.54" addlevel="request"/> +</gates> +<devices> +<device name="" package="SO28-3"> +<connects> +<connect gate="G$1" pin="!CS" pad="20"/> +<connect gate="G$1" pin="!OE" pad="22"/> +<connect gate="G$1" pin="!WE" pad="27"/> +<connect gate="G$1" pin="A0" pad="10"/> +<connect gate="G$1" pin="A1" pad="9"/> +<connect gate="G$1" pin="A10" pad="21"/> +<connect gate="G$1" pin="A11" pad="23"/> +<connect gate="G$1" pin="A12" pad="2"/> +<connect gate="G$1" pin="A13" pad="26"/> +<connect gate="G$1" pin="A14" pad="1"/> +<connect gate="G$1" pin="A2" pad="8"/> +<connect gate="G$1" pin="A3" pad="7"/> +<connect gate="G$1" pin="A4" pad="6"/> +<connect gate="G$1" pin="A5" pad="5"/> +<connect gate="G$1" pin="A6" pad="4"/> +<connect gate="G$1" pin="A7" pad="3"/> +<connect gate="G$1" pin="A8" pad="25"/> +<connect gate="G$1" pin="A9" pad="24"/> +<connect gate="G$1" pin="I/O1" pad="11"/> +<connect gate="G$1" pin="I/O2" pad="12"/> +<connect gate="G$1" pin="I/O3" pad="13"/> +<connect gate="G$1" pin="I/O4" pad="15"/> +<connect gate="G$1" pin="I/O5" pad="16"/> +<connect gate="G$1" pin="I/O6" pad="17"/> +<connect gate="G$1" pin="I/O7" pad="18"/> +<connect gate="G$1" pin="I/O8" pad="19"/> +<connect gate="P" pin="GND" pad="14"/> +<connect gate="P" pin="VCC" pad="28"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="IDT71256SA20YG" constant="no"/> +<attribute name="OC_FARNELL" value="1218010" constant="no"/> +<attribute name="OC_NEWARK" value="34M6449" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="supply1"> +<description><b>Supply Symbols</b><p> + GND, VCC, 0V, +5V, -5V, etc.<p> + Please keep in mind, that these devices are necessary for the + automatic wiring of the supply signals.<p> + The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> + In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> + <author>Created by librarian@cadsoft.de</author></description> +<packages> +</packages> +<symbols> +<symbol name="VCC"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="IC1" library="74xx-eu" deviceset="74*165" device="D" technology="AC"/> +<part name="IC2" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC3" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC4" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/> +<part name="IC5" library="memory-idt" deviceset="71256S" device=""/> +<part name="P+1" library="supply1" deviceset="VCC" device=""/> +<part name="IC6" library="memory-idt" deviceset="71256P" device=""/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="IC1" gate="A" x="162.56" y="83.82"/> +<instance part="IC2" gate="A" x="162.56" y="40.64" rot="R180"/> +<instance part="IC3" gate="A" x="45.72" y="88.9"/> +<instance part="IC4" gate="A" x="45.72" y="45.72"/> +<instance part="IC5" gate="G$1" x="101.6" y="55.88"/> +<instance part="P+1" gate="VCC" x="27.94" y="109.22"/> +<instance part="IC6" gate="G$1" x="101.6" y="129.54"/> +</instances> +<busses> +<bus name="A[0..14],/OE,/WE,/CS"> +<segment> +<wire x1="63.5" y1="99.06" x2="63.5" y2="81.28" width="0.762" layer="92"/> +<wire x1="63.5" y1="81.28" x2="81.28" y2="81.28" width="0.762" layer="92"/> +<wire x1="81.28" y1="81.28" x2="81.28" y2="30.48" width="0.762" layer="92"/> +<wire x1="81.28" y1="30.48" x2="63.5" y2="30.48" width="0.762" layer="92"/> +<wire x1="63.5" y1="30.48" x2="63.5" y2="55.88" width="0.762" layer="92"/> +<wire x1="81.28" y1="81.28" x2="81.28" y2="152.4" width="0.762" layer="92"/> +</segment> +</bus> +<bus name="D[0..7]"> +<segment> +<wire x1="134.62" y1="96.52" x2="134.62" y2="78.74" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="134.62" y2="30.48" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="121.92" y2="78.74" width="0.762" layer="92"/> +<wire x1="121.92" y1="78.74" x2="121.92" y2="60.96" width="0.762" layer="92"/> +<wire x1="121.92" y1="78.74" x2="121.92" y2="152.4" width="0.762" layer="92"/> +</segment> +</bus> +</busses> +<nets> +<net name="A1" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QB"/> +<wire x1="58.42" y1="96.52" x2="63.5" y2="96.52" width="0.1524" layer="91"/> +<label x="58.42" y="96.52" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A1"/> +<wire x1="81.28" y1="76.2" x2="88.9" y2="76.2" width="0.1524" layer="91"/> +<label x="88.9" y="76.2" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A1"/> +<wire x1="81.28" y1="149.86" x2="88.9" y2="149.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A0" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QA"/> +<wire x1="58.42" y1="99.06" x2="63.5" y2="99.06" width="0.1524" layer="91"/> +<label x="58.42" y="99.06" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A0"/> +<wire x1="81.28" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/> +<label x="88.9" y="78.74" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A0"/> +<wire x1="81.28" y1="152.4" x2="88.9" y2="152.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A3" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QD"/> +<wire x1="63.5" y1="91.44" x2="58.42" y2="91.44" width="0.1524" layer="91"/> +<label x="58.42" y="91.44" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A3"/> +<wire x1="81.28" y1="71.12" x2="88.9" y2="71.12" width="0.1524" layer="91"/> +<label x="88.9" y="71.12" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A3"/> +<wire x1="81.28" y1="144.78" x2="88.9" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A2" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QC"/> +<wire x1="63.5" y1="93.98" x2="58.42" y2="93.98" width="0.1524" layer="91"/> +<label x="58.42" y="93.98" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A2"/> +<wire x1="81.28" y1="73.66" x2="88.9" y2="73.66" width="0.1524" layer="91"/> +<label x="88.9" y="73.66" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A2"/> +<wire x1="81.28" y1="147.32" x2="88.9" y2="147.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A4" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QE"/> +<wire x1="63.5" y1="88.9" x2="58.42" y2="88.9" width="0.1524" layer="91"/> +<label x="58.42" y="88.9" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A4"/> +<wire x1="88.9" y1="68.58" x2="81.28" y2="68.58" width="0.1524" layer="91"/> +<label x="88.9" y="68.58" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A4"/> +<wire x1="81.28" y1="142.24" x2="88.9" y2="142.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A5" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QF"/> +<wire x1="63.5" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/> +<label x="58.42" y="86.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A5"/> +<wire x1="88.9" y1="66.04" x2="81.28" y2="66.04" width="0.1524" layer="91"/> +<label x="88.9" y="66.04" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A5"/> +<wire x1="81.28" y1="139.7" x2="88.9" y2="139.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A6" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QG"/> +<wire x1="63.5" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/> +<label x="58.42" y="83.82" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A6"/> +<wire x1="88.9" y1="63.5" x2="81.28" y2="63.5" width="0.1524" layer="91"/> +<label x="88.9" y="63.5" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A6"/> +<wire x1="81.28" y1="137.16" x2="88.9" y2="137.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A7" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QH"/> +<wire x1="63.5" y1="81.28" x2="58.42" y2="81.28" width="0.1524" layer="91"/> +<label x="58.42" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A7"/> +<wire x1="88.9" y1="60.96" x2="81.28" y2="60.96" width="0.1524" layer="91"/> +<label x="88.9" y="60.96" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A7"/> +<wire x1="81.28" y1="134.62" x2="88.9" y2="134.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A8" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QA"/> +<wire x1="58.42" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/> +<label x="58.42" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A8"/> +<wire x1="88.9" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/> +<label x="88.9" y="58.42" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A8"/> +<wire x1="81.28" y1="132.08" x2="88.9" y2="132.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A9" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QB"/> +<wire x1="58.42" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/> +<label x="58.42" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A9"/> +<wire x1="88.9" y1="55.88" x2="81.28" y2="55.88" width="0.1524" layer="91"/> +<label x="88.9" y="55.88" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A9"/> +<wire x1="81.28" y1="129.54" x2="88.9" y2="129.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A10" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QC"/> +<wire x1="58.42" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/> +<label x="58.42" y="50.8" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A10"/> +<wire x1="88.9" y1="53.34" x2="81.28" y2="53.34" width="0.1524" layer="91"/> +<label x="88.9" y="53.34" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A10"/> +<wire x1="81.28" y1="127" x2="88.9" y2="127" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A11" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QD"/> +<wire x1="58.42" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/> +<label x="58.42" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A11"/> +<wire x1="88.9" y1="50.8" x2="81.28" y2="50.8" width="0.1524" layer="91"/> +<label x="88.9" y="50.8" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A11"/> +<wire x1="81.28" y1="124.46" x2="88.9" y2="124.46" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A12" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QE"/> +<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/> +<label x="58.42" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A12"/> +<wire x1="88.9" y1="48.26" x2="81.28" y2="48.26" width="0.1524" layer="91"/> +<label x="88.9" y="48.26" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A12"/> +<wire x1="81.28" y1="121.92" x2="88.9" y2="121.92" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A13" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QF"/> +<wire x1="58.42" y1="43.18" x2="63.5" y2="43.18" width="0.1524" layer="91"/> +<label x="58.42" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A13"/> +<wire x1="81.28" y1="45.72" x2="88.9" y2="45.72" width="0.1524" layer="91"/> +<label x="88.9" y="45.72" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A13"/> +<wire x1="81.28" y1="119.38" x2="88.9" y2="119.38" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A14" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QG"/> +<wire x1="58.42" y1="40.64" x2="63.5" y2="40.64" width="0.1524" layer="91"/> +<label x="58.42" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="A14"/> +<wire x1="88.9" y1="43.18" x2="81.28" y2="43.18" width="0.1524" layer="91"/> +<label x="88.9" y="43.18" size="1.778" layer="95" rot="MR0"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="A14"/> +<wire x1="81.28" y1="116.84" x2="88.9" y2="116.84" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="QH*"/> +<wire x1="58.42" y1="76.2" x2="58.42" y2="66.04" width="0.1524" layer="91"/> +<wire x1="58.42" y1="66.04" x2="30.48" y2="66.04" width="0.1524" layer="91"/> +<wire x1="30.48" y1="66.04" x2="30.48" y2="55.88" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="SER"/> +<wire x1="30.48" y1="55.88" x2="33.02" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="A_EN" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="G"/> +<wire x1="33.02" y1="76.2" x2="22.86" y2="76.2" width="0.1524" layer="91"/> +<wire x1="22.86" y1="76.2" x2="22.86" y2="33.02" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="G"/> +<wire x1="22.86" y1="33.02" x2="22.86" y2="25.4" width="0.1524" layer="91"/> +<wire x1="33.02" y1="33.02" x2="22.86" y2="33.02" width="0.1524" layer="91"/> +<wire x1="22.86" y1="25.4" x2="5.08" y2="25.4" width="0.1524" layer="91"/> +<label x="5.08" y="27.94" size="1.778" layer="95"/> +<junction x="22.86" y="33.02"/> +</segment> +</net> +<net name="D0" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="A"/> +<wire x1="134.62" y1="96.52" x2="149.86" y2="96.52" width="0.1524" layer="91"/> +<label x="137.16" y="96.52" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QA"/> +<wire x1="134.62" y1="30.48" x2="149.86" y2="30.48" width="0.1524" layer="91"/> +<label x="137.16" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O1"/> +<wire x1="114.3" y1="78.74" x2="121.92" y2="78.74" width="0.1524" layer="91"/> +<label x="116.84" y="78.74" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O1"/> +<wire x1="114.3" y1="152.4" x2="121.92" y2="152.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D1" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="B"/> +<wire x1="134.62" y1="93.98" x2="149.86" y2="93.98" width="0.1524" layer="91"/> +<label x="137.16" y="93.98" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QB"/> +<wire x1="134.62" y1="33.02" x2="149.86" y2="33.02" width="0.1524" layer="91"/> +<label x="137.16" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O2"/> +<wire x1="114.3" y1="76.2" x2="121.92" y2="76.2" width="0.1524" layer="91"/> +<label x="116.84" y="76.2" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O2"/> +<wire x1="114.3" y1="149.86" x2="121.92" y2="149.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D2" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="C"/> +<wire x1="134.62" y1="91.44" x2="149.86" y2="91.44" width="0.1524" layer="91"/> +<label x="137.16" y="91.44" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QC"/> +<wire x1="134.62" y1="35.56" x2="149.86" y2="35.56" width="0.1524" layer="91"/> +<label x="137.16" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O3"/> +<wire x1="114.3" y1="73.66" x2="121.92" y2="73.66" width="0.1524" layer="91"/> +<label x="116.84" y="73.66" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O3"/> +<wire x1="114.3" y1="147.32" x2="121.92" y2="147.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D3" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="D"/> +<wire x1="134.62" y1="88.9" x2="149.86" y2="88.9" width="0.1524" layer="91"/> +<label x="137.16" y="88.9" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QD"/> +<wire x1="134.62" y1="38.1" x2="149.86" y2="38.1" width="0.1524" layer="91"/> +<label x="137.16" y="38.1" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O4"/> +<wire x1="121.92" y1="71.12" x2="114.3" y2="71.12" width="0.1524" layer="91"/> +<label x="116.84" y="71.12" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O4"/> +<wire x1="114.3" y1="144.78" x2="121.92" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D4" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="E"/> +<wire x1="134.62" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/> +<label x="137.16" y="86.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QE"/> +<wire x1="134.62" y1="40.64" x2="149.86" y2="40.64" width="0.1524" layer="91"/> +<label x="137.16" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O5"/> +<wire x1="121.92" y1="68.58" x2="114.3" y2="68.58" width="0.1524" layer="91"/> +<label x="116.84" y="68.58" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O5"/> +<wire x1="114.3" y1="142.24" x2="121.92" y2="142.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D5" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="F"/> +<wire x1="134.62" y1="83.82" x2="149.86" y2="83.82" width="0.1524" layer="91"/> +<label x="137.16" y="83.82" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QF"/> +<wire x1="134.62" y1="43.18" x2="149.86" y2="43.18" width="0.1524" layer="91"/> +<label x="137.16" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O6"/> +<wire x1="114.3" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/> +<label x="116.84" y="66.04" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O6"/> +<wire x1="114.3" y1="139.7" x2="121.92" y2="139.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D6" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="G"/> +<wire x1="134.62" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/> +<label x="137.16" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QG"/> +<wire x1="134.62" y1="45.72" x2="149.86" y2="45.72" width="0.1524" layer="91"/> +<label x="137.16" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O7"/> +<wire x1="114.3" y1="63.5" x2="121.92" y2="63.5" width="0.1524" layer="91"/> +<label x="116.84" y="63.5" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O7"/> +<wire x1="114.3" y1="137.16" x2="121.92" y2="137.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D7" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="H"/> +<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.1524" layer="91"/> +<label x="137.16" y="78.74" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="QH"/> +<wire x1="134.62" y1="48.26" x2="149.86" y2="48.26" width="0.1524" layer="91"/> +<label x="137.16" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="I/O8"/> +<wire x1="114.3" y1="60.96" x2="121.92" y2="60.96" width="0.1524" layer="91"/> +<label x="116.84" y="60.96" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="I/O8"/> +<wire x1="114.3" y1="134.62" x2="121.92" y2="134.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="QH*"/> +<wire x1="58.42" y1="33.02" x2="60.96" y2="33.02" width="0.1524" layer="91"/> +<wire x1="60.96" y1="33.02" x2="60.96" y2="15.24" width="0.1524" layer="91"/> +<wire x1="60.96" y1="15.24" x2="180.34" y2="15.24" width="0.1524" layer="91"/> +<wire x1="180.34" y1="15.24" x2="180.34" y2="30.48" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="SER"/> +<wire x1="180.34" y1="30.48" x2="175.26" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="QH*"/> +<wire x1="149.86" y1="53.34" x2="142.24" y2="53.34" width="0.1524" layer="91"/> +<wire x1="142.24" y1="53.34" x2="142.24" y2="99.06" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="SER"/> +<wire x1="142.24" y1="99.06" x2="149.86" y2="99.06" width="0.1524" layer="91"/> +</segment> +</net> +<net name="D_IN" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="SER"/> +<wire x1="33.02" y1="99.06" x2="20.32" y2="99.06" width="0.1524" layer="91"/> +<wire x1="20.32" y1="99.06" x2="20.32" y2="33.02" width="0.1524" layer="91"/> +<wire x1="20.32" y1="33.02" x2="5.08" y2="33.02" width="0.1524" layer="91"/> +<label x="5.08" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="D_CLK" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="SCK"/> +<wire x1="33.02" y1="93.98" x2="17.78" y2="93.98" width="0.1524" layer="91"/> +<wire x1="17.78" y1="93.98" x2="17.78" y2="50.8" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="SCK"/> +<wire x1="17.78" y1="50.8" x2="33.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="17.78" y1="50.8" x2="17.78" y2="40.64" width="0.1524" layer="91"/> +<wire x1="17.78" y1="40.64" x2="5.08" y2="40.64" width="0.1524" layer="91"/> +<label x="5.08" y="43.18" size="1.778" layer="95"/> +<wire x1="17.78" y1="40.64" x2="17.78" y2="7.62" width="0.1524" layer="91"/> +<wire x1="17.78" y1="7.62" x2="187.96" y2="7.62" width="0.1524" layer="91"/> +<wire x1="187.96" y1="7.62" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="SCK"/> +<wire x1="175.26" y1="35.56" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<wire x1="187.96" y1="35.56" x2="187.96" y2="60.96" width="0.1524" layer="91"/> +<wire x1="187.96" y1="60.96" x2="144.78" y2="60.96" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="CLK"/> +<wire x1="149.86" y1="73.66" x2="144.78" y2="73.66" width="0.1524" layer="91"/> +<wire x1="144.78" y1="73.66" x2="144.78" y2="60.96" width="0.1524" layer="91"/> +<junction x="17.78" y="40.64"/> +<junction x="187.96" y="35.56"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="RCK"/> +<wire x1="175.26" y1="43.18" x2="185.42" y2="43.18" width="0.1524" layer="91"/> +<wire x1="185.42" y1="43.18" x2="185.42" y2="10.16" width="0.1524" layer="91"/> +<wire x1="185.42" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<wire x1="25.4" y1="10.16" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="RCK"/> +<wire x1="33.02" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="RCK"/> +<wire x1="33.02" y1="86.36" x2="25.4" y2="86.36" width="0.1524" layer="91"/> +<wire x1="25.4" y1="86.36" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="SH/!LD"/> +<wire x1="149.86" y1="68.58" x2="147.32" y2="68.58" width="0.1524" layer="91"/> +<wire x1="147.32" y1="68.58" x2="147.32" y2="63.5" width="0.1524" layer="91"/> +<wire x1="147.32" y1="63.5" x2="185.42" y2="63.5" width="0.1524" layer="91"/> +<wire x1="185.42" y1="63.5" x2="185.42" y2="43.18" width="0.1524" layer="91"/> +<junction x="25.4" y="43.18"/> +<junction x="185.42" y="43.18"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="SCL"/> +<wire x1="33.02" y1="48.26" x2="27.94" y2="48.26" width="0.1524" layer="91"/> +<wire x1="27.94" y1="48.26" x2="27.94" y2="91.44" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="SCL"/> +<wire x1="27.94" y1="91.44" x2="27.94" y2="106.68" width="0.1524" layer="91"/> +<wire x1="33.02" y1="91.44" x2="27.94" y2="91.44" width="0.1524" layer="91"/> +<junction x="27.94" y="91.44"/> +<pinref part="P+1" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="/OE" class="0"> +<segment> +<pinref part="IC6" gate="G$1" pin="!OE"/> +<wire x1="81.28" y1="111.76" x2="88.9" y2="111.76" width="0.1524" layer="91"/> +<label x="83.82" y="111.76" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="!OE"/> +<wire x1="81.28" y1="38.1" x2="88.9" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="/WE" class="0"> +<segment> +<pinref part="IC6" gate="G$1" pin="!WE"/> +<wire x1="81.28" y1="109.22" x2="88.9" y2="109.22" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="!WE"/> +<wire x1="81.28" y1="35.56" x2="88.9" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="/CS" class="0"> +<segment> +<pinref part="IC6" gate="G$1" pin="!CS"/> +<wire x1="81.28" y1="106.68" x2="88.9" y2="106.68" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC5" gate="G$1" pin="!CS"/> +<wire x1="81.28" y1="33.02" x2="88.9" y2="33.02" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> diff --git a/vhdl/AS7C256A.vhd b/vhdl/AS7C256A.vhd new file mode 100644 index 0000000..60bd64c --- /dev/null +++ b/vhdl/AS7C256A.vhd @@ -0,0 +1,383 @@ +------------------------------------------------------------------------------------ +-- +-- File Name: AS7C256A.vhd +-- Version: 1.0 +-- Date: 2 April 2005 +-- Model: BUS Functional +-- +-- +-- Company: Alliance Semiconductor pvt ltd. +-- Part Number: AS7C256A (32K x 8) +-- +-- Description: Alliance 256k Fast Asynchronous SRAM +-- +-- Note: The model is Done for 10ns cycle time . To work with other cycle time, +-- we have to change the timing parameters according to Data sheet. +-- +------------------------------------------------------------------------------------ + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + +ENTITY AS7C256A IS + GENERIC ( + + Tsim : TIME := 10000 ns; + + -- write timings 10ns address access time + twc : TIME := 10 ns; + tcw : TIME := 8 ns; + taw : TIME := 8 ns; + tas : TIME := 0 ns; + twp : TIME := 7 ns; + twr : TIME := 0 ns; + tah : TIME := 0 ns; + tdw : TIME := 5 ns; + tdh : TIME := 0 ns; + twz : TIME := 5 ns; + tow : TIME := 3 ns; + + -- Read timings 10ns address access time + trc : TIME := 10 ns; + taa : TIME := 10 ns; + tace : TIME := 10 ns; + toe : TIME := 5 ns; + toh : TIME := 3 ns; + tclz : TIME := 3 ns; + tchz : TIME := 3 ns; + tolz : TIME := 0 ns; + tohz : TIME := 3 ns; + tpu : TIME := 0 ns; + tpd : TIME := 10 ns; + + t0 : TIME := 0.1 ns; + t1 : TIME := 1 ns; + + -- Bus Width and Data Bus + addr_bits : INTEGER := 15; + data_bits : INTEGER := 8 + ); + + + PORT ( + Address : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + DataIO : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + OE_bar : IN STD_LOGIC; + CE_bar : IN STD_LOGIC; + WE_bar : IN STD_LOGIC + ); + + + END AS7C256A; + + +ARCHITECTURE behave OF AS7C256A IS + TYPE memory IS ARRAY (2 ** addr_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); + + + --For Timig Checks + SIGNAL oe_n, ce_n, we_n : STD_LOGIC; + SIGNAL add_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + SIGNAL data_reg : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + + SIGNAL t2 : STD_LOGIC := '0' ; + SIGNAL Done : BOOLEAN := FALSE; + + + SIGNAL oe_n_dly, ce_n_dly, we_n_dly : STD_LOGIC; + SIGNAL add_reg_dly : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + SIGNAL data_reg_dly : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + + -- For Write access + SIGNAL initiate_cebar,initiate_webar,initiate_wecebar : STD_LOGIC; + SIGNAL initiate_write1,initiate_write2 : STD_LOGIC := '0'; + SIGNAL delayed_WE,delayed_OE : STD_LOGIC; + SIGNAL Address_write1,Address_write2 : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL dataIO1 : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + + -- For Read Access + SIGNAL data_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL Address_read1,Address_read2 : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL initiate_read1,initiate_read2 : STD_LOGIC := '0'; + + + + + --SIGNAL Tprev_address_event, Tprev_address_event1 : TIME ; + + BEGIN + oe_n <= OE_bar; + ce_n <= CE_bar; + we_n <= WE_bar; + + add_reg <= Address(addr_bits - 1 DOWNTO 0); + data_reg <= DataIO (7 DOWNTO 0); + + main : PROCESS (oe_n, ce_n, we_n, add_reg, data_reg,t2,initiate_cebar,initiate_webar,initiate_wecebar,initiate_write1,initiate_write2,initiate_read1,initiate_read2) + + -- Memory Array + VARIABLE dummy_array0 : memory; + VARIABLE mem_array0 : memory; + + + BEGIN + + oe_n_dly <= oe_n after t0; + ce_n_dly <= ce_n after t0 ; + we_n_dly <= we_n after t0 ; + + add_reg_dly <= add_reg(addr_bits - 1 DOWNTO 0) after t0; + data_reg_dly <= data_reg (7 DOWNTO 0) after t0; + +-- ******* Registering the Access ******** + if(ce_n'event or we_n'event or oe_n'event or add_reg'event or data_reg'event) then + + if((ce_n='0') and (we_n = '0')) then + + Address_write1 <= add_reg; + Address_write2 <= Address_write1; + dataIO1 <= data_reg; + dummy_array0(conv_integer(Address_write1)) := dataIO1(7 downto 0) ; + + + end if; + end if; + + + +-- **** Write Access ************* + +-- ****** CE_bar controlled *********** + + if(ce_n'event and (ce_n = '0') ) then + initiate_cebar <= '0'; + initiate_wecebar<= '0'; + end if; + + if(ce_n'event and (ce_n = '1') ) then + + if((ce_n_dly = '0') and (ce_n_dly'last_event >= (tcw-t0))) then + + if ((we_n_dly = '0') and (we_n_dly'last_event >= (twp-t0))) then + Address_write2 <= Address_write1; + dummy_array0(conv_integer(Address_write1)) := dataIO1(7 downto 0) ; + initiate_cebar <= '1'; + else + initiate_cebar <= '0'; + end if; + + else + initiate_cebar <= '0'; + end if; + + end if; + + +-- ***** WE_bar controlled ********** + + + + if(we_n'event and (we_n = '0') ) then + + initiate_webar <= '0'; + initiate_wecebar <= '0'; + delayed_WE <= we_n AFTER twz; + end if; + + + if(we_n'event and (we_n = '1') ) then + + + delayed_WE <= we_n; + + if ((we_n_dly = '0') and (we_n_dly'last_event >= (twp-t0))) then + + if((ce_n_dly = '0') and (ce_n_dly'last_event >= (tcw-t0))) then + Address_write2 <= Address_write1; + dummy_array0(conv_integer(Address_write1)) := dataIO1(7 downto 0) ; + initiate_webar <= '1'; + else + initiate_webar <= '0'; + end if; + else + initiate_webar <= '0'; + end if; + end if; + +-- ******* WE_bar & CE_bar controlled ( If both comes to high at the same time)********** + + if(we_n'event and ce_n'event ) then + + if ((ce_n = '1') and (we_n = '1')) then + + if (((we_n_dly = '0') and (we_n_dly'last_event >= (twp-t0))) and ((ce_n_dly = '0') and (ce_n_dly'last_event >= (tcw-t0))) ) then + Address_write2 <= Address_write1; + dummy_array0(conv_integer(Address_write1)) := dataIO1(7 downto 0) ; + initiate_wecebar <= '1'; + else + initiate_wecebar <= '0' ; + end if; + else + initiate_wecebar <= '0'; + end if; + end if; + +-- ******* initiate_cebar or initiate_webar or ini_wecebar goes high - initiate write access ************** + + if ( initiate_cebar'event or initiate_webar'event or initiate_wecebar'event) then + + if( (initiate_cebar = '1') or (initiate_webar = '1') or (initiate_wecebar = '1') ) then + + if (( add_reg_dly'last_event >= (twc-t0)) and ( data_reg_dly'last_event >= (tdw-t0))) then + initiate_write1 <= '1'; + else + initiate_write1 <= '0'; + end if; + else + initiate_write1 <= '0'; + end if; + end if; + +-- ******* Address/data changes before write completion, then New write(2) initation************************* + + + if (t2'event) then + + if (( add_reg_dly'last_event >= (twc-t0)) and ( data_reg_dly'last_event >= (tdw-t0))) then + + if ( (we_n_dly = '0') and (ce_n_dly = '0')) then + + if ( ( ce_n_dly'last_event >=(tcw-t0)) and ( we_n_dly'last_event >=(twp-t0)) ) then + Address_write2 <= Address_write1; + dummy_array0(conv_integer(Address_write1)) := dataIO1(7 downto 0) ; + initiate_write2 <= '1'; + else + initiate_write2 <= '0'; + end if; + else + initiate_write2 <= '0'; + end if; + else + initiate_write2 <= '0'; + end if; + end if; + + + -- ***** Write completion (Writing into mem_arrayx[][]) *********** + + + if(initiate_write1'event and (initiate_write1= '1')) then + + mem_array0(conv_integer(Address_write2)) := dummy_array0(conv_integer(Address_write2)); + initiate_write1 <= '0'; + +end if; + + + if(initiate_write2'event and (initiate_write2= '1')) then + + mem_array0(conv_integer(Address_write2)) := dummy_array0(conv_integer(Address_write2)); + initiate_write2 <= '0'; + +end if; + + +-- ****** Read Access ******************** + +-- ******** Address transition initiates the Read access ******** + + +if(add_reg'event) then + Address_read1 <=Address; + Address_read2 <=Address_read1; + if ( add_reg_dly'last_event >= (trc-t0)) then + if ( (ce_n_dly = '0') and (we_n_dly = '1') ) then + initiate_read1 <= '1'; + else + initiate_read1 <= '0'; + end if; + else + initiate_read1 <= '0'; + end if; +end if; + + +if (t2'event) then + if (( add_reg_dly'last_event >= (trc-t0))) then + + if ( (ce_n_dly = '0') and (we_n_dly = '1') ) then + Address_read2 <=Address_read1; + initiate_read2 <= '1'; + else + initiate_read2 <= '0'; + end if; + else + initiate_read2 <= '0'; + end if; +end if; + + +-- ***** Data drive to data_temp when $time >= taa & tace & trc (all are having same times) ****** + +if(initiate_read1'event or initiate_read2'event) then + + if ((initiate_read1 = '1') or (initiate_read2 = '1')) then + + if ((ce_n_dly = '0') and (we_n_dly = '1')) then + + if ( ((we_n_dly = '1') and ( we_n_dly'last_event >=(trc-t0))) and ((ce_n_dly = '0') and ( ce_n_dly'last_event >=(tace-t0))) and ((oe_n_dly = '0') and ( oe_n_dly'last_event >=(toe-t0)))) then + + data_temp(7 downto 0) <= mem_array0(conv_integer(Address_read2)); + + else + data_temp <= TRANSPORT (OTHERS => 'Z') after toh; + end if; + else + data_temp <= TRANSPORT (OTHERS => 'Z') after toh; + end if; + initiate_read1 <= '0'; + initiate_read2 <= '0'; + else + data_temp <= TRANSPORT (OTHERS => 'Z') after toh; + end if; + end if; + + +if(oe_n'event and (oe_n = '0') ) then + delayed_OE <= NOT(oe_n); + end if; + + + if(oe_n'event and (oe_n = '1') ) then + delayed_OE <= NOT(oe_n) AFTER tohz; + end if; + + + --WAIT FOR Tsim; + --Done <= TRUE; + +END PROCESS main; + +-- Output buffer + WITH (delayed_OE AND delayed_WE) SELECT + DataIO <= TRANSPORT data_temp WHEN '1', + (OTHERS => 'Z') WHEN '0', + (OTHERS => 'Z') WHEN OTHERS; + + + + + Time : PROCESS BEGIN + IF Done = FALSE THEN + WAIT FOR t1; + t2 <= '1'; + WAIT FOR t1; + t2 <= '0'; + ELSE + WAIT; + END IF; + END PROCESS; + + +END behave; diff --git a/vhdl/TEST_AS7C256A.vhd b/vhdl/TEST_AS7C256A.vhd new file mode 100644 index 0000000..5f49d4e --- /dev/null +++ b/vhdl/TEST_AS7C256A.vhd @@ -0,0 +1,264 @@ +-- Testbench for Alliance Semiconductors ASync SRAM + +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE testbench_arch OF testbench IS + -- Clock + CONSTANT tCYC : TIME := 12 ns; + CONSTANT tWC : TIME := 10 ns; + CONSTANT tRC : TIME := 10 ns; + CONSTANT t1 : TIME := 1 ns; + CONSTANT twz : TIME := 5 ns; + CONSTANT tcw : TIME := 7 ns; + -- Bus Width and Data Bus + CONSTANT addr_bits : INTEGER := 15; + CONSTANT data_bits : INTEGER := 8; + + COMPONENT AS7C256A + PORT ( + Address : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + DataIO : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + OE_bar : IN STD_LOGIC; + CE_bar : IN STD_LOGIC; + WE_bar : IN STD_LOGIC + ); + END COMPONENT; + + FOR ALL: AS7C256A USE ENTITY WORK.AS7C256A (behave); + + SIGNAL Address : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + SIGNAL DataIO : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL OE_bar : STD_LOGIC; + SIGNAL CE_bar : STD_LOGIC; + SIGNAL WE_bar : STD_LOGIC; + + SIGNAL Done : BOOLEAN := FALSE; + + BEGIN + U1 : AS7C256A PORT MAP (Address, DataIO, OE_bar, CE_bar, WE_bar); + + Stimulus : PROCESS + -- Deselect + PROCEDURE deselect IS + BEGIN + OE_bar <= '1'; + CE_bar <= '1'; + WE_bar <= '1'; + Address <= (OTHERS => '0'); + DataIO <= (OTHERS => 'Z'); + + WAIT FOR tCYC; + END; + + PROCEDURE write_ce (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR (tCYC-twz); + + CE_bar <= '1'; + WAIT FOR t1; + + END; + + PROCEDURE write_we (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR tCYC; + + WE_bar <= '1'; + WAIT FOR t1; + + END; + + + PROCEDURE write_wece (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR tCYC; + + WE_bar <= '1'; + CE_bar <= '1'; + WAIT FOR t1; + + END; + + PROCEDURE write_add (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + DataIO <= data_in; + WAIT FOR tWC; + + + END; + + PROCEDURE write_data (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '1'; + CE_bar <= '0'; + WE_bar <= '0'; + + WAIT FOR twz; + DataIO <= data_in; + WAIT FOR (tWC/2); + + + END; + + + + PROCEDURE read_ce (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + WAIT FOR t1; + OE_bar <= '0'; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR tCYC; + + END; + + PROCEDURE read_add (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + OE_bar <= '0'; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR tRC; + + END; + + + PROCEDURE read_oe (addr_in : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS + BEGIN + Address <= addr_in; + CE_bar <= '0'; + WE_bar <= '1'; + DataIO <= (OTHERS => 'Z'); + WAIT FOR (7*t1); + OE_bar <= '0'; + WAIT FOR tCYC; + + END; + + + + + + + + + BEGIN + -- Test vectors + deselect; + --deselect; + + --WWRR (we/ce controlled) + write_ce("000000000000001", + "00000001"); + + write_we("000000000000010", + "00000010"); + + read_ce ("000000000000001"); + + + read_ce ("000000000000010"); + deselect; + --WWRR ( only address controlled) + write_add("000000000000011", + "00000011"); + + write_add("000000000000100", + "00000100"); + + read_add ("000000000000011"); + + + read_add ("000000000000100"); + deselect; + + --WRWR (oe read controlled) + write_wece("000000000000101", + "00000101"); + + read_oe ("000000000000101"); + + + write_we("000000000000110", + "00000110"); + + read_oe ("000000000000110"); + + deselect; + --WRWR ( Data change) + write_add("000000000000111", + "00000001"); + + write_add("000000000000111", + "00000111"); + + read_ce ("000000000000111"); + + + write_data("000000000001000", + "00000011"); + + write_add("000000000001000", + "00001000"); + + read_ce ("000000000001000"); + + + + deselect; + + + + Done <= TRUE; + + + assert false report "end of test" severity note; + + WAIT; + END PROCESS; + + + END testbench_arch; + diff --git a/vhdl/fmf/conversions.vhd b/vhdl/fmf/conversions.vhd new file mode 100644 index 0000000..bc42e47 --- /dev/null +++ b/vhdl/fmf/conversions.vhd @@ -0,0 +1,1178 @@ +-------------------------------------------------------------------------------- +-- File Name: conversions.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- This package was originally written by SEVA Technologies, Inc. and donated +-- to the FMF. +-- www.seva.com +-- +-- MODIFICATION HISTORY: +-- +-- version: | author: | mod date: | changes made: +-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file +-- V1.1 R. Munden 98 NOV 28 Corrected some comments +-- Corrected function b +-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values +-- and combined into a single file +-- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int +-- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function +-- int_to_slv +-- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str +-- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0 +-- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in +-- function int_to_slv) from > to >= +-- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str +-- +-------------------------------------------------------------------------------- + +LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; + +-------------------------------------------------------------------------------- +-- CONVERSION FUNCTION SELECTION TABLES +-------------------------------------------------------------------------------- +-- +-- FROM TO: std_logic_vector std_logic natural time string +-- -----------------|---------------|---------|---------|---------|----------- +-- std_logic_vector | N/A | N/A | to_nat | combine | see below +-- std_logic | N/A | N/A | to_nat | combine | see below +-- natural | to_slv | to_sl | N/A | to_time | see below +-- integer | to_slv | N/A | N/A | N/A | N/A +-- time | N/A | N/A | to_nat | N/A | to_time_str +-- hex string | h | N/A | h | combine | N/A +-- decimal string | d | N/A | d | combine | N/A +-- octal string | o | N/A | o | combine | N/A +-- binary string | b | N/A | b | combine | N/A +-- -----------------|---------------|---------|---------|---------|----------- +-- +-- FROM TO: hex string decimal string octal string binary string +-- -----------------|------------|-------------|------------|---------------- +-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str +-- std_logic | N/A | N/A | N/A | to_bin_str +-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str +-- -----------------|------------|-------------|------------|---------------- +-- +-- FROM TO: integer +-- -----------------|---------------| +-- std_logic_vector | to_int | +-------------------------------------------------------------------------------- + +PACKAGE conversions IS + + ---------------------------------------------------------------------------- + -- the conversions in this package are not intended to be synthesizable. + -- + -- others functions available + -- fill creates a variable length string of the fill character + -- + -- + -- + -- input parameters of type natural or integer can be in the form: + -- normal -> 8, 99, 4_237 + -- base#value# -> 2#0101#, 16#fa4C#, 8#6_734# + -- with exponents(x10) -> 8e4, 16#2e#E4 + -- + -- input parameters of type string can be in the form: + -- "99", "4_237", "0101", "1010_1010" + -- + -- for bit/bit_vector <-> std_logic/std_logic_vector conversions use + -- package std_logic_1164 + -- to_bit(std_logic) + -- to_bitvector(std_logic_vector) + -- to_stdlogic(bit) + -- to_stdlogicvector(bit_vector) + -- + -- for "synthesizable" signed/unsigned/std_logic_vector/integer + -- conversions use + -- package std_logic_arith + -- conv_integer(signed/unsigned) + -- conv_unsigned(integer/signed,size) + -- conv_signed(integer/unsigned,size) + -- conv_std_logic_vector(integer/signed/unsigned,size) + -- + -- for "synthesizable" std_logic_vector -> integer conversions use + -- package std_logic_unsigned/std_logic_signed + -- <these packages are mutually exclusive> + -- conv_integer(std_logic_vector) + -- <except for this conversion, these packages are unnecessary) + -- to minimize compile problems write: + -- use std_logic_unsigned.conv_integer; + -- use std_logic_signed.conv_integer; + -- + -- std_logic_vector, signed and unsigned types are "closely related" + -- no type conversion functions are needed, use type casting or qualified + -- expressions + -- + -- type1(object of type2) <type casting> + -- type1'(expression of type2) <qualified expression> + -- + -- most conversions have 4 parmeters: + -- x : value to be converted + -- rtn_len : size of the return value + -- justify : justify value 'left' or 'right', default is right + -- basespec : print the base of the value - 'yes'/'no', default is yes + -- + -- Typical ways to call these functions: + -- simple, all defaults used + -- to_bin_str(x) + -- x will be converted to a string of minimum size with a + -- base specification appended for clarity + -- if x is 10101 then return is b"10101" + -- + -- to control size of return string + -- to_hex_str(x, + -- 6) + -- length of string returned will be 6 characters + -- value will be right justified in the field + -- if x is 10101 then return is ....h"15" + -- where '.' represents a blank + -- if 'rtn_len' parm defaults or is set to 0 then + -- return string will always be minimum size + -- + -- to left justify and suppress base specification + -- to_int_str(x, + -- 6, + -- justify => left, + -- basespec => yes) + -- length of return string will be 6 characters + -- the base specification will be suppressed + -- if x is 10101 then return is 21.... + -- where '.' represents a blank + -- + -- other usage notes + -- + -- if rtn_len less than or equal to x'length then ignore + -- rtn_len and return string of x'length + -- the 'justify' parm is effectively ignored in this case + -- + -- if rtn_len greater than x'length then return string + -- of rtn_len with blanks based on 'justify' parm + -- + -- these routines do not handle negative numbers + ---------------------------------------------------------------------------- + + type justify_side is (left, right); + type b_spec is (no , yes); + + -- std_logic_vector to binary string + function to_bin_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + + -- std_logic to binary string + function to_bin_str(x : std_logic; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + + -- natural to binary string + function to_bin_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + -- see note above regarding possible formats for x + + -- std_logic_vector to hex string + function to_hex_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + + -- natural to hex string + function to_hex_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + -- see note above regarding possible formats for x + + -- std_logic_vector to octal string + function to_oct_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + + -- natural to octal string + function to_oct_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + -- see note above regarding possible formats for x + + -- natural to integer string + function to_int_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + -- see note above regarding possible formats for x + + -- std_logic_vector to integer string + function to_int_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string; + + -- time to string + function to_time_str (x : time) + return string; + + -- add characters to a string + function fill (fill_char : character := '*'; + rtn_len : integer := 1) + return string; + -- usage: + -- fill + -- returns * + -- fill(' ',10) + -- returns .......... when '.' represents a blank + -- fill(lf) or fill(ht) + -- returns line feed character or tab character respectively + + -- std_logic_vector to natural + function to_nat (x : std_logic_vector) + return natural; + + -- std_logic to natural + function to_nat (x : std_logic) + return natural; + + -- time to natural + function to_nat (x : time) + return natural; + + -- hex string to std_logic_vector + function h (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than x'length*4, result will be truncated on the left + -- if x is other than characters 0 to 9 or a,A to f,F + -- or x,X,z,Z,u,U,-,w,W, result will be 0 + + -- decimal string to std_logic_vector + function d (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than x'length*4, result will be truncated on the left + -- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W, + -- result will be 0 + + -- octal string to std_logic_vector + function o (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than x'length*4, result will be truncated on the left + -- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W, + -- result will be 0 + + -- binary string to std_logic_vector + function b (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than x'length*4, result will be truncated on the left + -- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W, + -- result will be 0 + + -- hex string to natural + function h (x : string) + return natural; + -- if x is other than characters 0 to 9 or a,A to f,F, result will be 0 + + -- decimal string to natural + function d (x : string) + return natural; + -- if x is other than characters 0 to 9, result will be 0 + + -- octal string to natural + function o (x : string) + return natural; + -- if x is other than characters 0 to 7, result will be 0 + + -- binary string to natural + function b (x : string) + return natural; + -- if x is other than characters 0 to 1, result will be 0 + + -- natural to std_logic_vector + function to_slv (x : natural; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than sizeof(x), result will be truncated on the left + -- see note above regarding possible formats for x + + -- integer to std_logic_vector + function int_to_slv (x : integer; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector; + -- if rtn_len is < than sizeof(x), result will be truncated on the left + -- see note above regarding possible formats for x + + -- natural to std_logic + function to_sl (x : natural) + return std_logic; + + -- natural to time + function to_time (x : natural) + return time; + -- see note above regarding possible formats for x + + -- std_logic_vector to integer + function to_int (x : std_logic_vector) + return integer; + +END conversions; +-- +-------------------------------------------------------------------------------- +-- + +PACKAGE BODY conversions IS + + -- private declarations for this package + type basetype is (binary, octal, decimal, hex); + + function max(x,y: integer) return integer is + begin + if x > y then return x; else return y; end if; + end max; + + function min(x,y: integer) return integer is + begin + if x < y then return x; else return y; end if; + end min; + + -- consider function sizeof for string/slv/???, return natural + + -- function size(len: natural) return natural is + -- begin + -- if len=0 then + -- return 31; + -- else return len; + -- end if; + -- end size; + + function nextmultof (x : positive; + size : positive) return positive is + begin + case x mod size is + when 0 => return size * x/size; + when others => return size * (x/size + 1); + end case; + end nextmultof; + + function rtn_base (base : basetype) return character is + begin + case base is + when binary => return 'b'; + when octal => return 'o'; + when decimal => return 'd'; + when hex => return 'h'; + end case; + end rtn_base; + + function format (r : string; + base : basetype; + rtn_len : natural ; + justify : justify_side; + basespec : b_spec) return string is + variable int_rtn_len : integer; + begin + if basespec=yes then + int_rtn_len := rtn_len - 3; + else + int_rtn_len := rtn_len; + end if; + if int_rtn_len <= r'length then + case basespec is + when no => return r ; + when yes => return rtn_base(base) & '"' & r & '"'; + end case; + else + case justify is + when left => + case basespec is + when no => + return r & fill(' ',int_rtn_len - r'length); + when yes => + return rtn_base(base) & '"' & r & '"' & + fill(' ',int_rtn_len - r'length); + end case; + when right => + case basespec is + when no => + return fill(' ',int_rtn_len - r'length) & r ; + when yes => + return fill(' ',int_rtn_len - r'length) & + rtn_base(base) & '"' & r & '"'; + end case; + end case; + end if; + end format; + + -- convert numeric string of any base to natural + function cnvt_base (x : string; + inbase : natural range 2 to 16) return natural is + -- assumes x is an unsigned number string of base 'inbase' + -- values larger than natural'high are not supported + variable r,t : natural := 0; + variable place : positive := 1; + begin + for i in x'reverse_range loop + case x(i) is + when '0' => t := 0; + when '1' => t := 1; + when '2' => t := 2; + when '3' => t := 3; + when '4' => t := 4; + when '5' => t := 5; + when '6' => t := 6; + when '7' => t := 7; + when '8' => t := 8; + when '9' => t := 9; + when 'a'|'A' => t := 10; + when 'b'|'B' => t := 11; + when 'c'|'C' => t := 12; + when 'd'|'D' => t := 13; + when 'e'|'E' => t := 14; + when 'f'|'F' => t := 15; + when '_' => t := 0; -- ignore these characters + place := place / inbase; + when others => + assert false + report lf & + "CNVT_BASE found input value larger than base: " & lf & + "Input value: " & x(i) & + " Base: " & to_int_str(inbase) & lf & + "converting input to integer 0" + severity warning; + return 0; + end case; + if t / inbase > 1 then -- invalid value for base + assert false + report lf & + "CNVT_BASE found input value larger than base: " & lf & + "Input value: " & x(i) & + " Base: " & to_int_str(inbase) & lf & + "converting input to integer 0" + severity warning; + return 0; + else + r := r + (t * place); + place := place * inbase; + end if; + end loop; + return r; + end cnvt_base; + + function extend (x : std_logic; + len : positive) return std_logic_vector is + variable v : std_logic_vector(1 to len) := (others => x); + begin + return v; + end extend; + + + -- implementation of public declarations + + function to_bin_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + + variable int : std_logic_vector(1 to x'length):=x; + variable r : string(1 to x'length):=(others=>'$'); + begin + for i in int'range loop + r(i to i) := to_bin_str(int(i),basespec=>no); + end loop; + return format (r,binary,rtn_len,justify,basespec); + end to_bin_str; + + function to_bin_str(x : std_logic; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + variable r : string(1 to 1); + begin + case x is + when '0' => r(1) := '0'; + when '1' => r(1) := '1'; + when 'U' => r(1) := 'U'; + when 'X' => r(1) := 'X'; + when 'Z' => r(1) := 'Z'; + when 'W' => r(1) := 'W'; + when 'H' => r(1) := 'H'; + when 'L' => r(1) := 'L'; + when '-' => r(1) := '-'; + end case; + return format (r,binary,rtn_len,justify,basespec); + end to_bin_str; + + function to_bin_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + variable int : natural := x; + variable ptr : positive range 2 to 32 := 32; + variable r : string(2 to 32):=(others=>'$'); + begin + if int = 0 then + return format ("0",binary,rtn_len,justify,basespec); + end if; + + while int > 0 loop + case int rem 2 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when others => + assert false report lf & "TO_BIN_STR, shouldn't happen" + severity failure; + return "$"; + null; + end case; + int := int / 2; + ptr := ptr - 1; + end loop; + return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec); + end to_bin_str; + + function to_hex_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + -- will return x'length/4 + variable nxt : positive := nextmultof(x'length,4); + variable int : std_logic_vector(1 to nxt):= (others => '0'); + variable ptr : positive range 1 to (nxt/4)+1 := 1; + variable r : string(1 to nxt/4):=(others=>'$'); + subtype slv4 is std_logic_vector(1 to 4); + variable slv4_val : slv4; + begin + int(nxt-x'length+1 to nxt) := x; + if nxt-x'length > 0 and x(x'left) /= '1' then + int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length); + end if; + for i in int'range loop + next when i rem 4 /= 1; + slv4_val := int(i to i+3); + case slv4_val is + when "0000" => r(ptr) := '0'; + when "0001" => r(ptr) := '1'; + when "0010" => r(ptr) := '2'; + when "0011" => r(ptr) := '3'; + when "0100" => r(ptr) := '4'; + when "0101" => r(ptr) := '5'; + when "0110" => r(ptr) := '6'; + when "0111" => r(ptr) := '7'; + when "1000" => r(ptr) := '8'; + when "1001" => r(ptr) := '9'; + when "1010" => r(ptr) := 'A'; + when "1011" => r(ptr) := 'B'; + when "1100" => r(ptr) := 'C'; + when "1101" => r(ptr) := 'D'; + when "1110" => r(ptr) := 'E'; + when "1111" => r(ptr) := 'F'; + when "ZZZZ" => r(ptr) := 'Z'; + when "WWWW" => r(ptr) := 'W'; + when "LLLL" => r(ptr) := 'L'; + when "HHHH" => r(ptr) := 'H'; + when "UUUU" => r(ptr) := 'U'; + when "XXXX" => r(ptr) := 'X'; + when "----" => r(ptr) := '-'; + when others => + assert false + report lf & + "TO_HEX_STR found illegal value: " & + to_bin_str(int(i to i+3)) & lf & + "converting input to '-'" + severity warning; + r(ptr) := '-'; + end case; + ptr := ptr + 1; + end loop; + return format (r,hex,rtn_len,justify,basespec); + end to_hex_str; + + function to_hex_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + variable int : natural := x; + variable ptr : positive range 1 to 20 := 20; + variable r : string(1 to 20):=(others=>'$'); + begin + if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if; + while int > 0 loop + case int rem 16 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when 2 => r(ptr) := '2'; + when 3 => r(ptr) := '3'; + when 4 => r(ptr) := '4'; + when 5 => r(ptr) := '5'; + when 6 => r(ptr) := '6'; + when 7 => r(ptr) := '7'; + when 8 => r(ptr) := '8'; + when 9 => r(ptr) := '9'; + when 10 => r(ptr) := 'A'; + when 11 => r(ptr) := 'B'; + when 12 => r(ptr) := 'C'; + when 13 => r(ptr) := 'D'; + when 14 => r(ptr) := 'E'; + when 15 => r(ptr) := 'F'; + when others => + assert false report lf & "TO_HEX_STR, shouldn't happen" + severity failure; + return "$"; + end case; + int := int / 16; + ptr := ptr - 1; + end loop; + return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec); + end to_hex_str; + + function to_oct_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + -- will return x'length/3 + variable nxt : positive := nextmultof(x'length,3); + variable int : std_logic_vector(1 to nxt):= (others => '0'); + variable ptr : positive range 1 to (nxt/3)+1 := 1; + variable r : string(1 to nxt/3):=(others=>'$'); + subtype slv3 is std_logic_vector(1 to 3); + begin + int(nxt-x'length+1 to nxt) := x; + if nxt-x'length > 0 and x(x'left) /= '1' then + int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length); + end if; + for i in int'range loop + next when i rem 3 /= 1; + case slv3'(int(i to i+2)) is + when "000" => r(ptr) := '0'; + when "001" => r(ptr) := '1'; + when "010" => r(ptr) := '2'; + when "011" => r(ptr) := '3'; + when "100" => r(ptr) := '4'; + when "101" => r(ptr) := '5'; + when "110" => r(ptr) := '6'; + when "111" => r(ptr) := '7'; + when "ZZZ" => r(ptr) := 'Z'; + when "WWW" => r(ptr) := 'W'; + when "LLL" => r(ptr) := 'L'; + when "HHH" => r(ptr) := 'H'; + when "UUU" => r(ptr) := 'U'; + when "XXX" => r(ptr) := 'X'; + when "---" => r(ptr) := '-'; + when others => + assert false + report lf & + "TO_OCT_STR found illegal value: " & + to_bin_str(int(i to i+2)) & lf & + "converting input to '-'" + severity warning; + r(ptr) := '-'; + end case; + ptr := ptr + 1; + end loop; + return format (r,octal,rtn_len,justify,basespec); + end to_oct_str; + + function to_oct_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + variable int : natural := x; + variable ptr : positive range 1 to 20 := 20; + variable r : string(1 to 20):=(others=>'$'); + begin + if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if; + while int > 0 loop + case int rem 8 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when 2 => r(ptr) := '2'; + when 3 => r(ptr) := '3'; + when 4 => r(ptr) := '4'; + when 5 => r(ptr) := '5'; + when 6 => r(ptr) := '6'; + when 7 => r(ptr) := '7'; + when others => + assert false report lf & "TO_OCT_STR, shouldn't happen" + severity failure; + return "$"; + end case; + int := int / 8; + ptr := ptr - 1; + end loop; + return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec); + end to_oct_str; + + function to_int_str(x : natural; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) return string is + variable int : natural := x; + variable ptr : positive range 1 to 32 := 32; + variable r : string(1 to 32):=(others=>'$'); + begin + if x=0 then return format ("0",decimal,rtn_len,justify,basespec); + else + while int > 0 loop + case int rem 10 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when 2 => r(ptr) := '2'; + when 3 => r(ptr) := '3'; + when 4 => r(ptr) := '4'; + when 5 => r(ptr) := '5'; + when 6 => r(ptr) := '6'; + when 7 => r(ptr) := '7'; + when 8 => r(ptr) := '8'; + when 9 => r(ptr) := '9'; + when others => + assert false report lf & "TO_INT_STR, shouldn't happen" + severity failure; + return "$"; + end case; + int := int / 10; + ptr := ptr - 1; + end loop; + return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec); + end if; + end to_int_str; + + function to_int_str(x : std_logic_vector; + rtn_len : natural := 0; + justify : justify_side := right; + basespec : b_spec := yes) + return string is + begin + return to_int_str(to_nat(x),rtn_len,justify,basespec); + end to_int_str; + + + function to_time_str (x : time) + return string is + begin + return to_int_str(to_nat(x),basespec=>no) & " ns"; + end to_time_str; + + function fill (fill_char : character := '*'; + rtn_len : integer := 1) + return string is + variable r : string(1 to max(rtn_len,1)) := (others => fill_char); + variable len : integer; + begin + if rtn_len < 2 then -- always returns at least 1 fill char + len := 1; + else + len := rtn_len; + end if; + return r(1 to len); + end fill; + + function to_nat(x : std_logic_vector) return natural is + -- assumes x is an unsigned number, lsb on right, + -- more than 31 bits are truncated on left + variable t : std_logic_vector(1 to x'length) := x; + variable int : std_logic_vector(1 to 31) := (others => '0'); + variable r : natural := 0; + variable place : positive := 1; + begin + if x'length < 32 then + int(max(32-x'length,1) to 31) := t(1 to x'length); + else -- x'length >= 32 + int(1 to 31) := t(x'length-30 to x'length); + end if; + for i in int'reverse_range loop + case int(i) is + when '1' | 'H' => r := r + place; + when '0' | 'L' => null; + when others => + assert false + report lf & + "TO_NAT found illegal value: " & to_bin_str(int(i)) & lf & + "converting input to integer 0" + severity warning; + return 0; + end case; + exit when i=1; + place := place * 2; + end loop; + return r; + end to_nat; + + function to_nat (x : std_logic) + return natural is + begin + case x is + when '0' => return 0 ; + when '1' => return 1 ; + when others => + assert false + report lf & + "TO_NAT found illegal value: " & to_bin_str(x) & lf & + "converting input to integer 0" + severity warning; + return 0; + end case; + end to_nat; + + function to_nat (x : time) + return natural is + begin + return x / 1 ns; + end to_nat; + + function h(x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than x'length*4, result will be truncated on the left + -- if x is other than characters 0 to 9 or a,A to f,F or + -- x,X,z,Z,u,U,-,w,W, + -- those result bits will be set to 0 + variable int : string(1 to x'length) := x; + variable size: positive := max(x'length*4,rtn_len); + variable ptr : integer range -3 to size := size; + variable r : std_logic_vector(1 to size) := (others=>'0'); + begin + for i in int'reverse_range loop + case int(i) is + when '0' => r(ptr-3 to ptr) := "0000"; + when '1' => r(ptr-3 to ptr) := "0001"; + when '2' => r(ptr-3 to ptr) := "0010"; + when '3' => r(ptr-3 to ptr) := "0011"; + when '4' => r(ptr-3 to ptr) := "0100"; + when '5' => r(ptr-3 to ptr) := "0101"; + when '6' => r(ptr-3 to ptr) := "0110"; + when '7' => r(ptr-3 to ptr) := "0111"; + when '8' => r(ptr-3 to ptr) := "1000"; + when '9' => r(ptr-3 to ptr) := "1001"; + when 'a'|'A' => r(ptr-3 to ptr) := "1010"; + when 'b'|'B' => r(ptr-3 to ptr) := "1011"; + when 'c'|'C' => r(ptr-3 to ptr) := "1100"; + when 'd'|'D' => r(ptr-3 to ptr) := "1101"; + when 'e'|'E' => r(ptr-3 to ptr) := "1110"; + when 'f'|'F' => r(ptr-3 to ptr) := "1111"; + when 'U' => r(ptr-3 to ptr) := "UUUU"; + when 'X' => r(ptr-3 to ptr) := "XXXX"; + when 'Z' => r(ptr-3 to ptr) := "ZZZZ"; + when 'W' => r(ptr-3 to ptr) := "WWWW"; + when 'H' => r(ptr-3 to ptr) := "HHHH"; + when 'L' => r(ptr-3 to ptr) := "LLLL"; + when '-' => r(ptr-3 to ptr) := "----"; + when '_' => ptr := ptr + 4; + when others => + assert false + report lf & + "O conversion found illegal input character: " & + int(i) & lf & "converting character to '----'" + severity warning; + r(ptr-3 to ptr) := "----"; + end case; + ptr := ptr - 4; + end loop; + return r(size-rtn_len+1 to size); + end h; + + function d (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than binary length of x, result will be truncated on + -- the left + -- if x is other than characters 0 to 9, result will be 0 + begin + return to_slv(cnvt_base(x,10),rtn_len); + end d; + + function o (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than x'length*3, result will be truncated on the left + -- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W, + -- those result bits will be set to 0 + variable int : string(1 to x'length) := x; + variable size: positive := max(x'length*3,rtn_len); + variable ptr : integer range -2 to size := size; + variable r : std_logic_vector(1 to size) := (others=>'0'); + begin + for i in int'reverse_range loop + case int(i) is + when '0' => r(ptr-2 to ptr) := "000"; + when '1' => r(ptr-2 to ptr) := "001"; + when '2' => r(ptr-2 to ptr) := "010"; + when '3' => r(ptr-2 to ptr) := "011"; + when '4' => r(ptr-2 to ptr) := "100"; + when '5' => r(ptr-2 to ptr) := "101"; + when '6' => r(ptr-2 to ptr) := "110"; + when '7' => r(ptr-2 to ptr) := "111"; + when 'U' => r(ptr-2 to ptr) := "UUU"; + when 'X' => r(ptr-2 to ptr) := "XXX"; + when 'Z' => r(ptr-2 to ptr) := "ZZZ"; + when 'W' => r(ptr-2 to ptr) := "WWW"; + when 'H' => r(ptr-2 to ptr) := "HHH"; + when 'L' => r(ptr-2 to ptr) := "LLL"; + when '-' => r(ptr-2 to ptr) := "---"; + when '_' => ptr := ptr + 3; + when others => + assert false + report lf & + "O conversion found illegal input character: " & + int(i) & lf & "converting character to '---'" + severity warning; + r(ptr-2 to ptr) := "---"; + end case; + ptr := ptr - 3; + end loop; + return r(size-rtn_len+1 to size); + end o; + + function b (x : string; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than x'length, result will be truncated on the left + -- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W, + -- those result bits will be set to 0 + variable int : string(1 to x'length) := x; + variable size: positive := max(x'length,rtn_len); + variable ptr : integer range 0 to size+1 := size; -- csa + variable r : std_logic_vector(1 to size) := (others=>'0'); + begin + for i in int'reverse_range loop + case int(i) is + when '0' => r(ptr) := '0'; + when '1' => r(ptr) := '1'; + when 'U' => r(ptr) := 'U'; + when 'X' => r(ptr) := 'X'; + when 'Z' => r(ptr) := 'Z'; + when 'W' => r(ptr) := 'W'; + when 'H' => r(ptr) := 'H'; + when 'L' => r(ptr) := 'L'; + when '-' => r(ptr) := '-'; + when '_' => ptr := ptr + 1; + when others => + assert false + report lf & + "B conversion found illegal input character: " & + int(i) & lf & "converting character to '-'" + severity warning; + r(ptr) := '-'; + end case; + ptr := ptr - 1; + end loop; + return r(size-rtn_len+1 to size); + end b; + + function h (x : string) + return natural is + -- only following characters are allowed, otherwise result will be 0 + -- 0 to 9 + -- a,A to f,F + -- blanks, underscore + begin + return cnvt_base(x,16); + end h; + + function d (x : string) + return natural is + -- only following characters are allowed, otherwise result will be 0 + -- 0 to 9 + -- blanks, underscore + begin + return cnvt_base(x,10); + end d; + + function o (x : string) + return natural is + -- only following characters are allowed, otherwise result will be 0 + -- 0 to 7 + -- blanks, underscore + begin + return cnvt_base(x,8); + end o; + + function b (x : string) + return natural is + -- only following characters are allowed, otherwise result will be 0 + -- 0 to 1 + -- blanks, underscore + begin + return cnvt_base(x,2); + end b; + + function to_slv(x : natural; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than sizeof(x), result will be truncated on the left + variable int : natural := x; + variable ptr : positive := 32; + variable r : std_logic_vector(1 to 32) := (others=>'0'); + begin + while int > 0 loop + case int rem 2 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when others => + assert false report lf & "TO_SLV, shouldn't happen" + severity failure; + return "0"; + end case; + int := int / 2; + ptr := ptr - 1; + end loop; + return r(33-rtn_len to 32); + end to_slv; + + function to_sl(x : natural) + return std_logic is + variable r : std_logic := '0'; + begin + case x is + when 0 => null; + when 1 => r := '1'; + when others => + assert false + report lf & + "TO_SL found illegal input character: " & + to_int_str(x) & lf & "converting character to '-'" + severity warning; + return '-'; + end case; + return r; + end to_sl; + + function int_to_slv(x : integer; + rtn_len : positive range 1 to 32 := 32) + return std_logic_vector is + -- if rtn_len is < than sizeof(x), result will be truncated on the left + variable int : integer := x; + variable ptr : positive := 32; + variable r : std_logic_vector(1 to 32) := (others=>'0'); + begin + if int >= 0 or int = 0 then + while int > 0 loop + case int rem 2 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when others => + assert false report lf & " shouldn't happen" + severity failure; + return "0"; + end case; + int := int / 2; + ptr := ptr - 1; + end loop; + return r(33-rtn_len to 32); + else + int := 2**(rtn_len - 1) + int; + while int > 0 loop + case int rem 2 is + when 0 => r(ptr) := '0'; + when 1 => r(ptr) := '1'; + when others => + assert false report lf & " shouldn't happen" + severity failure; + return "0"; + end case; + int := int / 2; + ptr := ptr - 1; + end loop; + r(33-rtn_len) := '1'; + return r(33-rtn_len to 32); + end if; + end int_to_slv; + + function to_time (x: natural) return time is + begin + return x * 1 ns; + end to_time; + + function to_int(x : std_logic_vector) return integer is + -- assumes x is an signed number + -- more than 32 bits are truncated on left + variable t : std_logic_vector(x'length downto 1) := x; + variable int : std_logic_vector(32 downto 1) := (others => '0'); + variable sign : std_logic := '0'; + variable size : integer := 0; + variable inv : boolean := false; + variable r : integer := 0; + variable place : positive := 1; + begin + if x'length < 33 then + sign := t(x'length); + for i in t'reverse_range loop + if sign = '1' then + if inv = true then + t(i) := not(t(i)); + elsif t(i) = '1' then + inv := true; + end if; + end if; + size := size +1; + end loop; + inv := false; + for i in 1 to size - 1 loop + case t(i) is + when '1' | 'H' => r := r + place; + when '0' | 'L' => null; + when others => + assert false + report lf & + " TO_INT found illegal value " + severity warning; + return 0; + end case; + place := place * 2; + end loop; + if sign = '1' THEN + return (- r); + else + return r; + end if; + else -- x'length >= 33 + int := t(32 downto 1); + sign := t(32); + for i in 1 to 31 loop + if sign = '1' then + if inv = true then + int(i) := not(int(i)); + elsif int(i) = '1' then + inv := true; + end if; + end if; + end loop; + inv := false; + for i in 1 to 31 loop + case int(i) is + when '1' | 'H' => r := r + place; + when '0' | 'L' => null; + when others => + assert false + report lf & + " TO_INT found illegal value " + severity warning; + return 0; + end case; + place := place * 2; + end loop; + if sign = '1' THEN + return (- r); + else + return r; + end if; + end if; + end to_int; + +END conversions; diff --git a/vhdl/fmf/ecl_package.vhd b/vhdl/fmf/ecl_package.vhd new file mode 100644 index 0000000..0e0598e --- /dev/null +++ b/vhdl/fmf/ecl_package.vhd @@ -0,0 +1,116 @@ +-- --------------------------------------------------------------- +-- File name : ecl_package.vhd +-- --------------------------------------------------------------- +-- Copyright (C) 1995 Free Model Foundry http://www.FreeModelFoundry.com/ +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms og the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY : +-- +-- version no: | author: | mod. date: | changes made: +-- V1.0 rev3 95 SEP 22 Initial release +-- +LIBRARY IEEE; +USE IEEE.Std_Logic_1164.ALL; +USE IEEE.VITAL_primitives.all; +USE IEEE.VITAL_timing.all; + +PACKAGE ecl_package IS + + TYPE stdlogic_map IS ARRAY(std_ulogic) OF std_ulogic; + TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; + + --------------------------------------------------------------- + --------------------------------------------------------------- + -- Following are constants for ECL models + --------------------------------------------------------------- + --------------------------------------------------------------- + -- Result map for Wired-or output values + --------------------------------------------------------------- + CONSTANT ECL_wired_or_rmap : VitalResultMapType := ('U','X','L','1'); + + CONSTANT ECL_no_weak_inputs : stdlogic_map := + +-- ------------------------------------------------- +-- | U X 0 1 Z W L H - | +-- ------------------------------------------------- + ( 'X', 'X', '0', '1', 'X', 'X', 'X', 'X', 'X' ); + + --------------------------------------------------------------- + -- Table for determining whether input pair is differential or + -- single-ended. There are 3 values: + -- input, input_bar neither or both Vbb(W) mode => 'X' + -- input_bar -- Vbb(W) mode => '0' + -- input -- Vbb(W) mode => '1' + -- Used as input to ECL_clk_tab: return value name convention is 'Mode' + --------------------------------------------------------------- + CONSTANT ECL_diff_mode_tab : stdlogic_table := ( + +-- --------------------------------------------------------- +-- | U X 0 1 Z W L H - | | +-- --------------------------------------------------------- + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | U | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | X | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | 0 | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | 1 | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | Z | + ( '1', '1', '1', '1', '1', 'X', '1', '1', '1' ), -- | W | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | L | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | H | + ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ) -- | - | + ); + + --------------------------------------------------------------- + -- Table for determining value of a non-clk differential input pair. + -- 'W' is value of Vbb on either input when it occurs. + -- This table indicates 'X' whenever diff. inputs are the same, which + -- is the most conservative approach. + --------------------------------------------------------------- + CONSTANT ECL_s_or_d_inputs_tab : stdlogic_table := ( + +-- --------------------------------------------------------- +-- | U X 0 1 Z W L H - | | +-- --------------------------------------------------------- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | + ( 'U', 'X', 'X', '0', 'X', '0', 'X', '0', 'X' ), -- | 0 | + ( 'U', 'X', '1', 'X', 'X', '1', '1', 'X', 'X' ), -- | 1 | + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | W | + ( 'U', 'X', 'X', '0', 'X', '0', 'X', '0', 'X' ), -- | L | + ( 'U', 'X', '1', 'X', 'X', '1', '1', 'X', 'X' ), -- | H | + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | + ); + + --------------------------------------------------------------- + -- Table for computing a single signal from a differential ECL + -- clock. Mode is '1' or '0' when the signal is single-ended. The rest of + -- the table is self-explanatory :) + --------------------------------------------------------------- + CONSTANT ECL_clk_tab : VitalStateTableType := ( + + -- --INPUTS-------|-PREV---|-OUTPUT---- + -- CLK CLK_N Mode | CLKint | CLKint' -- + ------------------|--------|----------- + ( '-', 'X', '1', '-', 'X'), -- Single-ended, Vbb on CLK + ( '-', '0', '1', '-', '1'), -- Single-ended, Vbb on CLK + ( '-', '1', '1', '-', '0'), -- Single-ended, Vbb on CLK + ( 'X', '-', '0', '-', 'X'), -- Single-ended, Vbb on CLK_N + ( '0', '-', '0', '-', '0'), -- Single-ended, Vbb on CLK_N + ( '1', '-', '0', '-', '1'), -- Single-ended, Vbb on CLK_N + -- Below are differential input possibilities only + ( 'X', '-', 'X', '-', 'X'), -- CLK unknown + ( '-', 'X', 'X', '-', 'X'), -- CLK unknown + ( '1', '-', 'X', 'X', '1'), -- Recover from 'X' + ( '0', '-', 'X', 'X', '0'), -- Recover from 'X' + ( '/', '0', 'X', '0', '1'), -- valid ECL rising edge + ( '1', '\', 'X', '0', '1'), -- valid ECL rising edge + ( '\', '1', 'X', '1', '0'), -- valid ECL falling edge + ( '0', '/', 'X', '1', '0'), -- valid ECL falling edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + +END ecl_package; diff --git a/vhdl/fmf/ecl_utils.vhd b/vhdl/fmf/ecl_utils.vhd new file mode 100644 index 0000000..fca4db4 --- /dev/null +++ b/vhdl/fmf/ecl_utils.vhd @@ -0,0 +1,160 @@ +-------------------------------------------------------------------------------- +-- File name : ecl_utils.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 1996-1997 Free Model Foundry http://www.FreeModelFoundry.com/ +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY : +-- +-- version | author | mod date | changes made +-- V2.0 rev3 07 FEB 96 Changed ECL_wired_or_rmap +-- to have 'Z' for low out +-- Renamed, redefined types +-- Changed name, to ecl_utils +-- V2.1 rev3 06 AUG 96 Redefined CONSTANT tables to make +-- it easier to alter Vbb values (for +-- others, not us) +-- V2.2 rev3 27 FEB 97 Added Xon and MsgOn default values +-------------------------------------------------------------------------------- +LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL; + USE IEEE.VITAL_primitives.all; + USE IEEE.VITAL_timing.all; + +PACKAGE ecl_utils IS + + TYPE eclstdlogic_map IS ARRAY(std_ulogic) OF X01; + TYPE eclstdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF X01; + + --------------------------------------------------------------- + -- Result map for Wired-or output values + --------------------------------------------------------------- + CONSTANT ECL_wired_or_rmap : VitalResultMapType := ('U','X','Z','1'); + + CONSTANT ECLUnitDelay : VitalDelayType := 1 ns; + CONSTANT ECLUnitDelay01 : VitalDelayType01 := (1 ns, 1 ns); + CONSTANT ECLUnitDelay01Z : VitalDelayType01Z := (others => 1 ns); + + CONSTANT DefaultECLInstancePath : STRING := "*"; + CONSTANT DefaultECLTimingChecks : Boolean := FALSE; + CONSTANT DefaultECLTimingModel : STRING := "UNIT"; + CONSTANT DefaultECLXon : Boolean := TRUE; + CONSTANT DefaultECLMsgOn : Boolean := TRUE; + + -- Older, VITAL generic being phased out + CONSTANT DefaultECLXGeneration : Boolean := TRUE; + + --------------------------------------------------------------- + -- We have chosen to use the value 'W' as the value for + -- VBB. Vbb is an intermediate (halfway between logic 0 and 1) + -- value for ECL logic used to "convert" differential inputs to single + -- ended values. 'W' is good because it is not likely to appear by + -- accident in a design (one possibility would be pulled-up and + -- pulled-down signals tied together and fed into the differential + -- input pin - not likely, eh?). Also, 'W' is not affected by + -- resolution with 'Z' ('-' is) and so digital capacitor models + -- which output 'Z' won't foul it up. + --------------------------------------------------------------- + CONSTANT ECLVbbValue : std_logic := 'W'; + + CONSTANT ECL_no_weak_inputs : eclstdlogic_map := + --------------------------------------------------- + --| U X 0 1 Z W L H - | + --------------------------------------------------- + ( 'X', 'X', '0', '1', 'X', 'X', 'X', 'X', 'X' ); + + --------------------------------------------------------------- + -- Table for determining whether input pair is differential or + -- single-ended. There are 3 values: + -- input, input_bar neither or both Vbb, mode => 'X' + -- input_bar = Vbb, mode => '0' + -- input = Vbb, mode => '1' + -- Used as input to ECL_clk_tab: return value name convention is 'Mode' + -- Type of 'Mode' is X01 + --------------------------------------------------------------- + CONSTANT ECL_diff_mode_tab : eclstdlogic_table := ( + -- + -- For the case, ECLVbbValue = 'W', table looks like this: + ------------------------------------------------------------- + ----| U X 0 1 Z W L H - | | + ------------------------------------------------------------- + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | U | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | X | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | 0 | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | 1 | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | Z | + -- ( '1', '1', '1', '1', '1', 'X', '1', '1', '1' ), -- | W | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | L | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ), -- | H | + -- ( 'X', 'X', 'X', 'X', 'X', '0', 'X', 'X', 'X' ) -- | - | + --); + + ECLVbbValue => (ECLVbbValue => 'X', OTHERS => '1'), + OTHERS => (ECLVbbValue => '0', OTHERS => 'X') + ); + + + --------------------------------------------------------------- + -- Table for determining value of a non-clk differential input pair. + -- This table indicates 'X' whenever diff. inputs are the same, which + -- is the most conservative approach. + -- ECLVbbValue should not be '0', 'L', '1', or 'H' (duh) + --------------------------------------------------------------- + CONSTANT ECL_s_or_d_inputs_tab : eclstdlogic_table := ( + -- + -- For the case, ECLVbbValue = 'W', table looks like this: + ------------------------------------------------------------- + ----| U X 0 1 Z W L H - | | + ------------------------------------------------------------- + -- ( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | U | + -- ( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | + -- ( 'X', 'X', 'X', '0', 'X', '0', 'X', '0', 'X' ), -- | 0 | + -- ( 'X', 'X', '1', 'X', 'X', '1', '1', 'X', 'X' ), -- | 1 | + -- ( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | + -- ( 'X', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | W | + -- ( 'X', 'X', 'X', '0', 'X', '0', 'X', '0', 'X' ), -- | L | + -- ( 'X', 'X', '1', 'X', 'X', '1', '1', 'X', 'X' ), -- | H | + -- ( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | + --); + + '0' => ('1' => '0', 'H' => '0', ECLVbbValue => '0', OTHERS => 'X'), + 'L' => ('1' => '0', 'H' => '0', ECLVbbValue => '0', OTHERS => 'X'), + '1' => ('0' => '1', 'L' => '1', ECLVbbValue => '1', OTHERS => 'X'), + 'H' => ('0' => '1', 'L' => '1', ECLVbbValue => '1', OTHERS => 'X'), + ECLVbbValue => ('0' => '1', 'L' => '1', '1' => '0', 'H' => '0', + OTHERS => 'X'), + OTHERS => (OTHERS => 'X') + ); + + + --------------------------------------------------------------- + -- Table for computing a single signal from a differential ECL clock + -- pair. Mode is '1' or '0' when the signal is single-ended. The rest of + -- the table is self-explanatory :) + --------------------------------------------------------------- + CONSTANT ECL_clk_tab : VitalStateTableType := ( + ------------------------------------------- + ------INPUTS-------|-PREV---|-OUTPUT---- + -- CLK CLKNeg Mode | CLKint | CLKint' -- + -------------------|--------|----------- + ( '-', 'X', '1', '-', 'X'), -- Single-ended, Vbb on CLK + ( '-', '0', '1', '-', '1'), -- Single-ended, Vbb on CLK + ( '-', '1', '1', '-', '0'), -- Single-ended, Vbb on CLK + ( 'X', '-', '0', '-', 'X'), -- Single-ended, Vbb on CLK_N + ( '0', '-', '0', '-', '0'), -- Single-ended, Vbb on CLK_N + ( '1', '-', '0', '-', '1'), -- Single-ended, Vbb on CLK_N + -- Below are differential input possibilities only + ( 'X', '-', 'X', '-', 'X'), -- CLK unknown + ( '-', 'X', 'X', '-', 'X'), -- CLK unknown + ( '1', '-', 'X', 'X', '1'), -- Recover from 'X' + ( '0', '-', 'X', 'X', '0'), -- Recover from 'X' + ( '/', '0', 'X', '0', '1'), -- valid ECL rising edge + ( '1', '\', 'X', '0', '1'), -- valid ECL rising edge + ( '\', '1', 'X', '1', '0'), -- valid ECL falling edge + ( '0', '/', 'X', '1', '0'), -- valid ECL falling edge + ( '-', '-', '-', '-', 'S') -- default + ); -- end of VitalStateTableType definition + +END ecl_utils; diff --git a/vhdl/fmf/ff_package.vhd b/vhdl/fmf/ff_package.vhd new file mode 100644 index 0000000..7a9e443 --- /dev/null +++ b/vhdl/fmf/ff_package.vhd @@ -0,0 +1,926 @@ +-------------------------------------------------------------------------------- +-- File name : ff_pacakge.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 1996-2007 Free Model Foundry http://www.FreeModelFoundry.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY : +-- +-- version | author | mod date | changes made +-- V2.0 rev3 23 MAR 96 Copyright added, general clean-up +-- V2.1 R. Steele 17 JUL 96 added LATN and LATNR tables +-- V2.2 rev3 23 JUL 96 per R.Steele and R. Munden, reversed +-- Latch enable definition +-- V2.3 R. Steele 97 MAY 16 Fixed JK FF tables for toggle mode +-- V2.4 R. Steele 97 JUN 02 Fixed JK FF tables for J K inputs +-- V2.5 R. Munden 97 NOV 09 Added LATNDFF and LATNDFFN tables +-- V2.6 R. Munden 98 APR 10 Added LATNDFFCEN and LATNDFFNCEN tables +-- made LATNDFF and LATNDFFN less pessimistic +-- for clk unknown cases +-- V2.7 R. Munden 99 JAN 30 Added DFFCEN table +-- V2.8 R. Munden 07 JUN 27 Fixed DREG and DREGQN tables +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.Std_Logic_1164.ALL; +USE IEEE.VITAL_primitives.all; +USE IEEE.VITAL_timing.all; + +-------------------------------------------------------------------------------- +PACKAGE ff_package IS + + --************************************************************ + -- Key to table names: + -- <ff identifier>FF<N if clock active low>[S or R]<N if active low> + -- [M]<# of mux inputs><CE if clock enable><QN if outputs inverted>_tab + --************************************************************ + + --------------------------------------------------------------- + -- STANDARD D_TYPE STATE TABLES + -- These tables have robust pessimism reduction that considers + -- the previous state of the D_f/f. + --------------------------------------------------------------- + + --------------------------------------------------------------- + -- D-flip/flop with Set and Reset both active high + --------------------------------------------------------------- + CONSTANT DFFSR_tab : VitalStateTableType := ( + + -- -------INPUTS-----------|PREV-|-OUTPUT-- + -- Viol CLK D S R | QI | Q' -- + ---------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '1', '1'), -- set unknown + ( '-', '/', '1', 'X', '0', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', '-', 'X'), -- set unknown + ( '-', 'B', '-', '0', 'X', '0', '0'), -- reset unknown + ( '-', '/', '0', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '1', '-', 'X'), -- both asserted + ( '-', '-', '-', '1', '0', '-', '1'), -- set asserted + ( '-', '-', '-', '0', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '0', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '0', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Set and Reset both active high and active-low clk + --------------------------------------------------------------- + CONSTANT DFFNSR_tab : VitalStateTableType := ( + + -- -------INPUTS-----------|PREV-|-OUTPUT-- + -- Viol CLK D S R | QI | Q' -- + ---------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '1', '1'), -- set unknown + ( '-', '\', '1', 'X', '0', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', '-', 'X'), -- set unknown + ( '-', 'B', '-', '0', 'X', '0', '0'), -- reset unknown + ( '-', '\', '0', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '1', '-', 'X'), -- both asserted + ( '-', '-', '-', '1', '0', '-', '1'), -- set asserted + ( '-', '-', '-', '0', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '0', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '0', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '0', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Reset active high + --------------------------------------------------------------- + CONSTANT DFFR_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '0'), -- reset unknown + ( '-', '/', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Reset active high and active-low clock + --------------------------------------------------------------- + CONSTANT DFFNR_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '0'), -- reset unknown + ( '-', '\', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Reset active high, active-low clock, and + -- inverting outputs + --------------------------------------------------------------- + CONSTANT DFFNRQN_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '1', '1'), -- reset unknown + ( '-', '\', '0', 'X', '1', '1'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '-', '1'), -- reset asserted + ( '-', 'X', '0', '0', '1', '1'), -- clk unknown + ( '-', 'X', '1', '0', '0', '0'), -- clk unknown + ( '-', 'X', '-', '0', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', '-', '1'), -- active clock edge + ( '-', '\', '1', '0', '-', '0'), -- active clock edge + ( '-', '\', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + --------------------------------------------------------------- + -- D-flip/flop with Reset active low + --------------------------------------------------------------- + CONSTANT DFFRN_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '0'), -- reset unknown + ( '-', '/', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '0', '-', '0'), -- reset asserted + ( '-', 'X', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '1', '-', 'X'), -- clk unknown + ( '-', '/', '0', '1', '-', '0'), -- active clock edge + ( '-', '/', '1', '1', '-', '1'), -- active clock edge + ( '-', '/', '-', '1', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Reset active low and active-low clock + --------------------------------------------------------------- + CONSTANT DFFNRN_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '0', '0'), -- reset unknown + ( '-', '\', '0', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '0', '-', '0'), -- reset asserted + ( '-', 'X', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '1', '-', 'X'), -- clk unknown + ( '-', '\', '0', '1', '-', '0'), -- active clock edge + ( '-', '\', '1', '1', '-', '1'), -- active clock edge + ( '-', '\', '-', '1', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Set active high + --------------------------------------------------------------- + CONSTANT DFFS_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D S | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '1', '1'), -- set unknown + ( '-', '/', '1', 'X', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', 'X'), -- set unknown + ( '-', '-', '-', '1', '-', '1'), -- set asserted + ( '-', 'X', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Set active high and active-low clock + --------------------------------------------------------------- + CONSTANT DFFNS_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D S | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '1', '1'), -- set unknown + ( '-', '\', '1', 'X', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', 'X'), -- set unknown + ( '-', '-', '-', '1', '-', '1'), -- set asserted + ( '-', 'X', '0', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Set active low + --------------------------------------------------------------- + CONSTANT DFFSN_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D S | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '1', '1'), -- set unknown + ( '-', '/', '1', 'X', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', 'X'), -- set unknown + ( '-', '-', '-', '0', '-', '1'), -- set asserted + ( '-', 'X', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '1', '-', 'X'), -- clk unknown + ( '-', '/', '0', '1', '-', '0'), -- active clock edge + ( '-', '/', '1', '1', '-', '1'), -- active clock edge + ( '-', '/', '-', '1', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with Set active low and active-low clock + --------------------------------------------------------------- + CONSTANT DFFNSN_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol CLK D S | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', 'X', '1', '1'), -- set unknown + ( '-', '\', '1', 'X', '1', '1'), -- set unknown + ( '-', '-', '-', 'X', '-', 'X'), -- set unknown + ( '-', '-', '-', '0', '-', '1'), -- set asserted + ( '-', 'X', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '1', '-', 'X'), -- clk unknown + ( '-', '\', '0', '1', '-', '0'), -- active clock edge + ( '-', '\', '1', '1', '-', '1'), -- active clock edge + ( '-', '\', '-', '1', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with 2-input mux on D inputs with select + --------------------------------------------------------------- + CONSTANT DFFM2_tab : VitalStateTableType := ( + + ---------INPUTS-----------|PREV-|-OUTPUT-- + -- Viol CLK D0 D1 S | QI | Q' -- + --------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '-', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '-', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '0', '0', 'X', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', 'X', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '-', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '-', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', '0', '-', 'X'), -- active clock edge + ( '-', '/', '-', '0', '1', '-', '0'), -- active clock edge + ( '-', '/', '-', '1', '1', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', '1', '-', 'X'), -- active clock edge + ( '-', '/', '0', '0', 'X', '-', '0'), -- active clock edge + ( '-', '/', '1', '1', 'X', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + -------------------------------------------------------------- + -- D-flip/flop with 2-input mux on D inputs with select, and + -- active-low clock + --------------------------------------------------------------- + CONSTANT DFFNM2_tab : VitalStateTableType := ( + + ---------INPUTS-----------|PREV-|-OUTPUT-- + -- Viol CLK D0 D1 S | QI | Q' -- + --------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '-', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '-', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '0', '1', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '1', '1', '1'), -- clk unknown + ( '-', 'X', '0', '0', 'X', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', 'X', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '-', '-', 'X'), -- clk unknown + ( '-', '\', '0', '-', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '-', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', '0', '-', 'X'), -- active clock edge + ( '-', '\', '-', '0', '1', '-', '0'), -- active clock edge + ( '-', '\', '-', '1', '1', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', '1', '-', 'X'), -- active clock edge + ( '-', '\', '0', '0', 'X', '-', '0'), -- active clock edge + ( '-', '\', '1', '1', 'X', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop + --------------------------------------------------------------- + CONSTANT DFF_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with active low clock enable + --------------------------------------------------------------- + CONSTANT DFFCEN_tab : VitalStateTableType := ( + + ----INPUTS------------|PREV-|-OUTPUT-- + -- Viol CEN CLK D | QI | Q' -- + ----------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', '-', 'X', '0', '0', '0'), -- clk unknown + ( '-', '-', 'X', '1', '1', '1'), -- clk unknown + ( '-', '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', 'X', '-', '0', '0', '0'), -- clken unknown + ( '-', 'X', '-', '1', '1', '1'), -- clken unknown + ( '-', 'X', '-', '-', '-', 'X'), -- clken unknown + ( '-', '0', '/', '0', '-', '0'), -- active clock edge + ( '-', '0', '/', '1', '-', '1'), -- active clock edge + ( '-', '0', '/', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with inverting outputs + --------------------------------------------------------------- + CONSTANT DFFQN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '1', '1'), -- clk unknown + ( '-', 'X', '1', '0', '0'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '-', '1'), -- active clock edge + ( '-', '/', '1', '-', '0'), -- active clock edge + ( '-', '/', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with active-low clock + --------------------------------------------------------------- + CONSTANT DFFN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '\', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- D-flip/flop with active-low clock and inverting outputs + --------------------------------------------------------------- + CONSTANT DFFNQN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '1', '1'), -- clk unknown + ( '-', 'X', '1', '0', '0'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '\', '0', '-', '1'), -- active clock edge + ( '-', '\', '1', '-', '0'), -- active clock edge + ( '-', '\', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --************************************************************ + --------------------------------------------------------------- + -- J/K Flip/flop STATE TABLES + -- These tables have robust pessimism reduction that considers + -- the previous state of the J/K f/f. + --------------------------------------------------------------- + + --------------------------------------------------------------- + -- J/K flip/flop with Reset active high + --------------------------------------------------------------- + CONSTANT JKFFR_tab : VitalStateTableType := ( + + ----INPUTS-----------------|PREV-|-OUTPUT-- + -- Viol CLK J K R | QI | Q' -- + ---------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', '-', 'X', '0', '0'), -- reset unknown + ( '-', '/', '0', '-', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '-', '0', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', '0', 'X', 'X'), -- active clock edge + ( '-', '/', '0', '0', '0', '0', '0'), -- active clock edge + ( '-', '/', '0', '0', '0', '1', '1'), -- active clock edge + ( '-', '/', '1', '1', '0', '0', '1'), -- active clock edge + ( '-', '/', '1', '1', '0', '1', '0'), -- active clock edge + ( '-', '/', '0', '1', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '0', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- J/K flip/flop with Reset active high and active-low clock + --------------------------------------------------------------- + CONSTANT JKFFNR_tab : VitalStateTableType := ( + + ----INPUTS-----------------|PREV-|-OUTPUT-- + -- Viol CLK J K R | QI | Q' -- + ---------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', '-', '-', 'X', '0', '0'), -- reset unknown + ( '-', '\', '0', '-', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '-', '0', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '0', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '0', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', '0', 'X', 'X'), -- active clock edge + ( '-', '\', '0', '0', '0', '0', '0'), -- active clock edge + ( '-', '\', '0', '0', '0', '1', '1'), -- active clock edge + ( '-', '\', '1', '1', '0', '0', '1'), -- active clock edge + ( '-', '\', '1', '1', '0', '1', '0'), -- active clock edge + ( '-', '\', '0', '1', '0', '-', '0'), -- active clock edge + ( '-', '\', '1', '0', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', '0', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- J/K flip/flop + --------------------------------------------------------------- + CONSTANT JKFF_tab : VitalStateTableType := ( + + ----INPUTS------------|PREV-|-OUTPUT-- + -- Viol CLK J K | QI | Q' -- + ----------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '-', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', 'X', 'X'), -- active clock edge + ( '-', '/', '0', '0', '0', '0'), -- active clock edge + ( '-', '/', '0', '0', '1', '1'), -- active clock edge + ( '-', '/', '1', '1', '0', '1'), -- active clock edge + ( '-', '/', '1', '1', '1', '0'), -- active clock edge + ( '-', '/', '0', '1', '-', '0'), -- active clock edge + ( '-', '/', '1', '0', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- J/K flip/flop with active-low clock + --------------------------------------------------------------- + CONSTANT JKFFN_tab : VitalStateTableType := ( + + ----INPUTS------------|PREV-|-OUTPUT-- + -- Viol CLK J K | QI | Q' -- + ----------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '-', '0', '0'), -- clk unknown + ( '-', 'X', '-', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', '-', 'X'), -- clk unknown + ( '-', '\', '0', '0', 'X', 'X'), -- active clock edge + ( '-', '\', '0', '0', '0', '0'), -- active clock edge + ( '-', '\', '0', '0', '1', '1'), -- active clock edge + ( '-', '\', '1', '1', '0', '1'), -- active clock edge + ( '-', '\', '1', '1', '1', '0'), -- active clock edge + ( '-', '\', '0', '1', '-', '0'), -- active clock edge + ( '-', '\', '1', '0', '-', '1'), -- active clock edge + ( '-', '\', '-', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --************************************************************ + --------------------------------------------------------------- + -- Other flip/flop STATE TABLES + --------------------------------------------------------------- + --************************************************************ + + --------------------------------------------------------------- + -- Toggle flip/flop with no reset (unknown state -> 0 on clock) + -- Used where user doesn't care about phase of output, such as + -- for clock dividers + --------------------------------------------------------------- + CONSTANT TFF_tab : VitalStateTableType := ( + + ----INPUTS--|PREV-|-OUTPUT-- + -- Viol CLK | QI | Q' -- + ------------|-----|--------- + ( 'X', '-', '-', 'X'), -- timing violation + ( '-', 'X', '-', 'X'), -- clk unknown + ( '-', '/', 'X', '0'), -- active clock edge + ( '-', '/', '0', '1'), -- active clock edge + ( '-', '/', '1', '0'), -- active clock edge + ( '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Toggle flip/flop with Reset active high + --------------------------------------------------------------- + CONSTANT TFFR_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK R | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', 'X', '0', '0'), -- reset unknown + ( '-', '/', 'X', '1', '0'), -- reset unknown + ( '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '1', '-', '0'), -- reset active + ( '-', 'X', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', 'X', 'X'), -- active clock edge + ( '-', '/', '0', '0', '1'), -- active clock edge + ( '-', '/', '0', '1', '0'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Toggle flip/flop with Set and Reset both active high + --------------------------------------------------------------- + CONSTANT TFFSR_tab : VitalStateTableType := ( + + ----INPUTS-----------|PREV-|-OUTPUT-- + -- Viol CLK S R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'B', 'X', '0', '1', '1'), -- set unknown + ( '-', '/', 'X', '0', '0', '1'), -- set unknown + ( '-', '-', 'X', '-', '-', 'X'), -- set unknown + ( '-', 'B', '0', 'X', '0', '0'), -- reset unknown + ( '-', '/', '0', 'X', '1', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '1', '1', '-', 'X'), -- both asserted + ( '-', '-', '1', '0', '-', '1'), -- set asserted + ( '-', '-', '0', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '-', 'X'), -- clk unknown + ( '-', '/', '0', '0', 'X', 'X'), -- active clock edge + ( '-', '/', '0', '0', '0', '1'), -- active clock edge + ( '-', '/', '0', '0', '1', '0'), -- active clock edge + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Simple register without previous states + --------------------------------------------------------------- + CONSTANT DREG_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '0', '0'), -- clk unknown + ( '-', 'X', '1', '1', '1'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '-', '0'), -- active clock edge + ( '-', '/', '1', '-', '1'), -- active clock edge + ( '-', '/', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Simple register without previous states, inverting outputs + --------------------------------------------------------------- + CONSTANT DREGQN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol CLK D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '1', '1'), -- clk unknown + ( '-', 'X', '1', '0', '0'), -- clk unknown + ( '-', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '/', '0', '-', '1'), -- active clock edge + ( '-', '/', '1', '-', '0'), -- active clock edge + ( '-', '/', '-', '-', 'X'), -- active clock edge + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch + --------------------------------------------------------------- + CONSTANT LAT_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol LEN D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '0', '0'), -- len unknown + ( '-', 'X', '1', '1', '1'), -- len unknown + ( '-', 'X', '-', '-', 'X'), -- len unknown + ( '-', '0', '0', '-', '0'), -- Latch transparent + ( '-', '0', '1', '-', '1'), -- Latch transparent + ( '-', '0', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch with LEN transparent high + --------------------------------------------------------------- + CONSTANT LATN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol LEN D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '0', '0'), -- len unknown + ( '-', 'X', '1', '1', '1'), -- len unknown + ( '-', 'X', '-', '-', 'X'), -- len unknown + ( '-', '1', '0', '-', '0'), -- Latch transparent + ( '-', '1', '1', '-', '1'), -- Latch transparent + ( '-', '1', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch with inverting outputs + --------------------------------------------------------------- + CONSTANT LATQN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol LEN D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '1', '1'), -- len unknown + ( '-', 'X', '1', '0', '0'), -- len unknown + ( '-', 'X', '-', '-', 'X'), -- len unknown + ( '-', '0', '0', '-', '1'), -- Latch transparent + ( '-', '0', '1', '-', '0'), -- Latch transparent + ( '-', '0', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch with LEN transparent high and inverting outputs + --------------------------------------------------------------- + CONSTANT LATNQN_tab : VitalStateTableType := ( + + ----INPUTS-------|PREV-|-OUTPUT-- + -- Viol LEN D | QI | Q' -- + -----------------|-----|--------- + ( 'X', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', '0', '1', '1'), -- len unknown + ( '-', 'X', '1', '0', '0'), -- len unknown + ( '-', 'X', '-', '-', 'X'), -- len unknown + ( '-', '1', '0', '-', '1'), -- Latch transparent + ( '-', '1', '1', '-', '0'), -- Latch transparent + ( '-', '1', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch with Reset active high + --------------------------------------------------------------- + CONSTANT LATR_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol LEN D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', '0', '0', 'X', '0', '0'), -- reset unknown + ( '-', '1', '-', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0'), -- len unknown + ( '-', 'X', '1', '0', '1', '1'), -- len unknown + ( '-', 'X', '-', '0', '-', 'X'), -- len unknown + ( '-', '0', '0', '0', '-', '0'), -- Latch transparent + ( '-', '0', '1', '0', '-', '1'), -- Latch transparent + ( '-', '0', '-', '0', '-', 'X'), -- Latch transparent, unknown D + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch with Reset active high; LEN transparent high + --------------------------------------------------------------- + CONSTANT LATNR_tab : VitalStateTableType := ( + + ---------INPUTS------|PREV-|-OUTPUT-- + -- Viol LEN D R | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', '1', '0', 'X', '0', '0'), -- reset unknown + ( '-', '0', '-', 'X', '0', '0'), -- reset unknown + ( '-', '-', '-', 'X', '-', 'X'), -- reset unknown + ( '-', '-', '-', '1', '-', '0'), -- reset asserted + ( '-', 'X', '0', '0', '0', '0'), -- len unknown + ( '-', 'X', '1', '0', '1', '1'), -- len unknown + ( '-', 'X', '-', '0', '-', 'X'), -- len unknown + ( '-', '1', '0', '0', '-', '0'), -- Latch transparent + ( '-', '1', '1', '0', '-', '1'), -- Latch transparent + ( '-', '1', '-', '0', '-', 'X'), -- Latch transparent, unknown D + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch/D-flip/flop with LEN transparent high and active high clock + --------------------------------------------------------------- + CONSTANT LATNDFF_tab : VitalStateTableType := ( + + ----INPUTS-----------|PREV-|-OUTPUT-- + -- Viol LEN CLK D | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', 'X', '0', '0', '0'), -- len and clk unknown + ( '-', 'X', 'X', '1', '1', '1'), -- len and clk unknown + ( '-', 'X', '-', '-', '-', 'X'), -- len unknown + ( '-', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '1', '-', '0', '-', '0'), -- Latch transparent + ( '-', '1', '-', '1', '-', '1'), -- Latch transparent + ( '-', '1', '-', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '0', 'X', '0', '0', '0'), -- clk unknown + ( '-', '0', 'X', '1', '1', '1'), -- clk unknown + ( '-', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '0', '/', '0', '-', '0'), -- ff active clock edge + ( '-', '0', '/', '1', '-', '1'), -- ff active clock edge + ( '-', '0', '/', '-', '-', 'X'), -- ff active clock edge unknown D + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch/D-flip/flop with LEN transparent high and active low clock + --------------------------------------------------------------- + CONSTANT LATNDFFN_tab : VitalStateTableType := ( + + ----INPUTS-----------|PREV-|-OUTPUT-- + -- Viol LEN CLK D | QI | Q' -- + ---------------------|-----|--------- + ( 'X', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', 'X', 'X', '0', '0', '0'), -- len and clk unknown + ( '-', 'X', 'X', '1', '1', '1'), -- len and clk unknown + ( '-', 'X', '-', '-', '-', 'X'), -- len unknown + ( '-', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '1', '-', '0', '-', '0'), -- Latch transparent + ( '-', '1', '-', '1', '-', '1'), -- Latch transparent + ( '-', '1', '-', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '0', 'X', '0', '0', '0'), -- clk unknown + ( '-', '0', 'X', '1', '1', '1'), -- clk unknown + ( '-', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '0', '\', '0', '-', '0'), -- ff active clock edge + ( '-', '0', '\', '1', '-', '1'), -- ff active clock edge + ( '-', '0', '\', '-', '-', 'X'), -- ff active clock edge unknown D + ( '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + + --------------------------------------------------------------- + -- Latch/D-flip/flop with LEN transparent high, active high clock + -- and active low clock enable + --------------------------------------------------------------- + CONSTANT LATNDFFCEN_tab : VitalStateTableType := ( + + ----INPUTS----------------|PREV-|-OUTPUT-- + -- Viol CEN LEN CLK D | QI | Q' -- + --------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', '-', 'X', 'X', '0', '0', '0'), -- len and clk unknown + ( '-', '-', 'X', 'X', '1', '1', '1'), -- len and clk unknown + ( '-', '-', 'X', '-', '-', '-', 'X'), -- len unknown + ( '-', '0', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', 'X', '0', '/', '0', '0', '0'), -- clken unknown + ( '-', 'X', '0', '/', '1', '1', '1'), -- clken unknown + ( '-', 'X', '0', '/', '-', '-', 'X'), -- clken unknown + ( '-', '-', '1', '-', '0', '-', '0'), -- Latch transparent + ( '-', '-', '1', '-', '1', '-', '1'), -- Latch transparent + ( '-', '-', '1', '-', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '0', '0', 'X', '0', '0', '0'), -- clk unknown + ( '-', '0', '0', 'X', '1', '1', '1'), -- clk unknown + ( '-', '0', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '0', '0', '/', '0', '-', '0'), -- ff active clock edge + ( '-', '0', '0', '/', '1', '-', '1'), -- ff active clock edge + ( '-', '0', '0', '/', '-', '-', 'X'), -- ff active clock edge unknown D + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + --------------------------------------------------------------- + -- Latch/D-flip/flop with LEN transparent high, active low clock + -- and active low clock enable + --------------------------------------------------------------- + CONSTANT LATNDFFNCEN_tab : VitalStateTableType := ( + + ----INPUTS----------------|PREV-|-OUTPUT-- + -- Viol CEN LEN CLK D | QI | Q' -- + --------------------------|-----|--------- + ( 'X', '-', '-', '-', '-', '-', 'X'), -- timing violation + ( '-', '-', 'X', 'X', '0', '0', '0'), -- len and clk unknown + ( '-', '-', 'X', 'X', '1', '1', '1'), -- len and clk unknown + ( '-', '-', 'X', '-', '-', '-', 'X'), -- len unknown + ( '-', '0', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', 'X', '0', '\', '0', '0', '0'), -- clken unknown + ( '-', 'X', '0', '\', '1', '1', '1'), -- clken unknown + ( '-', 'X', '0', '\', '-', '-', 'X'), -- clken unknown + ( '-', '-', '1', '-', '0', '-', '0'), -- Latch transparent + ( '-', '-', '1', '-', '1', '-', '1'), -- Latch transparent + ( '-', '-', '1', '-', '-', '-', 'X'), -- Latch transparent unknown D + ( '-', '0', '0', 'X', '0', '0', '0'), -- clk unknown + ( '-', '0', '0', 'X', '1', '1', '1'), -- clk unknown + ( '-', '0', '0', 'X', '-', '-', 'X'), -- clk unknown + ( '-', '0', '0', '\', '0', '-', '0'), -- ff active clock edge + ( '-', '0', '0', '\', '1', '-', '1'), -- ff active clock edge + ( '-', '0', '0', '\', '-', '-', 'X'), -- ff active clock edge unknown D + ( '-', '-', '-', '-', '-', '-', 'S') -- default + + ); -- end of VitalStateTableType definition + + + + --------------------------------------------------------------------------- + +END ff_package; diff --git a/vhdl/fmf/gen_utils.vhd b/vhdl/fmf/gen_utils.vhd new file mode 100644 index 0000000..e21a070 --- /dev/null +++ b/vhdl/fmf/gen_utils.vhd @@ -0,0 +1,186 @@ +-------------------------------------------------------------------------------- +-- File name: gen_utils.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 1996-2003 Free Model Foundry; http://www.FreeModelFoundry.com/ +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY: +-- +-- version: | author: | mod date: | changes made: +-- V1.0 R. Steele 96 SEP 26 Initial release +-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics +-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and +-- V1.3 R. Steele 97 APR 16 Added diff. receiver table +-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity +-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX +-- V1.6 R. Munden 03 FEB 07 Added To_UXLHZ +-- +-------------------------------------------------------------------------------- +LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL; + USE IEEE.VITAL_primitives.ALL; + USE IEEE.VITAL_timing.ALL; + +PACKAGE gen_utils IS + + ---------------------------------------------------------------------------- + -- Result map for Wired-and output values (open collector) + ---------------------------------------------------------------------------- + CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z'); + + ---------------------------------------------------------------------------- + -- Table for computing a single signal from a differential receiver input + -- pair. + ---------------------------------------------------------------------------- + CONSTANT diff_rec_tab : VitalStateTableType := ( + + ------INPUTS--|-PREV-|-OUTPUT---- + -- A ANeg | Aint | Aint' -- + --------------|------|----------- + ( 'X', '-', '-', 'X'), -- A unknown + ( '-', 'X', '-', 'X'), -- A unknown + ( '1', '-', 'X', '1'), -- Recover from 'X' + ( '0', '-', 'X', '0'), -- Recover from 'X' + ( '/', '0', '0', '1'), -- valid diff. rising edge + ( '1', '\', '0', '1'), -- valid diff. rising edge + ( '\', '1', '1', '0'), -- valid diff. falling edge + ( '0', '/', '1', '0'), -- valid diff. falling edge + ( '-', '-', '-', 'S') -- default + ); -- end of VitalStateTableType definition + + + ---------------------------------------------------------------------------- + -- Default Constants + ---------------------------------------------------------------------------- + CONSTANT UnitDelay : VitalDelayType := 1 ns; + CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns); + CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns); + CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns); + + CONSTANT DefaultInstancePath : STRING := "*"; + CONSTANT DefaultTimingChecks : BOOLEAN := FALSE; + CONSTANT DefaultTimingModel : STRING := "UNIT"; + CONSTANT DefaultXon : BOOLEAN := TRUE; + CONSTANT DefaultMsgOn : BOOLEAN := TRUE; + + -- Older VITAL generic being phased out + CONSTANT DefaultXGeneration : BOOLEAN := TRUE; + + ------------------------------------------------------------------- + -- Generate Parity for each 8-bit in 9th bit + ------------------------------------------------------------------- + FUNCTION GenParity + (Data : in std_logic_vector; -- Data + ODDEVEN : in std_logic; -- ODD (1) / EVEN(0) + SIZE : in POSITIVE) -- Bit Size + RETURN std_logic_vector; + + ------------------------------------------------------------------- + -- Check Parity for each 8-bit in 9th bit + ------------------------------------------------------------------- + FUNCTION CheckParity + (Data : in std_logic_vector; -- Data + ODDEVEN : in std_logic; -- ODD (1) / EVEN(0) + SIZE : in POSITIVE) -- Bit Size + RETURN std_logic; -- '0' - Parity Error + + ------------------------------------------------------------------- + -- strength strippers + ------------------------------------------------------------------- + FUNCTION To_UXLHZ ( s : std_ulogic ) RETURN std_ulogic; + +END gen_utils; + +PACKAGE BODY gen_utils IS + + function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is + -- pragma subpgm_id 403 + variable result: STD_LOGIC; + begin + result := '0'; + for i in ARG'range loop + result := result xor ARG(i); + end loop; + return result; + end; + ------------------------------------------------------------------- + -- Generate Parity for each 8-bit in 9th bit + ------------------------------------------------------------------- + FUNCTION GenParity + (Data : in std_logic_vector; -- Data + ODDEVEN : in std_logic; -- ODD (1) / EVEN(0) + SIZE : in POSITIVE) -- Bit Size + RETURN std_logic_vector + IS + VARIABLE I: NATURAL; + VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0); + BEGIN + I := 0; + WHILE (I < SIZE) LOOP + Result(I+7 DOWNTO I) := Data(I+7 downto I); + Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN; + I := I + 9; + END LOOP; + RETURN Result; + END GenParity; + + ------------------------------------------------------------------- + -- Check Parity for each 8-bit in 9th bit + ------------------------------------------------------------------- + FUNCTION CheckParity + (Data : in std_logic_vector; -- Data + ODDEVEN : in std_logic; -- ODD (1) / EVEN(0) + SIZE : in POSITIVE) -- Bit Size + RETURN std_logic -- '0' - Parity Error + IS + VARIABLE I: NATURAL; + VARIABLE Result: std_logic; + BEGIN + I := 0; Result := '1'; + WHILE (I < SIZE) LOOP + Result := Result AND + NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN); + I := I + 9; + END LOOP; + RETURN Result; + END CheckParity; + + ------------------------------------------------------------------- + -- conversion tables + ------------------------------------------------------------------- + TYPE logic_UXLHZ_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF + std_ulogic; + ---------------------------------------------------------- + -- table name : cvt_to_UXLHZ + -- + -- parameters : + -- in : std_ulogic -- some logic value + -- returns : std_ulogic -- weak state of logic value + -- purpose : to convert strong-strength to weak-strength only + -- + -- example : if (cvt_to_UXLHZ (input_signal) = '1' ) then ... + -- + ---------------------------------------------------------- + CONSTANT cvt_to_UXLHZ : logic_UXLHZ_table := ( + 'U', -- 'U' + 'X', -- 'X' + 'L', -- '0' + 'H', -- '1' + 'Z', -- 'Z' + 'W', -- 'W' + 'L', -- 'L' + 'H', -- 'H' + '-' -- '-' + ); + + ------------------------------------------------------------------- + -- strength strippers + ------------------------------------------------------------------- + FUNCTION To_UXLHZ ( s : std_ulogic ) RETURN std_ulogic IS + BEGIN + RETURN (cvt_to_UXLHZ(s)); + END; + +END gen_utils; diff --git a/vhdl/fmf/memory.vhd b/vhdl/fmf/memory.vhd new file mode 100644 index 0000000..4b19e85 --- /dev/null +++ b/vhdl/fmf/memory.vhd @@ -0,0 +1,714 @@ +-------------------------------------------------------------------------------- +-- File Name: memory.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 2001-2005 Free Model Foundry; http://www.FreeModelFoundry.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY: +-- +-- version: | author: | mod date: | changes made: +-- V0.1 R. Munden 01 NOV 01 Initial beta release +-- V0.2 R. Munden 01 NOV 24 refined Table_generic_sram +-- V0.3 R. Munden 02 MAR 23 added Table_2_cntrl_sram +-- V0.4 A. Savic 05 JUN 15 extended for memory management routines +-- extended for routine comments +-- V0.5 R. Munden 06 JUN 04 corrected memory management routines +-- per Sergey Sulyutin +-- +-------------------------------------------------------------------------------- +LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; + USE IEEE.VITAL_primitives.ALL; + USE IEEE.VITAL_timing.ALL; + USE IEEE.vital_memory.ALL; + +-------------------------------------------------------------------------------- +PACKAGE memory IS + + ---------------------------------------------------------------------------- + -- Asynchronous SRAM with low chip enable and write enable + ---------------------------------------------------------------------------- + CONSTANT Table_2_cntrl_sram : VitalMemoryTableType := ( + + -- ---------------------------------------------------------- + -- CEN, WEN, Addr, DI, act, DO + -- ---------------------------------------------------------- + -- Address initiated read + ( '0', '1', 'G', '-', 's', 'm' ), + ( '0', '1', 'U', '-', 's', 'l' ), + + -- CEN initiated read + ( 'N', '1', 'g', '-', 's', 'm' ), + ( 'N', '1', 'u', '-', 's', 'l' ), + + -- Write Enable initiated Write + ( '0', 'P', 'g', '-', 'w', 'm' ), + ( '0', 'N', '-', '-', 's', 'Z' ), + + -- CEN initiated Write + ( 'P', '0', 'g', '-', 'w', 'Z' ), + ( 'N', '0', '-', '-', 's', 'Z' ), + + -- Address change during write + ( '0', '0', '*', '-', 'c', 'Z' ), + ( '0', 'X', '*', '-', 'c', 'Z' ), + + -- if WEN is X + ( '0', 'X', 'g', '*', 'e', 'e' ), + ( '0', 'X', 'u', '*', 'c', 'l' ), + + -- CEN is unasserted + ( 'X', '0', 'G', '-', 'e', 'Z' ), + ( 'X', '0', 'u', '-', 'c', 'Z' ), + ( 'X', '1', '-', '-', 's', 'l' ), + ( '1', '-', '-', '-', 's', 'Z' ) + + ); -- end of VitalMemoryTableType definition + + ---------------------------------------------------------------------------- + -- Asynchronous SRAM with high and low chip enables and output enable + ---------------------------------------------------------------------------- + CONSTANT Table_generic_sram : VitalMemoryTableType := ( + + -- ---------------------------------------------------------- + -- CE, CEN, OEN, WEN, Addr, DI, act, DO + -- ---------------------------------------------------------- + -- Address initiated read + ( '1', '0', '0', '1', 'G', '-', 's', 'm' ), + ( '1', '0', '0', '1', 'U', '-', 's', 'l' ), + + -- Output Enable initiated read + ( '1', '0', 'N', '1', 'g', '-', 's', 'm' ), + ( '1', '0', 'N', '1', 'u', '-', 's', 'l' ), + ( '1', '0', '0', '1', 'g', '-', 's', 'm' ), + + -- CE initiated read + ( 'P', '0', '0', '1', 'g', '-', 's', 'm' ), + ( 'P', '0', '0', '1', 'u', '-', 's', 'l' ), + + -- CEN initiated read + ( '1', 'N', '0', '1', 'g', '-', 's', 'm' ), + ( '1', 'N', '0', '1', 'u', '-', 's', 'l' ), + + -- Write Enable Implicit Read + ( '1', '0', '0', 'P', '-', '-', 's', 'M' ), + + -- Write Enable initiated Write + ( '1', '0', '1', 'N', 'g', '-', 'w', 'S' ), + ( '1', '0', '1', 'N', 'u', '-', 'c', 'S' ), + + -- CE initiated Write + ( 'P', '0', '1', '0', 'g', '-', 'w', 'S' ), + ( 'P', '0', '1', '0', 'u', '-', 'c', 'S' ), + + -- CEN initiated Write + ( '1', 'N', '1', '0', 'g', '-', 'w', 'Z' ), + ( '1', 'N', '1', '0', 'u', '-', 'c', 'Z' ), + + -- Address change during write + ( '1', '0', '1', '0', '*', '-', 'c', 'Z' ), + ( '1', '0', '1', 'X', '*', '-', 'c', 'Z' ), + + -- data initiated Write + ( '1', '0', '1', '0', 'g', '*', 'w', 'Z' ), + ( '1', '0', '1', '0', 'u', '-', 'c', 'Z' ), + ( '1', '0', '-', 'X', 'g', '*', 'e', 'e' ), + ( '1', '0', '-', 'X', 'u', '*', 'c', 'S' ), + + -- if WEN is X + ( '1', '0', '1', 'r', 'g', '*', 'e', 'e' ), + ( '1', '0', '1', 'r', 'u', '*', 'c', 'l' ), + ( '1', '0', '-', 'r', 'g', '*', 'e', 'S' ), + ( '1', '0', '-', 'r', 'u', '*', 'c', 'S' ), + ( '1', '0', '1', 'f', 'g', '*', 'e', 'e' ), + ( '1', '0', '1', 'f', 'u', '*', 'c', 'l' ), + ( '1', '0', '-', 'f', 'g', '*', 'e', 'S' ), + ( '1', '0', '-', 'f', 'u', '*', 'c', 'S' ), + + -- OEN is unasserted + ( '-', '-', '1', '-', '-', '-', 's', 'Z' ), + ( '1', '0', 'P', '-', '-', '-', 's', 'Z' ), + ( '1', '0', 'r', '-', '-', '-', 's', 'l' ), + ( '1', '0', 'f', '-', '-', '-', 's', 'l' ), + ( '1', '0', '1', '-', '-', '-', 's', 'Z' ), + + -- CE is unasserted + ( '0', '-', '-', '-', '-', '-', 's', 'Z' ), + ( 'N', '0', '-', '-', '-', '-', 's', 'Z' ), + ( 'f', '0', '-', '-', '-', '-', 's', 'l' ), + ( 'r', '0', '-', '-', '-', '-', 's', 'l' ), + ( '0', '0', '-', '-', '-', '-', 's', 'Z' ), + + -- CEN is unasserted + ( '-', '1', '-', '-', '-', '-', 's', 'Z' ), + ( '1', 'P', '-', '-', '-', '-', 's', 'Z' ), + ( '1', 'r', '-', '-', '-', '-', 's', 'l' ), + ( '1', 'f', '-', '-', '-', '-', 's', 'l' ), + ( '1', '1', '-', '-', '-', '-', 's', 'Z' ) + + ); -- end of VitalMemoryTableType definition + + -- ------------------------------------------------------------------------- + -- Memory data initial value. + -- Default value may be overridden by conigure_memory procedure + -- ------------------------------------------------------------------------- + SHARED VARIABLE max_data : NATURAL := 16#FF#; + + -- ------------------------------------------------------------------------- + -- Data types required to implement link list structure + -- ------------------------------------------------------------------------- + TYPE mem_data_t; + TYPE mem_data_pointer_t IS ACCESS mem_data_t; + TYPE mem_data_t IS RECORD + key_address : INTEGER; + val_data : INTEGER; + successor : mem_data_pointer_t; + END RECORD; + + -- ------------------------------------------------------------------------- + -- Array of linked lists. + -- Support memory region partitioning for faster access. + -- ------------------------------------------------------------------------- + TYPE mem_data_pointer_array_t IS + ARRAY(NATURAL RANGE <>) OF mem_data_pointer_t; + + -- ------------------------------------------------------------------------- + -- + -- Function Name: configure_memory + -- + -- Description: Override mechanism default parameter values. + -- configure_memory routine is used to override default + -- memory initialization package parameter. + -- + -- The value of max_data parameter value refers to memory + -- initial data value, memory data width dependent. + -- + -- Arguments: + -- + -- IN Type Description + -- max_data_c integer Memory data initial value. + -- The default is set to FFh. + -- + -- INOUT + -- none + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE configure_memory( + max_data_c : IN INTEGER); + + -- ------------------------------------------------------------------------- + -- + -- Function Name: corrupt_mem + -- + -- Description: corrupt_mem is used to perform memory data CORRUPT + -- operation above memory block or memory page region. + -- + -- Routine is built-in addressing performance parameters. + -- Routine performs N successive corrupt operations. + -- For N successive corrupt operations instead of : + -- N x find + N x corrupt --> + -- corrupt_mem provides the posiibility of : + -- 1 x find + N x iterate + N x corrupt + -- Reducing the number of find element calls, operation + -- execution time is significantly affected. + -- + -- [address_low, adress_high] must belong to the same + -- memory parition, handled by a single list. + -- + -- Arguments: + -- + -- IN Type Description + -- address_low integer Starting address of the memory + -- region to be corrupted. + -- address_high integer The last address of the memory + -- region to be corrupted. + -- + -- INOUT + -- linked_list mem_data_pointer_t Linked list holding memory region + -- to be corrupted. + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE corrupt_mem( + address_low : IN INTEGER; + address_high : IN INTEGER; + linked_list : INOUT mem_data_pointer_t); + + -- ------------------------------------------------------------------------- + -- + -- Function Name: erase_mem + -- + -- Description: erase_mem is used to perform memory data ERASE + -- operation above memory block or memory page region. + -- + -- Routine is built-in addressing performance parameters. + -- Routine performs N successive erase operations. + -- For N successive erase operations instead of : + -- N x find + N x erase --> + -- erase_mem provides the posiibility of : + -- 1 x find + N x iterate + N x erase + -- Reducing the number of find element calls, operation + -- execution time is significantly affected. + -- + -- [address_low, adress_high] must belong to the same + -- memory parition, handled by a single list. + -- + -- Arguments: + -- + -- IN Type Description + -- address_low integer Starting address of the memory + -- region to be erased. + -- address_high integer The last address of the memory + -- region to be erased. + -- + -- INOUT + -- linked_list mem_data_pointer_t Linked list holding memory region + -- to be erased. + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE erase_mem( + address_low : IN INTEGER; + address_high : IN INTEGER; + linked_list : INOUT mem_data_pointer_t); + + -- ------------------------------------------------------------------------ + -- + -- Function Name: read_mem + -- + -- Description: Memory READ operation performed above dynamically + -- allocated space. + -- + -- Iterates through a linked list data structure holding + -- memory data. Performs a search for an address match. + -- + -- If matched successfully, data kept by a linked list + -- element will be returned. + -- + -- In case no match occurred, no allocation has been + -- performed for the search address. + -- Memory data is never written, set to initial value. + -- Initial data value returned. + -- + -- Arguments: + -- + -- IN Type Description + -- address integer Data address to be read. + -- + -- INOUT + -- linked_list mem_data_pointer_t Linked list holding memory region + -- to be read. Depends on DUT + -- specific partition scheme. + -- data integer Read operation result. + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE read_mem( + linked_list : INOUT mem_data_pointer_t; + data : INOUT INTEGER; + address : IN INTEGER); + + -- ------------------------------------------------------------------------- + -- + -- Function Name: write_mem + -- + -- Description: Memory WRITE operation performed above dynamically + -- allocated space. + -- + -- Iterates through a linked list data structure holding + -- memory data. Performs a search for an address match. + -- + -- If matched successfully, data kept by a linked list + -- element will be aligned with data argument value. + -- + -- In case no match occurred, no allocation has been + -- performed for the search address. + -- Memory space for a new element is allocated, linked + -- into a list and set to data argument value. + -- + -- If data argument value is recognized as initial, + -- memory space will be de-allocated for the addressed + -- location. + -- + -- Arguments: + -- + -- IN Type Description + -- address integer Address to be written. + -- data integer Data to be written. + -- + -- INOUT + -- linked_list mem_data_pointer_t Linked list holding memory region + -- to be written. Depends on DUT + -- specific partition scheme. + -- + -- OUT + -- none + -- + -- Returns + -- none + -- + -- ------------------------------------------------------------------------- + PROCEDURE write_mem( + linked_list : INOUT mem_data_pointer_t; + address : IN INTEGER; + data : IN INTEGER); + +END PACKAGE memory; + +PACKAGE BODY memory IS + -- ------------------------------------------------------------------------- + -- Override mechanism provided for default parameter values + -- ------------------------------------------------------------------------- + PROCEDURE configure_memory( + max_data_c : IN INTEGER) IS + BEGIN + max_data := max_data_c; + END PROCEDURE configure_memory; + + -- ------------------------------------------------------------------------- + -- Create linked listed + -- ------------------------------------------------------------------------- + PROCEDURE create_list( + key_address : IN INTEGER; + val_data : IN INTEGER; + root : INOUT mem_data_pointer_t) IS + BEGIN + root := NEW mem_data_t; + root.successor := NULL; + root.key_address := key_address; + root.val_data := val_data; + END PROCEDURE create_list; + + -- ------------------------------------------------------------------------- + -- Iterate through linked listed comapring key values + -- Stop when key value greater or equal + -- ------------------------------------------------------------------------- + PROCEDURE position_list( + key_address : IN INTEGER; + root : INOUT mem_data_pointer_t; + found : INOUT mem_data_pointer_t; + prev : INOUT mem_data_pointer_t) IS + BEGIN + found := root; + prev := NULL; + -- Changed thanks to Sergey Selyutin + -- WHILE ((found /= NULL) AND (found.key_address < key_address)) LOOP + WHILE found /= NULL LOOP + IF (found.key_address >= key_address) THEN + EXIT; + END IF; + prev := found; + found := found.successor; + END LOOP; + END PROCEDURE position_list; + + -- ------------------------------------------------------------------------- + -- Add new element to a linked list + -- ------------------------------------------------------------------------- + PROCEDURE insert_list( + key_address : IN INTEGER; + val_data : IN INTEGER; + root : INOUT mem_data_pointer_t) IS + + VARIABLE new_element : mem_data_pointer_t; + VARIABLE found : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + BEGIN + position_list(key_address, root, found, prev); + + -- Insert at list tail + IF (found = NULL) THEN + prev.successor := NEW mem_data_t; + prev.successor.key_address := key_address; + prev.successor.val_data := val_data; + prev.successor.successor := NULL; + ELSE + -- Element exists, update memory data value + IF (found.key_address = key_address) THEN + found.val_data := val_data; + ELSE + -- No element found, allocate and link + new_element := NEW mem_data_t; + new_element.key_address := key_address; + new_element.val_data := val_data; + new_element.successor := found; + -- Possible root position + IF (prev /= NULL) THEN + prev.successor := new_element; + ELSE + root := new_element; + END IF; + END IF; + END IF; + END PROCEDURE insert_list; + + -- ------------------------------------------------------------------------- + -- Remove element from a linked list + -- ------------------------------------------------------------------------- + PROCEDURE remove_list( + key_address : IN INTEGER; + root : INOUT mem_data_pointer_t) IS + + VARIABLE found : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + BEGIN + position_list(key_address, root, found, prev); + IF (found /= NULL) THEN + -- Key value match + IF (found.key_address = key_address) THEN + -- Handle root position removal + IF (prev /= NULL) THEN + prev.successor := found.successor; + ELSE + root := found.successor; + END IF; + DEALLOCATE(found); + END IF; + END IF; + END PROCEDURE remove_list; + + -- ------------------------------------------------------------------------- + -- Remove range of elements from a linked list + -- Higher performance than one-by-one removal + -- ------------------------------------------------------------------------- + PROCEDURE remove_list_range( + address_low : IN INTEGER; + address_high : IN INTEGER; + root : INOUT mem_data_pointer_t) IS + + VARIABLE iter : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + VARIABLE link_element : mem_data_pointer_t; + BEGIN + iter := root; + prev := NULL; + -- Find first linked list element belonging to + -- a specified address range [address_low, address_high] + -- Changed thanks to Sergey Sulyutin + -- WHILE ((iter /= NULL) AND NOT ( + -- (iter.key_address >= address_low) AND + -- (iter.key_address <= address_high))) LOOP + WHILE iter /= NULL LOOP + IF ((iter.key_address >= address_low) AND + (iter.key_address <= address_high)) THEN + EXIT; + END IF; + prev := iter; + iter := iter.successor; + END LOOP; + -- Continue until address_high reached + -- Deallocate linked list elements pointed by iterator + IF (iter /= NULL) THEN + -- Changed thanks to Sergey Sulyutin + -- WHILE ((iter /= NULL) AND + -- (iter.key_address >= address_low) AND + -- (iter.key_address <= address_high)) LOOP + WHILE iter /= NULL LOOP + IF ((iter.key_address < address_low) OR + (iter.key_address > address_high)) THEN + EXIT; + END IF; + link_element := iter.successor; + DEALLOCATE(iter); + iter := link_element; + END LOOP; + -- Handle possible root value change + IF prev /= NULL THEN + prev.successor := link_element; + ELSE + root := link_element; + END IF; + END IF; + END PROCEDURE remove_list_range; + + -- ------------------------------------------------------------------------- + -- Create side linked list modelling corrupted memory area + -- ------------------------------------------------------------------------- + PROCEDURE create_list_range( + address_low : IN INTEGER; + address_high : IN INTEGER; + root : INOUT mem_data_pointer_t; + last : INOUT mem_data_pointer_t) IS + + VARIABLE new_element : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + BEGIN + create_list(address_low, -1, root); + prev := root; + -- Linked list representing memory region : + -- [address_low, address_high], memory data value corrupted + -- Heightens corrupt and erase operation performance + FOR I IN (address_low + 1) TO address_high LOOP + new_element := NEW mem_data_t; + new_element.key_address := I; + new_element.val_data := -1; + prev.successor := new_element; + prev := new_element; + END LOOP; + prev.successor := NULL; + last := prev; + END PROCEDURE create_list_range; + + -- ------------------------------------------------------------------------- + -- Merge corrupted with memory area + -- ------------------------------------------------------------------------- + PROCEDURE insert_list_range( + root_dst : INOUT mem_data_pointer_t; + root_src : INOUT mem_data_pointer_t; + root_src_last : INOUT mem_data_pointer_t) IS + + VARIABLE key : INTEGER; + VARIABLE found : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + BEGIN + IF (root_dst /= NULL) THEN + key := root_src.key_address; + -- Insert side created corrupted memory region + -- into corresponding linked list + position_list(key, root_dst, found, prev); + IF (found = NULL) THEN + prev.successor := root_src; + ELSE + root_src_last.successor := found; + IF (prev /= NULL) THEN + prev.successor := root_src; + ELSE + root_dst := root_src; + END IF; + END IF; + ELSE + root_dst := root_src; + END IF; + END PROCEDURE insert_list_range; + + -- ------------------------------------------------------------------------- + -- Address range to be corrupted + -- ------------------------------------------------------------------------- + PROCEDURE corrupt_mem( + address_low : IN INTEGER; + address_high : IN INTEGER; + linked_list : INOUT mem_data_pointer_t) IS + + VARIABLE sub_linked_list : mem_data_pointer_t; + VARIABLE sub_linked_list_last : mem_data_pointer_t; + BEGIN + sub_linked_list := NULL; + sub_linked_list_last := NULL; + IF (linked_list /= NULL) THEN + remove_list_range( + address_low, + address_high, + linked_list + ); + END IF; + create_list_range( + address_low, + address_high, + sub_linked_list, + sub_linked_list_last + ); + insert_list_range( + linked_list, + sub_linked_list, + sub_linked_list_last + ); + END PROCEDURE corrupt_mem; + + -- ------------------------------------------------------------------------- + -- Address range to be erased + -- ------------------------------------------------------------------------- + PROCEDURE erase_mem( + address_low : IN INTEGER; + address_high : IN INTEGER; + linked_list : INOUT mem_data_pointer_t) IS + + BEGIN + remove_list_range( + address_low, + address_high, + linked_list + ); + END PROCEDURE erase_mem; + + -- ------------------------------------------------------------------------- + -- Memory READ operation performed above dynamically allocated space + -- ------------------------------------------------------------------------- + PROCEDURE read_mem( + linked_list : INOUT mem_data_pointer_t; + data : INOUT INTEGER; + address : IN INTEGER) IS + + VARIABLE found : mem_data_pointer_t; + VARIABLE prev : mem_data_pointer_t; + VARIABLE mem_data : INTEGER; + BEGIN + IF (linked_list = NULL) THEN + -- Not allocated, not written, initial value + mem_data := max_data ; + ELSE + position_list(address, linked_list, found, prev); + IF (found /= NULL) THEN + IF found.key_address = address THEN + -- Allocated, val_data stored + mem_data := found.val_data; + ELSE + -- Not allocated, not written, initial value + mem_data := max_data ; + END IF; + ELSE + -- Not allocated, not written, initial value + mem_data := max_data ; + END IF; + END IF; + data := mem_data; + END PROCEDURE read_mem; + + -- ------------------------------------------------------------------------- + -- Memory WRITE operation performed above dynamically allocated space + -- ------------------------------------------------------------------------- + PROCEDURE write_mem( + linked_list : INOUT mem_data_pointer_t; + address : IN INTEGER; + data : IN INTEGER) IS + + BEGIN + IF (data /= max_data ) THEN + -- Handle possible root value update + IF (linked_list /= NULL) THEN + insert_list(address, data, linked_list); + ELSE + create_list(address, data, linked_list); + END IF; + ELSE + -- Deallocate if initial value written + -- No linked list, NOP, initial value implicit + IF (linked_list /= NULL) THEN + remove_list(address, linked_list); + END IF; + END IF; + END PROCEDURE write_mem; + +END PACKAGE BODY memory; diff --git a/vhdl/fmf/state_tab_package.vhd b/vhdl/fmf/state_tab_package.vhd new file mode 100644 index 0000000..8058420 --- /dev/null +++ b/vhdl/fmf/state_tab_package.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- File name : state_tab_package.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 1996 Free Model Foundry http://www.FreeModelFoundry.com/ +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY : +-- +-- version | author | mod date | changes made +-- V2.0 rev3 23 MAR 96 Added copyright, synch reset tables +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.Std_Logic_1164.ALL; +USE IEEE.VITAL_primitives.all; +USE IEEE.VITAL_timing.all; + +PACKAGE state_tab_package IS + + --************************************************************ + + ---------------------------------------------------------------------------- + -- 2 state table with active-high Reset + ---------------------------------------------------------------------------- + CONSTANT st2R_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV|-OUTPUTS-- + -- Viol CLK R | Sv0 | Sv0' -- + ----------------|-----|---------- + + ( 'X', '-', '-', '-', 'X'), + ( '-', '-', 'X', '-', 'X'), + ( '-', '-', '1', '-', '0'), + ( '-', 'X', '0', '-', 'X'), + ( '-', '/', '0', '0', '1'), + ( '-', '/', '0', '1', '0'), + ( '-', '-', '-', '-', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + -- 2 state table with active-high synchronous Reset + ---------------------------------------------------------------------------- + CONSTANT st2Rs_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV|-OUTPUTS-- + -- Viol CLK R | Sv0 | Sv0' -- + ----------------|-----|---------- + + ( 'X', '-', '-', '-', 'X'), + ( '-', 'X', '-', '-', 'X'), + ( '-', '/', 'X', '-', 'X'), + ( '-', '/', '1', '-', '0'), + ( '-', '/', '0', '0', '1'), + ( '-', '/', '0', '1', '0'), + ( '-', '-', '-', '-', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + -- 4 state table with active-high Reset + ---------------------------------------------------------------------------- + CONSTANT st4R_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV----|--OUTPUTS------ + -- Viol CLK R | Sv1 Sv0 | Sv1' Sv0' -- + ----------------|---------|--------------- + + ( 'X', '-', '-', '-', '-', 'X', 'X'), + ( '-', '-', 'X', '-', '-', 'X', 'X'), + ( '-', '-', '1', '-', '-', '0', '0'), + ( '-', 'X', '0', '-', '-', 'X', 'X'), + ( '-', '/', '0', '0', '0', '0', '1'), + ( '-', '/', '0', '0', '1', '1', '0'), + ( '-', '/', '0', '1', '0', '1', '1'), + ( '-', '/', '0', '1', '1', '0', '0'), + ( '-', '-', '-', '-', '-', 'S', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + -- 4 state table with active-high synchronous Reset + ---------------------------------------------------------------------------- + CONSTANT st4Rs_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV----|--OUTPUTS------ + -- Viol CLK R | Sv1 Sv0 | Sv1' Sv0' -- + ----------------|---------|--------------- + + ( 'X', '-', '-', '-', '-', 'X', 'X'), + ( '-', 'X', '-', '-', '-', 'X', 'X'), + ( '-', '/', 'X', '-', '-', 'X', 'X'), + ( '-', '/', '1', '-', '-', '0', '0'), + ( '-', '/', '0', '0', '0', '0', '1'), + ( '-', '/', '0', '0', '1', '1', '0'), + ( '-', '/', '0', '1', '0', '1', '1'), + ( '-', '/', '0', '1', '1', '0', '0'), + ( '-', '-', '-', '-', '-', 'S', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + -- 8 state table with active-high Reset + ---------------------------------------------------------------------------- + CONSTANT st8R_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV--------|--OUTPUTS---------- + -- Viol CLK R | Sv2 Sv1 Sv0 | Sv2' Sv1' Sv0' -- + ----------------|-------------|------------------- + + ( 'X', '-', '-', '-', '-', '-', 'X', 'X', 'X'), + ( '-', '-', 'X', '-', '-', '-', 'X', 'X', 'X'), + ( '-', '-', '1', '-', '-', '-', '0', '0', '0'), + ( '-', 'X', '0', '-', '-', '-', 'X', 'X', 'X'), + ( '-', '/', '0', '0', '0', '0', '0', '0', '1'), + ( '-', '/', '0', '0', '0', '1', '0', '1', '0'), + ( '-', '/', '0', '0', '1', '0', '0', '1', '1'), + ( '-', '/', '0', '0', '1', '1', '1', '0', '0'), + ( '-', '/', '0', '1', '0', '0', '1', '0', '1'), + ( '-', '/', '0', '1', '0', '1', '1', '1', '0'), + ( '-', '/', '0', '1', '1', '0', '1', '1', '1'), + ( '-', '/', '0', '1', '1', '1', '0', '0', '0'), + ( '-', '-', '-', '-', '-', '-', 'S', 'S', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + -- 8 state table with active-high synchronous Reset + ---------------------------------------------------------------------------- + CONSTANT st8Rs_tab : VitalStateTableType := ( + + -----INPUTS-----|-PREV--------|--OUTPUTS---------- + -- Viol CLK R | Sv2 Sv1 Sv0 | Sv2' Sv1' Sv0' -- + ----------------|-------------|------------------- + + ( 'X', '-', '-', '-', '-', '-', 'X', 'X', 'X'), + ( '-', 'X', '-', '-', '-', '-', 'X', 'X', 'X'), + ( '-', '/', 'X', '-', '-', '-', 'X', 'X', 'X'), + ( '-', '/', '1', '-', '-', '-', '0', '0', '0'), + ( '-', '/', '0', '0', '0', '0', '0', '0', '1'), + ( '-', '/', '0', '0', '0', '1', '0', '1', '0'), + ( '-', '/', '0', '0', '1', '0', '0', '1', '1'), + ( '-', '/', '0', '0', '1', '1', '1', '0', '0'), + ( '-', '/', '0', '1', '0', '0', '1', '0', '1'), + ( '-', '/', '0', '1', '0', '1', '1', '1', '0'), + ( '-', '/', '0', '1', '1', '0', '1', '1', '1'), + ( '-', '/', '0', '1', '1', '1', '0', '0', '0'), + ( '-', '-', '-', '-', '-', '-', 'S', 'S', 'S') + + ); -- end of VitalStateTableType definition + + ---------------------------------------------------------------------------- + +END state_tab_package; diff --git a/vhdl/fmf/std165.vhd b/vhdl/fmf/std165.vhd new file mode 100644 index 0000000..d45cb31 --- /dev/null +++ b/vhdl/fmf/std165.vhd @@ -0,0 +1,576 @@ +-------------------------------------------------------------------------------- +-- File Name: std165.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY: +-- +-- version: | author: | mod date: | changes made: +-- V1.0 R. Munden 01 Jan 06 Initial release +-- V1.1 R. Munden 01 Sep 02 Corrected path delays +-- +-------------------------------------------------------------------------------- +-- PART DESCRIPTION: +-- +-- Library: STND +-- Technology: 54/7400 +-- Part: STD165 +-- +-- Description: 8-Bit Parallel-Load Shift Register +-------------------------------------------------------------------------------- + +LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; + USE IEEE.VITAL_timing.ALL; + USE IEEE.VITAL_primitives.ALL; +LIBRARY FMF; USE FMF.gen_utils.ALL; + USE FMF.ff_package.ALL; + +-------------------------------------------------------------------------------- +-- ENTITY DECLARATION +-------------------------------------------------------------------------------- +ENTITY std165 IS + GENERIC ( + -- tipd delays: interconnect path delays + tipd_DH : VitalDelayType01 := VitalZeroDelay01; + tipd_DG : VitalDelayType01 := VitalZeroDelay01; + tipd_DF : VitalDelayType01 := VitalZeroDelay01; + tipd_DE : VitalDelayType01 := VitalZeroDelay01; + tipd_DD : VitalDelayType01 := VitalZeroDelay01; + tipd_DC : VitalDelayType01 := VitalZeroDelay01; + tipd_DB : VitalDelayType01 := VitalZeroDelay01; + tipd_DA : VitalDelayType01 := VitalZeroDelay01; + tipd_SH : VitalDelayType01 := VitalZeroDelay01; + tipd_SER : VitalDelayType01 := VitalZeroDelay01; + tipd_CLK : VitalDelayType01 := VitalZeroDelay01; + tipd_CLKINH : VitalDelayType01 := VitalZeroDelay01; + -- tpd delays + tpd_CLK_Q : VitalDelayType01 := UnitDelay01; + tpd_SH_Q : VitalDelayType01 := UnitDelay01; + tpd_DH_Q : VitalDelayType01 := UnitDelay01; + tpd_DH_QNeg : VitalDelayType01 := UnitDelay01; + -- tsetup values: setup times + tsetup_DA_SH : VitalDelayType := UnitDelay; + tsetup_SH_CLK : VitalDelayType := UnitDelay; + tsetup_SER_CLK : VitalDelayType := UnitDelay; + tsetup_CLKINH_CLK_negedge : VitalDelayType := UnitDelay; + tsetup_CLKINH_CLK_posedge : VitalDelayType := UnitDelay; + -- thold values: hold times + thold_SER_CLK : VitalDelayType := UnitDelay; + thold_DA_SH : VitalDelayType := UnitDelay; + -- tpw values: pulse widths + tpw_CLK_posedge : VitalDelayType := UnitDelay; + tpw_SH_negedge : VitalDelayType := UnitDelay; + -- tperiod_min: minimum clock period = 1/max freq + tperiod_CLK_posedge : VitalDelayType := UnitDelay; + -- generic control parameters + InstancePath : STRING := DefaultInstancePath; + TimingChecksOn : BOOLEAN := DefaultTimingChecks; + MsgOn : BOOLEAN := DefaultMsgOn; + XOn : BOOLEAN := DefaultXon; + -- For FMF SDF technology file usage + TimingModel : STRING := DefaultTimingModel + ); + PORT ( + Q : OUT std_ulogic := 'U'; + QNeg : OUT std_ulogic := 'U'; + DH : IN std_ulogic := 'U'; + DG : IN std_ulogic := 'U'; + DF : IN std_ulogic := 'U'; + DE : IN std_ulogic := 'U'; + DD : IN std_ulogic := 'U'; + DC : IN std_ulogic := 'U'; + DB : IN std_ulogic := 'U'; + DA : IN std_ulogic := 'U'; + SER : IN std_ulogic := 'U'; + SH : IN std_ulogic := 'U'; + CLK : IN std_ulogic := 'U'; + CLKINH : IN std_ulogic := 'U' + ); + ATTRIBUTE VITAL_LEVEL0 of std165 : ENTITY IS TRUE; +END std165; + +-------------------------------------------------------------------------------- +-- ARCHITECTURE DECLARATION +-------------------------------------------------------------------------------- +ARCHITECTURE vhdl_behavioral of std165 IS + ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; + + CONSTANT partID : STRING := "std165"; + + SIGNAL DH_ipd : std_ulogic := 'U'; + SIGNAL DG_ipd : std_ulogic := 'U'; + SIGNAL DF_ipd : std_ulogic := 'U'; + SIGNAL DE_ipd : std_ulogic := 'U'; + SIGNAL DD_ipd : std_ulogic := 'U'; + SIGNAL DC_ipd : std_ulogic := 'U'; + SIGNAL DB_ipd : std_ulogic := 'U'; + SIGNAL DA_ipd : std_ulogic := 'U'; + SIGNAL SER_ipd : std_ulogic := 'U'; + SIGNAL CLK_ipd : std_ulogic := 'U'; + SIGNAL CLKINH_ipd : std_ulogic := 'U'; + SIGNAL SH_ipd : std_ulogic := 'U'; + +BEGIN + + ---------------------------------------------------------------------------- + -- Wire Delays + ---------------------------------------------------------------------------- + WireDelay : BLOCK + BEGIN + + w_2 : VitalWireDelay (DH_ipd, DH, tipd_DH); + w_3 : VitalWireDelay (DG_ipd, DG, tipd_DG); + w_4 : VitalWireDelay (DF_ipd, DF, tipd_DF); + w_5 : VitalWireDelay (DE_ipd, DE, tipd_DE); + w_6 : VitalWireDelay (DD_ipd, DD, tipd_DD); + w_7 : VitalWireDelay (DC_ipd, DC, tipd_DC); + w_8 : VitalWireDelay (DB_ipd, DB, tipd_DB); + w_9 : VitalWireDelay (DA_ipd, DA, tipd_DA); + w_10 : VitalWireDelay (SER_ipd, SER, tipd_SER); + w_11 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); + w_12 : VitalWireDelay (CLKINH_ipd, CLKINH, tipd_CLKINH); + w_13 : VitalWireDelay (SH_ipd, SH, tipd_SH); + + END BLOCK; + + ---------------------------------------------------------------------------- + -- Behavior Process + ---------------------------------------------------------------------------- + VitalBehavior : PROCESS (CLK_ipd, CLKINH_ipd, DA_ipd, DB_ipd, DC_ipd, DD_ipd, + DE_ipd, DF_ipd, DG_ipd, DH_ipd, SH_ipd, SER_ipd) + + -- Timing Check Variables + VARIABLE Tviol_DH_SH : X01 := '0'; + VARIABLE TD_DH_SH : VitalTimingDataType; + + VARIABLE Tviol_DG_SH : X01 := '0'; + VARIABLE TD_DG_SH : VitalTimingDataType; + + VARIABLE Tviol_DF_SH : X01 := '0'; + VARIABLE TD_DF_SH : VitalTimingDataType; + + VARIABLE Tviol_DE_SH : X01 := '0'; + VARIABLE TD_DE_SH : VitalTimingDataType; + + VARIABLE Tviol_DD_SH : X01 := '0'; + VARIABLE TD_DD_SH : VitalTimingDataType; + + VARIABLE Tviol_DC_SH : X01 := '0'; + VARIABLE TD_DC_SH : VitalTimingDataType; + + VARIABLE Tviol_DB_SH : X01 := '0'; + VARIABLE TD_DB_SH : VitalTimingDataType; + + VARIABLE Tviol_DA_SH : X01 := '0'; + VARIABLE TD_DA_SH : VitalTimingDataType; + + VARIABLE Tviol_SH_CLK : X01 := '0'; + VARIABLE TD_SH_CLK : VitalTimingDataType; + + VARIABLE Tviol_SER_CLK : X01 := '0'; + VARIABLE TD_SER_CLK : VitalTimingDataType; + + VARIABLE Tviol_CLKINH_CLK : X01 := '0'; + VARIABLE TD_CLKINH_CLK : VitalTimingDataType; + + VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_CLK : X01 := '0'; + + VARIABLE PD_SH : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_SH : X01 := '0'; + + VARIABLE Violation : X01 := '0'; + + -- Functionality Results Variables + VARIABLE QNeg_zd : std_ulogic := 'U'; + VARIABLE Q_zd : std_ulogic := 'U'; + VARIABLE D1int : std_ulogic := 'U'; + VARIABLE D2int : std_ulogic := 'U'; + VARIABLE D3int : std_ulogic := 'U'; + VARIABLE D4int : std_ulogic := 'U'; + VARIABLE D5int : std_ulogic := 'U'; + VARIABLE D6int : std_ulogic := 'U'; + VARIABLE D7int : std_ulogic := 'U'; + VARIABLE CLKint : std_ulogic := 'U'; + VARIABLE LD : std_ulogic := 'U'; + VARIABLE R0 : std_ulogic := 'U'; + VARIABLE R1 : std_ulogic := 'U'; + VARIABLE R2 : std_ulogic := 'U'; + VARIABLE R3 : std_ulogic := 'U'; + VARIABLE R4 : std_ulogic := 'U'; + VARIABLE R5 : std_ulogic := 'U'; + VARIABLE R6 : std_ulogic := 'U'; + VARIABLE R7 : std_ulogic := 'U'; + VARIABLE S0 : std_ulogic := 'U'; + VARIABLE S1 : std_ulogic := 'U'; + VARIABLE S2 : std_ulogic := 'U'; + VARIABLE S3 : std_ulogic := 'U'; + VARIABLE S4 : std_ulogic := 'U'; + VARIABLE S5 : std_ulogic := 'U'; + VARIABLE S6 : std_ulogic := 'U'; + VARIABLE S7 : std_ulogic := 'U'; + + -- Output Glitch Detection Variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + VARIABLE QNeg_GlitchData : VitalGlitchDataType; + VARIABLE PrevData0 : std_logic_vector(0 to 4); + VARIABLE PrevData1 : std_logic_vector(0 to 4); + VARIABLE PrevData2 : std_logic_vector(0 to 4); + VARIABLE PrevData3 : std_logic_vector(0 to 4); + VARIABLE PrevData4 : std_logic_vector(0 to 4); + VARIABLE PrevData5 : std_logic_vector(0 to 4); + VARIABLE PrevData6 : std_logic_vector(0 to 4); + VARIABLE PrevData7 : std_logic_vector(0 to 4); + + BEGIN + ------------------------------------------------------------------------ + -- Timing Check Section + ------------------------------------------------------------------------ + IF (TimingChecksOn) THEN + + VitalSetupHoldCheck ( + TestSignal => DH_ipd, + TestSignalName => "DH", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DH_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DH_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DG_ipd, + TestSignalName => "DG", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DG_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DG_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DF_ipd, + TestSignalName => "DF", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DF_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DF_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DE_ipd, + TestSignalName => "DE", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DE_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DE_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DD_ipd, + TestSignalName => "DD", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DD_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DD_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DC_ipd, + TestSignalName => "DC", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DC_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DC_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DB_ipd, + TestSignalName => "DB", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DB_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DB_SH + ); + + VitalSetupHoldCheck ( + TestSignal => DA_ipd, + TestSignalName => "DA", + RefSignal => SH_ipd, + RefSignalName => "SH", + SetupHigh => tsetup_DA_SH, + SetupLow => tsetup_DA_SH, + HoldHigh => thold_DA_SH, + HoldLow => thold_DA_SH, + CheckEnabled => true, + RefTransition => '\', + HeaderMsg => InstancePath & partID, + TimingData => TD_DA_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_DA_SH + ); + + VitalSetupHoldCheck ( + TestSignal => SH_ipd, + TestSignalName => "SH", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_SH_CLK, + SetupLow => tsetup_SH_CLK, + CheckEnabled => true, + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_SH_CLK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_SH_CLK + ); + + VitalSetupHoldCheck ( + TestSignal => SER_ipd, + TestSignalName => "SER", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_SER_CLK, + SetupLow => tsetup_SER_CLK, + HoldHigh => thold_SER_CLK, + HoldLow => thold_SER_CLK, + CheckEnabled => true, + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_SER_CLK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_SER_CLK + ); + + VitalSetupHoldCheck ( + TestSignal => CLKINH_ipd, + TestSignalName => "CLKINH_ipd", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_CLKINH_CLK_posedge, + SetupLow => tsetup_CLKINH_CLK_negedge, + CheckEnabled => true, + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_CLKINH_CLK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_CLKINH_CLK + ); + + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK_ipd", + Period => tperiod_CLK_posedge, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_posedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath & partID, + PeriodData => PD_CLK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Pviol_CLK + ); + + VitalPeriodPulseCheck ( + TestSignal => SH_ipd, + TestSignalName => "SH_ipd", + PulseWidthLow => tpw_SH_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath & partID, + PeriodData => PD_SH, + XOn => XOn, + MsgOn => MsgOn, + Violation => Pviol_SH + ); + + END IF; + + ------------------------------------------------------------------------ + -- Functionality Section + ------------------------------------------------------------------------ + Violation := Pviol_SH OR Pviol_CLK OR Tviol_DA_SH OR + Tviol_SER_CLK OR Tviol_CLKINH_CLK; + + CLKint := VitalOR2 (a => CLK_ipd, b => CLKINH_ipd); + LD := VitalINV (data => SH_ipd); + S7 := VitalAND2 (a => LD, b => DH_ipd); + R7 := VitalAND2 (a => LD, b => not(DH_ipd)); + S6 := VitalAND2 (a => LD, b => DG_ipd); + R6 := VitalAND2 (a => LD, b => not(DG_ipd)); + S5 := VitalAND2 (a => LD, b => DF_ipd); + R5 := VitalAND2 (a => LD, b => not(DF_ipd)); + S4 := VitalAND2 (a => LD, b => DE_ipd); + R4 := VitalAND2 (a => LD, b => not(DE_ipd)); + S3 := VitalAND2 (a => LD, b => DD_ipd); + R3 := VitalAND2 (a => LD, b => not(DD_ipd)); + S2 := VitalAND2 (a => LD, b => DC_ipd); + R2 := VitalAND2 (a => LD, b => not(DC_ipd)); + S1 := VitalAND2 (a => LD, b => DB_ipd); + R1 := VitalAND2 (a => LD, b => not(DB_ipd)); + S0 := VitalAND2 (a => LD, b => DA_ipd); + R0 := VitalAND2 (a => LD, b => not(DA_ipd)); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D7int, S7, R7), + Result => Q_zd, + PreviousDataIn => PrevData7 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D6int, S6, R6), + Result => D7int, + PreviousDataIn => PrevData6 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D5int, S5, R5), + Result => D6int, + PreviousDataIn => PrevData5 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D4int, S4, R4), + Result => D5int, + PreviousDataIn => PrevData4 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D3int, S3, R3), + Result => D4int, + PreviousDataIn => PrevData3 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D2int, S2, R2), + Result => D3int, + PreviousDataIn => PrevData2 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, D1int, S1, R1), + Result => D2int, + PreviousDataIn => PrevData1 + ); + + VitalStateTable ( + StateTable => DFFSR_tab, + DataIn => (Violation, CLKint, SER_ipd, S0, R0), + Result => D1int, + PreviousDataIn => PrevData0 + ); + + QNeg_zd := VitalINV (data => Q_zd); + + ------------------------------------------------------------------------ + -- Path Delay Section + ------------------------------------------------------------------------ + VitalPathDelay01 ( + OutSignal => Q, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => ( + 0 => (InputChangeTime => SH_ipd'LAST_EVENT, + PathDelay => tpd_SH_Q, + PathCondition => true), + 1 => (InputChangeTime => CLK_ipd'LAST_EVENT, + PathDelay => tpd_CLK_Q, + PathCondition => (SH_ipd = '1') ), + 2 => (InputChangeTime => DH_ipd'LAST_EVENT, + PathDelay => tpd_DH_Q, + PathCondition => (SH_ipd = '0') ) ), + GlitchData => Q_GlitchData ); + + VitalPathDelay01 ( + OutSignal => QNeg, + OutSignalName => "QNeg", + OutTemp => QNeg_zd, + Paths => ( + 0 => (InputChangeTime => SH_ipd'LAST_EVENT, + PathDelay => tpd_SH_Q, + PathCondition => true), + 1 => (InputChangeTime => CLK_ipd'LAST_EVENT, + PathDelay => tpd_CLK_Q, + PathCondition => (SH_ipd = '1') ), + 2 => (InputChangeTime => DH_ipd'LAST_EVENT, + PathDelay => tpd_DH_QNeg, + PathCondition => (SH_ipd = '0') ) ), + GlitchData => QNeg_GlitchData ); + + END PROCESS; +END vhdl_behavioral; diff --git a/vhdl/fmf/std595.vhd b/vhdl/fmf/std595.vhd new file mode 100644 index 0000000..e4dace8 --- /dev/null +++ b/vhdl/fmf/std595.vhd @@ -0,0 +1,610 @@ +-------------------------------------------------------------------------------- +-- File Name: std595.vhd +-------------------------------------------------------------------------------- +-- Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License version 2 as +-- published by the Free Software Foundation. +-- +-- MODIFICATION HISTORY: +-- +-- version: | author: | mod date: | changes made: +-- V1.0 B.Bizic 01 JUN 10 Initial release +-- +-------------------------------------------------------------------------------- +-- PART DESCRIPTION: +-- +-- Library: STND +-- Technology: 54/7400 +-- Part: STD595 +-- +-- Description: 8-Bit Shift Register With Output Latches +-------------------------------------------------------------------------------- + +LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; + USE IEEE.VITAL_timing.ALL; + USE IEEE.VITAL_primitives.ALL; +LIBRARY FMF; USE FMF.gen_utils.ALL; + USE FMF.ff_package.ALL; + +-------------------------------------------------------------------------------- +-- ENTITY DECLARATION +-------------------------------------------------------------------------------- +ENTITY std595 IS + GENERIC ( + -- tipd delays: interconnect path delays + tipd_GNeg : VitalDelayType01 := VitalZeroDelay01; + tipd_RCK : VitalDelayType01 := VitalZeroDelay01; + tipd_SER : VitalDelayType01 := VitalZeroDelay01; + tipd_SCK : VitalDelayType01 := VitalZeroDelay01; + tipd_SCLRNeg : VitalDelayType01 := VitalZeroDelay01; + -- tpd delays + tpd_RCK_QA : VitalDelayType01 := UnitDelay01; + tpd_SCK_QHSER : VitalDelayType01 := UnitDelay01; + tpd_SCLRNeg_QHSER : VitalDelayType01 := UnitDelay01; + tpd_GNeg_QA : VitalDelayType01Z := UnitDelay01Z; + -- tsetup values: setup times + tsetup_SER_SCK : VitalDelayType := UnitDelay; + tsetup_SCK_RCK : VitalDelayType := UnitDelay; + tsetup_SCLRNeg_RCK : VitalDelayType := UnitDelay; + -- thold values: hold times + thold_SER_SCK : VitalDelayType := UnitDelay; + thold_SCK_RCK : VitalDelayType := UnitDelay; + thold_SCLRNeg_RCK : VitalDelayType := UnitDelay; + -- tpw values: pulse widths + tpw_SCLRNeg_negedge : VitalDelayType := UnitDelay; + tpw_SCK_posedge : VitalDelayType := UnitDelay; + tpw_RCK_posedge : VitalDelayType := UnitDelay; + -- tperiod_min: minimum clock period = 1/max freq + tperiod_SCK_posedge : VitalDelayType := UnitDelay; + tperiod_RCK_posedge : VitalDelayType := UnitDelay; + -- generic control parameters + InstancePath : STRING := DefaultInstancePath; + TimingChecksOn : BOOLEAN := DefaultTimingChecks; + MsgOn : BOOLEAN := DefaultMsgOn; + XOn : BOOLEAN := DefaultXon; + -- For FMF SDF technology file usage + TimingModel : STRING := DefaultTimingModel + ); + PORT ( + + GNeg : IN std_ulogic := 'U'; + RCK : IN std_ulogic := 'U'; + SER : IN std_ulogic := 'U'; + SCK : IN std_ulogic := 'U'; + SCLRNeg : IN std_ulogic := 'U'; + QA : OUT std_ulogic := 'U'; + QB : OUT std_ulogic := 'U'; + QC : OUT std_ulogic := 'U'; + QD : OUT std_ulogic := 'U'; + QE : OUT std_ulogic := 'U'; + QF : OUT std_ulogic := 'U'; + QG : OUT std_ulogic := 'U'; + QH : OUT std_ulogic := 'U'; + QHSER : OUT std_ulogic := 'U' + ); + ATTRIBUTE VITAL_LEVEL0 of std595 : ENTITY IS TRUE; +END std595; + +-------------------------------------------------------------------------------- +-- ARCHITECTURE DECLARATION +-------------------------------------------------------------------------------- +ARCHITECTURE vhdl_behavioral of std595 IS + ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; + + CONSTANT partID : STRING := "std595"; + + SIGNAL GNeg_ipd : std_ulogic := 'U'; + SIGNAL RCK_ipd : std_ulogic := 'U'; + SIGNAL SER_ipd : std_ulogic := 'U'; + SIGNAL SCK_ipd : std_ulogic := 'U'; + SIGNAL SCLRNeg_ipd : std_ulogic := 'U'; + + SIGNAL QA0_int : std_ulogic := 'U'; + SIGNAL QB0_int : std_ulogic := 'U'; + SIGNAL QC0_int : std_ulogic := 'U'; + SIGNAL QD0_int : std_ulogic := 'U'; + SIGNAL QE0_int : std_ulogic := 'U'; + SIGNAL QF0_int : std_ulogic := 'U'; + SIGNAL QG0_int : std_ulogic := 'U'; + SIGNAL QH0_int : std_ulogic := 'U'; + +BEGIN + + ---------------------------------------------------------------------------- + -- Wire Delays + ---------------------------------------------------------------------------- + WireDelay : BLOCK + BEGIN + + w_1 : VitalWireDelay (GNeg_ipd, GNeg, tipd_GNeg); + w_2 : VitalWireDelay (RCK_ipd, RCK, tipd_RCK); + w_3 : VitalWireDelay (SER_ipd, SER, tipd_SER); + w_4 : VitalWireDelay (SCK_ipd, SCK, tipd_SCK); + w_5 : VitalWireDelay (SCLRNeg_ipd, SCLRNeg, tipd_SCLRNeg); + + END BLOCK; + + ---------------------------------------------------------------------------- + -- Behavior Process + ---------------------------------------------------------------------------- + VitalBehavior : PROCESS (SER_ipd,SCK_ipd,RCK_ipd,SCLRNeg_ipd,GNeg_ipd) + + -- Timing Check Variables + VARIABLE Tviol_SER_SCK : X01 := '0'; + VARIABLE TD_SER_SCK : VitalTimingDataType; + + VARIABLE Tviol_SCK_RCK : X01 := '0'; + VARIABLE TD_SCK_RCK : VitalTimingDataType; + + VARIABLE Tviol_SCLRNeg_RCK : X01 := '0'; + VARIABLE TD_SCLRNeg_RCK : VitalTimingDataType; + + VARIABLE PD_SCLRNeg : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_SCLRNeg : X01 := '0'; + + VARIABLE PD_SCK : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_SCK : X01 := '0'; + + VARIABLE PD_RCK : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_RCK : X01 := '0'; + + VARIABLE Violation : X01 := '0'; + + -- Functionality Results Variables + VARIABLE Q7_zd : std_ulogic := 'U'; + VARIABLE Q6_zd : std_ulogic := 'U'; + VARIABLE Q5_zd : std_ulogic := 'U'; + VARIABLE Q4_zd : std_ulogic := 'U'; + VARIABLE Q3_zd : std_ulogic := 'U'; + VARIABLE Q2_zd : std_ulogic := 'U'; + VARIABLE Q1_zd : std_ulogic := 'U'; + VARIABLE Q0_zd : std_ulogic := 'U'; + + -- Temporary variables for tri state out + VARIABLE QA_int : std_ulogic := 'U'; + VARIABLE QB_int : std_ulogic := 'U'; + VARIABLE QC_int : std_ulogic := 'U'; + VARIABLE QD_int : std_ulogic := 'U'; + VARIABLE QE_int : std_ulogic := 'U'; + VARIABLE QF_int : std_ulogic := 'U'; + VARIABLE QG_int : std_ulogic := 'U'; + VARIABLE QH_int : std_ulogic := 'U'; + + VARIABLE QA0_int : std_ulogic := 'U'; + VARIABLE QB0_int : std_ulogic := 'U'; + VARIABLE QC0_int : std_ulogic := 'U'; + VARIABLE QD0_int : std_ulogic := 'U'; + VARIABLE QE0_int : std_ulogic := 'U'; + VARIABLE QF0_int : std_ulogic := 'U'; + VARIABLE QG0_int : std_ulogic := 'U'; + VARIABLE QH0_int : std_ulogic := 'U'; + + -- Output Glitch Detection Variables + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE Q2_GlitchData : VitalGlitchDataType; + VARIABLE Q3_GlitchData : VitalGlitchDataType; + VARIABLE Q4_GlitchData : VitalGlitchDataType; + VARIABLE Q5_GlitchData : VitalGlitchDataType; + VARIABLE Q6_GlitchData : VitalGlitchDataType; + VARIABLE Q7_GlitchData : VitalGlitchDataType; + VARIABLE QHSER_GlitchData : VitalGlitchDataType; + + -- Prevdata for DFF/DFFRN tab + VARIABLE PrevData00 : std_logic_vector(0 to 3); + VARIABLE PrevData01 : std_logic_vector(0 to 3); + VARIABLE PrevData02 : std_logic_vector(0 to 3); + VARIABLE PrevData03 : std_logic_vector(0 to 3); + VARIABLE PrevData04 : std_logic_vector(0 to 3); + VARIABLE PrevData05 : std_logic_vector(0 to 3); + VARIABLE PrevData06 : std_logic_vector(0 to 3); + VARIABLE PrevData07 : std_logic_vector(0 to 3); + + VARIABLE PrevData10 : std_logic_vector(0 to 2); + VARIABLE PrevData11 : std_logic_vector(0 to 2); + VARIABLE PrevData12 : std_logic_vector(0 to 2); + VARIABLE PrevData13 : std_logic_vector(0 to 2); + VARIABLE PrevData14 : std_logic_vector(0 to 2); + VARIABLE PrevData15 : std_logic_vector(0 to 2); + VARIABLE PrevData16 : std_logic_vector(0 to 2); + VARIABLE PrevData17 : std_logic_vector(0 to 2); + + BEGIN + + ------------------------------------------------------------------------ + -- Timing Check Section + ------------------------------------------------------------------------ + IF (TimingChecksOn) THEN + + VitalPeriodPulseCheck ( + TestSignal => SCK_ipd, + TestSignalName => "SCK_ipd", + Period => tperiod_SCK_posedge, + PulseWidthHigh => tpw_SCK_posedge, + PulseWidthLow => tpw_SCK_posedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath & partID, + PeriodData => PD_SCK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Pviol_SCK + ); + + VitalPeriodPulseCheck ( + TestSignal => RCK_ipd, + TestSignalName => "RCK_ipd", + Period => tperiod_RCK_posedge, + PulseWidthHigh => tpw_RCK_posedge, + PulseWidthLow => tpw_RCK_posedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath & partID, + PeriodData => PD_RCK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Pviol_RCK + ); + + VitalPeriodPulseCheck ( + TestSignal => SCLRNeg_ipd, + TestSignalName => "SCLRNeg_ipd", + PulseWidthLow => tpw_SCLRNeg_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath & partID, + PeriodData => PD_SCLRNeg, + XOn => XOn, + MsgOn => MsgOn, + Violation => Pviol_SCLRNeg + ); + + VitalSetupHoldCheck ( + TestSignal => SER_ipd, + TestSignalName => "SER", + RefSignal => SCK_ipd, + RefSignalName => "SCK", + SetupHigh => tsetup_SER_SCK, + SetupLow => tsetup_SER_SCK, + HoldHigh => thold_SER_SCK, + HoldLow => thold_SER_SCK, + CheckEnabled => (SCLRNeg_ipd = '1' OR SCLRNeg_ipd = 'H'), + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_SER_SCK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_SER_SCK + ); + + VitalSetupHoldCheck ( + TestSignal => SCK_ipd, + TestSignalName => "SCK", + RefSignal => RCK_ipd, + RefSignalName => "RCK", + SetupHigh => tsetup_SCK_RCK, + SetupLow => tsetup_SCK_RCK, + HoldHigh => thold_SCK_RCK, + HoldLow => thold_SCK_RCK, + CheckEnabled => (SCLRNeg_ipd = '1' OR SCLRNeg_ipd = 'H'), + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_SCK_RCK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_SCK_RCK + ); + + VitalSetupHoldCheck ( + TestSignal => SCLRNeg_ipd, + TestSignalName => "SCLRNeg", + RefSignal => RCK_ipd, + RefSignalName => "RCK", + SetupHigh => tsetup_SCLRNeg_RCK, + SetupLow => tsetup_SCLRNeg_RCK, + HoldHigh => thold_SCLRNeg_RCK, + HoldLow => thold_SCLRNeg_RCK, + CheckEnabled => (SCLRNeg_ipd = '1' OR SCLRNeg_ipd = 'H'), + RefTransition => '/', + HeaderMsg => InstancePath & partID, + TimingData => TD_SCLRNeg_RCK, + XOn => XOn, + MsgOn => MsgOn, + Violation => Tviol_SCLRNeg_RCK + ); + + END IF; + + ------------------------------------------------------------------------ + -- Functionality Section + ------------------------------------------------------------------------ + + Violation := Tviol_SER_SCK OR Tviol_SCK_RCK OR Tviol_SCLRNeg_RCK OR + Pviol_SCLRNeg OR Pviol_SCK OR Pviol_RCK; + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q6_zd, SCLRNeg_ipd), + Result => Q7_zd, + PreviousDataIn => PrevData07 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q5_zd, SCLRNeg_ipd), + Result => Q6_zd, + PreviousDataIn => PrevData06 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q4_zd, SCLRNeg_ipd), + Result => Q5_zd, + PreviousDataIn => PrevData05 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q3_zd, SCLRNeg_ipd), + Result => Q4_zd, + PreviousDataIn => PrevData04 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q2_zd, SCLRNeg_ipd), + Result => Q3_zd, + PreviousDataIn => PrevData03 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q1_zd, SCLRNeg_ipd), + Result => Q2_zd, + PreviousDataIn => PrevData02 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, Q0_zd, SCLRNeg_ipd), + Result => Q1_zd, + PreviousDataIn => PrevData01 + ); + + VitalStateTable ( + StateTable => DFFRN_tab, + DataIn => (Violation, SCK_ipd, SER_ipd, SCLRNeg_ipd), + Result => Q0_zd, + PreviousDataIn => PrevData00 + ); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q0_zd), + Result => QA_int, + PreviousDataIn => PrevData10 + ); + + QA0_int := VitalBUFIF0 (data => QA_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q1_zd), + Result => QB_int, + PreviousDataIn => PrevData11 + ); + + QB0_int := VitalBUFIF0 (data => QB_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q2_zd), + Result => QC_int, + PreviousDataIn => PrevData12 + ); + + QC0_int := VitalBUFIF0 (data => QC_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q3_zd), + Result => QD_int, + PreviousDataIn => PrevData13 + ); + + QD0_int := VitalBUFIF0 (data => QD_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q4_zd), + Result => QE_int, + PreviousDataIn => PrevData14 + ); + + QE0_int := VitalBUFIF0 (data => QE_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q5_zd), + Result => QF_int, + PreviousDataIn => PrevData15 + ); + + QF0_int := VitalBUFIF0 (data => QF_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q6_zd), + Result => QG_int, + PreviousDataIn => PrevData16 + ); + + QG0_int := VitalBUFIF0 (data => QG_int, + enable => GNeg_ipd); + + VitalStateTable ( + StateTable => DFF_tab, + DataIn => (Violation, RCK_ipd, Q7_zd), + Result => QH_int, + PreviousDataIn => PrevData17 + ); + + QH0_int := VitalBUFIF0 (data => QH_int, + enable => GNeg_ipd); + + ------------------------------------------------------------------------ + -- Path Delay Section + ------------------------------------------------------------------------ + + VitalPathDelay01 ( + OutSignal => QHSER, + OutSignalName => "QHSER", + OutTemp => Q7_zd, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => SCLRNeg_ipd'LAST_EVENT, + PathDelay => tpd_SCLRNeg_QHSER, + PathCondition => TRUE), + 1 => (InputChangeTime => SCK_ipd'LAST_EVENT, + PathDelay => tpd_SCK_QHSER, + PathCondition => (SCLRNeg_ipd = '1' OR + SCLRNeg_ipd = 'H') ) + ), + GlitchData => QHSER_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QA, + OutSignalName => "QA", + OutTemp => QA0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0'OR GNeg_ipd='L' )) + ), + GlitchData =>Q0_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QB, + OutSignalName => "QB", + OutTemp => QB0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q1_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QC, + OutSignalName => "QC", + OutTemp => QC0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q2_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QD, + OutSignalName => "QD", + OutTemp => QD0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q3_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QE, + OutSignalName => "QE", + OutTemp => QE0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q4_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QF, + OutSignalName => "QF", + OutTemp => QF0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q5_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QG, + OutSignalName => "QG", + OutTemp => QG0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q6_GlitchData ); + + VitalPathDelay01Z ( + OutSignal => QH, + OutSignalName => "QH", + OutTemp => QH0_int, + XOn => XOn, + MsgOn => MsgOn, + Paths => ( + 0 => (InputChangeTime => GNeg_ipd'LAST_EVENT, + PathDelay => tpd_GNeg_QA, + PathCondition => TRUE), + 1=> (InputChangeTime => RCK_ipd'LAST_EVENT, + PathDelay => VitalExtendToFillDelay(tpd_RCK_QA), + PathCondition => (GNeg_ipd='0' OR GNeg_ipd='L')) + ), + GlitchData => Q7_GlitchData ); + + END PROCESS; +END vhdl_behavioral; diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd new file mode 100644 index 0000000..22e1f51 --- /dev/null +++ b/vhdl/ice.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library fmf; +use fmf.std595; + +use work.all; + +entity ice is + port ( + bit_in : in std_logic; + bit_out : out std_logic; + bit_clk : in std_logic; + byte_clk : in std_logic; + a_oe : in std_logic; + d_oe : in std_logic; + + ah : out std_logic_vector(7 downto 0); + al : out std_logic_vector(7 downto 0); + d_out : out std_logic_vector(7 downto 0) + ); +end; + +architecture behave of ice is + signal ah_out : std_logic; + signal al_out : std_logic; + signal d_out_out : std_logic; +begin + ah_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => bit_in, + qhser => ah_out, + sck => bit_clk, + rck => byte_clk, + gneg => a_oe, + qa => ah(0), + qb => ah(1), + qc => ah(2), + qd => ah(3), + qe => ah(4), + qf => ah(5), + qg => ah(6), + qh => ah(7), + SCLRNeg => '1' + ); + + al_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => ah_out, + qhser => al_out, + sck => bit_clk, + rck => byte_clk, + gneg => a_oe, + qa => al(0), + qb => al(1), + qc => al(2), + qd => al(3), + qe => al(4), + qf => al(5), + qg => al(6), + qh => al(7), + SCLRNeg => '1' + ); + + d_out_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => al_out, + qhser => d_out_out, + sck => bit_clk, + rck => byte_clk, + gneg => d_oe, + qa => d_out(0), + qb => d_out(1), + qc => d_out(2), + qd => d_out(3), + qe => d_out(4), + qf => d_out(5), + qg => d_out(6), + qh => d_out(7), + SCLRNeg => '1' + ); +end; diff --git a/vhdl/ice_tb.vhd b/vhdl/ice_tb.vhd new file mode 100644 index 0000000..24916cd --- /dev/null +++ b/vhdl/ice_tb.vhd @@ -0,0 +1,66 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.all; + +entity ice_tb is +end ice_tb; + +architecture ice_tb_arch of ice_tb is + signal bit_in : std_logic; + signal bit_out : std_logic; + signal bit_clk : std_logic := '0'; + signal byte_clk : std_logic := '0'; + signal a_oe : std_logic := '1'; + signal d_oe : std_logic := '1'; + + signal ah : std_logic_vector(7 downto 0); + signal al : std_logic_vector(7 downto 0); + signal d_out : std_logic_vector(7 downto 0); + + constant tClk : time := 1 ns; +begin + ice : entity work.ice port map(bit_in, bit_out, bit_clk, byte_clk, a_oe, d_oe, ah, al, d_out); + + stimulus : process + procedure byte_out(byte : in std_logic_vector(7 downto 0)) is + begin + for i in byte'range loop + bit_in <= byte(i); + bit_clk <= '1'; + wait for tClk; + + bit_clk <= '0'; + wait for tClk; + end loop; + + byte_clk <= '1'; + wait for tClk; + + byte_clk <= '0'; + wait for tClk; + end; + + procedure write_ram( + data : in std_logic_vector(7 downto 0); + address : in std_logic_vector(15 downto 0)) is + begin + -- TODO: busreq + wait for busack + byte_out(data); + byte_out(address(7 downto 0)); + byte_out(address(15 downto 8)); + end; + + begin + write_ram("10100101", "0000000000000001"); + d_oe <= '0'; + a_oe <= '0'; + + wait for tClk; + assert ah = "00000000" report "ah failed"; + assert al = "00000001" report "al failed"; + assert d_out = "10100101" report "d_out failed"; + + assert false report "end of test" severity note; + wait; + end process; +end; |