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author | Trygve Laugstøl <trygvis@inamo.no> | 2013-02-17 12:30:14 +0100 |
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committer | Trygve Laugstøl <trygvis@inamo.no> | 2013-02-17 12:30:14 +0100 |
commit | ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4 (patch) | |
tree | 8cf52146d1e9f302506ac91b288de1144d4de325 /vhdl/ice.vhd | |
parent | fd3087cdb92724fb2dc4176a997afb25b48506a0 (diff) | |
download | rom-emulator-ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4.tar.gz rom-emulator-ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4.tar.bz2 rom-emulator-ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4.tar.xz rom-emulator-ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4.zip |
o Using a bus for the memory input too.
o Adding a test case for reading data from RAM.
Diffstat (limited to 'vhdl/ice.vhd')
-rw-r--r-- | vhdl/ice.vhd | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd index 8cbff92..5f0329e 100644 --- a/vhdl/ice.vhd +++ b/vhdl/ice.vhd @@ -7,9 +7,7 @@ entity ice is port ( mcu_in : in mcu_in; bit_out : out std_logic; - oe : in std_logic; - ce : in std_logic; - we : in std_logic + ram_in : in ram_in ); end ice; @@ -25,8 +23,7 @@ begin bit_out, ah, al, - d, -- d_out, - d -- d_in + d ); address : ram_address <= ah(14 downto 8) & al; @@ -34,9 +31,9 @@ begin ram : entity work.as7c256a port map( address => ram_address, dataio => d, - oe_bar => oe, - ce_bar => ce, - we_bar => we + oe_bar => ram_in.oe, + ce_bar => ram_in.ce, + we_bar => ram_in.we ); end; |