aboutsummaryrefslogtreecommitdiff
path: root/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
diff options
context:
space:
mode:
authorTrygve Laugstøl <trygvis@inamo.no>2017-01-25 22:24:18 +0100
committerTrygve Laugstøl <trygvis@inamo.no>2017-01-25 22:29:25 +0100
commit40e04e3772726829d66c12e69f24b03920d79c67 (patch)
tree636811bad956798c9d5d22de9e7ba8c799b8d791 /thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
parent2fff65aed2477a503c72629d27e2a330d30c02d1 (diff)
downloadstm32f103-playground-40e04e3772726829d66c12e69f24b03920d79c67.tar.gz
stm32f103-playground-40e04e3772726829d66c12e69f24b03920d79c67.tar.bz2
stm32f103-playground-40e04e3772726829d66c12e69f24b03920d79c67.tar.xz
stm32f103-playground-40e04e3772726829d66c12e69f24b03920d79c67.zip
o Moving tinyprintf and stm libraries under thirdparty.
Diffstat (limited to 'thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c')
-rw-r--r--thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c427
1 files changed, 427 insertions, 0 deletions
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
new file mode 100644
index 0000000..cdcfcdf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
@@ -0,0 +1,427 @@
+/**
+ ******************************************************************************
+ * @file fsmc_nor.c
+ * @author MCD Application Team
+ * @version V4.0.0
+ * @date 21-January-2013
+ * @brief This file provides a set of functions needed to drive the M29W128FL,
+ * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nor.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define Bank1_NOR2_ADDR ((uint32_t)0x64000000)
+
+/* Delay definition */
+#define BlockErase_Timeout ((uint32_t)0x00A00000)
+#define ChipErase_Timeout ((uint32_t)0x30000000)
+#define Program_Timeout ((uint32_t)0x00001400)
+
+/* Private macro -------------------------------------------------------------*/
+#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
+#define NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name : FSMC_NOR_Init
+* Description : Configures the FSMC and GPIOs to interface with the NOR memory.
+* This function must be called before any write/read operation
+* on the NOR.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_NOR_Init(void)
+{
+ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
+ FSMC_NORSRAMTimingInitTypeDef p;
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
+ RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+
+ /*-- GPIO Configuration ------------------------------------------------------*/
+ /* NOR Data lines configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+ GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+ GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
+ GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+ /* NOR Address lines configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+ GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
+ GPIO_Pin_14 | GPIO_Pin_15;
+ GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
+ GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
+ GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
+ GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+ /* NOE and NWE configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ /* NE2 configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+ GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+ /*-- FSMC Configuration ----------------------------------------------------*/
+ p.FSMC_AddressSetupTime = 0x02;
+ p.FSMC_AddressHoldTime = 0x00;
+ p.FSMC_DataSetupTime = 0x05;
+ p.FSMC_BusTurnAroundDuration = 0x00;
+ p.FSMC_CLKDivision = 0x00;
+ p.FSMC_DataLatency = 0x00;
+ p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+ /* Enable FSMC Bank1_NOR Bank */
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_ReadID
+* Description : Reads NOR memory's Manufacturer and Device Code.
+* Input : - NOR_ID: pointer to a NOR_IDTypeDef structure which will hold
+* the Manufacturer and Device Code.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_NOR_ReadID(NOR_IDTypeDef* NOR_ID)
+{
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
+
+ NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
+ NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
+ NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
+ NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
+}
+
+/*******************************************************************************
+* Function Name : FSMC_NOR_EraseBlock
+* Description : Erases the specified Nor memory block.
+* Input : - BlockAddr: address of the block to erase.
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_EraseBlock(uint32_t BlockAddr)
+{
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
+
+ return (FSMC_NOR_GetStatus(BlockErase_Timeout));
+}
+
+/*******************************************************************************
+* Function Name : FSMC_NOR_EraseChip
+* Description : Erases the entire chip.
+* Input : None
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_EraseChip(void)
+{
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
+
+ return (FSMC_NOR_GetStatus(ChipErase_Timeout));
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_WriteHalfWord
+* Description : Writes a half-word to the NOR memory.
+* Input : - WriteAddr : NOR memory internal address to write to.
+* - Data : Data to write.
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
+{
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
+ NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
+
+ return (FSMC_NOR_GetStatus(Program_Timeout));
+}
+
+/*******************************************************************************
+* Function Name : FSMC_NOR_WriteBuffer
+* Description : Writes a half-word buffer to the FSMC NOR memory.
+* Input : - pBuffer : pointer to buffer.
+* - WriteAddr : NOR memory internal address from which the data
+* will be written.
+* - NumHalfwordToWrite : number of Half words to write.
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+ NOR_Status status = NOR_ONGOING;
+
+ do
+ {
+ /* Transfer data to the memory */
+ status = FSMC_NOR_WriteHalfWord(WriteAddr, *pBuffer++);
+ WriteAddr = WriteAddr + 2;
+ NumHalfwordToWrite--;
+ }
+ while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
+
+ return (status);
+}
+
+/*******************************************************************************
+* Function Name : FSMC_NOR_ProgramBuffer
+* Description : Writes a half-word buffer to the FSMC NOR memory. This function
+* must be used only with S29GL128P NOR memory.
+* Input : - pBuffer : pointer to buffer.
+* - WriteAddr: NOR memory internal address from which the data
+* will be written.
+* - NumHalfwordToWrite: number of Half words to write.
+* The maximum allowed value is 32 Half words (64 bytes).
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+ uint32_t lastloadedaddress = 0x00;
+ uint32_t currentaddress = 0x00;
+ uint32_t endaddress = 0x00;
+
+ /* Initialize variables */
+ currentaddress = WriteAddr;
+ endaddress = WriteAddr + NumHalfwordToWrite - 1;
+ lastloadedaddress = WriteAddr;
+
+ /* Issue unlock command sequence */
+ NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+
+ /* Write Write Buffer Load Command */
+ NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
+ NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
+
+ /* Load Data into NOR Buffer */
+ while(currentaddress <= endaddress)
+ {
+ /* Store last loaded address & data value (for polling) */
+ lastloadedaddress = currentaddress;
+
+ NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
+ currentaddress += 1;
+ }
+
+ NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
+
+ return(FSMC_NOR_GetStatus(Program_Timeout));
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_ReadHalfWord
+* Description : Reads a half-word from the NOR memory.
+* Input : - ReadAddr : NOR memory internal address to read from.
+* Output : None
+* Return : Half-word read from the NOR memory
+*******************************************************************************/
+uint16_t FSMC_NOR_ReadHalfWord(uint32_t ReadAddr)
+{
+ NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
+ NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
+
+ return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
+}
+
+/*******************************************************************************
+* Function Name : FSMC_NOR_ReadBuffer
+* Description : Reads a block of data from the FSMC NOR memory.
+* Input : - pBuffer : pointer to the buffer that receives the data read
+* from the NOR memory.
+* - ReadAddr : NOR memory internal address to read from.
+* - NumHalfwordToRead : number of Half word to read.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
+{
+ NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+ NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
+
+ for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* while there is data to read */
+ {
+ /* Read a Halfword from the NOR */
+ *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
+ ReadAddr = ReadAddr + 2;
+ }
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_ReturnToReadMode
+* Description : Returns the NOR memory to Read mode.
+* Input : None
+* Output : None
+* Return : NOR_SUCCESS
+*******************************************************************************/
+NOR_Status FSMC_NOR_ReturnToReadMode(void)
+{
+ NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
+
+ return (NOR_SUCCESS);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_Reset
+* Description : Returns the NOR memory to Read mode and resets the errors in
+* the NOR memory Status Register.
+* Input : None
+* Output : None
+* Return : NOR_SUCCESS
+*******************************************************************************/
+NOR_Status FSMC_NOR_Reset(void)
+{
+ NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+ NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
+ NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
+
+ return (NOR_SUCCESS);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NOR_GetStatus
+* Description : Returns the NOR operation status.
+* Input : - Timeout: NOR programming Timeout
+* Output : None
+* Return : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+* or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_GetStatus(uint32_t Timeout)
+{
+ uint16_t val1 = 0x00, val2 = 0x00;
+ NOR_Status status = NOR_ONGOING;
+ uint32_t timeout = Timeout;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0))
+ {
+ timeout--;
+ }
+
+ timeout = Timeout;
+
+ while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))
+ {
+ timeout--;
+ }
+
+ /* Get the NOR memory operation status -------------------------------------*/
+ while((Timeout != 0x00) && (status != NOR_SUCCESS))
+ {
+ Timeout--;
+
+ /* Read DQ6 and DQ5 */
+ val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+ val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((val1 & 0x0040) == (val2 & 0x0040))
+ {
+ return NOR_SUCCESS;
+ }
+
+ if((val1 & 0x0020) != 0x0020)
+ {
+ status = NOR_ONGOING;
+ }
+
+ val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+ val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+
+ if((val1 & 0x0040) == (val2 & 0x0040))
+ {
+ return NOR_SUCCESS;
+ }
+ else if((val1 & 0x0020) == 0x0020)
+ {
+ return NOR_ERROR;
+ }
+ }
+
+ if(Timeout == 0x00)
+ {
+ status = NOR_TIMEOUT;
+ }
+
+ /* Return the operation status */
+ return (status);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/