o Moving tinyprintf and stm libraries under thirdparty.

684 files changed, 0 insertions, 249089 deletions

diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
deleted file mode 100644
index 7ab7b4b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
+++ /dev/null
@@ -1,1818 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- *   - Error 10: \n
- *     register uint32_t __regBasePri         __asm("basepri"); \n
- *     Error 10: Expecting ';'
- * .
- *   - Error 530: \n
- *     return(__regBasePri); \n
- *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * . 
- *   - Error 550: \n
- *     __regBasePri = (basePri & 0x1ff); \n
- *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- *   - Error 754: \n
- *     uint32_t RESERVED0[24]; \n
- *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
- * .
- *   - Error 750: \n
- *     #define __CM3_CORE_H__ \n
- *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- *   - Error 528: \n
- *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- *   - Error 751: \n
- *     } InterruptType_Type; \n
- *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note:  To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10  */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-    - CMSIS version number
-    - Cortex-M core registers and bitfields
-    - Cortex-M core peripheral base address
-  @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-  #define     __I     volatile                /*!< defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
-  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
-  @{
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
-  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
-  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
-  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
-  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
-  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
-  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
-  memory mapped structure for System Control Block (SCB)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
-  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
-  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
-  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
-  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
-  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
-  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
-} SCB_Type;                                                
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
-  memory mapped structure for Instrumentation Trace Macrocell (ITM)
-  @{
- */
-typedef struct
-{
-  __O  union  
-  {
-    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
-  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
-  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
-  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
-} ITM_Type;                                                
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
-  memory mapped structure for Interrupt Type
-  @{
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
-  memory mapped structure for Memory Protection Unit (MPU)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
-  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
-  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
-  memory mapped structure for Core Debug Register
-  @{
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
-
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-#define __RBIT                            __rbit
-#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
-#define __STREXB(value, ptr)              __strex(value, ptr)
-#define __STREXH(value, ptr)              __strex(value, ptr)
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param   priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX                           __clrex
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void)                                     */
-/* intrinsic void __DSB(void)                                     */
-/* intrinsic void __DMB(void)                                     */
-/* intrinsic void __set_PRIMASK();                                */
-/* intrinsic void __get_PRIMASK();                                */
-/* intrinsic void __set_FAULTMASK();                              */
-/* intrinsic void __get_FAULTMASK();                              */
-/* intrinsic uint32_t __REV(uint32_t value);                      */
-/* intrinsic uint32_t __REVSH(uint32_t value);                    */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *);              */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
-static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
-static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
-  Core  Function Interface containing:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Reset Functions
-*/
-/*@{*/
-
-/* ##########################   NVIC functions  #################################### */
-
-/**
- * @brief  Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param  PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field 
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-/**
- * @brief  Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field 
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn   The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn   The positive number of the external interrupt to disable
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn    The number of the device specifc interrupt
- * @return         1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending, 
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn    The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief  Read the active bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for read active bit
- * @return         1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active, 
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for set priority
- * @param  priority  The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for get priority
- * @return           The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/**
- * @brief  Encode the priority for an interrupt
- *
- * @param  PriorityGroup    The used priority group
- * @param  PreemptPriority  The preemptive priority value (starting from 0)
- * @param  SubPriority      The sub priority value (starting from 0)
- * @return                  The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/**
- * @brief  Decode the priority of an interrupt
- *
- * @param  Priority           The priority for the interrupt
- * @param  PriorityGroup      The used priority group
- * @param  pPreemptPriority   The preemptive priority value (starting from 0)
- * @param  pSubPriority       The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to 
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param   ticks   number of ticks between two interrupts
- * @return  1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
-  while(1);                                                    /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
-  Core Debug Interface containing:
-  - Core Debug Receive / Transmit Functions
-  - Core Debug Defines
-  - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief  Outputs a character via the ITM channel 0
- *
- * @param  ch   character to output
- * @return      character to output
- *
- * The function outputs a character via the ITM channel 0. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
-  return (ch);
-}
-
-
-/**
- * @brief  Inputs a character via variable ITM_RxBuffer
- *
- * @return      received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-
-
-/**
- * @brief  Check if a character via variable ITM_RxBuffer is available
- *
- * @return      1 = character available, 0 = no character available
- *
- * The function checks  variable ITM_RxBuffer whether a character is available or not. 
- * The function returns '1' if a character is available and '0' if no character is available. 
- */
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s
deleted file mode 100644
index a93e59b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s
+++ /dev/null
@@ -1,469 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x High Density Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Configure the clock system  
-  *                - Configure external SRAM mounted on STM3210E-EVAL board
-  *                  to be used as data memory (optional, to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-    .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-	.word	TIM1_TRG_COM_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler
-	.word	TIM8_BRK_IRQHandler
-	.word	TIM8_UP_IRQHandler
-	.word	TIM8_TRG_COM_IRQHandler
-	.word	TIM8_CC_IRQHandler
-	.word	ADC3_IRQHandler
-	.word	FSMC_IRQHandler
-	.word	SDIO_IRQHandler
-	.word	TIM5_IRQHandler
-	.word	SPI3_IRQHandler
-	.word	UART4_IRQHandler
-	.word	UART5_IRQHandler
-	.word	TIM6_IRQHandler
-	.word	TIM7_IRQHandler
-	.word	DMA2_Channel1_IRQHandler
-	.word	DMA2_Channel2_IRQHandler
-	.word	DMA2_Channel3_IRQHandler
-	.word	DMA2_Channel4_5_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	TIM4_IRQHandler
-	.thumb_set TIM4_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	USART3_IRQHandler
-	.thumb_set USART3_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-	.weak	TIM8_BRK_IRQHandler
-	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM8_UP_IRQHandler
-	.thumb_set TIM8_UP_IRQHandler,Default_Handler
-
-	.weak	TIM8_TRG_COM_IRQHandler
-	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM8_CC_IRQHandler
-	.thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-	.weak	ADC3_IRQHandler
-	.thumb_set ADC3_IRQHandler,Default_Handler
-
-	.weak	FSMC_IRQHandler
-	.thumb_set FSMC_IRQHandler,Default_Handler
-
-	.weak	SDIO_IRQHandler
-	.thumb_set SDIO_IRQHandler,Default_Handler
-
-	.weak	TIM5_IRQHandler
-	.thumb_set TIM5_IRQHandler,Default_Handler
-
-	.weak	SPI3_IRQHandler
-	.thumb_set SPI3_IRQHandler,Default_Handler
-
-	.weak	UART4_IRQHandler
-	.thumb_set UART4_IRQHandler,Default_Handler
-
-	.weak	UART5_IRQHandler
-	.thumb_set UART5_IRQHandler,Default_Handler
-
-	.weak	TIM6_IRQHandler
-	.thumb_set TIM6_IRQHandler,Default_Handler
-
-	.weak	TIM7_IRQHandler
-	.thumb_set TIM7_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_5_IRQHandler
-	.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s
deleted file mode 100644
index 4945a70..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s
+++ /dev/null
@@ -1,451 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd_vl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x High Density Value Line Devices vector table for Atollic 
-  *            toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system  
-  *                - Configure external SRAM mounted on STM32100E-EVAL board
-  *                  to be used as data memory (optional, to be enabled by user)   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-	
-/* Call the clock system intitialization function.*/
-  bl  SystemInit 
-/* Call static constructors */
-  bl __libc_init_array  
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_TIM15_IRQHandler
-	.word	TIM1_UP_TIM16_IRQHandler
-	.word	TIM1_TRG_COM_TIM17_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	CEC_IRQHandler
-  .word TIM12_IRQHandler
-  .word TIM13_IRQHandler
-  .word TIM14_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler  
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density Value line devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler 
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s
deleted file mode 100644
index 5f9df3d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s
+++ /dev/null
@@ -1,347 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_ld.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Low Density Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address.
-  *                - Configure the clock system 
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler
-  .word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s
deleted file mode 100644
index 3224b40..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s
+++ /dev/null
@@ -1,392 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_ld_vl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit  
-/* Call static constructors */
-  bl __libc_init_array 
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_TIM15_IRQHandler
-	.word	TIM1_UP_TIM16_IRQHandler
-	.word	TIM1_TRG_COM_TIM17_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	0
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	0
-	.word	0
-	.word	SPI1_IRQHandler
-	.word	0
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	0
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	CEC_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word 0  
-	.word 0
-	.word 0
-	.word 0
-	.word TIM6_DAC_IRQHandler
-	.word TIM7_IRQHandler  
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word BootRAM          /* @0x01CC. This is for boot in RAM mode for 
-                            STM32F10x Medium Value Line Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s
deleted file mode 100644
index bec2639..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s
+++ /dev/null
@@ -1,363 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_md.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Medium Density Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-	.word	TIM1_TRG_COM_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler
-  .word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM          /* @0x108. This is for boot in RAM mode for
-                            STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	TIM4_IRQHandler
-	.thumb_set TIM4_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	USART3_IRQHandler
-	.thumb_set USART3_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s
deleted file mode 100644
index b2fd0db..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s
+++ /dev/null
@@ -1,408 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_md_vl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Medium Density Value Line Devices vector table for Atollic 
-  *            toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-	
-/* Call the clock system intitialization function.*/
-  bl  SystemInit 
-/* Call static constructors */
-  bl __libc_init_array  
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_TIM15_IRQHandler
-	.word	TIM1_UP_TIM16_IRQHandler
-	.word	TIM1_TRG_COM_TIM17_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	CEC_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word 0  
-	.word 0
-	.word 0
-	.word 0
-	.word TIM6_DAC_IRQHandler
-	.word TIM7_IRQHandler  
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word 0
-	.word BootRAM          /* @0x01CC. This is for boot in RAM mode for 
-                         STM32F10x Medium Value Line Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s
deleted file mode 100644
index baf697b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,467 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_xl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM3210E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  main
-  bx  lr    
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s
deleted file mode 100644
index 833ece4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s
+++ /dev/null
@@ -1,368 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_cl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Connectivity line devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler        ; RTC alarm through EXTI line
-                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-                DCD     ETH_IRQHandler             ; Ethernet
-                DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
-                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-                DCD     OTG_FS_IRQHandler          ; USB OTG FS
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  CAN1_TX_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  ETH_IRQHandler             [WEAK]
-                EXPORT  ETH_WKUP_IRQHandler        [WEAK]
-                EXPORT  CAN2_TX_IRQHandler         [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_IRQHandler          [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s
deleted file mode 100644
index 8a19827..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s
+++ /dev/null
@@ -1,358 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_hd.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
-                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
-                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
-                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler            ; ADC3
-                DCD     FSMC_IRQHandler            ; FSMC
-                DCD     SDIO_IRQHandler            ; SDIO
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM8_UP_IRQHandler         [WEAK]
-                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM8_CC_IRQHandler         [WEAK]
-                EXPORT  ADC3_IRQHandler            [WEAK]
-                EXPORT  FSMC_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_IRQHandler
-TIM8_UP_IRQHandler
-TIM8_TRG_COM_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s
deleted file mode 100644
index f18be4b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s
+++ /dev/null
@@ -1,297 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s
deleted file mode 100644
index f7240dc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s
+++ /dev/null
@@ -1,304 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld_vl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Value Line Devices vector table  
-;*                      for MDK-ARM toolchain.  
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     0                               ; Reserved
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     0                               ; Reserved
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     0                               ; Reserved
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI-CEC
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTCAlarm_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-CEC_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s
deleted file mode 100644
index 076aa7f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s
+++ /dev/null
@@ -1,315 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_md_vl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Medium Density Value Line Devices vector table  
-;*                      for MDK-ARM toolchain.  
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI-CEC
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTCAlarm_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-CEC_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s
deleted file mode 100644
index 9fbc640..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,358 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_xl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x XL-Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-                DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-                DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-                DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-                DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-                DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-                DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-                DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler               ; ADC3
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     SDIO_IRQHandler               ; SDIO
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_2_IRQHandler             [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler     [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler    [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler           [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler           [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM1_BRK_TIM9_IRQHandler      [WEAK]
-                EXPORT  TIM1_UP_TIM10_IRQHandler      [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTCAlarm_IRQHandler           [WEAK]
-                EXPORT  USBWakeUp_IRQHandler          [WEAK]
-                EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]
-                EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]
-                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
-                EXPORT  TIM8_CC_IRQHandler            [WEAK]
-                EXPORT  ADC3_IRQHandler               [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  SDIO_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s
deleted file mode 100644
index cf0531e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s
+++ /dev/null
@@ -1,468 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_cl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR 
-  *                  address.
-  *                - Configure the clock system    
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-.equ  BootRAM, 0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b     LoopCopyDataInit
-
-CopyDataInit:
-  ldr   r3, =_sidata
-  ldr   r3, [r3, r1]
-  str   r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr   r0, =_sdata
-  ldr   r3, =_edata
-  adds  r2, r0, r1
-  cmp   r2, r3
-  bcc   CopyDataInit
-  ldr   r2, =_sbss
-  b     LoopFillZerobss
-
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs  r3, #0
-  str   r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr   r3, = _ebss
-  cmp   r2, r3
-  bcc   FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit  
-/* Call the application's entry point.*/
-  bl    main
-  bx    lr
-.size   Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt. This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-  .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  CAN1_TX_IRQHandler
-  .word  CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_IRQHandler
-  .word  TIM1_UP_IRQHandler
-  .word  TIM1_TRG_COM_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  OTG_FS_WKUP_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_IRQHandler
-  .word  DMA2_Channel5_IRQHandler
-  .word  ETH_IRQHandler
-  .word  ETH_WKUP_IRQHandler
-  .word  CAN2_TX_IRQHandler
-  .word  CAN2_RX0_IRQHandler
-  .word  CAN2_RX1_IRQHandler
-  .word  CAN2_SCE_IRQHandler
-  .word  OTG_FS_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM     /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x Connectivity line Devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*
-*******************************************************************************/
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler  
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler  
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler  
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler  
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler  
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler  
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler  
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler  
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_IRQHandler  
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler  
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak  ETH_IRQHandler  
-  .thumb_set ETH_IRQHandler,Default_Handler
-
-  .weak  ETH_WKUP_IRQHandler  
-  .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
-  .weak  CAN2_TX_IRQHandler  
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX0_IRQHandler  
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX1_IRQHandler  
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN2_SCE_IRQHandler  
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_IRQHandler  
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
- 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s
deleted file mode 100644
index 09291a5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s
+++ /dev/null
@@ -1,465 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x High Density Devices vector table for RIDE7 toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM3210E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit   
-/* Call the application's entry point.*/
-  bl  main
-  bx  lr    
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_IRQHandler
-  .word  TIM1_UP_IRQHandler
-  .word  TIM1_TRG_COM_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_IRQHandler
-  .word  TIM8_UP_IRQHandler
-  .word  TIM8_TRG_COM_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_IRQHandler
-  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_IRQHandler
-  .thumb_set TIM8_UP_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_IRQHandler
-  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s
deleted file mode 100644
index 460f06c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s
+++ /dev/null
@@ -1,442 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd_vl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x High Density Value Line Devices vector table for RIDE7
-  *            toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM32100E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)               
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval None
-*/
-
-  .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b     LoopCopyDataInit
-
-CopyDataInit:
-  ldr   r3, =_sidata
-  ldr   r3, [r3, r1]
-  str   r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr   r0, =_sdata
-  ldr   r3, =_edata
-  adds  r2, r0, r1
-  cmp   r2, r3
-  bcc   CopyDataInit
-  ldr   r2, =_sbss
-  b     LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str   r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr   r3, = _ebss
-  cmp   r2, r3
-  bcc   FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit   
-/* Call the application's entry point.*/
-  bl    main
-  bx    lr    
-.size   Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt. This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-  .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-******************************************************************************/    
-  .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM15_IRQHandler
-  .word  TIM1_UP_TIM16_IRQHandler
-  .word  TIM1_TRG_COM_TIM17_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  CEC_IRQHandler  
-  .word  TIM12_IRQHandler
-  .word  TIM13_IRQHandler
-  .word  TIM14_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_DAC_IRQHandler
-  .word  TIM7_IRQHandler  
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  DMA2_Channel5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density Value line devices. */
-   
-/*******************************************************************************
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler 
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler      
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s
deleted file mode 100644
index d771126..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_ld.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Low Density Devices vector table for RIDE7 toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system  
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */	
-    
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */  
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:	
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-    
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-    
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit  
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr    
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/    
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-	.word	TIM1_TRG_COM_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	0
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	0
-	.word	0
-	.word	SPI1_IRQHandler
-	.word	0
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	0
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler	
-  .word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM        /* @0x108. This is for boot in RAM mode for 
-                          STM32F10x Low Density devices.*/
-   
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*
-*******************************************************************************/
-    
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-	
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-	
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-	
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s
deleted file mode 100644
index 7333b16..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_md.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system 
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */  
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:	
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-    
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-    
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit 	
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr    
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt. This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/    
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-	.word	_estack
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-	.word	TIM1_TRG_COM_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler	
-  .word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32F10x Medium Density devices. */
-   
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*
-*******************************************************************************/
-    
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-	
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-	
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-	
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	TIM4_IRQHandler
-	.thumb_set TIM4_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	USART3_IRQHandler
-	.thumb_set USART3_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s
deleted file mode 100644
index 3bc91f8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,465 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_xl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x XL-Density Devices vector table for RIDE7 toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM3210E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit   
-/* Call the application's entry point.*/
-  bl  main
-  bx  lr    
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s
deleted file mode 100644
index 0c87160..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s
+++ /dev/null
@@ -1,507 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-;* File Name          : startup_stm32f10x_cl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Connectivity line devices vector table for 
-;*                      EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler            ; Window Watchdog
-        DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler          ; Tamper
-        DCD     RTC_IRQHandler             ; RTC
-        DCD     FLASH_IRQHandler           ; Flash
-        DCD     RCC_IRQHandler             ; RCC
-        DCD     EXTI0_IRQHandler           ; EXTI Line 0
-        DCD     EXTI1_IRQHandler           ; EXTI Line 1
-        DCD     EXTI2_IRQHandler           ; EXTI Line 2
-        DCD     EXTI3_IRQHandler           ; EXTI Line 3
-        DCD     EXTI4_IRQHandler           ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-        DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-        DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-        DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-        DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-        DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-        DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler            ; TIM2
-        DCD     TIM3_IRQHandler            ; TIM3
-        DCD     TIM4_IRQHandler            ; TIM4
-        DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-        DCD     SPI1_IRQHandler            ; SPI1
-        DCD     SPI2_IRQHandler            ; SPI2
-        DCD     USART1_IRQHandler          ; USART1
-        DCD     USART2_IRQHandler          ; USART2
-        DCD     USART3_IRQHandler          ; USART3
-        DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler        ; RTC alarm through EXTI line
-        DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     0                          ; Reserved
-        DCD     TIM5_IRQHandler            ; TIM5
-        DCD     SPI3_IRQHandler            ; SPI3
-        DCD     UART4_IRQHandler           ; UART4
-        DCD     UART5_IRQHandler           ; UART5
-        DCD     TIM6_IRQHandler            ; TIM6
-        DCD     TIM7_IRQHandler            ; TIM7
-        DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-        DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-        DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-        DCD     ETH_IRQHandler             ; Ethernet
-        DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
-        DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-        DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-        DCD     OTG_FS_IRQHandler          ; USB OTG FS
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_TX_IRQHandler
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX0_IRQHandler
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_SCE_IRQHandler
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler    
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-OTG_FS_WKUP_IRQHandler
-        B OTG_FS_WKUP_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ETH_IRQHandler
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ETH_WKUP_IRQHandler
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN2_TX_IRQHandler
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN2_RX0_IRQHandler
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN2_RX1_IRQHandler
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN2_SCE_IRQHandler
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-OTG_FS_IRQHandler
-        B OTG_FS_IRQHandler
-
-        END
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s
deleted file mode 100644
index 11ccfe3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s
+++ /dev/null
@@ -1,496 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_hd.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x High Density Devices vector table for EWARM 
-;*                      toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system and the external SRAM 
-;*                        mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR address,
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;     
-  
-    MODULE  ?cstartup
-        
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-       
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler         ; Tamper
-        DCD     RTC_IRQHandler            ; RTC
-        DCD     FLASH_IRQHandler          ; Flash
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
-        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
-        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
-        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
-        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
-        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
-        DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
-        DCD     TIM8_UP_IRQHandler        ; TIM8 Update
-        DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
-        DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
-        DCD     ADC3_IRQHandler           ; ADC3
-        DCD     FSMC_IRQHandler           ; FSMC
-        DCD     SDIO_IRQHandler           ; SDIO
-        DCD     TIM5_IRQHandler           ; TIM5
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel3
-        DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-               
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-
-        PUBWEAK USB_HP_CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_HP_CAN1_TX_IRQHandler
-        B USB_HP_CAN1_TX_IRQHandler
-
-        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_LP_CAN1_RX0_IRQHandler
-        B USB_LP_CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_SCE_IRQHandler
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK USBWakeUp_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBWakeUp_IRQHandler
-        B USBWakeUp_IRQHandler
-
-        PUBWEAK TIM8_BRK_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_BRK_IRQHandler
-        B TIM8_BRK_IRQHandler
-
-        PUBWEAK TIM8_UP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_UP_IRQHandler
-        B TIM8_UP_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_TRG_COM_IRQHandler
-        B TIM8_TRG_COM_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_CC_IRQHandler
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK ADC3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC3_IRQHandler
-        B ADC3_IRQHandler
-
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FSMC_IRQHandler
-        B FSMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel4_5_IRQHandler
-        B DMA2_Channel4_5_IRQHandler
-        
-        
-        END
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s
deleted file mode 100644
index 1c0a3e1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s
+++ /dev/null
@@ -1,366 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Devices vector table for EWARM
-;*                      toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler         ; Tamper
-        DCD     RTC_IRQHandler            ; RTC
-        DCD     FLASH_IRQHandler          ; Flash
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
-        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
-        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
-        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
-        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     0                         ; Reserved
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     0                         ; Reserved
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     0                         ; Reserved
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
-        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-        
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-        
-        PUBWEAK USB_HP_CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_HP_CAN1_TX_IRQHandler
-        B USB_HP_CAN1_TX_IRQHandler
-        
-        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_LP_CAN1_RX0_IRQHandler
-        B USB_LP_CAN1_RX0_IRQHandler
-        
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-        
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_SCE_IRQHandler
-        B CAN1_SCE_IRQHandler
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-        
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-        
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-                      
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK USBWakeUp_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBWakeUp_IRQHandler
-        B USBWakeUp_IRQHandler
-
-        END
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s
deleted file mode 100644
index 85531c5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s
+++ /dev/null
@@ -1,369 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld_vl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Value Line Devices vector table 
-;*                      for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler               ; Window Watchdog
-        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler             ; Tamper
-        DCD     RTC_IRQHandler                ; RTC
-        DCD     FLASH_IRQHandler              ; Flash
-        DCD     RCC_IRQHandler                ; RCC
-        DCD     EXTI0_IRQHandler              ; EXTI Line 0
-        DCD     EXTI1_IRQHandler              ; EXTI Line 1
-        DCD     EXTI2_IRQHandler              ; EXTI Line 2
-        DCD     EXTI3_IRQHandler              ; EXTI Line 3
-        DCD     EXTI4_IRQHandler              ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler               ; ADC1
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-        DCD     TIM1_BRK_TIM15_IRQHandler     ; TIM1 Break and TIM15
-        DCD     TIM1_UP_TIM16_IRQHandler      ; TIM1 Update and TIM16
-        DCD     TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
-        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler               ; TIM2
-        DCD     TIM3_IRQHandler               ; TIM3
-        DCD     0                             ; Reserved
-        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     SPI1_IRQHandler               ; SPI1
-        DCD     0                             ; Reserved
-        DCD     USART1_IRQHandler             ; USART1
-        DCD     USART2_IRQHandler             ; USART2
-        DCD     0                             ; Reserved
-        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-        DCD     CEC_IRQHandler                ; HDMI-CEC
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     TIM6_DAC_IRQHandler           ; TIM6 and DAC underrun
-        DCD     TIM7_IRQHandler               ; TIM7
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM15_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_TIM15_IRQHandler
-        B TIM1_BRK_TIM15_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM16_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_TIM16_IRQHandler
-        B TIM1_UP_TIM16_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_TIM17_IRQHandler
-        B TIM1_TRG_COM_TIM17_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK CEC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CEC_IRQHandler
-        B CEC_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s
deleted file mode 100644
index 7a25707..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s
+++ /dev/null
@@ -1,394 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_md_vl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Medium Density Value Line Devices vector table 
-;*                      for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler               ; Window Watchdog
-        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler             ; Tamper
-        DCD     RTC_IRQHandler                ; RTC
-        DCD     FLASH_IRQHandler              ; Flash
-        DCD     RCC_IRQHandler                ; RCC
-        DCD     EXTI0_IRQHandler              ; EXTI Line 0
-        DCD     EXTI1_IRQHandler              ; EXTI Line 1
-        DCD     EXTI2_IRQHandler              ; EXTI Line 2
-        DCD     EXTI3_IRQHandler              ; EXTI Line 3
-        DCD     EXTI4_IRQHandler              ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler               ; ADC1
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-        DCD     TIM1_BRK_TIM15_IRQHandler     ; TIM1 Break and TIM15
-        DCD     TIM1_UP_TIM16_IRQHandler      ; TIM1 Update and TIM16
-        DCD     TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
-        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler               ; TIM2
-        DCD     TIM3_IRQHandler               ; TIM3
-        DCD     TIM4_IRQHandler               ; TIM4
-        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-        DCD     SPI1_IRQHandler               ; SPI1
-        DCD     SPI2_IRQHandler               ; SPI2
-        DCD     USART1_IRQHandler             ; USART1
-        DCD     USART2_IRQHandler             ; USART2
-        DCD     USART3_IRQHandler             ; USART3
-        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-        DCD     CEC_IRQHandler                ; HDMI-CEC
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved                        
-        DCD     TIM6_DAC_IRQHandler           ; TIM6 and DAC underrun
-        DCD     TIM7_IRQHandler               ; TIM7                
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM15_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_TIM15_IRQHandler
-        B TIM1_BRK_TIM15_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM16_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_TIM16_IRQHandler
-        B TIM1_UP_TIM16_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_TIM17_IRQHandler
-        B TIM1_TRG_COM_TIM17_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK CEC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CEC_IRQHandler
-        B CEC_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s
deleted file mode 100644
index 029761a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,496 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_xl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x XL-Density Devices vector table for EWARM 
-;*                      toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system and the external SRAM 
-;*                        mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR address,
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;     
-  
-    MODULE  ?cstartup
-        
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-       
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler               ; Window Watchdog
-        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler             ; Tamper
-        DCD     RTC_IRQHandler                ; RTC
-        DCD     FLASH_IRQHandler              ; Flash
-        DCD     RCC_IRQHandler                ; RCC
-        DCD     EXTI0_IRQHandler              ; EXTI Line 0
-        DCD     EXTI1_IRQHandler              ; EXTI Line 1
-        DCD     EXTI2_IRQHandler              ; EXTI Line 2
-        DCD     EXTI3_IRQHandler              ; EXTI Line 3
-        DCD     EXTI4_IRQHandler              ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-        DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-        DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-        DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler               ; TIM2
-        DCD     TIM3_IRQHandler               ; TIM3
-        DCD     TIM4_IRQHandler               ; TIM4
-        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-        DCD     SPI1_IRQHandler               ; SPI1
-        DCD     SPI2_IRQHandler               ; SPI2
-        DCD     USART1_IRQHandler             ; USART1
-        DCD     USART2_IRQHandler             ; USART2
-        DCD     USART3_IRQHandler             ; USART3
-        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-        DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-        DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-        DCD     ADC3_IRQHandler               ; ADC3
-        DCD     FSMC_IRQHandler               ; FSMC
-        DCD     SDIO_IRQHandler               ; SDIO
-        DCD     TIM5_IRQHandler               ; TIM5
-        DCD     SPI3_IRQHandler               ; SPI3
-        DCD     UART4_IRQHandler              ; UART4
-        DCD     UART5_IRQHandler              ; UART5
-        DCD     TIM6_IRQHandler               ; TIM6
-        DCD     TIM7_IRQHandler               ; TIM7
-        DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-        DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-               
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-
-        PUBWEAK USB_HP_CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_HP_CAN1_TX_IRQHandler
-        B USB_HP_CAN1_TX_IRQHandler
-
-        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_LP_CAN1_RX0_IRQHandler
-        B USB_LP_CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_SCE_IRQHandler
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_TIM9_IRQHandler
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_TIM10_IRQHandler
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_TIM11_IRQHandler
-        B TIM1_TRG_COM_TIM11_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK USBWakeUp_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBWakeUp_IRQHandler
-        B USBWakeUp_IRQHandler
-
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_BRK_TIM12_IRQHandler
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_UP_TIM13_IRQHandler
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_TRG_COM_TIM14_IRQHandler
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_CC_IRQHandler
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK ADC3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC3_IRQHandler
-        B ADC3_IRQHandler
-
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FSMC_IRQHandler
-        B FSMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel4_5_IRQHandler
-        B DMA2_Channel4_5_IRQHandler
-        
-        
-        END
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
deleted file mode 100644
index 8bf7624..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
+++ /dev/null
@@ -1,8336 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F10x Connectivity line, 
-  *          High density, High density value line, Medium density, 
-  *          Medium density Value line, Low density, Low density Value line 
-  *          and XL-density devices.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x
-  * @{
-  */
-    
-#ifndef __STM32F10x_H
-#define __STM32F10x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
-  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
-  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
-  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
-  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
-  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
-  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
-  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
-  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
-#endif
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
-   where the Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density value line devices are STM32F100xx microcontrollers where the Flash
-   memory density ranges between 16 and 32 Kbytes.
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
-   where the Flash memory density ranges between 64 and 128 Kbytes.
- - Medium-density value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 64 and 128 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.   
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-  */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
- #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-#if !defined  HSE_VALUE
- #ifdef STM32F10X_CL   
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
- #else 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* STM32F10X_CL */
-#endif /* HSE_VALUE */
-
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
-
-#define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
-
-/**
- * @brief STM32F10x Standard Peripheral Library version number
-   */
-#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */                                  
-#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#ifdef STM32F10X_XL
- #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
-#else
- #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
-#endif /* STM32F10X_XL */
-#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
-
-/******  STM32 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
-  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
-  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
-
-#ifdef STM32F10X_LD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    
-#endif /* STM32F10X_LD */  
-
-#ifdef STM32F10X_LD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
-#endif /* STM32F10X_LD_VL */
-
-#ifdef STM32F10X_MD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  
-#endif /* STM32F10X_MD */  
-
-#ifdef STM32F10X_MD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
-#endif /* STM32F10X_MD_VL */
-
-#ifdef STM32F10X_HD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
-  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
-  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-#endif /* STM32F10X_HD */  
-
-#ifdef STM32F10X_HD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
-  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
-  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
-                                             mapped at position 60 only if the MISC_REMAP bit in 
-                                             the AFIO_MAPR2 register is set)                      */       
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_XL
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-#endif /* STM32F10X_XL */  
-
-#ifdef STM32F10X_CL
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
-  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
-#endif /* STM32F10X_CL */     
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32f10x.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
-#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
-#define HSE_Value            HSE_VALUE
-#define HSI_Value            HSI_VALUE
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;
-  __IO uint32_t CR1;
-  __IO uint32_t CR2;
-  __IO uint32_t SMPR1;
-  __IO uint32_t SMPR2;
-  __IO uint32_t JOFR1;
-  __IO uint32_t JOFR2;
-  __IO uint32_t JOFR3;
-  __IO uint32_t JOFR4;
-  __IO uint32_t HTR;
-  __IO uint32_t LTR;
-  __IO uint32_t SQR1;
-  __IO uint32_t SQR2;
-  __IO uint32_t SQR3;
-  __IO uint32_t JSQR;
-  __IO uint32_t JDR1;
-  __IO uint32_t JDR2;
-  __IO uint32_t JDR3;
-  __IO uint32_t JDR4;
-  __IO uint32_t DR;
-} ADC_TypeDef;
-
-/** 
-  * @brief Backup Registers  
-  */
-
-typedef struct
-{
-  uint32_t  RESERVED0;
-  __IO uint16_t DR1;
-  uint16_t  RESERVED1;
-  __IO uint16_t DR2;
-  uint16_t  RESERVED2;
-  __IO uint16_t DR3;
-  uint16_t  RESERVED3;
-  __IO uint16_t DR4;
-  uint16_t  RESERVED4;
-  __IO uint16_t DR5;
-  uint16_t  RESERVED5;
-  __IO uint16_t DR6;
-  uint16_t  RESERVED6;
-  __IO uint16_t DR7;
-  uint16_t  RESERVED7;
-  __IO uint16_t DR8;
-  uint16_t  RESERVED8;
-  __IO uint16_t DR9;
-  uint16_t  RESERVED9;
-  __IO uint16_t DR10;
-  uint16_t  RESERVED10; 
-  __IO uint16_t RTCCR;
-  uint16_t  RESERVED11;
-  __IO uint16_t CR;
-  uint16_t  RESERVED12;
-  __IO uint16_t CSR;
-  uint16_t  RESERVED13[5];
-  __IO uint16_t DR11;
-  uint16_t  RESERVED14;
-  __IO uint16_t DR12;
-  uint16_t  RESERVED15;
-  __IO uint16_t DR13;
-  uint16_t  RESERVED16;
-  __IO uint16_t DR14;
-  uint16_t  RESERVED17;
-  __IO uint16_t DR15;
-  uint16_t  RESERVED18;
-  __IO uint16_t DR16;
-  uint16_t  RESERVED19;
-  __IO uint16_t DR17;
-  uint16_t  RESERVED20;
-  __IO uint16_t DR18;
-  uint16_t  RESERVED21;
-  __IO uint16_t DR19;
-  uint16_t  RESERVED22;
-  __IO uint16_t DR20;
-  uint16_t  RESERVED23;
-  __IO uint16_t DR21;
-  uint16_t  RESERVED24;
-  __IO uint16_t DR22;
-  uint16_t  RESERVED25;
-  __IO uint16_t DR23;
-  uint16_t  RESERVED26;
-  __IO uint16_t DR24;
-  uint16_t  RESERVED27;
-  __IO uint16_t DR25;
-  uint16_t  RESERVED28;
-  __IO uint16_t DR26;
-  uint16_t  RESERVED29;
-  __IO uint16_t DR27;
-  uint16_t  RESERVED30;
-  __IO uint16_t DR28;
-  uint16_t  RESERVED31;
-  __IO uint16_t DR29;
-  uint16_t  RESERVED32;
-  __IO uint16_t DR30;
-  uint16_t  RESERVED33; 
-  __IO uint16_t DR31;
-  uint16_t  RESERVED34;
-  __IO uint16_t DR32;
-  uint16_t  RESERVED35;
-  __IO uint16_t DR33;
-  uint16_t  RESERVED36;
-  __IO uint16_t DR34;
-  uint16_t  RESERVED37;
-  __IO uint16_t DR35;
-  uint16_t  RESERVED38;
-  __IO uint16_t DR36;
-  uint16_t  RESERVED39;
-  __IO uint16_t DR37;
-  uint16_t  RESERVED40;
-  __IO uint16_t DR38;
-  uint16_t  RESERVED41;
-  __IO uint16_t DR39;
-  uint16_t  RESERVED42;
-  __IO uint16_t DR40;
-  uint16_t  RESERVED43;
-  __IO uint16_t DR41;
-  uint16_t  RESERVED44;
-  __IO uint16_t DR42;
-  uint16_t  RESERVED45;    
-} BKP_TypeDef;
-  
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;
-  __IO uint32_t TDTR;
-  __IO uint32_t TDLR;
-  __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;
-  __IO uint32_t RDTR;
-  __IO uint32_t RDLR;
-  __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1;
-  __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t MCR;
-  __IO uint32_t MSR;
-  __IO uint32_t TSR;
-  __IO uint32_t RF0R;
-  __IO uint32_t RF1R;
-  __IO uint32_t IER;
-  __IO uint32_t ESR;
-  __IO uint32_t BTR;
-  uint32_t  RESERVED0[88];
-  CAN_TxMailBox_TypeDef sTxMailBox[3];
-  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
-  uint32_t  RESERVED1[12];
-  __IO uint32_t FMR;
-  __IO uint32_t FM1R;
-  uint32_t  RESERVED2;
-  __IO uint32_t FS1R;
-  uint32_t  RESERVED3;
-  __IO uint32_t FFA1R;
-  uint32_t  RESERVED4;
-  __IO uint32_t FA1R;
-  uint32_t  RESERVED5[8];
-#ifndef STM32F10X_CL
-  CAN_FilterRegister_TypeDef sFilterRegister[14];
-#else
-  CAN_FilterRegister_TypeDef sFilterRegister[28];
-#endif /* STM32F10X_CL */  
-} CAN_TypeDef;
-
-/** 
-  * @brief Consumer Electronics Control (CEC)
-  */
-typedef struct
-{
-  __IO uint32_t CFGR;
-  __IO uint32_t OAR;
-  __IO uint32_t PRES;
-  __IO uint32_t ESR;
-  __IO uint32_t CSR;
-  __IO uint32_t TXD;
-  __IO uint32_t RXD;  
-} CEC_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;
-  __IO uint8_t  IDR;
-  uint8_t   RESERVED0;
-  uint16_t  RESERVED1;
-  __IO uint32_t CR;
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t SWTRIGR;
-  __IO uint32_t DHR12R1;
-  __IO uint32_t DHR12L1;
-  __IO uint32_t DHR8R1;
-  __IO uint32_t DHR12R2;
-  __IO uint32_t DHR12L2;
-  __IO uint32_t DHR8R2;
-  __IO uint32_t DHR12RD;
-  __IO uint32_t DHR12LD;
-  __IO uint32_t DHR8RD;
-  __IO uint32_t DOR1;
-  __IO uint32_t DOR2;
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  __IO uint32_t SR;
-#endif
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;
-  __IO uint32_t CR;	
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;
-  __IO uint32_t CNDTR;
-  __IO uint32_t CPAR;
-  __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;
-  __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-       uint32_t RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-       uint32_t RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-       uint32_t RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-       uint32_t RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-       uint32_t RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-       uint32_t RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-       uint32_t RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-       uint32_t RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-       uint32_t RESERVED8[567];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-       uint32_t RESERVED9[9];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;
-  __IO uint32_t EMR;
-  __IO uint32_t RTSR;
-  __IO uint32_t FTSR;
-  __IO uint32_t SWIER;
-  __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;
-  __IO uint32_t KEYR;
-  __IO uint32_t OPTKEYR;
-  __IO uint32_t SR;
-  __IO uint32_t CR;
-  __IO uint32_t AR;
-  __IO uint32_t RESERVED;
-  __IO uint32_t OBR;
-  __IO uint32_t WRPR;
-#ifdef STM32F10X_XL
-  uint32_t RESERVED1[8]; 
-  __IO uint32_t KEYR2;
-  uint32_t RESERVED2;   
-  __IO uint32_t SR2;
-  __IO uint32_t CR2;
-  __IO uint32_t AR2; 
-#endif /* STM32F10X_XL */  
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-  
-typedef struct
-{
-  __IO uint16_t RDP;
-  __IO uint16_t USER;
-  __IO uint16_t Data0;
-  __IO uint16_t Data1;
-  __IO uint16_t WRP0;
-  __IO uint16_t WRP1;
-  __IO uint16_t WRP2;
-  __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;
-  __IO uint32_t SR2;
-  __IO uint32_t PMEM2;
-  __IO uint32_t PATT2;
-  uint32_t  RESERVED0;   
-  __IO uint32_t ECCR2; 
-} FSMC_Bank2_TypeDef;  
-
-/** 
-  * @brief Flexible Static Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR3;
-  __IO uint32_t SR3;
-  __IO uint32_t PMEM3;
-  __IO uint32_t PATT3;
-  uint32_t  RESERVED0;   
-  __IO uint32_t ECCR3; 
-} FSMC_Bank3_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;
-  __IO uint32_t SR4;
-  __IO uint32_t PMEM4;
-  __IO uint32_t PATT4;
-  __IO uint32_t PIO4; 
-} FSMC_Bank4_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t CRL;
-  __IO uint32_t CRH;
-  __IO uint32_t IDR;
-  __IO uint32_t ODR;
-  __IO uint32_t BSRR;
-  __IO uint32_t BRR;
-  __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/** 
-  * @brief Alternate Function I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t EVCR;
-  __IO uint32_t MAPR;
-  __IO uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  __IO uint32_t MAPR2;  
-} AFIO_TypeDef;
-/** 
-  * @brief Inter Integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t OAR1;
-  uint16_t  RESERVED2;
-  __IO uint16_t OAR2;
-  uint16_t  RESERVED3;
-  __IO uint16_t DR;
-  uint16_t  RESERVED4;
-  __IO uint16_t SR1;
-  uint16_t  RESERVED5;
-  __IO uint16_t SR2;
-  uint16_t  RESERVED6;
-  __IO uint16_t CCR;
-  uint16_t  RESERVED7;
-  __IO uint16_t TRISE;
-  uint16_t  RESERVED8;
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;
-  __IO uint32_t PR;
-  __IO uint32_t RLR;
-  __IO uint32_t SR;
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CFGR;
-  __IO uint32_t CIR;
-  __IO uint32_t APB2RSTR;
-  __IO uint32_t APB1RSTR;
-  __IO uint32_t AHBENR;
-  __IO uint32_t APB2ENR;
-  __IO uint32_t APB1ENR;
-  __IO uint32_t BDCR;
-  __IO uint32_t CSR;
-
-#ifdef STM32F10X_CL  
-  __IO uint32_t AHBRSTR;
-  __IO uint32_t CFGR2;
-#endif /* STM32F10X_CL */ 
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
-  uint32_t RESERVED0;
-  __IO uint32_t CFGR2;
-#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint16_t CRH;
-  uint16_t  RESERVED0;
-  __IO uint16_t CRL;
-  uint16_t  RESERVED1;
-  __IO uint16_t PRLH;
-  uint16_t  RESERVED2;
-  __IO uint16_t PRLL;
-  uint16_t  RESERVED3;
-  __IO uint16_t DIVH;
-  uint16_t  RESERVED4;
-  __IO uint16_t DIVL;
-  uint16_t  RESERVED5;
-  __IO uint16_t CNTH;
-  uint16_t  RESERVED6;
-  __IO uint16_t CNTL;
-  uint16_t  RESERVED7;
-  __IO uint16_t ALRH;
-  uint16_t  RESERVED8;
-  __IO uint16_t ALRL;
-  uint16_t  RESERVED9;
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLKCR;
-  __IO uint32_t ARG;
-  __IO uint32_t CMD;
-  __I uint32_t RESPCMD;
-  __I uint32_t RESP1;
-  __I uint32_t RESP2;
-  __I uint32_t RESP3;
-  __I uint32_t RESP4;
-  __IO uint32_t DTIMER;
-  __IO uint32_t DLEN;
-  __IO uint32_t DCTRL;
-  __I uint32_t DCOUNT;
-  __I uint32_t STA;
-  __IO uint32_t ICR;
-  __IO uint32_t MASK;
-  uint32_t  RESERVED0[2];
-  __I uint32_t FIFOCNT;
-  uint32_t  RESERVED1[13];
-  __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t SR;
-  uint16_t  RESERVED2;
-  __IO uint16_t DR;
-  uint16_t  RESERVED3;
-  __IO uint16_t CRCPR;
-  uint16_t  RESERVED4;
-  __IO uint16_t RXCRCR;
-  uint16_t  RESERVED5;
-  __IO uint16_t TXCRCR;
-  uint16_t  RESERVED6;
-  __IO uint16_t I2SCFGR;
-  uint16_t  RESERVED7;
-  __IO uint16_t I2SPR;
-  uint16_t  RESERVED8;  
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t SMCR;
-  uint16_t  RESERVED2;
-  __IO uint16_t DIER;
-  uint16_t  RESERVED3;
-  __IO uint16_t SR;
-  uint16_t  RESERVED4;
-  __IO uint16_t EGR;
-  uint16_t  RESERVED5;
-  __IO uint16_t CCMR1;
-  uint16_t  RESERVED6;
-  __IO uint16_t CCMR2;
-  uint16_t  RESERVED7;
-  __IO uint16_t CCER;
-  uint16_t  RESERVED8;
-  __IO uint16_t CNT;
-  uint16_t  RESERVED9;
-  __IO uint16_t PSC;
-  uint16_t  RESERVED10;
-  __IO uint16_t ARR;
-  uint16_t  RESERVED11;
-  __IO uint16_t RCR;
-  uint16_t  RESERVED12;
-  __IO uint16_t CCR1;
-  uint16_t  RESERVED13;
-  __IO uint16_t CCR2;
-  uint16_t  RESERVED14;
-  __IO uint16_t CCR3;
-  uint16_t  RESERVED15;
-  __IO uint16_t CCR4;
-  uint16_t  RESERVED16;
-  __IO uint16_t BDTR;
-  uint16_t  RESERVED17;
-  __IO uint16_t DCR;
-  uint16_t  RESERVED18;
-  __IO uint16_t DMAR;
-  uint16_t  RESERVED19;
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint16_t SR;
-  uint16_t  RESERVED0;
-  __IO uint16_t DR;
-  uint16_t  RESERVED1;
-  __IO uint16_t BRR;
-  uint16_t  RESERVED2;
-  __IO uint16_t CR1;
-  uint16_t  RESERVED3;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED4;
-  __IO uint16_t CR3;
-  uint16_t  RESERVED5;
-  __IO uint16_t GTPR;
-  uint16_t  RESERVED6;
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CFR;
-  __IO uint32_t SR;
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
-
-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
-
-#define SDIO_BASE             (PERIPH_BASE + 0x18000)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
-
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
-
-#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
-
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
-#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
-
-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define BKP                 ((BKP_TypeDef *) BKP_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
-#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
-#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
-#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
-#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
-#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
-#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
-#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Backup registers                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for BKP_DR1 register  ********************/
-#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR2 register  ********************/
-#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR3 register  ********************/
-#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR4 register  ********************/
-#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR5 register  ********************/
-#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR6 register  ********************/
-#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR7 register  ********************/
-#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR8 register  ********************/
-#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR9 register  ********************/
-#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR10 register  *******************/
-#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR11 register  *******************/
-#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR12 register  *******************/
-#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR13 register  *******************/
-#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR14 register  *******************/
-#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR15 register  *******************/
-#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR16 register  *******************/
-#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR17 register  *******************/
-#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/******************  Bit definition for BKP_DR18 register  ********************/
-#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR19 register  *******************/
-#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR20 register  *******************/
-#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR21 register  *******************/
-#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR22 register  *******************/
-#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR23 register  *******************/
-#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR24 register  *******************/
-#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR25 register  *******************/
-#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR26 register  *******************/
-#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR27 register  *******************/
-#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR28 register  *******************/
-#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR29 register  *******************/
-#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR30 register  *******************/
-#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR31 register  *******************/
-#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR32 register  *******************/
-#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR33 register  *******************/
-#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR34 register  *******************/
-#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR35 register  *******************/
-#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR36 register  *******************/
-#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR37 register  *******************/
-#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR38 register  *******************/
-#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR39 register  *******************/
-#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR40 register  *******************/
-#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR41 register  *******************/
-#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR42 register  *******************/
-#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/******************  Bit definition for BKP_RTCCR register  *******************/
-#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
-#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
-#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
-#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
-
-/********************  Bit definition for BKP_CR register  ********************/
-#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
-#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
-
-/*******************  Bit definition for BKP_CSR register  ********************/
-#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
-#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
-#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
-#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
-#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-#ifdef STM32F10X_CL
- #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
- #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
- #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
- #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
-#endif /* STM32F10X_CL */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
-#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
-#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
-#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#ifdef STM32F10X_CL
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
- #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
- 
- #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
- 
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
- #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
- #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
- #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
- #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
- #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
- #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
- #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
- #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
- #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
- #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
- #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
- #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
- #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
- #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
- #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-#else
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
- #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
- #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
- #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
- #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
- #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
- #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
- #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
- #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
- #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
-
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
- #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-#endif /* STM32F10X_CL */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-#ifdef STM32F10X_CL
- #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
- #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
- #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
- #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
- #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
- #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
-#endif /* STM32F10X_CL */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
-#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
-#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
-#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
-#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
-#endif
-
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
- #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
- #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
- #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
- #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
-#endif
-
-#ifdef STM32F10X_XL
- #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
- #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
- #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
-#endif /* STM32F10X_XL */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
-#endif
-
-#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
- #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
- #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
- #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
- #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
-#endif
-
-#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
- #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
- #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
- #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
- #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
- #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
- #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
- #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
- #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
- #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
- #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
- #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
-#endif
-
-#if defined  (STM32F10X_HD_VL)
- #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
- #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
- #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
- #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
- #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
- #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
- #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
-#endif
-
-#ifdef STM32F10X_CL
- #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
- #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
- #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
-#endif /* STM32F10X_XL */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
-
-#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
- #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
-#endif
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
- #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
-#endif
-
-#ifdef STM32F10X_CL
- #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
- #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
- #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
- #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
-#endif /* STM32F10X_CL */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
-#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
-#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
-#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
-#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
-#endif
-
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
- #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
- #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
- #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
- #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
-#endif
-
-#ifdef STM32F10X_XL
- #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
- #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
- #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
-#endif
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
-#endif
-
-#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
- #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
- #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
- #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
- #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
-#endif
-
-#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
- #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
- #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
- #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
- #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
- #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
- #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
- #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
- #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
- #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
- #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
- #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
-#endif
-
-#ifdef STM32F10X_HD_VL
- #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
- #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
- #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
- #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
- #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
- #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
- #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_CL
- #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
- #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
- #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
-#endif /* STM32F10X_XL */
-
-/*******************  Bit definition for RCC_BDCR register  *******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/*******************  Bit definition for RCC_CSR register  ********************/  
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-#ifdef STM32F10X_CL
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
- #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
- #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
- #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
- #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
- #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*!< PREDIV2 configuration */
- #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
- #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
- #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
-
-/*!< PLL2MUL configuration */
- #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
- #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
- #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
- #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
- #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
- #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
- #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
- #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
- #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
- #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
- #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
- #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
- #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
-
-/*!< PLL3MUL configuration */
- #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
- #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
- #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
- #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
- #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
- #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
- #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
- #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
- #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
- #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
- #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
- #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
- #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
-
- #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
- #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
- #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
- #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
- #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
- #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
- #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
- #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-#endif
- 
-/******************************************************************************/
-/*                                                                            */
-/*                General Purpose and Alternate Function I/O                  */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for GPIO_CRL register  *******************/
-#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
-
-#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
-
-#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
-
-/*******************  Bit definition for GPIO_CRH register  *******************/
-#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
-
-#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
-
-#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
-
-/*!<******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
-
-/*******************  Bit definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
-
-/******************  Bit definition for GPIO_BSRR register  *******************/
-#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
-
-/*******************  Bit definition for GPIO_BRR register  *******************/
-#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
-
-/******************  Bit definition for GPIO_LCKR register  *******************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for AFIO_EVCR register  *******************/
-#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
-#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
-#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
-#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
-#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
-#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
-
-/******************  Bit definition for AFIO_MAPR register  *******************/
-#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-#ifdef STM32F10X_CL
-/*!< ETH_REMAP configuration */
- #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
-
-/*!< CAN2_REMAP configuration */
- #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
-
-/*!< MII_RMII_SEL configuration */
- #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
-
-/*!< SPI3_REMAP configuration */
- #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
-
-/*!< TIM2ITR1_IREMAP configuration */
- #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
-
-/*!< PTP_PPS_REMAP configuration */
- #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
-#endif
-
-/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
-#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */  
-#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
-
-/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
-#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */  
-#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
-
-/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
-#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */  
-#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
-
-/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
-#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */  
-#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/******************  Bit definition for AFIO_MAPR2 register  ******************/
-#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
-#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
-#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
-#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
-#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
-#endif
-
-#ifdef STM32F10X_HD_VL
-#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
-#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
-#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
-#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
-#endif
-
-#ifdef STM32F10X_XL 
-/******************  Bit definition for AFIO_MAPR2 register  ******************/
-#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
-#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
-#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
-#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
-#endif
-
-/******************************************************************************/
-/*                                                                            */
-/*                               SystemTick                                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  Nested Vectored Interrupt Controller                      */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR1 register  *******************/
-#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
-#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR2 register  *******************/
-#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR3 register  *******************/
-#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*!<******************  Bit definition for DMA_CCR4 register  *******************/
-#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CCR5 register  *******************/
-#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/*******************  Bit definition for DMA_CCR6 register  *******************/
-#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR7 register  *******************/
-#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
-#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
-#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
-#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    CEC                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for CEC_CFGR register  ******************/
-#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
-#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
-#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
-#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
-
-/********************  Bit definition for CEC_OAR register  ******************/
-#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
-#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
-#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
-#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
-#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
-
-/********************  Bit definition for CEC_PRES register  ******************/
-#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
-
-/********************  Bit definition for CEC_ESR register  ******************/
-#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
-#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
-#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
-#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
-#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
-#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
-#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
-
-/********************  Bit definition for CEC_CSR register  ******************/
-#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
-#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
-#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
-#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
-#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
-#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
-#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
-#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
-
-/********************  Bit definition for CEC_TXD register  ******************/
-#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
-
-/********************  Bit definition for CEC_RXD register  ******************/
-#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Real-Time Clock                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for RTC_CRH register  ********************/
-#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
-#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
-#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
-
-/*******************  Bit definition for RTC_CRL register  ********************/
-#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
-#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
-#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
-#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
-#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
-#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
-
-/*******************  Bit definition for RTC_PRLH register  *******************/
-#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
-
-/*******************  Bit definition for RTC_PRLL register  *******************/
-#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
-
-/*******************  Bit definition for RTC_DIVH register  *******************/
-#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
-
-/*******************  Bit definition for RTC_DIVL register  *******************/
-#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
-
-/*******************  Bit definition for RTC_CNTH register  *******************/
-#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
-
-/*******************  Bit definition for RTC_CNTL register  *******************/
-#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
-
-/*******************  Bit definition for RTC_ALRH register  *******************/
-#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
-
-/*******************  Bit definition for RTC_ALRL register  *******************/
-#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
-#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
-#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
-#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
-#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
-
-#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
-#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
-#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
-#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
-#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
-#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
-#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
-#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                   USB Device FS                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
-#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
-#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
-#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
-#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
-#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
-#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
-#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
-#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
-
-/*!< Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
-#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
-#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
-
-#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
-#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
-#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
-#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
-
-#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
-#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
-#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for FLASH_RDP register  *******************/
-#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for FLASH_USER register  ******************/
-#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for FLASH_Data0 register  *****************/
-#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
-#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_Data1 register  *****************/
-#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
-#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_WRP0 register  ******************/
-#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP1 register  ******************/
-#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-#ifdef STM32F10X_CL
-/******************************************************************************/
-/*                Ethernet MAC Registers bits definitions                     */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
-#endif /* STM32F10X_CL */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f10x_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm
deleted file mode 100644
index 36e0446..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm
+++ /dev/null
@@ -1,243 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Debug Support</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
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-               line-height: 120%; font-style: normal }
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-/*-----------------------------------------------------------
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-               padding-bottom: 2pt }
-/*-----------------------------------------------------------
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--->
-
-</style>
-</head>
-
-<body>
-
-<h1>CMSIS Debug Support</h1>
-
-<hr>
-
-<h2>Cortex-M3 ITM Debug Access</h2>
-<p>
-  The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with 
-  the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 
-  32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM 
-  communication channels are used by CMSIS to output the following information:
-</p>
-<ul>
-	<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
-	<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
-</ul>
-
-<h2>Debug IN / OUT functions</h2>
-<p>CMSIS provides following debug functions:</p>
-<ul>
-	<li>ITM_SendChar (uses ITM channel 0)</li>
-	<li>ITM_ReceiveChar (uses global variable)</li>
-	<li>ITM_CheckChar (uses global variable)</li>
-</ul>
-
-<h3>ITM_SendChar</h3>
-<p>
-  <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from 
-  the microcontroller system to the debug system. <br>
-  Only a 8 bit value is transmitted.
-</p>
-<pre>
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  /* check if debugger connected and ITM channel enabled for tracing */
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &amp;&amp;
-      (ITM-&gt;TCR & ITM_TCR_ITMENA)                  &amp;&amp;
-      (ITM-&gt;TER & (1UL &lt;&lt; 0))  ) 
-  {
-    while (ITM-&gt;PORT[0].u32 == 0);
-    ITM-&gt;PORT[0].u8 = (uint8_t)ch;
-  }  
-  return (ch);
-}</pre>
-
-<h3>ITM_ReceiveChar</h3>
-<p>
-  ITM communication channel is only capable for OUT direction. For IN direction
-  a globel variable is used. A simple mechansim detects if a character is received.
-  The project to test need to be build with debug information.
-</p>
-
-<p>
-  The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
-  to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
-</p>
-<pre>
-extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
-</pre>
-<p>
-  A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
-  or contains a valid value.
-</p>
-<pre>
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-</pre>
-<p>
-  <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
-  It returns the received character or '-1' if no character was available.
-</p>
-<pre>
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-</pre>
-
-<h3>ITM_CheckChar</h3>
-<p>
-  <strong>ITM_CheckChar</strong> is used to check if a character is received.
-</p>
-<pre>
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}</pre>
-
-
-<h2>ITM Debug Support in uVision</h2>
-<p>
-  uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to 
-  display the debug data.
-</p>
-<p>Direction microcontroller system -&gt; uVision:</p>
-<ul>
-  <li>
-    Characters received via ITM communication channel 0 are written in a printf style
-    to <strong>Debug (printf) Viewer</strong> window.
-  </li>
-</ul>
-
-<p>Direction uVision -&gt; microcontroller system:</p>
-<ul>
-  <li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
-  <li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
-  <li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
-  <li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
-  </li>
-</ul>
-
-<h2>RTX Kernel awareness in uVision</h2>
-<p>
-  uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
-  No format overhead is necessary.<br>
-  uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
-  to ITM communication channel 31.
-</p>
-
-<p>Following RTX events are traced:</p>
-<ul>
-  <li>Task Create / Delete event
-    <ol>
-      <li>32 bit access. Task start address is transmitted</li>
-      <li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
-          High byte holds Create/Delete flag, Low byte holds TASK ID.
-      </li>
-    </ol>
-  </li>
-  <li>Task switch event
-    <ol>
-      <li>8 bit access. Task ID of current task is transmitted</li>
-    </ol>
-  </li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
-  <li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
-  </li>
-</ul>
-
-
-<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
-
-<hr>
-
-<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
-All rights reserved.<br>
-Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
-</p>
-
-</body>
-
-</html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm
deleted file mode 100644
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--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Changes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
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-body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: 
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-               text-align: Center; margin-right: 3 }
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-               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; 
-               padding: 6 }
-h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: 
-               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
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-               margin-left: 24; margin-right: 24 }
-ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
-ol           { margin-top: 6pt; margin-bottom: 0 }
-li           { clear: both; margin-bottom: 6pt }
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-               bottom; padding-right: 6pt }
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-.TinyT       { font-size: 8pt; text-align: Center }
-code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; 
-               line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------
-Notes
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-p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------
-Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand      { text-decoration: none; margin-bottom: 3pt }
-img.expand   { border-style: none; border-width: medium }
-div.expand   { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
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-table.wh     { width: 100% }
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-               6pt }
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-td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; 
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-               padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>Changes to CMSIS version V1.20</h1>
-
-<hr>
-
-<h2>1. Removed CMSIS Middelware packages</h2>
-<p>
-  CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-</p>
-
-<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
-<p>
-  The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
-  because the variable holds the clock value at which the core is running.
-</p>
-
-<h2>3. Changed startup concept</h2>
-<p>
-  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 
-  from main) has the weakness that it does not work for controllers which need a already 
-  configuerd clock system to configure the external memory controller.
-</p>
-
-<h3>Changed startup concept</h3>
-<ul>
-  <li>
-    SystemInit() is called from startup file before <strong>premain</strong>.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> configures the clock system and also configures
-    an existing external memory controller.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> must not use global variables.
-  </li>
-  <li>
-    <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
-  </li>
-  <li>
-    Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
-   <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
-   and must be called whenever the core clock is changed.<br>
-   <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
-   the current core clock.
-  </li>
-</ul>
-      
-
-<h2>4. Advanced Debug Functions</h2>
-<p>
-  ITM communication channel is only capable for OUT direction. To allow also communication for
-  IN direction a simple concept is provided.
-</p>
-<ul>
-  <li>
-    Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
-  </li>
-  <li>
-    Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
-  </li>
-  <li>
-    Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
-  </li>
-</ul>
-
-<p>
-  For detailed explanation see file <strong>CMSIS debug support.htm</strong>. 
-</p>
-
-
-<h2>5. Core Register Bit Definitions</h2>
-<p>
-  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
-  defines correspond with the Cortex-M Technical Reference Manual.  
-</p>
-<p>
-  e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
-
-<h2>7. DoxyGen Tags</h2>
-<p>
-  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
-  using DoxyGen.
-</p>
-
-<h2>8. Folder Structure</h2>
-<p>
-  The folder structure is changed to differentiate the single support packages.
-</p>
-
-  <ul>
-    <li>CM0</li>
-    <li>CM3
-       <ul>
-         <li>CoreSupport</li>
-         <li>DeviceSupport</li>
-           <ul>
-             <li>Vendor 
-               <ul>
-                 <li>Device
-                   <ul>
-                      <li>Startup
-                        <ul>
-                          <li>Toolchain</li>
-                          <li>Toolchain</li>
-                          <li>...</li>
-                        </ul>
-                      </li>
-                   </ul>
-                 </li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Vendor</li>
-             <li>...</li>
-           </ul>
-         </li>
-         <li>Example
-           <ul>
-             <li>Toolchain 
-               <ul>
-                 <li>Device</li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Toolchain</li>
-             <li>...</li>
-           </ul>
-         </li>
-       </ul>
-    </li>
-     
-    <li>Documentation</li>
-  </ul>
-
-<h2>9. Open Points</h2>
-<p>
-  Following points need to be clarified and solved:
-</p>
-<ul>
-  <li>
-    <p>
-      Equivalent C and Assembler startup files.
-    </p>
-    <p>
-      Is there a need for having C startup files although assembler startup files are
-      very efficient and do not need to be changed?
-    <p/>
-  </li>
-  <li>
-    <p>
-      Placing of HEAP in external RAM.
-    </p>
-    <p>
-      It must be possible to place HEAP in external RAM if the device supports an 
-      external memory controller.
-    </p>
-  </li>
-  <li>
-    <p>
-      Placing of STACK /HEAP.
-    </p>
-    <p>
-      STACK should always be placed at the end of internal RAM.
-    </p>
-    <p>
-      If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-    </p>
-  </li>
-  <li>
-    <p>
-      Removing core_cm3.c and core_cm0.c.
-    </p>
-    <p>
-      On a long term the functions in core_cm3.c and core_cm0.c must be replaced with 
-      appropriate compiler intrinsics.
-    </p>
-  </li>
-</ul>
-
-
-<h2>10. Limitations</h2>
-<p>
-  The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
-  No <strong>C startup files</strong> for ARM toolchain are provided. 
- </li>
- <li>
-  No <strong>C startup files</strong> for GNU toolchain are provided. 
- </li>
- <li>
-  No <strong>C startup files</strong> for IAR toolchain are provided. 
- </li>
- <li>
-  No <strong>Tasking</strong> projects are provided yet. 
- </li>
-</ul>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc
deleted file mode 100644
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--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc
+++ /dev/null
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-            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>
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-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x Standard Peripherals Library Drivers
-(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr>
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
-Drivers update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;">
-</span>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
-Peripherals Library Drivers&nbsp; update History</span></h2><br>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c files:</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 5 new functions</span></li>
-                <ul>
-                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">3
-new functions controlling the counter errors: CAN_GetLastErrorCode(),
-CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().</span></li>
-                </ul>
-                <ul>
-                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to select the CAN operating mode: CAN_OperatingModeRequest().</span></li>
-                </ul>
-                <ul>
-                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to support CAN TT mode: CAN_TTComModeCmd().</span><span style="font-size: 10pt; font-family: Verdana;"><br>
-  </span></li>
-                </ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN_TransmitStatus() function updated to support all CAN transmit intermediate states<br>
-                  </span></li>
-              </ul>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c files:</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 1 new function:</span></li>
-                <ul>
-                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_NACKPositionConfig():
-This function configures the same bit (POS) as I2C_PECPositionConfig()
-but is intended to be used in I2C mode while I2C_PECPositionConfig() is
-intended to used in SMBUS mode.</span></li>
-                </ul>
-              </ul>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c files:</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the <span style="font-style: italic;">TIM_DMABurstLength_xBytes</span> definitions to <span style="font-style: italic;">TIM_DMABurstLength_xTansfers</span><br>
-                  </span></li>
-              </ul>
-
-
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
-            <ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>
-            </ul>
-
-            <ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-            
-            <ul style="margin-top: 0in;" type="disc">
-
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>
-</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>
-                  </span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()
-and CAN_ClearFlag() functions: updated to support new flags (were not
-supported in previous version). These flags are:&nbsp; CAN_FLAG_RQCP0,
-CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,
-CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,&nbsp;&nbsp; CAN_FLAG_FOV0,
-CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>
-                  </span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()
-function: add a check of the interrupt enable bit before getting the
-status of corresponding interrupt pending bit. <br>
-                  </span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>
-                  </span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>
-                  </span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>
-            
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
-- 04/16/2010</span></h3>
-
-<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>
-<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:
-updated to support Bank2 of XL-density devices (up to 1MByte of Flash
-memory). For more details, refer to the description provided within
-stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>
-function: updated to check whether the last event contains the
-I2C_EVENT&nbsp; (instead of check whether the last event is equal to
-I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add
-detailed description of I2C events and how to manage them using the
-functions provided by this driver. For more information, refer to
-stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h:&nbsp;</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br>&nbsp;
-#define
-SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp; ((uint32_t)0x00000000)<br>&nbsp; #define
-SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-((uint32_t)0x00000001)<br>by<br>&nbsp; #define
-SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp; ((uint32_t)0x00000001)<br>&nbsp; #define
-SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-((uint32_t)0x00000000)</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost
-peripherals drivers were updated to support Value
-line devices features</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-</ul>
-<ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
-firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART
-driver: add support for Oversampling by 8 mode and onebit method. 2
-functions has been added: USART_OverSampling8Cmd() and
-USART_OneBitMethodCmd().<br>
-                </span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC
-driver: add new functions handling the DAC under run feature:
-DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()
-and DAC_ClearITPendingBit().</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>
-                </span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH
-driver: the FLASH_EraseOptionBytes() function updated. This is now just
-erasing the option bytes without modifying the RDP status either
-enabled or disabled.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR
-driver: the PWR_EnterSTOPMode() function updated. When woken up from
-STOP mode, this function resets again the SLEEPDEEP bit in the
-Cortex-M3 System Control register to allow Sleep mode entering.</span></li>
-              
-
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
deleted file mode 100644
index 9a6bd07..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the miscellaneous
-  *          firmware library functions (add-on to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/** @defgroup MISC_Exported_Types
-  * @{
-  */
-
-/** 
-  * @brief  NVIC Init Structure definition  
-  */
-
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be a value of @ref IRQn_Type 
-                                                   (For the complete STM32 Devices IRQ Channels list, please
-                                                    refer to stm32f10x.h file) */
-
-  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
-                                                   specified in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
-  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
-                                                   in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
-  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled. 
-                                                   This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
- 
-/**
-  * @}
-  */
-
-/** @defgroup NVIC_Priority_Table 
-  * @{
-  */
-
-/**
-@code  
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
-  ============================================================================================================================
-    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
-  ============================================================================================================================
-   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
-                         |                                   |                             |   4 bits for subpriority
-  ----------------------------------------------------------------------------------------------------------------------------
-   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
-                         |                                   |                             |   3 bits for subpriority
-  ----------------------------------------------------------------------------------------------------------------------------    
-   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
-                         |                                   |                             |   2 bits for subpriority
-  ----------------------------------------------------------------------------------------------------------------------------    
-   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
-                         |                                   |                             |   1 bits for subpriority
-  ----------------------------------------------------------------------------------------------------------------------------    
-   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
-                         |                                   |                             |   0 bits for subpriority                       
-  ============================================================================================================================
-@endcode
-*/
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup Vector_Table_Base 
-  * @{
-  */
-
-#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
-                                  ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
-  * @}
-  */
-
-/** @defgroup System_Low_Power 
-  * @{
-  */
-
-#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup Preemption_Priority_Group 
-  * @{
-  */
-
-#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
-                                                            4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
-                                                            3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
-                                                            2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
-                                                            1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
-                                                            0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
-                                       ((GROUP) == NVIC_PriorityGroup_1) || \
-                                       ((GROUP) == NVIC_PriorityGroup_2) || \
-                                       ((GROUP) == NVIC_PriorityGroup_3) || \
-                                       ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup SysTick_clock_source 
-  * @{
-  */
-
-#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
-                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Exported_Functions
-  * @{
-  */
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
deleted file mode 100644
index d185aa2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_can.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the CAN firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CAN_H
-#define __STM32F10x_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/** @defgroup CAN_Exported_Types
-  * @{
-  */
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
-                                   ((PERIPH) == CAN2))
-
-/** 
-  * @brief  CAN init structure definition
-  */
-
-typedef struct
-{
-  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
-                                 It ranges from 1 to 1024. */
-  
-  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
-                                 This parameter can be a value of 
-                                @ref CAN_operating_mode */
-
-  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
-                                 the CAN hardware is allowed to lengthen or 
-                                 shorten a bit to perform resynchronization.
-                                 This parameter can be a value of 
-                                 @ref CAN_synchronisation_jump_width */
-
-  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
-                                 Segment 1. This parameter can be a value of 
-                                 @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit 
-                                 Segment 2.
-                                 This parameter can be a value of 
-                                 @ref CAN_time_quantum_in_bit_segment_2 */
-  
-  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered 
-                                 communication mode. This parameter can be set 
-                                 either to ENABLE or DISABLE. */
-  
-  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off 
-                                  management. This parameter can be set either 
-                                  to ENABLE or DISABLE. */
-
-  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
-                                  This parameter can be set either to ENABLE or 
-                                  DISABLE. */
-
-  FunctionalState CAN_NART;  /*!< Enable or disable the no-automatic 
-                                  retransmission mode. This parameter can be 
-                                  set either to ENABLE or DISABLE. */
-
-  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
-                                  This parameter can be set either to ENABLE 
-                                  or DISABLE. */
-
-  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
-                                  This parameter can be set either to ENABLE 
-                                  or DISABLE. */
-} CAN_InitTypeDef;
-
-/** 
-  * @brief  CAN filter init structure definition
-  */
-
-typedef struct
-{
-  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                              configuration, first one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                              configuration, second one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
-                                              according to the mode (MSBs for a 32-bit configuration,
-                                              first one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
-                                              according to the mode (LSBs for a 32-bit configuration,
-                                              second one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                              This parameter can be a value of @ref CAN_filter_FIFO */
-  
-  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
-  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                              This parameter can be a value of @ref CAN_filter_mode */
-
-  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
-                                              This parameter can be a value of @ref CAN_filter_scale */
-
-  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
-                                              This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/** 
-  * @brief  CAN Tx message structure definition  
-  */
-
-typedef struct
-{
-  uint32_t StdId;  /*!< Specifies the standard identifier.
-                        This parameter can be a value between 0 to 0x7FF. */
-
-  uint32_t ExtId;  /*!< Specifies the extended identifier.
-                        This parameter can be a value between 0 to 0x1FFFFFFF. */
-
-  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
-                        will be transmitted. This parameter can be a value 
-                        of @ref CAN_identifier_type */
-
-  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
-                        be transmitted. This parameter can be a value of 
-                        @ref CAN_remote_transmission_request */
-
-  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
-                        transmitted. This parameter can be a value between 
-                        0 to 8 */
-
-  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
-                        to 0xFF. */
-} CanTxMsg;
-
-/** 
-  * @brief  CAN Rx message structure definition  
-  */
-
-typedef struct
-{
-  uint32_t StdId;  /*!< Specifies the standard identifier.
-                        This parameter can be a value between 0 to 0x7FF. */
-
-  uint32_t ExtId;  /*!< Specifies the extended identifier.
-                        This parameter can be a value between 0 to 0x1FFFFFFF. */
-
-  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
-                        will be received. This parameter can be a value of 
-                        @ref CAN_identifier_type */
-
-  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
-                        This parameter can be a value of 
-                        @ref CAN_remote_transmission_request */
-
-  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
-                        This parameter can be a value between 0 to 8 */
-
-  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
-                        0xFF. */
-
-  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
-                        the mailbox passes through. This parameter can be a 
-                        value between 0 to 0xFF */
-} CanRxMsg;
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Constants
-  * @{
-  */
-
-/** @defgroup CAN_sleep_constants 
-  * @{
-  */
-
-#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Mode 
-  * @{
-  */
-
-#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
-#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
-#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
-                           ((MODE) == CAN_Mode_LoopBack)|| \
-                           ((MODE) == CAN_Mode_Silent) || \
-                           ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
-  * @}
-  */
-
-
-/**
-  * @defgroup CAN_Operating_Mode 
-  * @{
-  */  
-#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
-                                    ((MODE) == CAN_OperatingMode_Normal)|| \
-																		((MODE) == CAN_OperatingMode_Sleep))
-/**
-  * @}
-  */
-  
-/**
-  * @defgroup CAN_Mode_Status
-  * @{
-  */  
-
-#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_synchronisation_jump_width 
-  * @{
-  */
-
-#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
-                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 
-  * @{
-  */
-
-#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
-#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
-#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
-#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
-#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
-#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
-#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
-#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
-#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
-#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
-#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
-#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 
-  * @{
-  */
-
-#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
-#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
-#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
-#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_clock_prescaler 
-  * @{
-  */
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_number 
-  * @{
-  */
-#ifndef STM32F10X_CL
-  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
-#else
-  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-#endif /* STM32F10X_CL */ 
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode 
-  * @{
-  */
-
-#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
-                                  ((MODE) == CAN_FilterMode_IdList))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale 
-  * @{
-  */
-
-#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
-                                    ((SCALE) == CAN_FilterScale_32bit))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO
-  * @{
-  */
-
-#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
-                                  ((FIFO) == CAN_FilterFIFO1))
-/**
-  * @}
-  */
-
-/** @defgroup Start_bank_filter_for_slave_CAN 
-  * @{
-  */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Tx 
-  * @{
-  */
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_identifier_type 
-  * @{
-  */
-
-#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
-#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
-                               ((IDTYPE) == CAN_Id_Extended))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request 
-  * @{
-  */
-
-#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
-#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_transmit_constants 
-  * @{
-  */
-
-#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants 
-  * @{
-  */
-
-#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_sleep_constants 
-  * @{
-  */
-
-#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_wake_up_constants 
-  * @{
-  */
-
-#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup   CAN_Error_Code_constants
-  * @{
-  */  
-                                                                
-#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
-#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
-#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
-#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
-#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
-#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
-#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
-#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
-
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags 
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
-#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
-#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
-#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
-#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
-                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
-                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
-                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
-                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
-                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
-                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
-                               ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
-                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
-                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
-                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
-                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
-  * @}
-  */
-
-  
-/** @defgroup CAN_interrupts 
-  * @{
-  */
-
-
-  
-#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0   CAN_IT_TME
-#define CAN_IT_RQCP1   CAN_IT_TME
-#define CAN_IT_RQCP2   CAN_IT_TME
-
-
-#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
-                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
-                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
-                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
-                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
-                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
-                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
-                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
-                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
-                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
-                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
-                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Legacy 
-  * @{
-  */
-#define CANINITFAILED               CAN_InitStatus_Failed
-#define CANINITOK                   CAN_InitStatus_Success
-#define CAN_FilterFIFO0             CAN_Filter_FIFO0
-#define CAN_FilterFIFO1             CAN_Filter_FIFO1
-#define CAN_ID_STD                  CAN_Id_Standard           
-#define CAN_ID_EXT                  CAN_Id_Extended
-#define CAN_RTR_DATA                CAN_RTR_Data         
-#define CAN_RTR_REMOTE              CAN_RTR_Remote
-#define CANTXFAILE                  CAN_TxStatus_Failed
-#define CANTXOK                     CAN_TxStatus_Ok
-#define CANTXPENDING                CAN_TxStatus_Pending
-#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
-#define CANSLEEPFAILED              CAN_Sleep_Failed
-#define CANSLEEPOK                  CAN_Sleep_Ok
-#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
-#define CANWAKEUPOK                 CAN_WakeUp_Ok        
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions
-  * @{
-  */
-/*  Function used to set the CAN configuration to the default reset state *****/ 
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/ 
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* Transmit functions *********************************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* Receive functions **********************************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* Error management functions *************************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_CAN_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
deleted file mode 100644
index 3362fca..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_crc.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the CRC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CRC_H
-#define __STM32F10x_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/** @defgroup CRC_Exported_Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions
-  * @{
-  */
-
-void CRC_ResetDR(void);
-uint32_t CRC_CalcCRC(uint32_t Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-void CRC_SetIDRegister(uint8_t IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_CRC_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
deleted file mode 100644
index 89ceb9a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dbgmcu.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the DBGMCU 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_DBGMCU_H
-#define __STM32F10x_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DBGMCU
-  * @{
-  */
-
-/** @defgroup DBGMCU_Exported_Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Exported_Constants
-  * @{
-  */
-
-#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
-#define DBGMCU_STOP                  ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
-#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
-#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
-#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
-#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
-#define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
-#define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
-#define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
-#define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
-#define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
-#define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
-#define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
-#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
-#define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
-#define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
-#define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
-#define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
-#define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
-#define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
-#define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
-#define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
-#define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
-                                              
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup DBGMCU_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Exported_Functions
-  * @{
-  */
-
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_DBGMCU_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
deleted file mode 100644
index 14275fe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
+++ /dev/null
@@ -1,439 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dma.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the DMA firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_DMA_H
-#define __STM32F10x_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Types
-  * @{
-  */
-
-/** 
-  * @brief  DMA Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
-
-  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
-
-  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
-                                        This parameter can be a value of @ref DMA_data_transfer_direction */
-
-  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
-                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
-                                        or DMA_MemoryDataSize members depending in the transfer direction. */
-
-  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
-                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
-  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
-                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
-
-  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
-                                        This parameter can be a value of @ref DMA_peripheral_data_size */
-
-  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
-                                        This parameter can be a value of @ref DMA_memory_data_size */
-
-  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
-                                        This parameter can be a value of @ref DMA_circular_normal_mode.
-                                        @note: The circular buffer mode cannot be used if the memory-to-memory
-                                              data transfer is configured on the selected Channel */
-
-  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
-                                        This parameter can be a value of @ref DMA_priority_level */
-
-  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
-                                        This parameter can be a value of @ref DMA_memory_to_memory */
-}DMA_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Constants
-  * @{
-  */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
-                                   ((PERIPH) == DMA1_Channel2) || \
-                                   ((PERIPH) == DMA1_Channel3) || \
-                                   ((PERIPH) == DMA1_Channel4) || \
-                                   ((PERIPH) == DMA1_Channel5) || \
-                                   ((PERIPH) == DMA1_Channel6) || \
-                                   ((PERIPH) == DMA1_Channel7) || \
-                                   ((PERIPH) == DMA2_Channel1) || \
-                                   ((PERIPH) == DMA2_Channel2) || \
-                                   ((PERIPH) == DMA2_Channel3) || \
-                                   ((PERIPH) == DMA2_Channel4) || \
-                                   ((PERIPH) == DMA2_Channel5))
-
-/** @defgroup DMA_data_transfer_direction 
-  * @{
-  */
-
-#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
-#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
-                         ((DIR) == DMA_DIR_PeripheralSRC))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_peripheral_incremented_mode 
-  * @{
-  */
-
-#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
-#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
-                                            ((STATE) == DMA_PeripheralInc_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_incremented_mode 
-  * @{
-  */
-
-#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
-#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
-                                        ((STATE) == DMA_MemoryInc_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_peripheral_data_size 
-  * @{
-  */
-
-#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
-#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
-                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
-                                           ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_data_size 
-  * @{
-  */
-
-#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
-#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
-                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
-                                       ((SIZE) == DMA_MemoryDataSize_Word))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_circular_normal_mode 
-  * @{
-  */
-
-#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
-#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_priority_level 
-  * @{
-  */
-
-#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
-#define DMA_Priority_High                  ((uint32_t)0x00002000)
-#define DMA_Priority_Medium                ((uint32_t)0x00001000)
-#define DMA_Priority_Low                   ((uint32_t)0x00000000)
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
-                                   ((PRIORITY) == DMA_Priority_High) || \
-                                   ((PRIORITY) == DMA_Priority_Medium) || \
-                                   ((PRIORITY) == DMA_Priority_Low))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_to_memory 
-  * @{
-  */
-
-#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
-#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupts_definition 
-  * @{
-  */
-
-#define DMA_IT_TC                          ((uint32_t)0x00000002)
-#define DMA_IT_HT                          ((uint32_t)0x00000004)
-#define DMA_IT_TE                          ((uint32_t)0x00000008)
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
-#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
-#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
-#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
-#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
-#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
-#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
-#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
-#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
-#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
-#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
-#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
-#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
-#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
-#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
-#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
-#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
-#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
-#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
-#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
-#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
-#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
-#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
-#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
-#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
-#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
-#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
-#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
-
-#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
-#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
-#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
-#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
-#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
-#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
-#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
-#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
-#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
-#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
-#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
-#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
-#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
-#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
-#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
-#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
-#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
-#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
-#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
-#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
-                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
-                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
-                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
-                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
-                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
-                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
-                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
-                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
-                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
-                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
-                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
-                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
-                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
-                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
-                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
-                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
-                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
-                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
-                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
-                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
-                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
-                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
-                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flags_definition 
-  * @{
-  */
-#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
-#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
-#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
-#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
-#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
-#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
-#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
-#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
-#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
-#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
-#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
-#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
-#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
-#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
-#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
-#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
-#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
-#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
-#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
-#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
-#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
-#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
-#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
-#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
-#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
-#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
-#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
-#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
-
-#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
-#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
-#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
-#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
-#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
-#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
-#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
-#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
-#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
-#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
-#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
-#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
-#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
-#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
-#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
-#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
-#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
-#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
-#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
-#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
-                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
-                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
-                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
-                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
-                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
-                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
-                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
-                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
-                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
-                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
-                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
-                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
-                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
-                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
-                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
-                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
-                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
-                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
-                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
-                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
-                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
-                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
-                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Buffer_Size 
-  * @{
-  */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions
-  * @{
-  */
-
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
-void DMA_ClearFlag(uint32_t DMAy_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
-void DMA_ClearITPendingBit(uint32_t DMAy_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_DMA_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
deleted file mode 100644
index 6e1769d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
+++ /dev/null
@@ -1,733 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_fsmc.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the FSMC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_FSMC_H
-#define __STM32F10x_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FSMC
-  * @{
-  */
-
-/** @defgroup FSMC_Exported_Types
-  * @{
-  */
-
-/** 
-  * @brief  Timing parameters For NOR/SRAM Banks  
-  */
-
-typedef struct
-{
-  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the address setup time. 
-                                             This parameter can be a value between 0 and 0xF.
-                                             @note: It is not used with synchronous NOR Flash memories. */
-
-  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the address hold time.
-                                             This parameter can be a value between 0 and 0xF. 
-                                             @note: It is not used with synchronous NOR Flash memories.*/
-
-  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the data setup time.
-                                             This parameter can be a value between 0 and 0xFF.
-                                             @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
-  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the bus turnaround.
-                                             This parameter can be a value between 0 and 0xF.
-                                             @note: It is only used for multiplexed NOR Flash memories. */
-
-  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
-                                             This parameter can be a value between 1 and 0xF.
-                                             @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
-  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
-                                             to the memory before getting the first data.
-                                             The value of this parameter depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between 0 and 0xF in NOR Flash memories
-                                                with synchronous burst mode enable */
-
-  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
-                                             This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/** 
-  * @brief  FSMC NOR/SRAM Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
-                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
-  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
-                                          multiplexed on the databus or not. 
-                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
-  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
-                                          the corresponding memory bank.
-                                          This parameter can be a value of @ref FSMC_Memory_Type */
-
-  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
-                                          This parameter can be a value of @ref FSMC_Data_Width */
-
-  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
-                                          valid only with synchronous burst Flash memories.
-                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-                                       
-  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
-                                          valid only with asynchronous Flash memories.
-                                          This parameter can be a value of @ref FSMC_AsynchronousWait */
-
-  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
-                                          the Flash memory in burst mode.
-                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
-  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
-                                          memory, valid only when accessing Flash memories in burst mode.
-                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
-
-  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
-                                          clock cycle before the wait state or during the wait state,
-                                          valid only when accessing memories in burst mode. 
-                                          This parameter can be a value of @ref FSMC_Wait_Timing */
-
-  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
-                                          This parameter can be a value of @ref FSMC_Write_Operation */
-
-  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
-                                          signal, valid for Flash memory access in burst mode. 
-                                          This parameter can be a value of @ref FSMC_Wait_Signal */
-
-  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
-                                          This parameter can be a value of @ref FSMC_Extended_Mode */
-
-  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
-                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
-
-  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
-
-  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
-}FSMC_NORSRAMInitTypeDef;
-
-/** 
-  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
-  */
-
-typedef struct
-{
-  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
-                                     the command assertion for NAND-Flash read or write access
-                                     to common/Attribute or I/O memory space (depending on
-                                     the memory space timing to be configured).
-                                     This parameter can be a value between 0 and 0xFF.*/
-
-  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
-                                     command for NAND-Flash read or write access to
-                                     common/Attribute or I/O memory space (depending on the
-                                     memory space timing to be configured). 
-                                     This parameter can be a number between 0x00 and 0xFF */
-
-  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
-                                     (and data for write access) after the command deassertion
-                                     for NAND-Flash read or write access to common/Attribute
-                                     or I/O memory space (depending on the memory space timing
-                                     to be configured).
-                                     This parameter can be a number between 0x00 and 0xFF */
-
-  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
-                                     databus is kept in HiZ after the start of a NAND-Flash
-                                     write access to common/Attribute or I/O memory space (depending
-                                     on the memory space timing to be configured).
-                                     This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/** 
-  * @brief  FSMC NAND Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
-                                      This parameter can be a value of @ref FSMC_NAND_Bank */
-
-  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
-                                       This parameter can be any value of @ref FSMC_Wait_feature */
-
-  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
-                                       This parameter can be any value of @ref FSMC_Data_Width */
-
-  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
-                                       This parameter can be any value of @ref FSMC_ECC */
-
-  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
-                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
-  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
-                                       delay between CLE low and RE low.
-                                       This parameter can be a value between 0 and 0xFF. */
-
-  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
-                                       delay between ALE low and RE low.
-                                       This parameter can be a number between 0x0 and 0xFF */ 
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/** 
-  * @brief  FSMC PCCARD Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
-                                    This parameter can be any value of @ref FSMC_Wait_feature */
-
-  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
-                                     delay between CLE low and RE low.
-                                     This parameter can be a value between 0 and 0xFF. */
-
-  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
-                                     delay between ALE low and RE low.
-                                     This parameter can be a number between 0x0 and 0xFF */ 
-
-  
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
-  
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
-}FSMC_PCCARDInitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup FSMC_NORSRAM_Bank 
-  * @{
-  */
-#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NAND_Bank 
-  * @{
-  */  
-#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_PCCARD_Bank 
-  * @{
-  */    
-#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
-/**
-  * @}
-  */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                                 ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                                    ((BANK) == FSMC_Bank3_NAND) || \
-                                    ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                               ((BANK) == FSMC_Bank3_NAND) || \
-                               ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup NOR_SRAM_Controller 
-  * @{
-  */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
-  * @{
-  */
-
-#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
-                          ((MUX) == FSMC_DataAddressMux_Enable))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Memory_Type 
-  * @{
-  */
-
-#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
-                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
-                                ((MEMORY) == FSMC_MemoryType_NOR))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Width 
-  * @{
-  */
-
-#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
-                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Burst_Access_Mode 
-  * @{
-  */
-
-#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
-#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
-                                  ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
-  * @}
-  */
-  
-/** @defgroup FSMC_AsynchronousWait 
-  * @{
-  */
-#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
-                                 ((STATE) == FSMC_AsynchronousWait_Enable))
-
-/**
-  * @}
-  */
-  
-/** @defgroup FSMC_Wait_Signal_Polarity 
-  * @{
-  */
-
-#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
-                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wrap_Mode 
-  * @{
-  */
-
-#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
-                                 ((MODE) == FSMC_WrapMode_Enable))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Timing 
-  * @{
-  */
-
-#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
-                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Operation 
-  * @{
-  */
-
-#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
-                                            ((OPERATION) == FSMC_WriteOperation_Enable))
-                              
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal 
-  * @{
-  */
-
-#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
-                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Extended_Mode 
-  * @{
-  */
-
-#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
-                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Burst 
-  * @{
-  */
-
-#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
-                                    ((BURST) == FSMC_WriteBurst_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Hold_Time 
-  * @{
-  */
-
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration 
-  * @{
-  */
-
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_CLK_Division 
-  * @{
-  */
-
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Latency 
-  * @{
-  */
-
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Access_Mode 
-  * @{
-  */
-
-#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
-#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
-                                   ((MODE) == FSMC_AccessMode_B) || \
-                                   ((MODE) == FSMC_AccessMode_C) || \
-                                   ((MODE) == FSMC_AccessMode_D)) 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup NAND_PCCARD_Controller 
-  * @{
-  */
-
-/** @defgroup FSMC_Wait_feature 
-  * @{
-  */
-
-#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
-                                       ((FEATURE) == FSMC_Waitfeature_Enable))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup FSMC_ECC 
-  * @{
-  */
-
-#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
-                                  ((STATE) == FSMC_ECC_Enable))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_ECC_Page_Size 
-  * @{
-  */
-
-#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_TCLR_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_TAR_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Hold_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_HiZ_Setup_Time 
-  * @{
-  */
-
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Interrupt_sources 
-  * @{
-  */
-
-#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
-#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
-                            ((IT) == FSMC_IT_Level) || \
-                            ((IT) == FSMC_IT_FallingEdge)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Flags 
-  * @{
-  */
-
-#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
-                                ((FLAG) == FSMC_FLAG_Level) || \
-                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
-                                ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Exported_Functions
-  * @{
-  */
-
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_PCCARDDeInit(void);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_FSMC_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
deleted file mode 100644
index dd28da8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
+++ /dev/null
@@ -1,385 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_gpio.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the GPIO 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_GPIO_H
-#define __STM32F10x_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Types
-  * @{
-  */
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
-                                    ((PERIPH) == GPIOB) || \
-                                    ((PERIPH) == GPIOC) || \
-                                    ((PERIPH) == GPIOD) || \
-                                    ((PERIPH) == GPIOE) || \
-                                    ((PERIPH) == GPIOF) || \
-                                    ((PERIPH) == GPIOG))
-                                     
-/** 
-  * @brief  Output Maximum frequency selection  
-  */
-
-typedef enum
-{ 
-  GPIO_Speed_10MHz = 1,
-  GPIO_Speed_2MHz, 
-  GPIO_Speed_50MHz
-}GPIOSpeed_TypeDef;
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
-                              ((SPEED) == GPIO_Speed_50MHz))
-
-/** 
-  * @brief  Configuration Mode enumeration  
-  */
-
-typedef enum
-{ GPIO_Mode_AIN = 0x0,
-  GPIO_Mode_IN_FLOATING = 0x04,
-  GPIO_Mode_IPD = 0x28,
-  GPIO_Mode_IPU = 0x48,
-  GPIO_Mode_Out_OD = 0x14,
-  GPIO_Mode_Out_PP = 0x10,
-  GPIO_Mode_AF_OD = 0x1C,
-  GPIO_Mode_AF_PP = 0x18
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
-                            ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
-                            ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
-                            ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
-
-/** 
-  * @brief  GPIO Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t GPIO_Pin;             /*!< Specifies the GPIO pins to be configured.
-                                      This parameter can be any value of @ref GPIO_pins_define */
-
-  GPIOSpeed_TypeDef GPIO_Speed;  /*!< Specifies the speed for the selected pins.
-                                      This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
-  GPIOMode_TypeDef GPIO_Mode;    /*!< Specifies the operating mode for the selected pins.
-                                      This parameter can be a value of @ref GPIOMode_TypeDef */
-}GPIO_InitTypeDef;
-
-
-/** 
-  * @brief  Bit_SET and Bit_RESET enumeration  
-  */
-
-typedef enum
-{ Bit_RESET = 0,
-  Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Constants
-  * @{
-  */
-
-/** @defgroup GPIO_pins_define 
-  * @{
-  */
-
-#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
-#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
-#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
-#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
-#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
-#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
-#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
-#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
-#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
-#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
-#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
-#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
-#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
-#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
-#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
-#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
-#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
-                              ((PIN) == GPIO_Pin_1) || \
-                              ((PIN) == GPIO_Pin_2) || \
-                              ((PIN) == GPIO_Pin_3) || \
-                              ((PIN) == GPIO_Pin_4) || \
-                              ((PIN) == GPIO_Pin_5) || \
-                              ((PIN) == GPIO_Pin_6) || \
-                              ((PIN) == GPIO_Pin_7) || \
-                              ((PIN) == GPIO_Pin_8) || \
-                              ((PIN) == GPIO_Pin_9) || \
-                              ((PIN) == GPIO_Pin_10) || \
-                              ((PIN) == GPIO_Pin_11) || \
-                              ((PIN) == GPIO_Pin_12) || \
-                              ((PIN) == GPIO_Pin_13) || \
-                              ((PIN) == GPIO_Pin_14) || \
-                              ((PIN) == GPIO_Pin_15))
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Remap_define 
-  * @{
-  */
-
-#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping */
-#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
-#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
-#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
-#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /*!< USART3 Partial Alternate Function mapping */
-#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /*!< USART3 Full Alternate Function mapping */
-#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /*!< TIM1 Partial Alternate Function mapping */
-#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /*!< TIM1 Full Alternate Function mapping */
-#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /*!< TIM2 Partial1 Alternate Function mapping */
-#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /*!< TIM2 Partial2 Alternate Function mapping */
-#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /*!< TIM2 Full Alternate Function mapping */
-#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /*!< TIM3 Partial Alternate Function mapping */
-#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /*!< TIM3 Full Alternate Function mapping */
-#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /*!< TIM4 Alternate Function mapping */
-#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /*!< CAN1 Alternate Function mapping */
-#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /*!< CAN1 Alternate Function mapping */
-#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
-#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /*!< LSI connected to TIM5 Channel4 input capture for calibration */
-#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /*!< ADC1 External Trigger Injected Conversion remapping */
-#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /*!< ADC1 External Trigger Regular Conversion remapping */
-#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /*!< ADC2 External Trigger Injected Conversion remapping */
-#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /*!< ADC2 External Trigger Regular Conversion remapping */
-#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /*!< Ethernet remapping (only for Connectivity line devices) */
-#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /*!< CAN2 remapping (only for Connectivity line devices) */
-#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
-#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
-#define GPIO_Remap_SPI3             ((uint32_t)0x00201100)  /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
-#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
-                                                                 to TIM2 Internal Trigger 1 for calibration
-                                                                 (only for Connectivity line devices) */
-#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
-
-#define GPIO_Remap_TIM15            ((uint32_t)0x80000001)  /*!< TIM15 Alternate Function mapping (only for Value line devices) */
-#define GPIO_Remap_TIM16            ((uint32_t)0x80000002)  /*!< TIM16 Alternate Function mapping (only for Value line devices) */
-#define GPIO_Remap_TIM17            ((uint32_t)0x80000004)  /*!< TIM17 Alternate Function mapping (only for Value line devices) */
-#define GPIO_Remap_CEC              ((uint32_t)0x80000008)  /*!< CEC Alternate Function mapping (only for Value line devices) */
-#define GPIO_Remap_TIM1_DMA         ((uint32_t)0x80000010)  /*!< TIM1 DMA requests mapping (only for Value line devices) */
-
-#define GPIO_Remap_TIM9             ((uint32_t)0x80000020)  /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
-#define GPIO_Remap_TIM10            ((uint32_t)0x80000040)  /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
-#define GPIO_Remap_TIM11            ((uint32_t)0x80000080)  /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
-#define GPIO_Remap_TIM13            ((uint32_t)0x80000100)  /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
-#define GPIO_Remap_TIM14            ((uint32_t)0x80000200)  /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
-#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
-
-#define GPIO_Remap_TIM67_DAC_DMA    ((uint32_t)0x80000800)  /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
-#define GPIO_Remap_TIM12            ((uint32_t)0x80001000)  /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
-#define GPIO_Remap_MISC             ((uint32_t)0x80002000)  /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
-                                                                 only for High density Value line devices) */                                                       
-
-#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
-                              ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
-                              ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
-                              ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
-                              ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
-                              ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
-                              ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
-                              ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
-                              ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
-                              ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
-                              ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
-                              ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
-                              ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
-                              ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
-                              ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
-                              ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
-                              ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
-                              ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
-                              ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
-                              ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
-                              ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
-                              ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
-                              
-/**
-  * @}
-  */ 
-
-/** @defgroup GPIO_Port_Sources 
-  * @{
-  */
-
-#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
-#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
-#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
-#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
-#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
-#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
-#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
-#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
-                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
-                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
-                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
-                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))
-
-#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
-                                              ((PORTSOURCE) == GPIO_PortSourceGPIOG))
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Pin_sources 
-  * @{
-  */
-
-#define GPIO_PinSource0            ((uint8_t)0x00)
-#define GPIO_PinSource1            ((uint8_t)0x01)
-#define GPIO_PinSource2            ((uint8_t)0x02)
-#define GPIO_PinSource3            ((uint8_t)0x03)
-#define GPIO_PinSource4            ((uint8_t)0x04)
-#define GPIO_PinSource5            ((uint8_t)0x05)
-#define GPIO_PinSource6            ((uint8_t)0x06)
-#define GPIO_PinSource7            ((uint8_t)0x07)
-#define GPIO_PinSource8            ((uint8_t)0x08)
-#define GPIO_PinSource9            ((uint8_t)0x09)
-#define GPIO_PinSource10           ((uint8_t)0x0A)
-#define GPIO_PinSource11           ((uint8_t)0x0B)
-#define GPIO_PinSource12           ((uint8_t)0x0C)
-#define GPIO_PinSource13           ((uint8_t)0x0D)
-#define GPIO_PinSource14           ((uint8_t)0x0E)
-#define GPIO_PinSource15           ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
-                                       ((PINSOURCE) == GPIO_PinSource1) || \
-                                       ((PINSOURCE) == GPIO_PinSource2) || \
-                                       ((PINSOURCE) == GPIO_PinSource3) || \
-                                       ((PINSOURCE) == GPIO_PinSource4) || \
-                                       ((PINSOURCE) == GPIO_PinSource5) || \
-                                       ((PINSOURCE) == GPIO_PinSource6) || \
-                                       ((PINSOURCE) == GPIO_PinSource7) || \
-                                       ((PINSOURCE) == GPIO_PinSource8) || \
-                                       ((PINSOURCE) == GPIO_PinSource9) || \
-                                       ((PINSOURCE) == GPIO_PinSource10) || \
-                                       ((PINSOURCE) == GPIO_PinSource11) || \
-                                       ((PINSOURCE) == GPIO_PinSource12) || \
-                                       ((PINSOURCE) == GPIO_PinSource13) || \
-                                       ((PINSOURCE) == GPIO_PinSource14) || \
-                                       ((PINSOURCE) == GPIO_PinSource15))
-
-/**
-  * @}
-  */
-
-/** @defgroup Ethernet_Media_Interface 
-  * @{
-  */ 
-#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000) 
-#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)                                       
-
-#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
-                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
-
-/**
-  * @}
-  */                                                
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions
-  * @{
-  */
-
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-void GPIO_AFIODeInit(void);
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
-void GPIO_EventOutputCmd(FunctionalState NewState);
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_GPIO_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
deleted file mode 100644
index 1149c34..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
+++ /dev/null
@@ -1,727 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_rcc.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the RCC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_RCC_H
-#define __STM32F10x_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Types
-  * @{
-  */
-
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
-  uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
-  uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
-  uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
-  uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
-}RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup HSE_configuration 
-  * @{
-  */
-
-#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
-#define RCC_HSE_ON                       ((uint32_t)0x00010000)
-#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_Bypass))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup PLL_entry_clock_source 
-  * @{
-  */
-
-#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
- #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
- #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
- #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
-                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
-                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))
-#else
- #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
- #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
-                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup PLL_multiplication_factor 
-  * @{
-  */
-#ifndef STM32F10X_CL
- #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
- #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
- #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
- #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
- #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
- #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
- #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
- #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
- #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
- #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
- #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
- #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
- #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
- #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
- #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
- #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
-                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
-                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
-                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
-                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
-                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
-                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
-                              ((MUL) == RCC_PLLMul_16))
-
-#else
- #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
- #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
- #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
- #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
- #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
- #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
- #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
-
- #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
-                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
-                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
-                              ((MUL) == RCC_PLLMul_6_5))
-#endif /* STM32F10X_CL */                              
-/**
-  * @}
-  */
-
-/** @defgroup PREDIV1_division_factor
-  * @{
-  */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
- #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
- #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
- #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
- #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
- #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
- #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
- #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
- #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
- #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
- #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
- #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
- #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
- #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
- #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
- #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
- #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
-
- #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
-                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup PREDIV1_clock_source
-  * @{
-  */
-#ifdef STM32F10X_CL
-/* PREDIV1 clock source (for STM32 connectivity line devices) */
- #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
- #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000) 
-
- #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
-                                        ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/* PREDIV1 clock source (for STM32 Value line devices) */
- #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
-
- #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 
-#endif
-/**
-  * @}
-  */
-
-#ifdef STM32F10X_CL
-/** @defgroup PREDIV2_division_factor
-  * @{
-  */
-  
- #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
- #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
- #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
- #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
- #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
- #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
- #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
- #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
- #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
- #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
- #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
- #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
- #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
- #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
- #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
- #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
-
- #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
-                                  ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
-/**
-  * @}
-  */
-
-
-/** @defgroup PLL2_multiplication_factor
-  * @{
-  */
-  
- #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
- #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
- #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
- #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
- #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
- #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
- #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
- #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
- #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
-
- #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
-                               ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
-                               ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
-                               ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
-                               ((MUL) == RCC_PLL2Mul_20))
-/**
-  * @}
-  */
-
-
-/** @defgroup PLL3_multiplication_factor
-  * @{
-  */
-
- #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
- #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
- #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
- #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
- #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
- #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
- #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
- #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
- #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
-
- #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
-                               ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
-                               ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
-                               ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
-                               ((MUL) == RCC_PLL3Mul_20))
-/**
-  * @}
-  */
-
-#endif /* STM32F10X_CL */
-
-
-/** @defgroup System_clock_source 
-  * @{
-  */
-
-#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
-  * @}
-  */
-
-/** @defgroup AHB_clock_source 
-  * @{
-  */
-
-#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
-#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
-#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
-#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
-                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
-                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
-                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
-                           ((HCLK) == RCC_SYSCLK_Div512))
-/**
-  * @}
-  */ 
-
-/** @defgroup APB1_APB2_clock_source 
-  * @{
-  */
-
-#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
-#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
-#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
-#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
-                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
-                           ((PCLK) == RCC_HCLK_Div16))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt_source 
-  * @{
-  */
-
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
-#define RCC_IT_CSS                       ((uint8_t)0x80)
-
-#ifndef STM32F10X_CL
- #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
- #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
-                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
-                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
- #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
-#else
- #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
- #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
- #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
- #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
-                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
-                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
-                            ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
- #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
-#endif /* STM32F10X_CL */ 
-
-
-/**
-  * @}
-  */
-
-#ifndef STM32F10X_CL
-/** @defgroup USB_Device_clock_source 
-  * @{
-  */
-
- #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
- #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
-
- #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
-                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
-/**
-  * @}
-  */
-#else
-/** @defgroup USB_OTG_FS_clock_source 
-  * @{
-  */
- #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
- #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
-
- #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
-                                         ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
-/**
-  * @}
-  */
-#endif /* STM32F10X_CL */ 
-
-
-#ifdef STM32F10X_CL
-/** @defgroup I2S2_clock_source 
-  * @{
-  */
- #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
- #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
-
- #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
-                                        ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
-/**
-  * @}
-  */
-
-/** @defgroup I2S3_clock_source 
-  * @{
-  */
- #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
- #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
-
- #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
-                                        ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))    
-/**
-  * @}
-  */
-#endif /* STM32F10X_CL */  
-  
-
-/** @defgroup ADC_clock_source 
-  * @{
-  */
-
-#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
-#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
-#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
-#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
-                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
-/**
-  * @}
-  */
-
-/** @defgroup LSE_configuration 
-  * @{
-  */
-
-#define RCC_LSE_OFF                      ((uint8_t)0x00)
-#define RCC_LSE_ON                       ((uint8_t)0x01)
-#define RCC_LSE_Bypass                   ((uint8_t)0x04)
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_Bypass))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_clock_source 
-  * @{
-  */
-
-#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
-#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
-#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
-/**
-  * @}
-  */
-
-/** @defgroup AHB_peripheral 
-  * @{
-  */
-
-#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
-#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
-#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
-#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
-#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
-
-#ifndef STM32F10X_CL
- #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
- #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
- #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
-#else
- #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
- #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
- #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
- #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
-
- #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
- #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
-#endif /* STM32F10X_CL */
-/**
-  * @}
-  */
-
-/** @defgroup APB2_peripheral 
-  * @{
-  */
-
-#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
-#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
-#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
-#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
-#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
-#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
-#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
-#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
-#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
-#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
-#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
-#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
-#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
-#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
-#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
-#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
-#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
-#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
-#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
-#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup APB1_peripheral 
-  * @{
-  */
-
-#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
-#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
-#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
-#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
-#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
-#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
-#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
-#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
-#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
-#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
-#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
-#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
-#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
-#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
-#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
-#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
-#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
-#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
-#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
-#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
-#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
-#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
-#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
-#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
-#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
- 
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup Clock_source_to_output_on_MCO_pin 
-  * @{
-  */
-
-#define RCC_MCO_NoClock                  ((uint8_t)0x00)
-#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
-#define RCC_MCO_HSI                      ((uint8_t)0x05)
-#define RCC_MCO_HSE                      ((uint8_t)0x06)
-#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
-
-#ifndef STM32F10X_CL
- #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
-                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
-                          ((MCO) == RCC_MCO_PLLCLK_Div2))
-#else
- #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
- #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
- #define RCC_MCO_XT1                     ((uint8_t)0x0A)
- #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
-
- #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
-                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
-                          ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
-                          ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
-                          ((MCO) == RCC_MCO_PLL3CLK))
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag 
-  * @{
-  */
-
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
-
-#ifndef STM32F10X_CL
- #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
-                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
-                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
-                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
-                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
-                            ((FLAG) == RCC_FLAG_LPWRRST))
-#else
- #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B) 
- #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D) 
- #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
-                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
-                            ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
-                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
-                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
-                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
-                            ((FLAG) == RCC_FLAG_LPWRRST))
-#endif /* STM32F10X_CL */ 
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions
-  * @{
-  */
-
-void RCC_DeInit(void);
-void RCC_HSEConfig(uint32_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
- void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
-#endif
-
-#ifdef  STM32F10X_CL
- void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
- void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
- void RCC_PLL2Cmd(FunctionalState NewState);
- void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
- void RCC_PLL3Cmd(FunctionalState NewState);
-#endif /* STM32F10X_CL */ 
-
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-
-#ifndef STM32F10X_CL
- void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
-#else
- void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
-#endif /* STM32F10X_CL */ 
-
-void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
-
-#ifdef STM32F10X_CL
- void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);                                  
- void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
-#endif /* STM32F10X_CL */ 
-
-void RCC_LSEConfig(uint8_t RCC_LSE);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-#ifdef STM32F10X_CL
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-#endif /* STM32F10X_CL */ 
-
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCOConfig(uint8_t RCC_MCO);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_RCC_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
deleted file mode 100644
index 81c058a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_sdio.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the SDIO firmware
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_SDIO_H
-#define __STM32F10x_SDIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup SDIO
-  * @{
-  */
-
-/** @defgroup SDIO_Exported_Types
-  * @{
-  */
-
-typedef struct
-{
-  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SDIO_Clock_Edge */
-
-  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
-                                           enabled or disabled.
-                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
-
-  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
-                                           disabled when the bus is idle.
-                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
-
-  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
-                                           This parameter can be a value of @ref SDIO_Bus_Wide */
-
-  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
-                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
-
-  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
-                                           This parameter can be a value between 0x00 and 0xFF. */
-                                           
-} SDIO_InitTypeDef;
-
-typedef struct
-{
-  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
-                                to a card as part of a command message. If a command
-                                contains an argument, it must be loaded into this register
-                                before writing the command to the command register */
-
-  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
-
-  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
-                                This parameter can be a value of @ref SDIO_Response_Type */
-
-  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
-                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
-
-  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
-                                is enabled or disabled.
-                                This parameter can be a value of @ref SDIO_CPSM_State */
-} SDIO_CmdInitTypeDef;
-
-typedef struct
-{
-  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
-
-  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
- 
-  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
- 
-  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
- 
-  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDIO_Transfer_Type */
- 
-  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_DPSM_State */
-} SDIO_DataInitTypeDef;
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Exported_Constants
-  * @{
-  */
-
-/** @defgroup SDIO_Clock_Edge 
-  * @{
-  */
-
-#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
-#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
-                                  ((EDGE) == SDIO_ClockEdge_Falling))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Clock_Bypass 
-  * @{
-  */
-
-#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
-#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
-                                     ((BYPASS) == SDIO_ClockBypass_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Clock_Power_Save 
-  * @{
-  */
-
-#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
-#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
-                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Bus_Wide 
-  * @{
-  */
-
-#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
-#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
-#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
-                                ((WIDE) == SDIO_BusWide_8b))
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Hardware_Flow_Control 
-  * @{
-  */
-
-#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
-#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
-                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Power_State 
-  * @{
-  */
-
-#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
-#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup SDIO_Interrupt_sources 
-  * @{
-  */
-
-#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
-#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
-#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
-#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
-#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
-#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
-#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
-#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
-#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
-#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
-#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
-#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
-#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
-#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
-#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
-#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
-#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
-#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
-#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
-#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
-#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
-#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
-#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
-#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Command_Index
-  * @{
-  */
-
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Response_Type 
-  * @{
-  */
-
-#define SDIO_Response_No                    ((uint32_t)0x00000000)
-#define SDIO_Response_Short                 ((uint32_t)0x00000040)
-#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
-                                    ((RESPONSE) == SDIO_Response_Short) || \
-                                    ((RESPONSE) == SDIO_Response_Long))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Wait_Interrupt_State 
-  * @{
-  */
-
-#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
-#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
-#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
-                            ((WAIT) == SDIO_Wait_Pend))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_CPSM_State 
-  * @{
-  */
-
-#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
-#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_Response_Registers 
-  * @{
-  */
-
-#define SDIO_RESP1                          ((uint32_t)0x00000000)
-#define SDIO_RESP2                          ((uint32_t)0x00000004)
-#define SDIO_RESP3                          ((uint32_t)0x00000008)
-#define SDIO_RESP4                          ((uint32_t)0x0000000C)
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
-                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Data_Length 
-  * @{
-  */
-
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Data_Block_Size 
-  * @{
-  */
-
-#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
-#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
-#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
-#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
-#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
-#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
-#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
-#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
-#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
-#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
-#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
-#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
-#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
-#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
-#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
-                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Transfer_Direction 
-  * @{
-  */
-
-#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
-#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
-                                   ((DIR) == SDIO_TransferDir_ToSDIO))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Transfer_Type 
-  * @{
-  */
-
-#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
-#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
-                                     ((MODE) == SDIO_TransferMode_Block))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_DPSM_State 
-  * @{
-  */
-
-#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
-#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Flags 
-  * @{
-  */
-
-#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
-#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
-#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
-#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
-#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
-#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
-#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
-                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
-                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
-                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
-                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
-                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
-                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
-                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
-                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
-                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
-                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
-                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
-                            ((FLAG)  == SDIO_FLAG_TXACT) || \
-                            ((FLAG)  == SDIO_FLAG_RXACT) || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
-                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
-                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
-                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
-                            ((FLAG)  == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
-                            ((IT)  == SDIO_IT_DCRCFAIL) || \
-                            ((IT)  == SDIO_IT_CTIMEOUT) || \
-                            ((IT)  == SDIO_IT_DTIMEOUT) || \
-                            ((IT)  == SDIO_IT_TXUNDERR) || \
-                            ((IT)  == SDIO_IT_RXOVERR) || \
-                            ((IT)  == SDIO_IT_CMDREND) || \
-                            ((IT)  == SDIO_IT_CMDSENT) || \
-                            ((IT)  == SDIO_IT_DATAEND) || \
-                            ((IT)  == SDIO_IT_STBITERR) || \
-                            ((IT)  == SDIO_IT_DBCKEND) || \
-                            ((IT)  == SDIO_IT_CMDACT) || \
-                            ((IT)  == SDIO_IT_TXACT) || \
-                            ((IT)  == SDIO_IT_RXACT) || \
-                            ((IT)  == SDIO_IT_TXFIFOHE) || \
-                            ((IT)  == SDIO_IT_RXFIFOHF) || \
-                            ((IT)  == SDIO_IT_TXFIFOF) || \
-                            ((IT)  == SDIO_IT_RXFIFOF) || \
-                            ((IT)  == SDIO_IT_TXFIFOE) || \
-                            ((IT)  == SDIO_IT_RXFIFOE) || \
-                            ((IT)  == SDIO_IT_TXDAVL) || \
-                            ((IT)  == SDIO_IT_RXDAVL) || \
-                            ((IT)  == SDIO_IT_SDIOIT) || \
-                            ((IT)  == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Read_Wait_Mode 
-  * @{
-  */
-
-#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
-#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
-                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_Exported_Functions
-  * @{
-  */
-
-void SDIO_DeInit(void);
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ClockCmd(FunctionalState NewState);
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);
-uint32_t SDIO_GetPowerState(void);
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
-void SDIO_DMACmd(FunctionalState NewState);
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
-uint8_t SDIO_GetCommandResponse(void);
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t SDIO_GetDataCounter(void);
-uint32_t SDIO_ReadData(void);
-void SDIO_WriteData(uint32_t Data);
-uint32_t SDIO_GetFIFOCount(void);
-void SDIO_StartSDIOReadWait(FunctionalState NewState);
-void SDIO_StopSDIOReadWait(FunctionalState NewState);
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-void SDIO_SetSDIOOperation(FunctionalState NewState);
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
-void SDIO_CommandCompletionCmd(FunctionalState NewState);
-void SDIO_CEATAITCmd(FunctionalState NewState);
-void SDIO_SendCEATACmd(FunctionalState NewState);
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_SDIO_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
deleted file mode 100644
index 23cc26d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
+++ /dev/null
@@ -1,487 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_spi.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the SPI firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_SPI_H
-#define __STM32F10x_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */ 
-
-/** @defgroup SPI_Exported_Types
-  * @{
-  */
-
-/** 
-  * @brief  SPI Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
-                                         This parameter can be a value of @ref SPI_data_direction */
-
-  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
-                                         This parameter can be a value of @ref SPI_mode */
-
-  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
-                                         This parameter can be a value of @ref SPI_data_size */
-
-  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
-                                         This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
-                                         This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                         hardware (NSS pin) or by software using the SSI bit.
-                                         This parameter can be a value of @ref SPI_Slave_Select_management */
- 
-  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                         used to configure the transmit and receive SCK clock.
-                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
-                                         @note The communication clock is derived from the master
-                                               clock. The slave clock does not need to be set. */
-
-  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-/** 
-  * @brief  I2S Init structure definition  
-  */
-
-typedef struct
-{
-
-  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
-                                  This parameter can be a value of @ref I2S_Mode */
-
-  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
-                                  This parameter can be a value of @ref I2S_Standard */
-
-  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
-                                  This parameter can be a value of @ref I2S_Data_Format */
-
-  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                  This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                                  This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
-                                  This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Constants
-  * @{
-  */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
-                                   ((PERIPH) == SPI2) || \
-                                   ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
-                                  ((PERIPH) == SPI3))
-
-/** @defgroup SPI_data_direction 
-  * @{
-  */
-  
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
-                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
-                                     ((MODE) == SPI_Direction_1Line_Rx) || \
-                                     ((MODE) == SPI_Direction_1Line_Tx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_mode 
-  * @{
-  */
-
-#define SPI_Mode_Master                 ((uint16_t)0x0104)
-#define SPI_Mode_Slave                  ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
-                           ((MODE) == SPI_Mode_Slave))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_data_size 
-  * @{
-  */
-
-#define SPI_DataSize_16b                ((uint16_t)0x0800)
-#define SPI_DataSize_8b                 ((uint16_t)0x0000)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
-                                   ((DATASIZE) == SPI_DataSize_8b))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_Clock_Polarity 
-  * @{
-  */
-
-#define SPI_CPOL_Low                    ((uint16_t)0x0000)
-#define SPI_CPOL_High                   ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
-                           ((CPOL) == SPI_CPOL_High))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase 
-  * @{
-  */
-
-#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
-                           ((CPHA) == SPI_CPHA_2Edge))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management 
-  * @{
-  */
-
-#define SPI_NSS_Soft                    ((uint16_t)0x0200)
-#define SPI_NSS_Hard                    ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
-                         ((NSS) == SPI_NSS_Hard))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_BaudRate_Prescaler 
-  * @{
-  */
-
-#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_MSB_LSB_transmission 
-  * @{
-  */
-
-#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
-                               ((BIT) == SPI_FirstBit_LSB))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode 
-  * @{
-  */
-
-#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
-                           ((MODE) == I2S_Mode_SlaveRx) || \
-                           ((MODE) == I2S_Mode_MasterTx) || \
-                           ((MODE) == I2S_Mode_MasterRx) )
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Standard 
-  * @{
-  */
-
-#define I2S_Standard_Phillips           ((uint16_t)0x0000)
-#define I2S_Standard_MSB                ((uint16_t)0x0010)
-#define I2S_Standard_LSB                ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
-                                   ((STANDARD) == I2S_Standard_MSB) || \
-                                   ((STANDARD) == I2S_Standard_LSB) || \
-                                   ((STANDARD) == I2S_Standard_PCMShort) || \
-                                   ((STANDARD) == I2S_Standard_PCMLong))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Data_Format 
-  * @{
-  */
-
-#define I2S_DataFormat_16b              ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
-#define I2S_DataFormat_24b              ((uint16_t)0x0003)
-#define I2S_DataFormat_32b              ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
-                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
-                                    ((FORMAT) == I2S_DataFormat_24b) || \
-                                    ((FORMAT) == I2S_DataFormat_32b))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2S_MCLK_Output 
-  * @{
-  */
-
-#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
-                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency 
-  * @{
-  */
-
-#define I2S_AudioFreq_192k               ((uint32_t)192000)
-#define I2S_AudioFreq_96k                ((uint32_t)96000)
-#define I2S_AudioFreq_48k                ((uint32_t)48000)
-#define I2S_AudioFreq_44k                ((uint32_t)44100)
-#define I2S_AudioFreq_32k                ((uint32_t)32000)
-#define I2S_AudioFreq_22k                ((uint32_t)22050)
-#define I2S_AudioFreq_16k                ((uint32_t)16000)
-#define I2S_AudioFreq_11k                ((uint32_t)11025)
-#define I2S_AudioFreq_8k                 ((uint32_t)8000)
-#define I2S_AudioFreq_Default            ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
-                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
-                                 ((FREQ) == I2S_AudioFreq_Default))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2S_Clock_Polarity 
-  * @{
-  */
-
-#define I2S_CPOL_Low                    ((uint16_t)0x0000)
-#define I2S_CPOL_High                   ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
-                           ((CPOL) == I2S_CPOL_High))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests 
-  * @{
-  */
-
-#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_NSS_internal_software_management 
-  * @{
-  */
-
-#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
-                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Transmit_Receive 
-  * @{
-  */
-
-#define SPI_CRC_Tx                      ((uint8_t)0x00)
-#define SPI_CRC_Rx                      ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_direction_transmit_receive 
-  * @{
-  */
-
-#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx                ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
-                                     ((DIRECTION) == SPI_Direction_Tx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_interrupts_definition 
-  * @{
-  */
-
-#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
-                                 ((IT) == SPI_I2S_IT_RXNE) || \
-                                 ((IT) == SPI_I2S_IT_ERR))
-#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
-#define SPI_IT_MODF                     ((uint8_t)0x55)
-#define SPI_IT_CRCERR                   ((uint8_t)0x54)
-#define I2S_IT_UDR                      ((uint8_t)0x53)
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
-                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
-                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_flags_definition 
-  * @{
-  */
-
-#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
-#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
-#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
-                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
-                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
-                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_polynomial 
-  * @{
-  */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions
-  * @{
-  */
-
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_SPI_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
deleted file mode 100644
index 65bf76a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
+++ /dev/null
@@ -1,1164 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_tim.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the TIM firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_TIM_H
-#define __STM32F10x_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */ 
-
-/** @defgroup TIM_Exported_Types
-  * @{
-  */ 
-
-/** 
-  * @brief  TIM Time Base Init structure definition
-  * @note   This structure is used with all TIMx except for TIM6 and TIM7.    
-  */
-
-typedef struct
-{
-  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                       This parameter can be a number between 0x0000 and 0xFFFF */
-
-  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
-                                       This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint16_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
-                                       Auto-Reload Register at the next update event.
-                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
-
-  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
-                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
-  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                       reaches zero, an update event is generated and counting restarts
-                                       from the RCR value (N).
-                                       This means in PWM mode that (N+1) corresponds to:
-                                          - the number of PWM periods in edge-aligned mode
-                                          - the number of half PWM period in center-aligned mode
-                                       This parameter must be a number between 0x00 and 0xFF. 
-                                       @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_TimeBaseInitTypeDef;       
-
-/** 
-  * @brief  TIM Output Compare Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
-                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_state */
-
-  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
-                                   @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint16_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                   This parameter can be a number between 0x0000 and 0xFFFF */
-
-  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
-                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                                   @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                                   @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                                   @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OCInitTypeDef;
-
-/** 
-  * @brief  TIM Input Capture Init structure definition  
-  */
-
-typedef struct
-{
-
-  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
-                                  This parameter can be a value of @ref TIM_Channel */
-
-  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint16_t TIM_ICSelection;  /*!< Specifies the input.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
-                                  This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/** 
-  * @brief  BDTR structure definition 
-  * @note   This structure is used only with TIM1 and TIM8.    
-  */
-
-typedef struct
-{
-
-  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
-                                      This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
-
-  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
-                                      This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
-
-  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
-                                      This parameter can be a value of @ref Lock_level */ 
-
-  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
-                                      switching-on of the outputs.
-                                      This parameter can be a number between 0x00 and 0xFF  */
-
-  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
-                                      This parameter can be a value of @ref Break_Input_enable_disable */
-
-  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
-                                      This parameter can be a value of @ref Break_Polarity */
-
-  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
-                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/** @defgroup TIM_Exported_constants 
-  * @{
-  */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                   ((PERIPH) == TIM2) || \
-                                   ((PERIPH) == TIM3) || \
-                                   ((PERIPH) == TIM4) || \
-                                   ((PERIPH) == TIM5) || \
-                                   ((PERIPH) == TIM6) || \
-                                   ((PERIPH) == TIM7) || \
-                                   ((PERIPH) == TIM8) || \
-                                   ((PERIPH) == TIM9) || \
-                                   ((PERIPH) == TIM10)|| \
-                                   ((PERIPH) == TIM11)|| \
-                                   ((PERIPH) == TIM12)|| \
-                                   ((PERIPH) == TIM13)|| \
-                                   ((PERIPH) == TIM14)|| \
-                                   ((PERIPH) == TIM15)|| \
-                                   ((PERIPH) == TIM16)|| \
-                                   ((PERIPH) == TIM17))
-
-/* LIST1: TIM 1 and 8 */
-#define IS_TIM_LIST1_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM8))
-
-/* LIST2: TIM 1, 8, 15 16 and 17 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM8) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17)) 
-
-/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM4) || \
-                                     ((PERIPH) == TIM5) || \
-                                     ((PERIPH) == TIM8)) 
-									                                 
-/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM4) || \
-                                     ((PERIPH) == TIM5) || \
-                                     ((PERIPH) == TIM8) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17))
-
-/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */                                            
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM4) || \
-                                     ((PERIPH) == TIM5) || \
-                                     ((PERIPH) == TIM8) || \
-                                     ((PERIPH) == TIM15)) 
-
-/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
-#define IS_TIM_LIST6_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM4) || \
-                                      ((PERIPH) == TIM5) || \
-                                      ((PERIPH) == TIM8) || \
-                                      ((PERIPH) == TIM9) || \
-									  ((PERIPH) == TIM12)|| \
-                                      ((PERIPH) == TIM15))
-
-/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
-#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM4) || \
-                                      ((PERIPH) == TIM5) || \
-                                      ((PERIPH) == TIM6) || \
-                                      ((PERIPH) == TIM7) || \
-                                      ((PERIPH) == TIM8) || \
-                                      ((PERIPH) == TIM9) || \
-                                      ((PERIPH) == TIM12)|| \
-                                      ((PERIPH) == TIM15))                                    
-
-/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */                                        
-#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM4) || \
-                                      ((PERIPH) == TIM5) || \
-                                      ((PERIPH) == TIM8) || \
-                                      ((PERIPH) == TIM9) || \
-                                      ((PERIPH) == TIM10)|| \
-                                      ((PERIPH) == TIM11)|| \
-                                      ((PERIPH) == TIM12)|| \
-                                      ((PERIPH) == TIM13)|| \
-                                      ((PERIPH) == TIM14)|| \
-                                      ((PERIPH) == TIM15)|| \
-                                      ((PERIPH) == TIM16)|| \
-                                      ((PERIPH) == TIM17))
-
-/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
-#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM4) || \
-                                      ((PERIPH) == TIM5) || \
-                                      ((PERIPH) == TIM6) || \
-                                      ((PERIPH) == TIM7) || \
-                                      ((PERIPH) == TIM8) || \
-                                      ((PERIPH) == TIM15)|| \
-                                      ((PERIPH) == TIM16)|| \
-                                      ((PERIPH) == TIM17))  
-                                                                                                                                                                                                                          
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes 
-  * @{
-  */
-
-#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
-#define TIM_OCMode_Active                  ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
-                              ((MODE) == TIM_OCMode_Active) || \
-                              ((MODE) == TIM_OCMode_Inactive) || \
-                              ((MODE) == TIM_OCMode_Toggle)|| \
-                              ((MODE) == TIM_OCMode_PWM1) || \
-                              ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
-                          ((MODE) == TIM_OCMode_Active) || \
-                          ((MODE) == TIM_OCMode_Inactive) || \
-                          ((MODE) == TIM_OCMode_Toggle)|| \
-                          ((MODE) == TIM_OCMode_PWM1) || \
-                          ((MODE) == TIM_OCMode_PWM2) ||	\
-                          ((MODE) == TIM_ForcedAction_Active) || \
-                          ((MODE) == TIM_ForcedAction_InActive))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode 
-  * @{
-  */
-
-#define TIM_OPMode_Single                  ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
-                               ((MODE) == TIM_OPMode_Repetitive))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Channel 
-  * @{
-  */
-
-#define TIM_Channel_1                      ((uint16_t)0x0000)
-#define TIM_Channel_2                      ((uint16_t)0x0004)
-#define TIM_Channel_3                      ((uint16_t)0x0008)
-#define TIM_Channel_4                      ((uint16_t)0x000C)
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                 ((CHANNEL) == TIM_Channel_2) || \
-                                 ((CHANNEL) == TIM_Channel_3) || \
-                                 ((CHANNEL) == TIM_Channel_4))
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                      ((CHANNEL) == TIM_Channel_2))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                               ((CHANNEL) == TIM_Channel_2) || \
-                                               ((CHANNEL) == TIM_Channel_3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Clock_Division_CKD 
-  * @{
-  */
-
-#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
-#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
-#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
-                             ((DIV) == TIM_CKD_DIV2) || \
-                             ((DIV) == TIM_CKD_DIV4))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode 
-  * @{
-  */
-
-#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
-#define TIM_CounterMode_Down               ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
-                                   ((MODE) == TIM_CounterMode_Down) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Polarity 
-  * @{
-  */
-
-#define TIM_OCPolarity_High                ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
-                                      ((POLARITY) == TIM_OCPolarity_Low))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity 
-  * @{
-  */
-  
-#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
-                                       ((POLARITY) == TIM_OCNPolarity_Low))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_state 
-  * @{
-  */
-
-#define TIM_OutputState_Disable            ((uint16_t)0x0000)
-#define TIM_OutputState_Enable             ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
-                                    ((STATE) == TIM_OutputState_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_N_state 
-  * @{
-  */
-
-#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
-                                     ((STATE) == TIM_OutputNState_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Capture_Compare_state 
-  * @{
-  */
-
-#define TIM_CCx_Enable                      ((uint16_t)0x0001)
-#define TIM_CCx_Disable                     ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
-                         ((CCX) == TIM_CCx_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Capture_Compare_N_state 
-  * @{
-  */
-
-#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
-#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
-                           ((CCXN) == TIM_CCxN_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup Break_Input_enable_disable 
-  * @{
-  */
-
-#define TIM_Break_Enable                   ((uint16_t)0x1000)
-#define TIM_Break_Disable                  ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
-                                   ((STATE) == TIM_Break_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup Break_Polarity 
-  * @{
-  */
-
-#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
-                                         ((POLARITY) == TIM_BreakPolarity_High))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_AOE_Bit_Set_Reset 
-  * @{
-  */
-
-#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
-                                              ((STATE) == TIM_AutomaticOutput_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup Lock_level 
-  * @{
-  */
-
-#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLevel_1) || \
-                                  ((LEVEL) == TIM_LOCKLevel_2) || \
-                                  ((LEVEL) == TIM_LOCKLevel_3))
-/**
-  * @}
-  */ 
-
-/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state 
-  * @{
-  */
-
-#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
-                                  ((STATE) == TIM_OSSIState_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state 
-  * @{
-  */
-
-#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
-                                  ((STATE) == TIM_OSSRState_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Idle_State 
-  * @{
-  */
-
-#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
-                                    ((STATE) == TIM_OCIdleState_Reset))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_N_Idle_State 
-  * @{
-  */
-
-#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
-                                     ((STATE) == TIM_OCNIdleState_Reset))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Polarity 
-  * @{
-  */
-
-#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
-#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
-#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
-                                      ((POLARITY) == TIM_ICPolarity_Falling))
-#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
-                                           ((POLARITY) == TIM_ICPolarity_Falling)|| \
-                                           ((POLARITY) == TIM_ICPolarity_BothEdge))                                      
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Selection 
-  * @{
-  */
-
-#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
-                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
-                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
-                                        ((SELECTION) == TIM_ICSelection_TRC))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Prescaler 
-  * @{
-  */
-
-#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_interrupt_sources 
-  * @{
-  */
-
-#define TIM_IT_Update                      ((uint16_t)0x0001)
-#define TIM_IT_CC1                         ((uint16_t)0x0002)
-#define TIM_IT_CC2                         ((uint16_t)0x0004)
-#define TIM_IT_CC3                         ((uint16_t)0x0008)
-#define TIM_IT_CC4                         ((uint16_t)0x0010)
-#define TIM_IT_COM                         ((uint16_t)0x0020)
-#define TIM_IT_Trigger                     ((uint16_t)0x0040)
-#define TIM_IT_Break                       ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
-                           ((IT) == TIM_IT_CC1) || \
-                           ((IT) == TIM_IT_CC2) || \
-                           ((IT) == TIM_IT_CC3) || \
-                           ((IT) == TIM_IT_CC4) || \
-                           ((IT) == TIM_IT_COM) || \
-                           ((IT) == TIM_IT_Trigger) || \
-                           ((IT) == TIM_IT_Break))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_Base_address 
-  * @{
-  */
-
-#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
-#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
-#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
-#define TIM_DMABase_SR                     ((uint16_t)0x0004)
-#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
-#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
-#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
-#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
-#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
-#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
-#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
-                               ((BASE) == TIM_DMABase_CR2) || \
-                               ((BASE) == TIM_DMABase_SMCR) || \
-                               ((BASE) == TIM_DMABase_DIER) || \
-                               ((BASE) == TIM_DMABase_SR) || \
-                               ((BASE) == TIM_DMABase_EGR) || \
-                               ((BASE) == TIM_DMABase_CCMR1) || \
-                               ((BASE) == TIM_DMABase_CCMR2) || \
-                               ((BASE) == TIM_DMABase_CCER) || \
-                               ((BASE) == TIM_DMABase_CNT) || \
-                               ((BASE) == TIM_DMABase_PSC) || \
-                               ((BASE) == TIM_DMABase_ARR) || \
-                               ((BASE) == TIM_DMABase_RCR) || \
-                               ((BASE) == TIM_DMABase_CCR1) || \
-                               ((BASE) == TIM_DMABase_CCR2) || \
-                               ((BASE) == TIM_DMABase_CCR3) || \
-                               ((BASE) == TIM_DMABase_CCR4) || \
-                               ((BASE) == TIM_DMABase_BDTR) || \
-                               ((BASE) == TIM_DMABase_DCR))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_Burst_Length 
-  * @{
-  */
-
-#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
-                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_sources 
-  * @{
-  */
-
-#define TIM_DMA_Update                     ((uint16_t)0x0100)
-#define TIM_DMA_CC1                        ((uint16_t)0x0200)
-#define TIM_DMA_CC2                        ((uint16_t)0x0400)
-#define TIM_DMA_CC3                        ((uint16_t)0x0800)
-#define TIM_DMA_CC4                        ((uint16_t)0x1000)
-#define TIM_DMA_COM                        ((uint16_t)0x2000)
-#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Prescaler 
-  * @{
-  */
-
-#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Internal_Trigger_Selection 
-  * @{
-  */
-
-#define TIM_TS_ITR0                        ((uint16_t)0x0000)
-#define TIM_TS_ITR1                        ((uint16_t)0x0010)
-#define TIM_TS_ITR2                        ((uint16_t)0x0020)
-#define TIM_TS_ITR3                        ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
-#define TIM_TS_ETRF                        ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                             ((SELECTION) == TIM_TS_ITR1) || \
-                                             ((SELECTION) == TIM_TS_ITR2) || \
-                                             ((SELECTION) == TIM_TS_ITR3) || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1) || \
-                                             ((SELECTION) == TIM_TS_TI2FP2) || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                      ((SELECTION) == TIM_TS_ITR1) || \
-                                                      ((SELECTION) == TIM_TS_ITR2) || \
-                                                      ((SELECTION) == TIM_TS_ITR3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_TIx_External_Clock_Source 
-  * @{
-  */
-
-#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
-#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
-                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
-                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Polarity 
-  * @{
-  */ 
-#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
-                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Prescaler_Reload_Mode 
-  * @{
-  */
-
-#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
-                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Forced_Action 
-  * @{
-  */
-
-#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
-                                      ((ACTION) == TIM_ForcedAction_InActive))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Encoder_Mode 
-  * @{
-  */
-
-#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
-                                   ((MODE) == TIM_EncoderMode_TI2) || \
-                                   ((MODE) == TIM_EncoderMode_TI12))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup TIM_Event_Source 
-  * @{
-  */
-
-#define TIM_EventSource_Update             ((uint16_t)0x0001)
-#define TIM_EventSource_CC1                ((uint16_t)0x0002)
-#define TIM_EventSource_CC2                ((uint16_t)0x0004)
-#define TIM_EventSource_CC3                ((uint16_t)0x0008)
-#define TIM_EventSource_CC4                ((uint16_t)0x0010)
-#define TIM_EventSource_COM                ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
-#define TIM_EventSource_Break              ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Update_Source 
-  * @{
-  */
-
-#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
-                                                                   or the setting of UG bit, or an update generation
-                                                                   through the slave mode controller. */
-#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
-                                      ((SOURCE) == TIM_UpdateSource_Regular))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Preload_State 
-  * @{
-  */
-
-#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
-                                       ((STATE) == TIM_OCPreload_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Fast_State 
-  * @{
-  */
-
-#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
-#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
-                                    ((STATE) == TIM_OCFast_Disable))
-                                     
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Clear_State 
-  * @{
-  */
-
-#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
-#define TIM_OCClear_Disable                ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
-                                     ((STATE) == TIM_OCClear_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Trigger_Output_Source 
-  * @{
-  */
-
-#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
-                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
-                                    ((SOURCE) == TIM_TRGOSource_Update) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Slave_Mode 
-  * @{
-  */
-
-#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
-                                 ((MODE) == TIM_SlaveMode_Gated) || \
-                                 ((MODE) == TIM_SlaveMode_Trigger) || \
-                                 ((MODE) == TIM_SlaveMode_External1))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Master_Slave_Mode 
-  * @{
-  */
-
-#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
-                                 ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Flags 
-  * @{
-  */
-
-#define TIM_FLAG_Update                    ((uint16_t)0x0001)
-#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
-#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
-#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
-#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
-#define TIM_FLAG_COM                       ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
-#define TIM_FLAG_Break                     ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
-                               ((FLAG) == TIM_FLAG_CC1) || \
-                               ((FLAG) == TIM_FLAG_CC2) || \
-                               ((FLAG) == TIM_FLAG_CC3) || \
-                               ((FLAG) == TIM_FLAG_CC4) || \
-                               ((FLAG) == TIM_FLAG_COM) || \
-                               ((FLAG) == TIM_FLAG_Trigger) || \
-                               ((FLAG) == TIM_FLAG_Break) || \
-                               ((FLAG) == TIM_FLAG_CC1OF) || \
-                               ((FLAG) == TIM_FLAG_CC2OF) || \
-                               ((FLAG) == TIM_FLAG_CC3OF) || \
-                               ((FLAG) == TIM_FLAG_CC4OF))
-                               
-                               
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Filer_Value 
-  * @{
-  */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Filter 
-  * @{
-  */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Legacy 
-  * @{
-  */
-
-#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Exported_Functions
-  * @{
-  */
-
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
-                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                             uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
-                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                   uint16_t ExtTRGFilter);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
-                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F10x_TIM_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
deleted file mode 100644
index 162fa87..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_usart.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file contains all the functions prototypes for the USART 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_USART_H
-#define __STM32F10x_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */ 
-
-/** @defgroup USART_Exported_Types
-  * @{
-  */ 
-
-/** 
-  * @brief  USART Init Structure definition  
-  */ 
-  
-typedef struct
-{
-  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
-                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
-
-  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint16_t USART_Parity;              /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitTypeDef;
-
-/** 
-  * @brief  USART Clock Init Structure definition  
-  */ 
-  
-typedef struct
-{
-
-  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
-                               This parameter can be a value of @ref USART_Clock */
-
-  uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.
-                               This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
-                               This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                               This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Exported_Constants
-  * @{
-  */ 
-  
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                     ((PERIPH) == USART2) || \
-                                     ((PERIPH) == USART3) || \
-                                     ((PERIPH) == UART4) || \
-                                     ((PERIPH) == UART5))
-
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                     ((PERIPH) == USART2) || \
-                                     ((PERIPH) == USART3))
-
-#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                      ((PERIPH) == USART2) || \
-                                      ((PERIPH) == USART3) || \
-                                      ((PERIPH) == UART4))
-/** @defgroup USART_Word_Length 
-  * @{
-  */ 
-  
-#define USART_WordLength_8b                  ((uint16_t)0x0000)
-#define USART_WordLength_9b                  ((uint16_t)0x1000)
-                                    
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
-                                      ((LENGTH) == USART_WordLength_9b))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Stop_Bits 
-  * @{
-  */ 
-  
-#define USART_StopBits_1                     ((uint16_t)0x0000)
-#define USART_StopBits_0_5                   ((uint16_t)0x1000)
-#define USART_StopBits_2                     ((uint16_t)0x2000)
-#define USART_StopBits_1_5                   ((uint16_t)0x3000)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
-                                     ((STOPBITS) == USART_StopBits_0_5) || \
-                                     ((STOPBITS) == USART_StopBits_2) || \
-                                     ((STOPBITS) == USART_StopBits_1_5))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Parity 
-  * @{
-  */ 
-  
-#define USART_Parity_No                      ((uint16_t)0x0000)
-#define USART_Parity_Even                    ((uint16_t)0x0400)
-#define USART_Parity_Odd                     ((uint16_t)0x0600) 
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
-                                 ((PARITY) == USART_Parity_Even) || \
-                                 ((PARITY) == USART_Parity_Odd))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Mode 
-  * @{
-  */ 
-  
-#define USART_Mode_Rx                        ((uint16_t)0x0004)
-#define USART_Mode_Tx                        ((uint16_t)0x0008)
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Hardware_Flow_Control 
-  * @{
-  */ 
-#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == USART_HardwareFlowControl_None) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock 
-  * @{
-  */ 
-#define USART_Clock_Disable                  ((uint16_t)0x0000)
-#define USART_Clock_Enable                   ((uint16_t)0x0800)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
-                               ((CLOCK) == USART_Clock_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Polarity 
-  * @{
-  */
-  
-#define USART_CPOL_Low                       ((uint16_t)0x0000)
-#define USART_CPOL_High                      ((uint16_t)0x0400)
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Phase
-  * @{
-  */
-
-#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
-#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit
-  * @{
-  */
-
-#define USART_LastBit_Disable                ((uint16_t)0x0000)
-#define USART_LastBit_Enable                 ((uint16_t)0x0100)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
-                                   ((LASTBIT) == USART_LastBit_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Interrupt_definition 
-  * @{
-  */
-  
-#define USART_IT_PE                          ((uint16_t)0x0028)
-#define USART_IT_TXE                         ((uint16_t)0x0727)
-#define USART_IT_TC                          ((uint16_t)0x0626)
-#define USART_IT_RXNE                        ((uint16_t)0x0525)
-#define USART_IT_IDLE                        ((uint16_t)0x0424)
-#define USART_IT_LBD                         ((uint16_t)0x0846)
-#define USART_IT_CTS                         ((uint16_t)0x096A)
-#define USART_IT_ERR                         ((uint16_t)0x0060)
-#define USART_IT_ORE                         ((uint16_t)0x0360)
-#define USART_IT_NE                          ((uint16_t)0x0260)
-#define USART_IT_FE                          ((uint16_t)0x0160)
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                               ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                               ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                               ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                            ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                            ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                            ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
-                            ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
-/**
-  * @}
-  */
-
-/** @defgroup USART_DMA_Requests 
-  * @{
-  */
-
-#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
-#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_WakeUp_methods
-  * @{
-  */
-
-#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
-                                 ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
-  * @}
-  */
-
-/** @defgroup USART_LIN_Break_Detection_Length 
-  * @{
-  */
-  
-#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
-                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
-                                ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
-  * @}
-  */
-
-/** @defgroup USART_IrDA_Low_Power 
-  * @{
-  */
-
-#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
-                                  ((MODE) == USART_IrDAMode_Normal))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Flags 
-  * @{
-  */
-
-#define USART_FLAG_CTS                       ((uint16_t)0x0200)
-#define USART_FLAG_LBD                       ((uint16_t)0x0100)
-#define USART_FLAG_TXE                       ((uint16_t)0x0080)
-#define USART_FLAG_TC                        ((uint16_t)0x0040)
-#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
-#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
-#define USART_FLAG_ORE                       ((uint16_t)0x0008)
-#define USART_FLAG_NE                        ((uint16_t)0x0004)
-#define USART_FLAG_FE                        ((uint16_t)0x0002)
-#define USART_FLAG_PE                        ((uint16_t)0x0001)
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
-                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
-                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
-                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
-                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
-                              
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
-                                                  ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
-                                                  || ((USART_FLAG) != USART_FLAG_CTS)) 
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Exported_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Exported_Functions
-  * @{
-  */
-
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-void USART_SendBreak(USART_TypeDef* USARTx);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_USART_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
deleted file mode 100644
index c0a5e11..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the miscellaneous firmware functions (add-on
-  *          to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "misc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup MISC 
-  * @brief MISC driver modules
-  * @{
-  */
-
-/** @defgroup MISC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup MISC_Private_Defines
-  * @{
-  */
-
-#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
-  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
-  *                                4 bits for subpriority
-  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
-  *                                3 bits for subpriority
-  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
-  *                                2 bits for subpriority
-  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
-  *                                1 bits for subpriority
-  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
-  *                                0 bits for subpriority
-  * @retval None
-  */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
-  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
-  * @brief  Initializes the NVIC peripheral according to the specified
-  *         parameters in the NVIC_InitStruct.
-  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
-  *         the configuration information for the specified NVIC peripheral.
-  * @retval None
-  */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
-  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
-  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-    
-  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
-  {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/    
-    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
-    tmppre = (0x4 - tmppriority);
-    tmpsub = tmpsub >> tmppriority;
-
-    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
-    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
-    tmppriority = tmppriority << 0x04;
-        
-    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-    
-    /* Enable the Selected IRQ Channels --------------------------------------*/
-    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-  else
-  {
-    /* Disable the Selected IRQ Channels -------------------------------------*/
-    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-}
-
-/**
-  * @brief  Sets the vector table location and Offset.
-  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_VectTab_RAM
-  *     @arg NVIC_VectTab_FLASH
-  * @param  Offset: Vector Table base offset field. This value must be a multiple 
-  *         of 0x200.
-  * @retval None
-  */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{ 
-  /* Check the parameters */
-  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
-  assert_param(IS_NVIC_OFFSET(Offset));  
-   
-  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
-  * @brief  Selects the condition for the system to enter low power mode.
-  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_LP_SEVONPEND
-  *     @arg NVIC_LP_SLEEPDEEP
-  *     @arg NVIC_LP_SLEEPONEXIT
-  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_LP(LowPowerMode));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if (NewState != DISABLE)
-  {
-    SCB->SCR |= LowPowerMode;
-  }
-  else
-  {
-    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
-  }
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  SysTick_CLKSource: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
-  {
-    SysTick->CTRL |= SysTick_CLKSource_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
deleted file mode 100644
index 997eecc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_bkp.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the BKP firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup BKP 
-  * @brief BKP driver modules
-  * @{
-  */
-
-/** @defgroup BKP_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Defines
-  * @{
-  */
-
-/* ------------ BKP registers bit address in the alias region --------------- */
-#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
-
-/* --- CR Register ----*/
-
-/* Alias word address of TPAL bit */
-#define CR_OFFSET         (BKP_OFFSET + 0x30)
-#define TPAL_BitNumber    0x01
-#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
-
-/* Alias word address of TPE bit */
-#define TPE_BitNumber     0x00
-#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TPIE bit */
-#define CSR_OFFSET        (BKP_OFFSET + 0x34)
-#define TPIE_BitNumber    0x02
-#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
-
-/* Alias word address of TIF bit */
-#define TIF_BitNumber     0x09
-#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
-
-/* Alias word address of TEF bit */
-#define TEF_BitNumber     0x08
-#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
-
-/* ---------------------- BKP registers bit mask ------------------------ */
-
-/* RTCCR register bit mask */
-#define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
-#define RTCCR_MASK        ((uint16_t)0xFC7F)
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup BKP_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup BKP_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void BKP_DeInit(void)
-{
-  RCC_BackupResetCmd(ENABLE);
-  RCC_BackupResetCmd(DISABLE);
-}
-
-/**
-  * @brief  Configures the Tamper Pin active level.
-  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
-  *   This parameter can be one of the following values:
-  *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
-  *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
-  * @retval None
-  */
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
-{
-  /* Check the parameters */
-  assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
-  *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
-}
-
-/**
-  * @brief  Enables or disables the Tamper Pin activation.
-  * @param  NewState: new state of the Tamper Pin activation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void BKP_TamperPinCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Tamper Pin Interrupt.
-  * @param  NewState: new state of the Tamper Pin Interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void BKP_ITConfig(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Select the RTC output source to output on the Tamper pin.
-  * @param  BKP_RTCOutputSource: specifies the RTC output source.
-  *   This parameter can be one of the following values:
-  *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
-  *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
-  *                                          divided by 64 on the Tamper pin.
-  *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
-  *                                     the Tamper pin.
-  *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
-  *                                      the Tamper pin.  
-  * @retval None
-  */
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
-{
-  uint16_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
-  tmpreg = BKP->RTCCR;
-  /* Clear CCO, ASOE and ASOS bits */
-  tmpreg &= RTCCR_MASK;
-  
-  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
-  tmpreg |= BKP_RTCOutputSource;
-  /* Store the new value */
-  BKP->RTCCR = tmpreg;
-}
-
-/**
-  * @brief  Sets RTC Clock Calibration value.
-  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
-  *   This parameter must be a number between 0 and 0x7F.
-  * @retval None
-  */
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
-{
-  uint16_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
-  tmpreg = BKP->RTCCR;
-  /* Clear CAL[6:0] bits */
-  tmpreg &= RTCCR_CAL_MASK;
-  /* Set CAL[6:0] bits according to CalibrationValue value */
-  tmpreg |= CalibrationValue;
-  /* Store the new value */
-  BKP->RTCCR = tmpreg;
-}
-
-/**
-  * @brief  Writes user data to the specified Data Backup Register.
-  * @param  BKP_DR: specifies the Data Backup Register.
-  *   This parameter can be BKP_DRx where x:[1, 42]
-  * @param  Data: data to write
-  * @retval None
-  */
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_BKP_DR(BKP_DR));
-
-  tmp = (uint32_t)BKP_BASE; 
-  tmp += BKP_DR;
-
-  *(__IO uint32_t *) tmp = Data;
-}
-
-/**
-  * @brief  Reads data from the specified Data Backup Register.
-  * @param  BKP_DR: specifies the Data Backup Register.
-  *   This parameter can be BKP_DRx where x:[1, 42]
-  * @retval The content of the specified Data Backup Register
-  */
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_BKP_DR(BKP_DR));
-
-  tmp = (uint32_t)BKP_BASE; 
-  tmp += BKP_DR;
-
-  return (*(__IO uint16_t *) tmp);
-}
-
-/**
-  * @brief  Checks whether the Tamper Pin Event flag is set or not.
-  * @param  None
-  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
-  */
-FlagStatus BKP_GetFlagStatus(void)
-{
-  return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
-}
-
-/**
-  * @brief  Clears Tamper Pin Event pending flag.
-  * @param  None
-  * @retval None
-  */
-void BKP_ClearFlag(void)
-{
-  /* Set CTE bit to clear Tamper Pin Event flag */
-  BKP->CSR |= BKP_CSR_CTE;
-}
-
-/**
-  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
-  * @param  None
-  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
-  */
-ITStatus BKP_GetITStatus(void)
-{
-  return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
-}
-
-/**
-  * @brief  Clears Tamper Pin Interrupt pending bit.
-  * @param  None
-  * @retval None
-  */
-void BKP_ClearITPendingBit(void)
-{
-  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
-  BKP->CSR |= BKP_CSR_CTI;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
deleted file mode 100644
index ec8e049..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
+++ /dev/null
@@ -1,1415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_can.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the CAN firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_can.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CAN 
-  * @brief CAN driver modules
-  * @{
-  */ 
-
-/** @defgroup CAN_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Defines
-  * @{
-  */
-
-/* CAN Master Control Register bits */
-
-#define MCR_DBF      ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ  ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT    ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT        ((uint32_t)0x0000FFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT        ((uint32_t)0x0000FFFF)
-
-
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR              ((uint32_t)0x08000000) 
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R             ((uint32_t)0x04000000) 
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R             ((uint32_t)0x02000000) 
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR              ((uint32_t)0x01000000) 
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR              ((uint32_t)0x00F00000) 
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0                   ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1                   ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2                   ((uint8_t)0x02) 
-
-
-
-#define CAN_MODE_MASK              ((uint32_t) 0x00000003)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_FunctionPrototypes
-  * @{
-  */
-
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
-  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
-  * @retval None.
-  */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
- 
-  if (CANx == CAN1)
-  {
-    /* Enable CAN1 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
-    /* Release CAN1 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
-  }
-  else
-  {  
-    /* Enable CAN2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
-    /* Release CAN2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  CANx:           where x can be 1 or 2 to to select the CAN 
-  *                         peripheral.
-  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
-  *                         contains the configuration information for the 
-  *                         CAN peripheral.
-  * @retval Constant indicates initialization succeed which will be 
-  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
-  */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
-  uint8_t InitStatus = CAN_InitStatus_Failed;
-  uint32_t wait_ack = 0x00000000;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
-  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
-  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
-  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
-  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
-  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
-  /* Exit from sleep mode */
-  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  CANx->MCR |= CAN_MCR_INRQ ;
-
-  /* Wait the acknowledge */
-  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
-  {
-    wait_ack++;
-  }
-
-  /* Check acknowledge */
-  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
-  {
-    InitStatus = CAN_InitStatus_Failed;
-  }
-  else 
-  {
-    /* Set the time triggered communication mode */
-    if (CAN_InitStruct->CAN_TTCM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
-
-    /* Set the automatic bus-off management */
-    if (CAN_InitStruct->CAN_ABOM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
-
-    /* Set the automatic wake-up mode */
-    if (CAN_InitStruct->CAN_AWUM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
-
-    /* Set the no automatic retransmission */
-    if (CAN_InitStruct->CAN_NART == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_NART;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
-
-    /* Set the receive FIFO locked mode */
-    if (CAN_InitStruct->CAN_RFLM == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
-
-    /* Set the transmit FIFO priority */
-    if (CAN_InitStruct->CAN_TXFP == ENABLE)
-    {
-      CANx->MCR |= CAN_MCR_TXFP;
-    }
-    else
-    {
-      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
-                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
-                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
-                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
-               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
-    /* Request leave initialisation */
-    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
-   /* Wait the acknowledge */
-   wait_ack = 0;
-
-   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
-   {
-     wait_ack++;
-   }
-
-    /* ...and check acknowledged */
-    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      InitStatus = CAN_InitStatus_Failed;
-    }
-    else
-    {
-      InitStatus = CAN_InitStatus_Success ;
-    }
-  }
-
-  /* At this step, return the status of initialization */
-  return InitStatus;
-}
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
-  *                               structure that contains the configuration 
-  *                               information.
-  * @retval None.
-  */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
-  uint32_t filter_number_bit_pos = 0;
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
-  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
-  /* Initialisation mode for the filter */
-  CAN1->FMR |= FMR_FINIT;
-
-  /* Filter Deactivation */
-  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
-  /* Filter Scale */
-  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
-  {
-    /* 16-bit scale for the filter */
-    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
-  }
-
-  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
-  {
-    /* 32-bit scale for the filter */
-    CAN1->FS1R |= filter_number_bit_pos;
-    /* 32-bit identifier or First 32-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-    /* 32-bit mask or Second 32-bit identifier */
-    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
-    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
-  }
-
-  /* Filter Mode */
-  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
-  {
-    /*Id/Mask mode for the filter*/
-    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
-  }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-  {
-    /*Identifier list mode for the filter*/
-    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
-  }
-
-  /* Filter FIFO assignment */
-  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
-  {
-    /* FIFO 0 assignation for the filter */
-    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
-  }
-
-  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
-  {
-    /* FIFO 1 assignation for the filter */
-    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
-  }
-  
-  /* Filter activation */
-  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
-  {
-    CAN1->FA1R |= filter_number_bit_pos;
-  }
-
-  /* Leave the initialisation mode for the filter */
-  CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
-  * @brief  Fills each CAN_InitStruct member with its default value.
-  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
-  *                         will be initialized.
-  * @retval None.
-  */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
-  /* Reset CAN init structure parameters values */
-  
-  /* Initialize the time triggered communication mode */
-  CAN_InitStruct->CAN_TTCM = DISABLE;
-  
-  /* Initialize the automatic bus-off management */
-  CAN_InitStruct->CAN_ABOM = DISABLE;
-  
-  /* Initialize the automatic wake-up mode */
-  CAN_InitStruct->CAN_AWUM = DISABLE;
-  
-  /* Initialize the no automatic retransmission */
-  CAN_InitStruct->CAN_NART = DISABLE;
-  
-  /* Initialize the receive FIFO locked mode */
-  CAN_InitStruct->CAN_RFLM = DISABLE;
-  
-  /* Initialize the transmit FIFO priority */
-  CAN_InitStruct->CAN_TXFP = DISABLE;
-  
-  /* Initialize the CAN_Mode member */
-  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-  
-  /* Initialize the CAN_SJW member */
-  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-  
-  /* Initialize the CAN_BS1 member */
-  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-  
-  /* Initialize the CAN_BS2 member */
-  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-  
-  /* Initialize the CAN_Prescaler member */
-  CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
-  * @brief  Select the start bank filter for slave CAN.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
-  * @retval None.
-  */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-  
-  /* Enter Initialisation mode for the filter */
-  CAN1->FMR |= FMR_FINIT;
-  
-  /* Select the start slave bank */
-  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
-  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-  
-  /* Leave Initialisation mode for the filter */
-  CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
-  * @brief  Enables or disables the DBG Freeze for CAN.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  NewState: new state of the CAN peripheral. This parameter can 
-  *                   be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Debug Freeze  */
-    CANx->MCR |= MCR_DBF;
-  }
-  else
-  {
-    /* Disable Debug Freeze */
-    CANx->MCR &= ~MCR_DBF;
-  }
-}
-
-
-/**
-  * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
-  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  NewState : Mode new state , can be one of @ref FunctionalState.
-  * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last 
-  *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6 
-  *         and TIME[15:8] in data byte 7 
-  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
-  *         sent over the CAN bus.  
-  * @retval None
-  */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the TTCM mode */
-    CANx->MCR |= CAN_MCR_TTCM;
-
-    /* Set TGT bits */
-    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
-    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
-    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
-  }
-  else
-  {
-    /* Disable the TTCM mode */
-    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
-    /* Reset TGT bits */
-    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
-    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
-    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
-  }
-}
-/**
-  * @brief  Initiates the transmission of a message.
-  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN
-  *                    DLC and CAN data.
-  * @retval The number of the mailbox that is used for transmission
-  *                    or CAN_TxStatus_NoMailBox if there is no empty mailbox.
-  */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
-  uint8_t transmit_mailbox = 0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
-  assert_param(IS_CAN_RTR(TxMessage->RTR));
-  assert_param(IS_CAN_DLC(TxMessage->DLC));
-
-  /* Select one empty transmit mailbox */
-  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
-  {
-    transmit_mailbox = 0;
-  }
-  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
-  {
-    transmit_mailbox = 1;
-  }
-  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
-  {
-    transmit_mailbox = 2;
-  }
-  else
-  {
-    transmit_mailbox = CAN_TxStatus_NoMailBox;
-  }
-
-  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
-  {
-    /* Set up the Id */
-    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
-    if (TxMessage->IDE == CAN_Id_Standard)
-    {
-      assert_param(IS_CAN_STDID(TxMessage->StdId));  
-      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
-                                                  TxMessage->RTR);
-    }
-    else
-    {
-      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
-      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
-                                                  TxMessage->IDE | \
-                                                  TxMessage->RTR);
-    }
-    
-    /* Set up the DLC */
-    TxMessage->DLC &= (uint8_t)0x0000000F;
-    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
-    /* Set up the data field */
-    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
-                                             ((uint32_t)TxMessage->Data[2] << 16) |
-                                             ((uint32_t)TxMessage->Data[1] << 8) | 
-                                             ((uint32_t)TxMessage->Data[0]));
-    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
-                                             ((uint32_t)TxMessage->Data[6] << 16) |
-                                             ((uint32_t)TxMessage->Data[5] << 8) |
-                                             ((uint32_t)TxMessage->Data[4]));
-    /* Request transmission */
-    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
-  }
-  return transmit_mailbox;
-}
-
-/**
-  * @brief  Checks the transmission of a message.
-  * @param  CANx:            where x can be 1 or 2 to to select the 
-  *                          CAN peripheral.
-  * @param  TransmitMailbox: the number of the mailbox that is used for 
-  *                          transmission.
-  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed 
-  *         in an other case.
-  */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
-  uint32_t state = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
- 
-  switch (TransmitMailbox)
-  {
-    case (CAN_TXMAILBOX_0): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
-      break;
-    case (CAN_TXMAILBOX_1): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
-      break;
-    case (CAN_TXMAILBOX_2): 
-      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
-      break;
-    default:
-      state = CAN_TxStatus_Failed;
-      break;
-  }
-  switch (state)
-  {
-      /* transmit pending  */
-    case (0x0): state = CAN_TxStatus_Pending;
-      break;
-      /* transmit failed  */
-     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
-      break;
-     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
-      break;
-     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
-      break;
-      /* transmit succeeded  */
-    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
-      break;
-    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
-      break;
-    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
-      break;
-    default: state = CAN_TxStatus_Failed;
-      break;
-  }
-  return (uint8_t) state;
-}
-
-/**
-  * @brief  Cancels a transmit request.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral. 
-  * @param  Mailbox:  Mailbox number.
-  * @retval None.
-  */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
-  /* abort transmission */
-  switch (Mailbox)
-  {
-    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
-      break;
-    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
-      break;
-    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
-      break;
-    default:
-      break;
-  }
-}
-
-
-/**
-  * @brief  Receives a message.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @param  RxMessage:  pointer to a structure receive message which contains 
-  *                     CAN Id, CAN DLC, CAN datas and FMI number.
-  * @retval None.
-  */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  /* Get the Id */
-  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
-  if (RxMessage->IDE == CAN_Id_Standard)
-  {
-    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
-  {
-    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
-  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
-  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    CANx->RF0R |= CAN_RF0R_RFOM0;
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    CANx->RF1R |= CAN_RF1R_RFOM1;
-  }
-}
-
-/**
-  * @brief  Releases the specified FIFO.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral. 
-  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None.
-  */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    CANx->RF0R |= CAN_RF0R_RFOM0;
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    CANx->RF1R |= CAN_RF1R_RFOM1;
-  }
-}
-
-/**
-  * @brief  Returns the number of pending messages.
-  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval NbMessage : which is the number of pending message.
-  */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
-  uint8_t message_pending=0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  if (FIFONumber == CAN_FIFO0)
-  {
-    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
-  }
-  else if (FIFONumber == CAN_FIFO1)
-  {
-    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
-  }
-  else
-  {
-    message_pending = 0;
-  }
-  return message_pending;
-}
-
-
-/**
-  * @brief   Select the CAN Operation mode.
-  * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one 
-  *                            of @ref CAN_OperatingMode_TypeDef enumeration.
-  * @retval status of the requested mode which can be 
-  *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode 
-  *         - CAN_ModeStatus_Success   CAN Succeed entering the specific mode 
-
-  */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
-  uint8_t status = CAN_ModeStatus_Failed;
-  
-  /* Timeout for INAK or also for SLAK bits*/
-  uint32_t timeout = INAK_TIMEOUT; 
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
-  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
-  {
-    /* Request initialisation */
-    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
-  {
-    /* Request leave initialisation and sleep mode  and enter Normal mode */
-    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != 0)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
-  {
-    /* Request Sleep mode */
-    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
-    /* Wait the acknowledge */
-    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
-    {
-      timeout--;
-    }
-    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
-    {
-      status = CAN_ModeStatus_Failed;
-    }
-    else
-    {
-      status = CAN_ModeStatus_Success;
-    }
-  }
-  else
-  {
-    status = CAN_ModeStatus_Failed;
-  }
-
-  return  (uint8_t) status;
-}
-
-/**
-  * @brief  Enters the low power mode.
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
-  * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an 
-  *                 other case.
-  */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
-  uint8_t sleepstatus = CAN_Sleep_Failed;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-    
-  /* Request Sleep mode */
-   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-   
-  /* Sleep mode status */
-  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
-  {
-    /* Sleep mode not entered */
-    sleepstatus =  CAN_Sleep_Ok;
-  }
-  /* return sleep mode status */
-   return (uint8_t)sleepstatus;
-}
-
-/**
-  * @brief  Wakes the CAN up.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @retval status:  CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an 
-  *                  other case.
-  */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
-  uint32_t wait_slak = SLAK_TIMEOUT;
-  uint8_t wakeupstatus = CAN_WakeUp_Failed;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-    
-  /* Wake up request */
-  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-    
-  /* Sleep mode status */
-  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
-  {
-   wait_slak--;
-  }
-  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
-  {
-   /* wake up done : Sleep mode exited */
-    wakeupstatus = CAN_WakeUp_Ok;
-  }
-  /* return wakeup status */
-  return (uint8_t)wakeupstatus;
-}
-
-
-/**
-  * @brief  Returns the CANx's last error code (LEC).
-  * @param  CANx:          where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval CAN_ErrorCode: specifies the Error code : 
-  *                        - CAN_ERRORCODE_NoErr            No Error  
-  *                        - CAN_ERRORCODE_StuffErr         Stuff Error
-  *                        - CAN_ERRORCODE_FormErr          Form Error
-  *                        - CAN_ERRORCODE_ACKErr           Acknowledgment Error
-  *                        - CAN_ERRORCODE_BitRecessiveErr  Bit Recessive Error
-  *                        - CAN_ERRORCODE_BitDominantErr   Bit Dominant Error
-  *                        - CAN_ERRORCODE_CRCErr           CRC Error
-  *                        - CAN_ERRORCODE_SoftwareSetErr   Software Set Error  
-  */
- 
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
-  uint8_t errorcode=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the error code*/
-  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-  
-  /* Return the error code*/
-  return errorcode;
-}
-/**
-  * @brief  Returns the CANx Receive Error Counter (REC).
-  * @note   In case of an error during reception, this counter is incremented 
-  *         by 1 or by 8 depending on the error condition as defined by the CAN 
-  *         standard. After every successful reception, the counter is 
-  *         decremented by 1 or reset to 120 if its value was higher than 128. 
-  *         When the counter value exceeds 127, the CAN controller enters the 
-  *         error passive state.  
-  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval CAN Receive Error Counter. 
-  */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
-  uint8_t counter=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the Receive Error Counter*/
-  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-  
-  /* Return the Receive Error Counter*/
-  return counter;
-}
-
-
-/**
-  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.  
-  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
-  */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
-  uint8_t counter=0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  
-  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
-  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-  
-  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
-  return counter;
-}
-
-
-/**
-  * @brief  Enables or disables the specified CANx interrupts.
-  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
-  *                 This parameter can be: 
-  *                 - CAN_IT_TME, 
-  *                 - CAN_IT_FMP0, 
-  *                 - CAN_IT_FF0,
-  *                 - CAN_IT_FOV0, 
-  *                 - CAN_IT_FMP1, 
-  *                 - CAN_IT_FF1,
-  *                 - CAN_IT_FOV1, 
-  *                 - CAN_IT_EWG, 
-  *                 - CAN_IT_EPV,
-  *                 - CAN_IT_LEC, 
-  *                 - CAN_IT_ERR, 
-  *                 - CAN_IT_WKU or 
-  *                 - CAN_IT_SLK.
-  * @param  NewState: new state of the CAN interrupts.
-  *                   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IT(CAN_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected CANx interrupt */
-    CANx->IER |= CAN_IT;
-  }
-  else
-  {
-    /* Disable the selected CANx interrupt */
-    CANx->IER &= ~CAN_IT;
-  }
-}
-/**
-  * @brief  Checks whether the specified CAN flag is set or not.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_FLAG: specifies the flag to check.
-  *                   This parameter can be one of the following flags: 
-  *                  - CAN_FLAG_EWG
-  *                  - CAN_FLAG_EPV 
-  *                  - CAN_FLAG_BOF
-  *                  - CAN_FLAG_RQCP0
-  *                  - CAN_FLAG_RQCP1
-  *                  - CAN_FLAG_RQCP2
-  *                  - CAN_FLAG_FMP1   
-  *                  - CAN_FLAG_FF1       
-  *                  - CAN_FLAG_FOV1   
-  *                  - CAN_FLAG_FMP0   
-  *                  - CAN_FLAG_FF0       
-  *                  - CAN_FLAG_FOV0   
-  *                  - CAN_FLAG_WKU 
-  *                  - CAN_FLAG_SLAK  
-  *                  - CAN_FLAG_LEC       
-  * @retval The new state of CAN_FLAG (SET or RESET).
-  */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-  
-
-  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
-  { 
-    /* Check the status of the specified CAN flag */
-    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
-    { 
-      /* CAN_FLAG is set */
-      bitstatus = SET;
-    }
-    else
-    { 
-      /* CAN_FLAG is reset */
-      bitstatus = RESET;
-    }
-  }
-  /* Return the CAN_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CAN's pending flags.
-  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_FLAG: specifies the flag to clear.
-  *                   This parameter can be one of the following flags: 
-  *                    - CAN_FLAG_RQCP0
-  *                    - CAN_FLAG_RQCP1
-  *                    - CAN_FLAG_RQCP2
-  *                    - CAN_FLAG_FF1       
-  *                    - CAN_FLAG_FOV1   
-  *                    - CAN_FLAG_FF0       
-  *                    - CAN_FLAG_FOV0   
-  *                    - CAN_FLAG_WKU   
-  *                    - CAN_FLAG_SLAK    
-  *                    - CAN_FLAG_LEC       
-  * @retval None.
-  */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
-  uint32_t flagtmp=0;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-  
-  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
-  {
-    /* Clear the selected CAN flags */
-    CANx->ESR = (uint32_t)RESET;
-  }
-  else /* MSR or TSR or RF0R or RF1R */
-  {
-    flagtmp = CAN_FLAG & 0x000FFFFF;
-
-    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
-    {
-      /* Receive Flags */
-      CANx->RF0R = (uint32_t)(flagtmp);
-    }
-    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
-    {
-      /* Receive Flags */
-      CANx->RF1R = (uint32_t)(flagtmp);
-    }
-    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
-    {
-      /* Transmit Flags */
-      CANx->TSR = (uint32_t)(flagtmp);
-    }
-    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
-    {
-      /* Operating mode Flags */
-      CANx->MSR = (uint32_t)(flagtmp);
-    }
-  }
-}
-
-/**
-  * @brief  Checks whether the specified CANx interrupt has occurred or not.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT:  specifies the CAN interrupt source to check.
-  *                  This parameter can be one of the following flags: 
-  *                 -  CAN_IT_TME               
-  *                 -  CAN_IT_FMP0              
-  *                 -  CAN_IT_FF0               
-  *                 -  CAN_IT_FOV0              
-  *                 -  CAN_IT_FMP1              
-  *                 -  CAN_IT_FF1               
-  *                 -  CAN_IT_FOV1              
-  *                 -  CAN_IT_WKU  
-  *                 -  CAN_IT_SLK  
-  *                 -  CAN_IT_EWG    
-  *                 -  CAN_IT_EPV    
-  *                 -  CAN_IT_BOF    
-  *                 -  CAN_IT_LEC    
-  *                 -  CAN_IT_ERR 
-  * @retval The current state of CAN_IT (SET or RESET).
-  */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
-  ITStatus itstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_IT(CAN_IT));
-  
-  /* check the enable interrupt bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
-   /* in case the Interrupt is enabled, .... */
-    switch (CAN_IT)
-    {
-      case CAN_IT_TME:
-               /* Check CAN_TSR_RQCPx bits */
-	             itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
-	      break;
-      case CAN_IT_FMP0:
-               /* Check CAN_RF0R_FMP0 bit */
-	             itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
-	      break;
-      case CAN_IT_FF0:
-               /* Check CAN_RF0R_FULL0 bit */
-               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
-	      break;
-      case CAN_IT_FOV0:
-               /* Check CAN_RF0R_FOVR0 bit */
-               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
-	      break;
-      case CAN_IT_FMP1:
-               /* Check CAN_RF1R_FMP1 bit */
-               itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
-	      break;
-      case CAN_IT_FF1:
-               /* Check CAN_RF1R_FULL1 bit */
-	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
-	      break;
-      case CAN_IT_FOV1:
-               /* Check CAN_RF1R_FOVR1 bit */
-	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
-	      break;
-      case CAN_IT_WKU:
-               /* Check CAN_MSR_WKUI bit */
-               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
-	      break;
-      case CAN_IT_SLK:
-               /* Check CAN_MSR_SLAKI bit */
-	             itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
-	      break;
-      case CAN_IT_EWG:
-               /* Check CAN_ESR_EWGF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
-	      break;
-      case CAN_IT_EPV:
-               /* Check CAN_ESR_EPVF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
-	      break;
-      case CAN_IT_BOF:
-               /* Check CAN_ESR_BOFF bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
-	      break;
-      case CAN_IT_LEC:
-               /* Check CAN_ESR_LEC bit */
-	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
-	      break;
-      case CAN_IT_ERR:
-               /* Check CAN_MSR_ERRI bit */ 
-               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
-	      break;
-      default :
-               /* in case of error, return RESET */
-              itstatus = RESET;
-              break;
-    }
-  }
-  else
-  {
-   /* in case the Interrupt is not enabled, return RESET */
-    itstatus  = RESET;
-  }
-  
-  /* Return the CAN_IT status */
-  return  itstatus;
-}
-
-/**
-  * @brief  Clears the CANx's interrupt pending bits.
-  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
-  * @param  CAN_IT: specifies the interrupt pending bit to clear.
-  *                  -  CAN_IT_TME                     
-  *                  -  CAN_IT_FF0               
-  *                  -  CAN_IT_FOV0                     
-  *                  -  CAN_IT_FF1               
-  *                  -  CAN_IT_FOV1              
-  *                  -  CAN_IT_WKU  
-  *                  -  CAN_IT_SLK  
-  *                  -  CAN_IT_EWG    
-  *                  -  CAN_IT_EPV    
-  *                  -  CAN_IT_BOF    
-  *                  -  CAN_IT_LEC    
-  *                  -  CAN_IT_ERR 
-  * @retval None.
-  */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
-  switch (CAN_IT)
-  {
-      case CAN_IT_TME:
-              /* Clear CAN_TSR_RQCPx (rc_w1)*/
-	      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
-	      break;
-      case CAN_IT_FF0:
-              /* Clear CAN_RF0R_FULL0 (rc_w1)*/
-	      CANx->RF0R = CAN_RF0R_FULL0; 
-	      break;
-      case CAN_IT_FOV0:
-              /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
-	      CANx->RF0R = CAN_RF0R_FOVR0; 
-	      break;
-      case CAN_IT_FF1:
-              /* Clear CAN_RF1R_FULL1 (rc_w1)*/
-	      CANx->RF1R = CAN_RF1R_FULL1;  
-	      break;
-      case CAN_IT_FOV1:
-              /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
-	      CANx->RF1R = CAN_RF1R_FOVR1; 
-	      break;
-      case CAN_IT_WKU:
-              /* Clear CAN_MSR_WKUI (rc_w1)*/
-	      CANx->MSR = CAN_MSR_WKUI;  
-	      break;
-      case CAN_IT_SLK:
-              /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
-	      CANx->MSR = CAN_MSR_SLAKI;   
-	      break;
-      case CAN_IT_EWG:
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI;
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/ 
-	      break;
-      case CAN_IT_EPV:
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/
-	      break;
-      case CAN_IT_BOF:
-              /* Clear CAN_MSR_ERRI (rc_w1) */ 
-	      CANx->MSR = CAN_MSR_ERRI; 
-              /* Note : the corresponding Flag is cleared by hardware depending 
-                        of the CAN Bus status*/
-	      break;
-      case CAN_IT_LEC:
-              /*  Clear LEC bits */
-	      CANx->ESR = RESET; 
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-	      break;
-      case CAN_IT_ERR:
-              /*Clear LEC bits */
-	      CANx->ESR = RESET; 
-              /* Clear CAN_MSR_ERRI (rc_w1) */
-	      CANx->MSR = CAN_MSR_ERRI; 
-	      /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending 
-                  of the CAN Bus status*/
-	      break;
-      default :
-	      break;
-   }
-}
-
-/**
-  * @brief  Checks whether the CAN interrupt has occurred or not.
-  * @param  CAN_Reg: specifies the CAN interrupt register to check.
-  * @param  It_Bit:  specifies the interrupt source bit to check.
-  * @retval The new state of the CAN Interrupt (SET or RESET).
-  */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
-  ITStatus pendingbitstatus = RESET;
-  
-  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
-  {
-    /* CAN_IT is set */
-    pendingbitstatus = SET;
-  }
-  else
-  {
-    /* CAN_IT is reset */
-    pendingbitstatus = RESET;
-  }
-  return pendingbitstatus;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
deleted file mode 100644
index 4dc615f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_cec.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the CEC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_cec.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CEC 
-  * @brief CEC driver modules
-  * @{
-  */
-
-/** @defgroup CEC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CEC_Private_Defines
-  * @{
-  */ 
-
-/* ------------ CEC registers bit address in the alias region ----------- */
-#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
-
-/* --- CFGR Register ---*/
-
-/* Alias word address of PE bit */
-#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
-#define PE_BitNumber                0x00
-#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
-
-/* Alias word address of IE bit */
-#define IE_BitNumber                0x01
-#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of TSOM bit */
-#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
-#define TSOM_BitNumber              0x00
-#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
-
-/* Alias word address of TEOM bit */
-#define TEOM_BitNumber              0x01
-#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
-  
-#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
-#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_FunctionPrototypes
-  * @{
-  */
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup CEC_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Deinitializes the CEC peripheral registers to their default reset 
-  *         values.
-  * @param  None
-  * @retval None
-  */
-void CEC_DeInit(void)
-{
-  /* Enable CEC reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
-  /* Release CEC from reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
-}
-
-
-/**
-  * @brief  Initializes the CEC peripheral according to the specified 
-  *         parameters in the CEC_InitStruct.
-  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
-  *         contains the configuration information for the specified
-  *         CEC peripheral.
-  * @retval None
-  */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
-  uint16_t tmpreg = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
-  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
-     
-  /*---------------------------- CEC CFGR Configuration -----------------*/
-  /* Get the CEC CFGR value */
-  tmpreg = CEC->CFGR;
-  
-  /* Clear BTEM and BPEM bits */
-  tmpreg &= CFGR_CLEAR_Mask;
-  
-  /* Configure CEC: Bit Timing Error and Bit Period Error */
-  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
-
-  /* Write to CEC CFGR  register*/
-  CEC->CFGR = tmpreg;
-  
-}
-
-/**
-  * @brief  Enables or disables the specified CEC peripheral.
-  * @param  NewState: new state of the CEC peripheral. 
-  *     This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
-
-  if(NewState == DISABLE)
-  {
-    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
-    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
-    {
-    }  
-  }  
-}
-
-/**
-  * @brief  Enables or disables the CEC interrupt.
-  * @param  NewState: new state of the CEC interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_ITConfig(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Defines the Own Address of the CEC device.
-  * @param  CEC_OwnAddress: The CEC own address
-  * @retval None
-  */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
-  /* Check the parameters */
-  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
-
-  /* Set the CEC own address */
-  CEC->OAR = CEC_OwnAddress;
-}
-
-/**
-  * @brief  Sets the CEC prescaler value.
-  * @param  CEC_Prescaler: CEC prescaler new value
-  * @retval None
-  */
-void CEC_SetPrescaler(uint16_t CEC_Prescaler)
-{
-  /* Check the parameters */
-  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
-
-  /* Set the  Prescaler value*/
-  CEC->PRES = CEC_Prescaler;
-}
-
-/**
-  * @brief  Transmits single data through the CEC peripheral.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void CEC_SendDataByte(uint8_t Data)
-{  
-  /* Transmit Data */
-  CEC->TXD = Data ;
-}
-
-
-/**
-  * @brief  Returns the most recent received data by the CEC peripheral.
-  * @param  None
-  * @retval The received data.
-  */
-uint8_t CEC_ReceiveDataByte(void)
-{
-  /* Receive Data */
-  return (uint8_t)(CEC->RXD);
-}
-
-/**
-  * @brief  Starts a new message.
-  * @param  None
-  * @retval None
-  */
-void CEC_StartOfMessage(void)
-{  
-  /* Starts of new message */
-  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
-}
-
-/**
-  * @brief  Transmits message with or without an EOM bit.
-  * @param  NewState: new state of the CEC Tx End Of Message. 
-  *     This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_EndOfMessageCmd(FunctionalState NewState)
-{   
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  /* The data byte will be transmitted with or without an EOM bit*/
-  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Gets the CEC flag status
-  * @param  CEC_FLAG: specifies the CEC flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg CEC_FLAG_BTE: Bit Timing Error
-  *     @arg CEC_FLAG_BPE: Bit Period Error
-  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
-  *     @arg CEC_FLAG_SBE: Start Bit Error
-  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
-  *     @arg CEC_FLAG_LINE: Line Error
-  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
-  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
-  *     @arg CEC_FLAG_TERR: Tx Error
-  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
-  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
-  *     @arg CEC_FLAG_REOM: Rx End Of Message
-  *     @arg CEC_FLAG_RERR: Rx Error
-  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
-  * @retval The new state of CEC_FLAG (SET or RESET)
-  */
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t cecreg = 0, cecbase = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
- 
-  /* Get the CEC peripheral base address */
-  cecbase = (uint32_t)(CEC_BASE);
-  
-  /* Read flag register index */
-  cecreg = CEC_FLAG >> 28;
-  
-  /* Get bit[23:0] of the flag */
-  CEC_FLAG &= FLAG_Mask;
-  
-  if(cecreg != 0)
-  {
-    /* Flag in CEC ESR Register */
-    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
-    
-    /* Get the CEC ESR register address */
-    cecbase += 0xC;
-  }
-  else
-  {
-    /* Get the CEC CSR register address */
-    cecbase += 0x10;
-  }
-  
-  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
-  {
-    /* CEC_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the CEC_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's pending flags.
-  * @param  CEC_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_FLAG_TERR: Tx Error
-  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
-  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
-  *     @arg CEC_FLAG_REOM: Rx End Of Message
-  *     @arg CEC_FLAG_RERR: Rx Error
-  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
-  * @retval None
-  */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{ 
-  uint32_t tmp = 0x0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
-  tmp = CEC->CSR & 0x2;
-       
-  /* Clear the selected CEC flags */
-  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
-}
-
-/**
-  * @brief  Checks whether the specified CEC interrupt has occurred or not.
-  * @param  CEC_IT: specifies the CEC interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg CEC_IT_TERR: Tx Error
-  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_IT_RERR: Rx Error
-  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
-  * @retval The new state of CEC_IT (SET or RESET).
-  */
-ITStatus CEC_GetITStatus(uint8_t CEC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  
-  /* Check the parameters */
-   assert_param(IS_CEC_GET_IT(CEC_IT));
-   
-  /* Get the CEC IT enable bit status */
-  enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
-  
-  /* Check the status of the specified CEC interrupt */
-  if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
-  {
-    /* CEC_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the CEC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's interrupt pending bits.
-  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_IT_TERR: Tx Error
-  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
-  *     @arg CEC_IT_RERR: Rx Error
-  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
-  * @retval None
-  */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
-  uint32_t tmp = 0x0;
-  
-  /* Check the parameters */
-  assert_param(IS_CEC_GET_IT(CEC_IT));
-  
-  tmp = CEC->CSR & 0x2;
-  
-  /* Clear the selected CEC interrupt pending bits */
-  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
deleted file mode 100644
index 96a8fde..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dbgmcu.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the DBGMCU firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dbgmcu.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DBGMCU 
-  * @brief DBGMCU driver modules
-  * @{
-  */ 
-
-/** @defgroup DBGMCU_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Defines
-  * @{
-  */
-
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @param  None
-  * @retval Device revision identifier
-  */
-uint32_t DBGMCU_GetREVID(void)
-{
-   return(DBGMCU->IDCODE >> 16);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @param  None
-  * @retval Device identifier
-  */
-uint32_t DBGMCU_GetDEVID(void)
-{
-   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Configures the specified peripheral and low power mode behavior
-  *   when the MCU under Debug mode.
-  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
-  *   This parameter can be any combination of the following values:
-  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
-  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
-  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
-  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
-  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
-  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
-  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
-  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
-  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
-  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
-  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
-  *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
-  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
-  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
-  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
-  * @param  NewState: new state of the specified peripheral in Debug mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    DBGMCU->CR |= DBGMCU_Periph;
-  }
-  else
-  {
-    DBGMCU->CR &= ~DBGMCU_Periph;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
deleted file mode 100644
index bf072df..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_dma.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the DMA firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_dma.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DMA 
-  * @brief DMA driver modules
-  * @{
-  */ 
-
-/** @defgroup DMA_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Defines
-  * @{
-  */
-
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
-#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-
-/* DMA2 FLAG mask */
-#define FLAG_Mask                ((uint32_t)0x10000000)
-
-/* DMA registers Masks */
-#define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the DMAy Channelx registers to their default reset
-  *         values.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @retval None
-  */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  
-  /* Disable the selected DMAy Channelx */
-  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
-  
-  /* Reset DMAy Channelx control register */
-  DMAy_Channelx->CCR  = 0;
-  
-  /* Reset DMAy Channelx remaining bytes register */
-  DMAy_Channelx->CNDTR = 0;
-  
-  /* Reset DMAy Channelx peripheral address register */
-  DMAy_Channelx->CPAR  = 0;
-  
-  /* Reset DMAy Channelx memory address register */
-  DMAy_Channelx->CMAR = 0;
-  
-  if (DMAy_Channelx == DMA1_Channel1)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel1 */
-    DMA1->IFCR |= DMA1_Channel1_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel2)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel2 */
-    DMA1->IFCR |= DMA1_Channel2_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel3)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel3 */
-    DMA1->IFCR |= DMA1_Channel3_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel4)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel4 */
-    DMA1->IFCR |= DMA1_Channel4_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel5)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel5 */
-    DMA1->IFCR |= DMA1_Channel5_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel6)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel6 */
-    DMA1->IFCR |= DMA1_Channel6_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA1_Channel7)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel7 */
-    DMA1->IFCR |= DMA1_Channel7_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel1)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel1 */
-    DMA2->IFCR |= DMA2_Channel1_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel2)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel2 */
-    DMA2->IFCR |= DMA2_Channel2_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel3)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel3 */
-    DMA2->IFCR |= DMA2_Channel3_IT_Mask;
-  }
-  else if (DMAy_Channelx == DMA2_Channel4)
-  {
-    /* Reset interrupt pending bits for DMA2 Channel4 */
-    DMA2->IFCR |= DMA2_Channel4_IT_Mask;
-  }
-  else
-  { 
-    if (DMAy_Channelx == DMA2_Channel5)
-    {
-      /* Reset interrupt pending bits for DMA2 Channel5 */
-      DMA2->IFCR |= DMA2_Channel5_IT_Mask;
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the DMAy Channelx according to the specified
-  *         parameters in the DMA_InitStruct.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
-  *         contains the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
-  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
-  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
-  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
-  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
-  /* Get the DMAy_Channelx CCR value */
-  tmpreg = DMAy_Channelx->CCR;
-  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
-  tmpreg &= CCR_CLEAR_Mask;
-  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
-  /* Set DIR bit according to DMA_DIR value */
-  /* Set CIRC bit according to DMA_Mode value */
-  /* Set PINC bit according to DMA_PeripheralInc value */
-  /* Set MINC bit according to DMA_MemoryInc value */
-  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
-  /* Set MSIZE bits according to DMA_MemoryDataSize value */
-  /* Set PL bits according to DMA_Priority value */
-  /* Set the MEM2MEM bit according to DMA_M2M value */
-  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
-            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
-            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
-            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
-  /* Write to DMAy Channelx CCR */
-  DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
-  /* Write to DMAy Channelx CPAR */
-  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
-  /* Write to DMAy Channelx CMAR */
-  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
-  * @brief  Fills each DMA_InitStruct member with its default value.
-  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
-  /* Initialize the DMA_PeripheralBaseAddr member */
-  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-  /* Initialize the DMA_MemoryBaseAddr member */
-  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
-  /* Initialize the DMA_DIR member */
-  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
-  /* Initialize the DMA_BufferSize member */
-  DMA_InitStruct->DMA_BufferSize = 0;
-  /* Initialize the DMA_PeripheralInc member */
-  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  /* Initialize the DMA_MemoryInc member */
-  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-  /* Initialize the DMA_PeripheralDataSize member */
-  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  /* Initialize the DMA_MemoryDataSize member */
-  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  /* Initialize the DMA_Mode member */
-  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-  /* Initialize the DMA_Priority member */
-  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-  /* Initialize the DMA_M2M member */
-  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  NewState: new state of the DMAy Channelx. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMAy Channelx */
-    DMAy_Channelx->CCR |= DMA_CCR1_EN;
-  }
-  else
-  {
-    /* Disable the selected DMAy Channelx */
-    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx interrupts.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
-  *   or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *     @arg DMA_IT_HT:  Half transfer interrupt mask
-  *     @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @param  NewState: new state of the specified DMA interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMA interrupts */
-    DMAy_Channelx->CCR |= DMA_IT;
-  }
-  else
-  {
-    /* Disable the selected DMA interrupts */
-    DMAy_Channelx->CCR &= ~DMA_IT;
-  }
-}
-
-/**
-  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @param  DataNumber: The number of data units in the current DMAy Channelx
-  *         transfer.   
-  * @note   This function can only be used when the DMAy_Channelx is disabled.                 
-  * @retval None.
-  */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DataNumber;  
-}
-
-/**
-  * @brief  Returns the number of remaining data units in the current
-  *         DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
-  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
-  * @retval The number of remaining data units in the current DMAy Channelx
-  *         transfer.
-  */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  /* Return the number of remaining data units for DMAy Channelx */
-  return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
-  * @param  DMAy_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-  * @retval The new state of DMAy_FLAG (SET or RESET).
-  */
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Get DMA2 ISR register value */
-    tmpreg = DMA2->ISR ;
-  }
-  else
-  {
-    /* Get DMA1 ISR register value */
-    tmpreg = DMA1->ISR ;
-  }
-
-  /* Check the status of the specified DMAy flag */
-  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
-  {
-    /* DMAy_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMAy_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the DMAy_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's pending flags.
-  * @param  DMAy_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
-  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
-  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
-  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
-  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
-  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
-  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
-  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
-  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
-  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
-  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
-  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
-  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
-  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
-  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
-  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
-  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
-  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
-  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
-  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
-  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
-  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
-  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
-  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
-  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
-  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
-  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
-  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
-  * @retval None
-  */
-void DMA_ClearFlag(uint32_t DMAy_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Clear the selected DMAy flags */
-    DMA2->IFCR = DMAy_FLAG;
-  }
-  else
-  {
-    /* Clear the selected DMAy flags */
-    DMA1->IFCR = DMAy_FLAG;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
-  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-  * @retval The new state of DMAy_IT (SET or RESET).
-  */
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_IT(DMAy_IT));
-
-  /* Calculate the used DMA */
-  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Get DMA2 ISR register value */
-    tmpreg = DMA2->ISR;
-  }
-  else
-  {
-    /* Get DMA1 ISR register value */
-    tmpreg = DMA1->ISR;
-  }
-
-  /* Check the status of the specified DMAy interrupt */
-  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
-  {
-    /* DMAy_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMAy_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DMA_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's interrupt pending bits.
-  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
-  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
-  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
-  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
-  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
-  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
-  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
-  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
-  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
-  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
-  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
-  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
-  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
-  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
-  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
-  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
-  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
-  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
-  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
-  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
-  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
-  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
-  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
-  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
-  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
-  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
-  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
-  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
-  * @retval None
-  */
-void DMA_ClearITPendingBit(uint32_t DMAy_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
-
-  /* Calculate the used DMAy */
-  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
-  {
-    /* Clear the selected DMAy interrupt pending bits */
-    DMA2->IFCR = DMAy_IT;
-  }
-  else
-  {
-    /* Clear the selected DMAy interrupt pending bits */
-    DMA1->IFCR = DMAy_IT;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
deleted file mode 100644
index b6290d5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_exti.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the EXTI firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_exti.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup EXTI 
-  * @brief EXTI driver modules
-  * @{
-  */
-
-/** @defgroup EXTI_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Defines
-  * @{
-  */
-
-#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void EXTI_DeInit(void)
-{
-  EXTI->IMR = 0x00000000;
-  EXTI->EMR = 0x00000000;
-  EXTI->RTSR = 0x00000000; 
-  EXTI->FTSR = 0x00000000; 
-  EXTI->PR = 0x000FFFFF;
-}
-
-/**
-  * @brief  Initializes the EXTI peripheral according to the specified
-  *         parameters in the EXTI_InitStruct.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
-  *         that contains the configuration information for the EXTI peripheral.
-  * @retval None
-  */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
-  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
-  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
-  tmp = (uint32_t)EXTI_BASE;
-     
-  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
-  {
-    /* Clear EXTI line configuration */
-    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-    
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
-    /* Clear Rising Falling edge configuration */
-    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-    
-    /* Select the trigger for the selected external interrupts */
-    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
-    {
-      /* Rising Falling edge */
-      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
-      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
-    }
-    else
-    {
-      tmp = (uint32_t)EXTI_BASE;
-      tmp += EXTI_InitStruct->EXTI_Trigger;
-
-      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-    }
-  }
-  else
-  {
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    /* Disable the selected external lines */
-    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
-  }
-}
-
-/**
-  * @brief  Fills each EXTI_InitStruct member with its reset value.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
-  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
-  * @brief  Generates a Software interrupt.
-  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->SWIER |= EXTI_Line;
-}
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  EXTI_Line: specifies the EXTI line flag to check.
-  *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-  
-  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  EXTI_Line: specifies the EXTI line to check.
-  *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-  
-  enablestatus =  EXTI->IMR & EXTI_Line;
-  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  EXTI_Line: specifies the EXTI lines to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-  
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
deleted file mode 100644
index cdff9e9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
+++ /dev/null
@@ -1,1684 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_flash.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the FLASH firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_flash.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup FLASH 
-  * @brief FLASH driver modules
-  * @{
-  */ 
-
-/** @defgroup FLASH_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Defines
-  * @{
-  */ 
-
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
-#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
-#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
-
-/* Flash Access Control Register bits */
-#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020) 
-
-/* Flash Control Register bits */
-#define CR_PG_Set                ((uint32_t)0x00000001)
-#define CR_PG_Reset              ((uint32_t)0x00001FFE) 
-#define CR_PER_Set               ((uint32_t)0x00000002)
-#define CR_PER_Reset             ((uint32_t)0x00001FFD)
-#define CR_MER_Set               ((uint32_t)0x00000004)
-#define CR_MER_Reset             ((uint32_t)0x00001FFB)
-#define CR_OPTPG_Set             ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
-#define CR_OPTER_Set             ((uint32_t)0x00000020)
-#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
-#define CR_STRT_Set              ((uint32_t)0x00000040)
-#define CR_LOCK_Set              ((uint32_t)0x00000080)
-
-/* FLASH Mask */
-#define RDPRT_Mask               ((uint32_t)0x00000002)
-#define WRP0_Mask                ((uint32_t)0x000000FF)
-#define WRP1_Mask                ((uint32_t)0x0000FF00)
-#define WRP2_Mask                ((uint32_t)0x00FF0000)
-#define WRP3_Mask                ((uint32_t)0xFF000000)
-#define OB_USER_BFB2             ((uint16_t)0x0008)
-
-/* FLASH Keys */
-#define RDP_Key                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               ((uint32_t)0x45670123)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
-
-/* FLASH BANK address */
-#define FLASH_BANK1_END_ADDRESS   ((uint32_t)0x807FFFF)
-
-/* Delay definition */   
-#define EraseTimeout          ((uint32_t)0x000B0000)
-#define ProgramTimeout        ((uint32_t)0x00002000)
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Private_FunctionPrototypes
-  * @{
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Private_Functions
-  * @{
-  */
-
-/**
-@code  
- 
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
- including the latest STM32F10x_XL density devices. 
-
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
-    - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
-    - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
-
- In version V3.3.0, some functions were updated and new ones were added to support
- STM32F10x_XL devices. Thus some functions manages all devices, while other are 
- dedicated for XL devices only.
- 
- The table below presents the list of available functions depending on the used STM32F10x devices.  
-      
-   ***************************************************
-   * Legacy functions used for all STM32F10x devices *
-   ***************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
-   |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
-   |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
-   |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
-   |                                    |            |               |   to FLASH_LockBank1 function.                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
-   |                                    |            |               | - For other devices: erase a page in Bank1                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
-   |                                    |            |               | - For other devices: erase all pages in Bank1                  |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
-   |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
-   |                                    |            |               | - For other devices: return Bank1's flag status                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
-   |                                    |            |               | - For other devices: clear Bank1's flag                        |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
-   |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
-   |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-
-   ************************************************************************************************************************
-   * New functions used for all STM32F10x devices to manage Bank1:                                                        *
-   *   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
-   *   - For other devices, these functions are optional (covered by functions listed above)                              *
-   ************************************************************************************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-
-   *****************************************************************************
-   * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
-   *****************************************************************************
-   +----------------------------------------------------------------------------------------------------------------------------------+
-   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
-   |                                    |   devices  |  devices      |                                                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
-   |----------------------------------------------------------------------------------------------------------------------------------|
-   | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
-   +----------------------------------------------------------------------------------------------------------------------------------+
-@endcode
-*/
-
-
-/**
-  * @brief  Sets the code latency value.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_Latency: specifies the FLASH Latency value.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_Latency_0: FLASH Zero Latency cycle
-  *     @arg FLASH_Latency_1: FLASH One Latency cycle
-  *     @arg FLASH_Latency_2: FLASH Two Latency cycles
-  * @retval None
-  */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-  
-  /* Read the ACR register */
-  tmpreg = FLASH->ACR;  
-  
-  /* Sets the Latency value */
-  tmpreg &= ACR_LATENCY_Mask;
-  tmpreg |= FLASH_Latency;
-  
-  /* Write the ACR register */
-  FLASH->ACR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Half cycle flash access.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
-  *     @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
-  * @retval None
-  */
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
-  
-  /* Enable or disable the Half cycle access */
-  FLASH->ACR &= ACR_HLFCYA_Mask;
-  FLASH->ACR |= FLASH_HalfCycleAccess;
-}
-
-/**
-  * @brief  Enables or disables the Prefetch Buffer.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
-  *     @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
-  * @retval None
-  */
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
-  
-  /* Enable or disable the Prefetch Buffer */
-  FLASH->ACR &= ACR_PRFTBE_Mask;
-  FLASH->ACR |= FLASH_PrefetchBuffer;
-}
-
-/**
-  * @brief  Unlocks the FLASH Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
-  *         - For all other devices it unlocks Bank1 and it is equivalent 
-  *           to FLASH_UnlockBank1 function.. 
-  * @param  None
-  * @retval None
-  */
-void FLASH_Unlock(void)
-{
-  /* Authorize the FPEC of Bank1 Access */
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-
-#ifdef STM32F10X_XL
-  /* Authorize the FPEC of Bank2 Access */
-  FLASH->KEYR2 = FLASH_KEY1;
-  FLASH->KEYR2 = FLASH_KEY2;
-#endif /* STM32F10X_XL */
-}
-/**
-  * @brief  Unlocks the FLASH Bank1 Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function unlocks Bank1.
-  *         - For all other devices it unlocks Bank1 and it is 
-  *           equivalent to FLASH_Unlock function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_UnlockBank1(void)
-{
-  /* Authorize the FPEC of Bank1 Access */
-  FLASH->KEYR = FLASH_KEY1;
-  FLASH->KEYR = FLASH_KEY2;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Unlocks the FLASH Bank2 Program Erase Controller.
-  * @note   This function can be used only for STM32F10X_XL density devices.
-  * @param  None
-  * @retval None
-  */
-void FLASH_UnlockBank2(void)
-{
-  /* Authorize the FPEC of Bank2 Access */
-  FLASH->KEYR2 = FLASH_KEY1;
-  FLASH->KEYR2 = FLASH_KEY2;
-
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Locks the FLASH Program Erase Controller.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
-  *         - For all other devices it Locks Bank1 and it is equivalent 
-  *           to FLASH_LockBank1 function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_Lock(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
-  FLASH->CR |= CR_LOCK_Set;
-
-#ifdef STM32F10X_XL
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
-  FLASH->CR2 |= CR_LOCK_Set;
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Locks the FLASH Bank1 Program Erase Controller.
-  * @note   this function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function Locks Bank1.
-  *         - For all other devices it Locks Bank1 and it is equivalent 
-  *           to FLASH_Lock function.
-  * @param  None
-  * @retval None
-  */
-void FLASH_LockBank1(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
-  FLASH->CR |= CR_LOCK_Set;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Locks the FLASH Bank2 Program Erase Controller.
-  * @note   This function can be used only for STM32F10X_XL density devices.
-  * @param  None
-  * @retval None
-  */
-void FLASH_LockBank2(void)
-{
-  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
-  FLASH->CR2 |= CR_LOCK_Set;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Erases a specified FLASH page.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Page_Address: The page address to be erased.
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Page_Address));
-
-#ifdef STM32F10X_XL
-  if(Page_Address < FLASH_BANK1_END_ADDRESS)  
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    { 
-      /* if the previous operation is completed, proceed to erase the page */
-      FLASH->CR|= CR_PER_Set;
-      FLASH->AR = Page_Address; 
-      FLASH->CR|= CR_STRT_Set;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-
-      /* Disable the PER Bit */
-      FLASH->CR &= CR_PER_Reset;
-    }
-  }
-  else
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    { 
-      /* if the previous operation is completed, proceed to erase the page */
-      FLASH->CR2|= CR_PER_Set;
-      FLASH->AR2 = Page_Address; 
-      FLASH->CR2|= CR_STRT_Set;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-      
-      /* Disable the PER Bit */
-      FLASH->CR2 &= CR_PER_Reset;
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  { 
-    /* if the previous operation is completed, proceed to erase the page */
-    FLASH->CR|= CR_PER_Set;
-    FLASH->AR = Page_Address; 
-    FLASH->CR|= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    
-    /* Disable the PER Bit */
-    FLASH->CR &= CR_PER_Reset;
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Erases all FLASH pages.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllPages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-
-#ifdef STM32F10X_XL
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }    
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR2 |= CR_MER_Set;
-     FLASH->CR2 |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR2 &= CR_MER_Reset;
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Erases all Bank1 FLASH pages.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices this function erases all Bank1 pages.
-  *         - For all other devices it erases all Bank1 pages and it is equivalent 
-  *           to FLASH_EraseAllPages function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllBank1Pages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= CR_MER_Set;
-     FLASH->CR |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
-    
-    /* Disable the MER Bit */
-    FLASH->CR &= CR_MER_Reset;
-  }    
-  /* Return the Erase Status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Erases all Bank2 FLASH pages.
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllBank2Pages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR2 |= CR_MER_Set;
-     FLASH->CR2 |= CR_STRT_Set;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
-
-    /* Disable the MER Bit */
-    FLASH->CR2 &= CR_MER_Reset;
-  }    
-  /* Return the Erase Status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Erases the FLASH option bytes.
-  * @note   This functions erases all option bytes except the Read protection (RDP). 
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseOptionBytes(void)
-{
-  uint16_t rdptmp = RDP_Key;
-
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Get the actual read protection Option Byte value */ 
-  if(FLASH_GetReadOutProtectionStatus() != RESET)
-  {
-    rdptmp = 0x00;  
-  }
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorize the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    
-    /* if the previous operation is completed, proceed to erase the option bytes */
-    FLASH->CR |= CR_OPTER_Set;
-    FLASH->CR |= CR_STRT_Set;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= CR_OPTER_Reset;
-       
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= CR_OPTPG_Set;
-      /* Restore the last read protection Option Byte value */
-      OB->RDP = (uint16_t)rdptmp; 
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }
-    else
-    {
-      if (status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }  
-  }
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
-  if(Address < FLASH_BANK1_END_ADDRESS - 2)
-  { 
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(ProgramTimeout); 
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-      if(status == FLASH_COMPLETE)
-      {
-        /* if the previous operation is completed, proceed to program the new second 
-        half word */
-        tmp = Address + 2;
-
-        *(__IO uint16_t*) tmp = Data >> 16;
-    
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation(ProgramTimeout);
-        
-        /* Disable the PG Bit */
-        FLASH->CR &= CR_PG_Reset;
-      }
-      else
-      {
-        /* Disable the PG Bit */
-        FLASH->CR &= CR_PG_Reset;
-       }
-    }
-  }
-  else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-      
-	  /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new second 
-      half word */
-      FLASH->CR2 |= CR_PG_Set;
-      tmp = Address + 2;
-
-      *(__IO uint16_t*) tmp = Data >> 16;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-        
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-  }
-  else
-  {
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new first 
-        half word */
-      FLASH->CR2 |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = (uint16_t)Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
- 
-      if(status == FLASH_COMPLETE)
-      {
-        /* if the previous operation is completed, proceed to program the new second 
-        half word */
-        tmp = Address + 2;
-
-        *(__IO uint16_t*) tmp = Data >> 16;
-    
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-        
-        /* Disable the PG Bit */
-        FLASH->CR2 &= CR_PG_Reset;
-      }
-      else
-      {
-        /* Disable the PG Bit */
-        FLASH->CR2 &= CR_PG_Reset;
-      }
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to program the new first 
-    half word */
-    FLASH->CR |= CR_PG_Set;
-  
-    *(__IO uint16_t*)Address = (uint16_t)Data;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
- 
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new second 
-      half word */
-      tmp = Address + 2;
-
-      *(__IO uint16_t*) tmp = Data >> 16;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-        
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-  }         
-#endif /* STM32F10X_XL */
-   
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a half word at a specified address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-
-#ifdef STM32F10X_XL
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(Address < FLASH_BANK1_END_ADDRESS)
-  {
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new data */
-      FLASH->CR |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
-
-      /* Disable the PG Bit */
-      FLASH->CR &= CR_PG_Reset;
-    }
-  }
-  else
-  {
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the previous operation is completed, proceed to program the new data */
-      FLASH->CR2 |= CR_PG_Set;
-  
-      *(__IO uint16_t*)Address = Data;
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
-
-      /* Disable the PG Bit */
-      FLASH->CR2 &= CR_PG_Reset;
-    }
-  }
-#else
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to program the new data */
-    FLASH->CR |= CR_PG_Set;
-  
-    *(__IO uint16_t*)Address = Data;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    
-    /* Disable the PG Bit */
-    FLASH->CR &= CR_PG_Reset;
-  } 
-#endif  /* STM32F10X_XL */
-  
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a half word at a specified Option Byte Data address.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Address: specifies the address to be programmed.
-  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_OB_DATA_ADDRESS(Address));
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorize the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    /* Enables the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-    *(__IO uint16_t*)Address = Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }
-  /* Return the Option Byte Data Program Status */
-  return status;
-}
-
-/**
-  * @brief  Write protects the desired pages
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  FLASH_Pages: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31  
-  *     @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
-  *       and FLASH_WRProt_Pages124to127
-  *     @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
-  *     @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127    
-  *     @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
-  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
-  *     @arg FLASH_WRProt_AllPages
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
-{
-  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-  
-  FLASH_Status status = FLASH_COMPLETE;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
-  
-  FLASH_Pages = (uint32_t)(~FLASH_Pages);
-  WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
-  WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
-  WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
-  WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorizes the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    FLASH->CR |= CR_OPTPG_Set;
-    if(WRP0_Data != 0xFF)
-    {
-      OB->WRP0 = WRP0_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
-    {
-      OB->WRP1 = WRP1_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
-    {
-      OB->WRP2 = WRP2_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-    
-    if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
-    {
-      OB->WRP3 = WRP3_Data;
-     
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(ProgramTimeout);
-    }
-          
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  } 
-  /* Return the write protection operation Status */
-  return status;       
-}
-
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note   If the user has already programmed the other option bytes before calling 
-  *   this function, he must re-program them since this function erases all option bytes.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  Newstate: new state of the ReadOut Protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  status = FLASH_WaitForLastOperation(EraseTimeout);
-  if(status == FLASH_COMPLETE)
-  {
-    /* Authorizes the small information block programming */
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-    FLASH->CR |= CR_OPTER_Set;
-    FLASH->CR |= CR_STRT_Set;
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(EraseTimeout);
-    if(status == FLASH_COMPLETE)
-    {
-      /* if the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= CR_OPTER_Reset;
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= CR_OPTPG_Set; 
-      if(NewState != DISABLE)
-      {
-        OB->RDP = 0x00;
-      }
-      else
-      {
-        OB->RDP = RDP_Key;  
-      }
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(EraseTimeout); 
-    
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= CR_OPTPG_Reset;
-      }
-    }
-    else 
-    {
-      if(status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTER Bit */
-        FLASH->CR &= CR_OPTER_Reset;
-      }
-    }
-  }
-  /* Return the protection operation Status */
-  return status;       
-}
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  OB_IWDG: Selects the IWDG mode
-  *   This parameter can be one of the following values:
-  *     @arg OB_IWDG_SW: Software IWDG selected
-  *     @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  OB_STOP: Reset event when entering STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
-  *     @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  OB_STDBY: Reset event when entering Standby mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
-  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Authorize the small information block programming */
-  FLASH->OPTKEYR = FLASH_KEY1;
-  FLASH->OPTKEYR = FLASH_KEY2;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-           
-    OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); 
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Configures to boot from Bank1 or Bank2.  
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  FLASH_BOOT: select the FLASH Bank to boot from.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank1(Default).
-  *     @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
-  *        depending on the activation of the bank. The active banks are checked in
-  *        the following order: Bank2, followed by Bank1.
-  *        The active bank is recognized by the value programmed at the base address
-  *        of the respective bank (corresponding to the initial stack pointer value
-  *        in the interrupt vector table).
-  *        For more information, please refer to AN2606 from www.st.com.    
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
-{ 
-  FLASH_Status status = FLASH_COMPLETE; 
-  assert_param(IS_FLASH_BOOT(FLASH_BOOT));
-  /* Authorize the small information block programming */
-  FLASH->OPTKEYR = FLASH_KEY1;
-  FLASH->OPTKEYR = FLASH_KEY2;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(ProgramTimeout);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= CR_OPTPG_Set; 
-
-    if(FLASH_BOOT == FLASH_BOOT_Bank1)
-    {
-      OB->USER |= OB_USER_BFB2;
-    }
-    else
-    {
-      OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
-    }
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(ProgramTimeout);
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= CR_OPTPG_Reset;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
-  *         and RST_STDBY(Bit2).
-  */
-uint32_t FLASH_GetUserOptionByte(void)
-{
-  /* Return the User Option Byte */
-  return (uint32_t)(FLASH->OBR >> 2);
-}
-
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes Register value.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval The FLASH Write Protection  Option Bytes Register value
-  */
-uint32_t FLASH_GetWriteProtectionOptionByte(void)
-{
-  /* Return the Flash write protection Register value */
-  return (uint32_t)(FLASH->WRPR);
-}
-
-/**
-  * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH ReadOut Protection Status(SET or RESET)
-  */
-FlagStatus FLASH_GetReadOutProtectionStatus(void)
-{
-  FlagStatus readoutstatus = RESET;
-  if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
-  {
-    readoutstatus = SET;
-  }
-  else
-  {
-    readoutstatus = RESET;
-  }
-  return readoutstatus;
-}
-
-/**
-  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  * @param  None
-  * @retval FLASH Prefetch Buffer Status (SET or RESET).
-  */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
-  FlagStatus bitstatus = RESET;
-  
-  if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
-  return bitstatus; 
-}
-
-/**
-  * @brief  Enables or disables the specified FLASH interrupts.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
-              for Bank1 and Bank2.
-  *         - For other devices it enables or disables the specified FLASH interrupts for Bank1.
-  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_ERROR: FLASH Error Interrupt
-  *     @arg FLASH_IT_EOP: FLASH end of operation Interrupt
-  * @param  NewState: new state of the specified Flash interrupts.
-  *   This parameter can be: ENABLE or DISABLE.      
-  * @retval None 
-  */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_IT(FLASH_IT)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if((FLASH_IT & 0x80000000) != 0x0)
-  {
-    if(NewState != DISABLE)
-    {
-      /* Enable the interrupt sources */
-      FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
-    }
-    else
-    {
-      /* Disable the interrupt sources */
-      FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
-    }
-  }
-  else
-  {
-    if(NewState != DISABLE)
-    {
-      /* Enable the interrupt sources */
-      FLASH->CR |= FLASH_IT;
-    }
-    else
-    {
-      /* Disable the interrupt sources */
-      FLASH->CR &= ~(uint32_t)FLASH_IT;
-    }
-  }
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_IT(FLASH_IT)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if(NewState != DISABLE)
-  {
-    /* Enable the interrupt sources */
-    FLASH->CR |= FLASH_IT;
-  }
-  else
-  {
-    /* Disable the interrupt sources */
-    FLASH->CR &= ~(uint32_t)FLASH_IT;
-  }
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Checks whether the specified FLASH flag is set or not.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, this function checks whether the specified 
-  *           Bank1 or Bank2 flag is set or not.
-  *         - For other devices, it checks whether the specified Bank1 flag is 
-  *           set or not.
-  * @param  FLASH_FLAG: specifies the FLASH flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_FLAG_BSY: FLASH Busy flag           
-  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
-  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
-  *     @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag     
-  * @retval The new state of FLASH_FLAG (SET or RESET).
-  */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
-  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
-  {
-    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-  else
-  {
-    if((FLASH_FLAG & 0x80000000) != 0x0)
-    {
-      if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
-      {
-        bitstatus = SET;
-      }
-      else
-      {
-        bitstatus = RESET;
-      }
-    }
-    else
-    {
-      if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
-      {
-        bitstatus = SET;
-      }
-      else
-      {
-        bitstatus = RESET;
-      }
-    }
-  }
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
-  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
-  {
-    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-  else
-  {
-   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
-    {
-      bitstatus = SET;
-    }
-    else
-    {
-      bitstatus = RESET;
-    }
-  }
-#endif /* STM32F10X_XL */
-
-  /* Return the new state of FLASH_FLAG (SET or RESET) */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the FLASH's pending flags.
-  * @note   This function can be used for all STM32F10x devices.
-  *         - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
-  *         - For other devices, it clears Bank1’s pending flags.
-  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
-  *   This parameter can be any combination of the following values:         
-  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
-  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
-  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
-  * @retval None
-  */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
-#ifdef STM32F10X_XL
-  /* Check the parameters */
-  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-
-  if((FLASH_FLAG & 0x80000000) != 0x0)
-  {
-    /* Clear the flags */
-    FLASH->SR2 = FLASH_FLAG;
-  }
-  else
-  {
-    /* Clear the flags */
-    FLASH->SR = FLASH_FLAG;
-  }  
-
-#else
-  /* Check the parameters */
-  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
-  
-  /* Clear the flags */
-  FLASH->SR = FLASH_FLAG;
-#endif /* STM32F10X_XL */
-}
-
-/**
-  * @brief  Returns the FLASH Status.
-  * @note   This function can be used for all STM32F10x devices, it is equivalent
-  *         to FLASH_GetBank1Status function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetStatus(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-
-/**
-  * @brief  Returns the FLASH Bank1 Status.
-  * @note   This function can be used for all STM32F10x devices, it is equivalent
-  *         to FLASH_GetStatus function.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetBank1Status(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Returns the FLASH Bank2 Status.
-  * @note   This function can be used for STM32F10x_XL density devices.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
-  *        FLASH_ERROR_WRP or FLASH_COMPLETE
-  */
-FLASH_Status FLASH_GetBank2Status(void)
-{
-  FLASH_Status flashstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) 
-  {
-    flashstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
-    { 
-      flashstatus = FLASH_ERROR_PG;
-    }
-    else 
-    {
-      if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
-      {
-        flashstatus = FLASH_ERROR_WRP;
-      }
-      else
-      {
-        flashstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the Flash Status */
-  return flashstatus;
-}
-#endif /* STM32F10X_XL */
-/**
-  * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
-  * @note   This function can be used for all STM32F10x devices, 
-  *         it is equivalent to FLASH_WaitForLastBank1Operation.
-  *         - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
-  *           to complete or a TIMEOUT to occur.
-  *         - For all other devices it waits for a Flash operation to complete 
-  *           or a TIMEOUT to occur.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank1Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == FLASH_BUSY) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank1Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-
-/**
-  * @brief  Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
-  * @note   This function can be used for all STM32F10x devices, 
-  *         it is equivalent to FLASH_WaitForLastOperation.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank1Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank1Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-
-#ifdef STM32F10X_XL
-/**
-  * @brief  Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
-  * @note   This function can be used only for STM32F10x_XL density devices.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the Flash Status */
-  status = FLASH_GetBank2Status();
-  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
-  while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
-  {
-    status = FLASH_GetBank2Status();
-    Timeout--;
-  }
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-#endif /* STM32F10X_XL */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
deleted file mode 100644
index 457ff11..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_gpio.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the GPIO firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup GPIO 
-  * @brief GPIO driver modules
-  * @{
-  */ 
-
-/** @defgroup GPIO_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Defines
-  * @{
-  */
-
-/* ------------ RCC registers bit address in the alias region ----------------*/
-#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
-
-/* --- EVENTCR Register -----*/
-
-/* Alias word address of EVOE bit */
-#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
-#define EVOE_BitNumber              ((uint8_t)0x07)
-#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
-
-
-/* ---  MAPR Register ---*/ 
-/* Alias word address of MII_RMII_SEL bit */ 
-#define MAPR_OFFSET                 (AFIO_OFFSET + 0x04) 
-#define MII_RMII_SEL_BitNumber      ((u8)0x17) 
-#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
-
-#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
-#define LSB_MASK                    ((uint16_t)0xFFFF)
-#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
-#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
-#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
-#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval None
-  */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  if (GPIOx == GPIOA)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
-  }
-  else if (GPIOx == GPIOD)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
-  }    
-  else if (GPIOx == GPIOE)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
-  } 
-  else if (GPIOx == GPIOF)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
-  }
-  else
-  {
-    if (GPIOx == GPIOG)
-    {
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Deinitializes the Alternate Functions (remap, event control
-  *   and EXTI configuration) registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void GPIO_AFIODeInit(void)
-{
-  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
-  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
-}
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified
-  *         parameters in the GPIO_InitStruct.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
-  *         contains the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
-  uint32_t tmpreg = 0x00, pinmask = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
-  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
-  
-/*---------------------------- GPIO Mode Configuration -----------------------*/
-  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
-  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
-  { 
-    /* Check the parameters */
-    assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-    /* Output mode */
-    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
-  }
-/*---------------------------- GPIO CRL Configuration ------------------------*/
-  /* Configure the eight low port pins */
-  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
-  {
-    tmpreg = GPIOx->CRL;
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = ((uint32_t)0x01) << pinpos;
-      /* Get the port pins position */
-      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding low control register bits */
-        pinmask = ((uint32_t)0x0F) << pos;
-        tmpreg &= ~pinmask;
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          GPIOx->BRR = (((uint32_t)0x01) << pinpos);
-        }
-        else
-        {
-          /* Set the corresponding ODR bit */
-          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-          {
-            GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
-          }
-        }
-      }
-    }
-    GPIOx->CRL = tmpreg;
-  }
-/*---------------------------- GPIO CRH Configuration ------------------------*/
-  /* Configure the eight high port pins */
-  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
-  {
-    tmpreg = GPIOx->CRH;
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = (((uint32_t)0x01) << (pinpos + 0x08));
-      /* Get the port pins position */
-      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding high control register bits */
-        pinmask = ((uint32_t)0x0F) << pos;
-        tmpreg &= ~pinmask;
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
-        }
-        /* Set the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-        {
-          GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
-        }
-      }
-    }
-    GPIOx->CRH = tmpreg;
-  }
-}
-
-/**
-  * @brief  Fills each GPIO_InitStruct member with its default value.
-  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
-  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
-  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
-}
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin:  specifies the port bit to read.
-  *   This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
-  
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO input data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval GPIO input data port value.
-  */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  return ((uint16_t)GPIOx->IDR);
-}
-
-/**
-  * @brief  Reads the specified output data port bit.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin:  specifies the port bit to read.
-  *   This parameter can be GPIO_Pin_x where x can be (0..15).
-  * @retval The output port pin value.
-  */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
-  
-  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO output data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @retval GPIO output data port value.
-  */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-    
-  return ((uint16_t)GPIOx->ODR);
-}
-
-/**
-  * @brief  Sets the selected data port bits.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Clears the selected data port bits.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be one of the BitAction enum values:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_BIT_ACTION(BitVal)); 
-  
-  if (BitVal != Bit_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BRR = GPIO_Pin;
-  }
-}
-
-/**
-  * @brief  Writes data to the specified GPIO data port.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  PortVal: specifies the value to be written to the port output data register.
-  * @retval None
-  */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  
-  GPIOx->ODR = PortVal;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint32_t tmp = 0x00010000;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  tmp |= GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKK bit */
-  GPIOx->LCKR =  GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-}
-
-/**
-  * @brief  Selects the GPIO pin used as Event output.
-  * @param  GPIO_PortSource: selects the GPIO port to be used as source
-  *   for Event output.
-  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
-  * @param  GPIO_PinSource: specifies the pin for the Event output.
-  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @retval None
-  */
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
-  uint32_t tmpreg = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-    
-  tmpreg = AFIO->EVCR;
-  /* Clear the PORT[6:4] and PIN[3:0] bits */
-  tmpreg &= EVCR_PORTPINCONFIG_MASK;
-  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
-  tmpreg |= GPIO_PinSource;
-  AFIO->EVCR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Event Output.
-  * @param  NewState: new state of the Event output.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void GPIO_EventOutputCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Changes the mapping of the specified pin.
-  * @param  GPIO_Remap: selects the pin to remap.
-  *   This parameter can be one of the following values:
-  *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
-  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
-  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
-  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
-  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
-  *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
-  *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
-  *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
-  *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
-  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
-  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
-  *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
-  *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
-  *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
-  *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
-  *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
-  *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
-  *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
-  *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
-  *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
-  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
-  *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
-  *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
-  *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
-  *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.   
-  *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
-  *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
-  *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to 
-  *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.    
-  *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
-  *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
-  *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
-  *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
-  *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
-  *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
-  *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
-  *                                        only for High density Value line devices)     
-  * @param  NewState: new state of the port pin remapping.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
-{
-  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_REMAP(GPIO_Remap));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if((GPIO_Remap & 0x80000000) == 0x80000000)
-  {
-    tmpreg = AFIO->MAPR2;
-  }
-  else
-  {
-    tmpreg = AFIO->MAPR;
-  }
-
-  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
-  tmp = GPIO_Remap & LSB_MASK;
-
-  if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
-  {
-    tmpreg &= DBGAFR_SWJCFG_MASK;
-    AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
-  }
-  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
-  {
-    tmp1 = ((uint32_t)0x03) << tmpmask;
-    tmpreg &= ~tmp1;
-    tmpreg |= ~DBGAFR_SWJCFG_MASK;
-  }
-  else
-  {
-    tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
-    tmpreg |= ~DBGAFR_SWJCFG_MASK;
-  }
-
-  if (NewState != DISABLE)
-  {
-    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
-  }
-
-  if((GPIO_Remap & 0x80000000) == 0x80000000)
-  {
-    AFIO->MAPR2 = tmpreg;
-  }
-  else
-  {
-    AFIO->MAPR = tmpreg;
-  }  
-}
-
-/**
-  * @brief  Selects the GPIO pin used as EXTI Line.
-  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
-  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
-  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
-  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @retval None
-  */
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
-  uint32_t tmp = 0x00;
-  /* Check the parameters */
-  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-  
-  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
-  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
-  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
-}
-
-/**
-  * @brief  Selects the Ethernet media interface.
-  * @note   This function applies only to STM32 Connectivity line devices.  
-  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
-  *   This parameter can be one of the following values:
-  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
-  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
-  * @retval None
-  */
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
-{ 
-  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
-
-  /* Configure MII_RMII selection bit */ 
-  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
-}
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
deleted file mode 100644
index 4ea321c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
+++ /dev/null
@@ -1,1331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_i2c.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the I2C firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_rcc.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup I2C 
-  * @brief I2C driver modules
-  * @{
-  */ 
-
-/** @defgroup I2C_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Defines
-  * @{
-  */
-
-/* I2C SPE mask */
-#define CR1_PE_Set              ((uint16_t)0x0001)
-#define CR1_PE_Reset            ((uint16_t)0xFFFE)
-
-/* I2C START mask */
-#define CR1_START_Set           ((uint16_t)0x0100)
-#define CR1_START_Reset         ((uint16_t)0xFEFF)
-
-/* I2C STOP mask */
-#define CR1_STOP_Set            ((uint16_t)0x0200)
-#define CR1_STOP_Reset          ((uint16_t)0xFDFF)
-
-/* I2C ACK mask */
-#define CR1_ACK_Set             ((uint16_t)0x0400)
-#define CR1_ACK_Reset           ((uint16_t)0xFBFF)
-
-/* I2C ENGC mask */
-#define CR1_ENGC_Set            ((uint16_t)0x0040)
-#define CR1_ENGC_Reset          ((uint16_t)0xFFBF)
-
-/* I2C SWRST mask */
-#define CR1_SWRST_Set           ((uint16_t)0x8000)
-#define CR1_SWRST_Reset         ((uint16_t)0x7FFF)
-
-/* I2C PEC mask */
-#define CR1_PEC_Set             ((uint16_t)0x1000)
-#define CR1_PEC_Reset           ((uint16_t)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CR1_ENPEC_Set           ((uint16_t)0x0020)
-#define CR1_ENPEC_Reset         ((uint16_t)0xFFDF)
-
-/* I2C ENARP mask */
-#define CR1_ENARP_Set           ((uint16_t)0x0010)
-#define CR1_ENARP_Reset         ((uint16_t)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CR1_NOSTRETCH_Set       ((uint16_t)0x0080)
-#define CR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
-
-/* I2C registers Masks */
-#define CR1_CLEAR_Mask          ((uint16_t)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CR2_DMAEN_Set           ((uint16_t)0x0800)
-#define CR2_DMAEN_Reset         ((uint16_t)0xF7FF)
-
-/* I2C LAST mask */
-#define CR2_LAST_Set            ((uint16_t)0x1000)
-#define CR2_LAST_Reset          ((uint16_t)0xEFFF)
-
-/* I2C FREQ mask */
-#define CR2_FREQ_Reset          ((uint16_t)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OAR1_ADD0_Set           ((uint16_t)0x0001)
-#define OAR1_ADD0_Reset         ((uint16_t)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OAR2_ENDUAL_Set         ((uint16_t)0x0001)
-#define OAR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OAR2_ADD2_Reset         ((uint16_t)0xFF01)
-
-/* I2C F/S mask */
-#define CCR_FS_Set              ((uint16_t)0x8000)
-
-/* I2C CCR mask */
-#define CCR_CCR_Set             ((uint16_t)0x0FFF)
-
-/* I2C FLAG mask */
-#define FLAG_Mask               ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask               ((uint32_t)0x07000000)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval None
-  */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Enable I2C1 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
-    /* Release I2C1 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
-  }
-  else
-  {
-    /* Enable I2C2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
-    /* Release I2C2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the I2Cx peripheral according to the specified 
-  *   parameters in the I2C_InitStruct.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
-  *   contains the configuration information for the specified I2C peripheral.
-  * @retval None
-  */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
-  uint16_t tmpreg = 0, freqrange = 0;
-  uint16_t result = 0x04;
-  uint32_t pclk1 = 8000000;
-  RCC_ClocksTypeDef  rcc_clocks;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
-  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
-  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
-  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
-  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
-  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/
-  /* Get the I2Cx CR2 value */
-  tmpreg = I2Cx->CR2;
-  /* Clear frequency FREQ[5:0] bits */
-  tmpreg &= CR2_FREQ_Reset;
-  /* Get pclk1 frequency value */
-  RCC_GetClocksFreq(&rcc_clocks);
-  pclk1 = rcc_clocks.PCLK1_Frequency;
-  /* Set frequency bits depending on pclk1 value */
-  freqrange = (uint16_t)(pclk1 / 1000000);
-  tmpreg |= freqrange;
-  /* Write to I2Cx CR2 */
-  I2Cx->CR2 = tmpreg;
-
-/*---------------------------- I2Cx CCR Configuration ------------------------*/
-  /* Disable the selected I2C peripheral to configure TRISE */
-  I2Cx->CR1 &= CR1_PE_Reset;
-  /* Reset tmpreg value */
-  /* Clear F/S, DUTY and CCR[11:0] bits */
-  tmpreg = 0;
-
-  /* Configure speed in standard mode */
-  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
-  {
-    /* Standard mode speed calculate */
-    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
-    /* Test if CCR value is under 0x4*/
-    if (result < 0x04)
-    {
-      /* Set minimum allowed value */
-      result = 0x04;  
-    }
-    /* Set speed value for standard mode */
-    tmpreg |= result;	  
-    /* Set Maximum Rise Time for standard mode */
-    I2Cx->TRISE = freqrange + 1; 
-  }
-  /* Configure speed in fast mode */
-  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
-  {
-    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
-    {
-      /* Fast mode speed calculate: Tlow/Thigh = 2 */
-      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
-    }
-    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
-    {
-      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
-      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
-      /* Set DUTY bit */
-      result |= I2C_DutyCycle_16_9;
-    }
-
-    /* Test if CCR value is under 0x1*/
-    if ((result & CCR_CCR_Set) == 0)
-    {
-      /* Set minimum allowed value */
-      result |= (uint16_t)0x0001;  
-    }
-    /* Set speed value and set F/S bit for fast mode */
-    tmpreg |= (uint16_t)(result | CCR_FS_Set);
-    /* Set Maximum Rise Time for fast mode */
-    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
-  }
-
-  /* Write to I2Cx CCR */
-  I2Cx->CCR = tmpreg;
-  /* Enable the selected I2C peripheral */
-  I2Cx->CR1 |= CR1_PE_Set;
-
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/
-  /* Get the I2Cx CR1 value */
-  tmpreg = I2Cx->CR1;
-  /* Clear ACK, SMBTYPE and  SMBUS bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure I2Cx: mode and acknowledgement */
-  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
-  /* Set ACK bit according to I2C_Ack value */
-  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
-  /* Write to I2Cx CR1 */
-  I2Cx->CR1 = tmpreg;
-
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
-  /* Set I2Cx Own Address1 and acknowledged address */
-  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
-}
-
-/**
-  * @brief  Fills each I2C_InitStruct member with its default value.
-  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-/*---------------- Reset I2C init structure parameters values ----------------*/
-  /* initialize the I2C_ClockSpeed member */
-  I2C_InitStruct->I2C_ClockSpeed = 5000;
-  /* Initialize the I2C_Mode member */
-  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
-  /* Initialize the I2C_DutyCycle member */
-  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
-  /* Initialize the I2C_OwnAddress1 member */
-  I2C_InitStruct->I2C_OwnAddress1 = 0;
-  /* Initialize the I2C_Ack member */
-  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
-  /* Initialize the I2C_AcknowledgedAddress member */
-  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
-  * @brief  Enables or disables the specified I2C peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C peripheral */
-    I2Cx->CR1 |= CR1_PE_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C peripheral */
-    I2Cx->CR1 &= CR1_PE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C DMA requests.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C DMA transfer.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C DMA requests */
-    I2Cx->CR2 |= CR2_DMAEN_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C DMA requests */
-    I2Cx->CR2 &= CR2_DMAEN_Reset;
-  }
-}
-
-/**
-  * @brief  Specifies if the next DMA transfer will be the last one.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C DMA last transfer.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Next DMA transfer is the last transfer */
-    I2Cx->CR2 |= CR2_LAST_Set;
-  }
-  else
-  {
-    /* Next DMA transfer is not the last transfer */
-    I2Cx->CR2 &= CR2_LAST_Reset;
-  }
-}
-
-/**
-  * @brief  Generates I2Cx communication START condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C START condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Generate a START condition */
-    I2Cx->CR1 |= CR1_START_Set;
-  }
-  else
-  {
-    /* Disable the START condition generation */
-    I2Cx->CR1 &= CR1_START_Reset;
-  }
-}
-
-/**
-  * @brief  Generates I2Cx communication STOP condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C STOP condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Generate a STOP condition */
-    I2Cx->CR1 |= CR1_STOP_Set;
-  }
-  else
-  {
-    /* Disable the STOP condition generation */
-    I2Cx->CR1 &= CR1_STOP_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C acknowledge feature.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C Acknowledgement.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None.
-  */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the acknowledgement */
-    I2Cx->CR1 |= CR1_ACK_Set;
-  }
-  else
-  {
-    /* Disable the acknowledgement */
-    I2Cx->CR1 &= CR1_ACK_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the specified I2C own address2.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the 7bit I2C own address2.
-  * @retval None.
-  */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
-{
-  uint16_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  /* Get the old register value */
-  tmpreg = I2Cx->OAR2;
-
-  /* Reset I2Cx Own address2 bit [7:1] */
-  tmpreg &= OAR2_ADD2_Reset;
-
-  /* Set I2Cx Own address2 */
-  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
-
-  /* Store the new register value */
-  I2Cx->OAR2 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the specified I2C dual addressing mode.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C dual addressing mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable dual addressing mode */
-    I2Cx->OAR2 |= OAR2_ENDUAL_Set;
-  }
-  else
-  {
-    /* Disable dual addressing mode */
-    I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C general call feature.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C General call.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable generall call */
-    I2Cx->CR1 |= CR1_ENGC_Set;
-  }
-  else
-  {
-    /* Disable generall call */
-    I2Cx->CR1 &= CR1_ENGC_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C interrupts.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_BUF: Buffer interrupt mask
-  *     @arg I2C_IT_EVT: Event interrupt mask
-  *     @arg I2C_IT_ERR: Error interrupt mask
-  * @param  NewState: new state of the specified I2C interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C interrupts */
-    I2Cx->CR2 |= I2C_IT;
-  }
-  else
-  {
-    /* Disable the selected I2C interrupts */
-    I2Cx->CR2 &= (uint16_t)~I2C_IT;
-  }
-}
-
-/**
-  * @brief  Sends a data byte through the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Data: Byte to be transmitted..
-  * @retval None
-  */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Write in the DR register the data to be sent */
-  I2Cx->DR = Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The value of the received data.
-  */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Return the data in the DR register */
-  return (uint8_t)I2Cx->DR;
-}
-
-/**
-  * @brief  Transmits the address byte to select the slave device.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the slave address which will be transmitted
-  * @param  I2C_Direction: specifies whether the I2C device will be a
-  *   Transmitter or a Receiver. This parameter can be one of the following values
-  *     @arg I2C_Direction_Transmitter: Transmitter mode
-  *     @arg I2C_Direction_Receiver: Receiver mode
-  * @retval None.
-  */
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_DIRECTION(I2C_Direction));
-  /* Test on the direction to set/reset the read/write bit */
-  if (I2C_Direction != I2C_Direction_Transmitter)
-  {
-    /* Set the address bit0 for read */
-    Address |= OAR1_ADD0_Set;
-  }
-  else
-  {
-    /* Reset the address bit0 for write */
-    Address &= OAR1_ADD0_Reset;
-  }
-  /* Send the address */
-  I2Cx->DR = Address;
-}
-
-/**
-  * @brief  Reads the specified I2C register and returns its value.
-  * @param  I2C_Register: specifies the register to read.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_Register_CR1:  CR1 register.
-  *     @arg I2C_Register_CR2:   CR2 register.
-  *     @arg I2C_Register_OAR1:  OAR1 register.
-  *     @arg I2C_Register_OAR2:  OAR2 register.
-  *     @arg I2C_Register_DR:    DR register.
-  *     @arg I2C_Register_SR1:   SR1 register.
-  *     @arg I2C_Register_SR2:   SR2 register.
-  *     @arg I2C_Register_CCR:   CCR register.
-  *     @arg I2C_Register_TRISE: TRISE register.
-  * @retval The value of the read register.
-  */
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_REGISTER(I2C_Register));
-
-  tmp = (uint32_t) I2Cx;
-  tmp += I2C_Register;
-
-  /* Return the selected register value */
-  return (*(__IO uint16_t *) tmp);
-}
-
-/**
-  * @brief  Enables or disables the specified I2C software reset.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C software reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Peripheral under reset */
-    I2Cx->CR1 |= CR1_SWRST_Set;
-  }
-  else
-  {
-    /* Peripheral not under reset */
-    I2Cx->CR1 &= CR1_SWRST_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C NACK position in master receiver mode.
-  *         This function is useful in I2C Master Receiver mode when the number
-  *         of data to be received is equal to 2. In this case, this function 
-  *         should be called (with parameter I2C_NACKPosition_Next) before data 
-  *         reception starts,as described in the 2-byte reception procedure 
-  *         recommended in Reference Manual in Section: Master receiver.                
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_NACKPosition: specifies the NACK position. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
-  *          received byte.  
-  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last 
-  *          received byte.
-  *            
-  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
-  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
-  *          is intended to used in SMBUS mode. 
-  *            
-  * @retval None
-  */
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
-  
-  /* Check the input parameter */
-  if (I2C_NACKPosition == I2C_NACKPosition_Next)
-  {
-    /* Next byte in shift register is the last received byte */
-    I2Cx->CR1 |= I2C_NACKPosition_Next;
-  }
-  else
-  {
-    /* Current byte in shift register is the last received byte */
-    I2Cx->CR1 &= I2C_NACKPosition_Current;
-  }
-}
-
-/**
-  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
-  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
-  * @retval None
-  */
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
-  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
-  {
-    /* Drive the SMBusAlert pin Low */
-    I2Cx->CR1 |= I2C_SMBusAlert_Low;
-  }
-  else
-  {
-    /* Drive the SMBusAlert pin High  */
-    I2Cx->CR1 &= I2C_SMBusAlert_High;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C PEC transfer.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C PEC transmission.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C PEC transmission */
-    I2Cx->CR1 |= CR1_PEC_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C PEC transmission */
-    I2Cx->CR1 &= CR1_PEC_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C PEC position.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_PECPosition: specifies the PEC position. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
-  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
-  *       
-  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
-  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
-  *          is intended to used in I2C mode.
-  *               
-  * @retval None
-  */
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
-  if (I2C_PECPosition == I2C_PECPosition_Next)
-  {
-    /* Next byte in shift register is PEC */
-    I2Cx->CR1 |= I2C_PECPosition_Next;
-  }
-  else
-  {
-    /* Current byte in shift register is PEC */
-    I2Cx->CR1 &= I2C_PECPosition_Current;
-  }
-}
-
-/**
-  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx PEC value calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C PEC calculation */
-    I2Cx->CR1 |= CR1_ENPEC_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C PEC calculation */
-    I2Cx->CR1 &= CR1_ENPEC_Reset;
-  }
-}
-
-/**
-  * @brief  Returns the PEC value for the specified I2C.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The PEC value.
-  */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  /* Return the selected I2C PEC value */
-  return ((I2Cx->SR2) >> 8);
-}
-
-/**
-  * @brief  Enables or disables the specified I2C ARP.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx ARP. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C ARP */
-    I2Cx->CR1 |= CR1_ENARP_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C ARP */
-    I2Cx->CR1 &= CR1_ENARP_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C Clock stretching.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx Clock stretching.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState == DISABLE)
-  {
-    /* Enable the selected I2C Clock stretching */
-    I2Cx->CR1 |= CR1_NOSTRETCH_Set;
-  }
-  else
-  {
-    /* Disable the selected I2C Clock stretching */
-    I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
-  }
-}
-
-/**
-  * @brief  Selects the specified I2C fast mode duty cycle.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
-  *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
-  * @retval None
-  */
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
-  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
-  {
-    /* I2C fast mode Tlow/Thigh=2 */
-    I2Cx->CCR &= I2C_DutyCycle_2;
-  }
-  else
-  {
-    /* I2C fast mode Tlow/Thigh=16/9 */
-    I2Cx->CCR |= I2C_DutyCycle_16_9;
-  }
-}
-
-
-
-/**
- * @brief
- ****************************************************************************************
- *
- *                         I2C State Monitoring Functions
- *                       
- ****************************************************************************************   
- * This I2C driver provides three different ways for I2C state monitoring
- *  depending on the application requirements and constraints:
- *        
- *  
- * 1) Basic state monitoring:
- *    Using I2C_CheckEvent() function:
- *    It compares the status registers (SR1 and SR2) content to a given event
- *    (can be the combination of one or more flags).
- *    It returns SUCCESS if the current status includes the given flags 
- *    and returns ERROR if one or more flags are missing in the current status.
- *    - When to use:
- *      - This function is suitable for most applications as well as for startup 
- *      activity since the events are fully described in the product reference manual 
- *      (RM0008).
- *      - It is also suitable for users who need to define their own events.
- *    - Limitations:
- *      - If an error occurs (ie. error flags are set besides to the monitored flags),
- *        the I2C_CheckEvent() function may return SUCCESS despite the communication
- *        hold or corrupted real state. 
- *        In this case, it is advised to use error interrupts to monitor the error
- *        events and handle them in the interrupt IRQ handler.
- *        
- *        @note 
- *        For error management, it is advised to use the following functions:
- *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- *            Where x is the peripheral instance (I2C1, I2C2 ...)
- *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() 
- *            in order to determine which error occured.
- *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- *            and/or I2C_GenerateStop() in order to clear the error flag and source,
- *            and return to correct communication status.
- *            
- *
- *  2) Advanced state monitoring:
- *     Using the function I2C_GetLastEvent() which returns the image of both status 
- *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
- *     by 16 bits and concatenated to Status Register 1).
- *     - When to use:
- *       - This function is suitable for the same applications above but it allows to
- *         overcome the mentioned limitation of I2C_GetFlagStatus() function.
- *         The returned value could be compared to events already defined in the 
- *         library (stm32f10x_i2c.h) or to custom values defined by user.
- *       - This function is suitable when multiple flags are monitored at the same time.
- *       - At the opposite of I2C_CheckEvent() function, this function allows user to
- *         choose when an event is accepted (when all events flags are set and no 
- *         other flags are set or just when the needed flags are set like 
- *         I2C_CheckEvent() function).
- *     - Limitations:
- *       - User may need to define his own events.
- *       - Same remark concerning the error management is applicable for this 
- *         function if user decides to check only regular communication flags (and 
- *         ignores error flags).
- *     
- *
- *  3) Flag-based state monitoring:
- *     Using the function I2C_GetFlagStatus() which simply returns the status of 
- *     one single flag (ie. I2C_FLAG_RXNE ...). 
- *     - When to use:
- *        - This function could be used for specific applications or in debug phase.
- *        - It is suitable when only one flag checking is needed (most I2C events 
- *          are monitored through multiple flags).
- *     - Limitations: 
- *        - When calling this function, the Status register is accessed. Some flags are
- *          cleared when the status register is accessed. So checking the status
- *          of one Flag, may clear other ones.
- *        - Function may need to be called twice or more in order to monitor one 
- *          single event.
- *
- *  For detailed description of Events, please refer to section I2C_Events in 
- *  stm32f10x_i2c.h file.
- *  
- */
-
-/**
- * 
- *  1) Basic state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Checks whether the last I2Cx Event is equal to the one passed
-  *   as parameter.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_EVENT: specifies the event to be checked. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
-  *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
-  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED     : EV1
-  *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED        : EV1
-  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
-  *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
-  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)      : EV2
-  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
-  *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
-  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)   : EV3
-  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
-  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
-  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
-  *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
-  *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6     
-  *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
-  *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
-  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
-  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
-  *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
-  *     
-  * @note: For detailed description of Events, please refer to section 
-  *    I2C_Events in stm32f10x_i2c.h file.
-  *    
-  * @retval An ErrorStatus enumeration value:
-  * - SUCCESS: Last event is equal to the I2C_EVENT
-  * - ERROR: Last event is different from the I2C_EVENT
-  */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
-{
-  uint32_t lastevent = 0;
-  uint32_t flag1 = 0, flag2 = 0;
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_EVENT(I2C_EVENT));
-
-  /* Read the I2Cx status register */
-  flag1 = I2Cx->SR1;
-  flag2 = I2Cx->SR2;
-  flag2 = flag2 << 16;
-
-  /* Get the last event value from I2C status register */
-  lastevent = (flag1 | flag2) & FLAG_Mask;
-
-  /* Check whether the last event contains the I2C_EVENT */
-  if ((lastevent & I2C_EVENT) == I2C_EVENT)
-  {
-    /* SUCCESS: last event is equal to I2C_EVENT */
-    status = SUCCESS;
-  }
-  else
-  {
-    /* ERROR: last event is different from I2C_EVENT */
-    status = ERROR;
-  }
-  /* Return status */
-  return status;
-}
-
-/**
- * 
- *  2) Advanced state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Returns the last I2Cx Event.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  *     
-  * @note: For detailed description of Events, please refer to section 
-  *    I2C_Events in stm32f10x_i2c.h file.
-  *    
-  * @retval The last event
-  */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
-{
-  uint32_t lastevent = 0;
-  uint32_t flag1 = 0, flag2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  /* Read the I2Cx status register */
-  flag1 = I2Cx->SR1;
-  flag2 = I2Cx->SR2;
-  flag2 = flag2 << 16;
-
-  /* Get the last event value from I2C status register */
-  lastevent = (flag1 | flag2) & FLAG_Mask;
-
-  /* Return status */
-  return lastevent;
-}
-
-/**
- * 
- *  3) Flag-based state monitoring
- *******************************************************************************
- */
-
-/**
-  * @brief  Checks whether the specified I2C flag is set or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
-  *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
-  *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
-  *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
-  *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
-  *     @arg I2C_FLAG_BUSY: Bus busy flag
-  *     @arg I2C_FLAG_MSL: Master/Slave flag
-  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_FLAG_AF: Acknowledge failure flag
-  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_FLAG_BERR: Bus error flag
-  *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
-  *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
-  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
-  *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
-  *     @arg I2C_FLAG_BTF: Byte transfer finished flag
-  *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
-  *   Address matched flag (Slave mode)"ENDA"
-  *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
-  * @retval The new state of I2C_FLAG (SET or RESET).
-  */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  __IO uint32_t i2creg = 0, i2cxbase = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
-  /* Get the I2Cx peripheral base address */
-  i2cxbase = (uint32_t)I2Cx;
-  
-  /* Read flag register index */
-  i2creg = I2C_FLAG >> 28;
-  
-  /* Get bit[23:0] of the flag */
-  I2C_FLAG &= FLAG_Mask;
-  
-  if(i2creg != 0)
-  {
-    /* Get the I2Cx SR1 register address */
-    i2cxbase += 0x14;
-  }
-  else
-  {
-    /* Flag in I2Cx SR2 Register */
-    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
-    /* Get the I2Cx SR2 register address */
-    i2cxbase += 0x18;
-  }
-  
-  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
-  {
-    /* I2C_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_FLAG is reset */
-    bitstatus = RESET;
-  }
-  
-  /* Return the I2C_FLAG status */
-  return  bitstatus;
-}
-
-
-
-/**
-  * @brief  Clears the I2Cx's pending flags.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_FLAG_AF: Acknowledge failure flag
-  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_FLAG_BERR: Bus error flag
-  *   
-  * @note
-  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
-  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
-  *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
-  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
-  *     second byte of the address in DR register.
-  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
-  *     read/write to I2C_DR register (I2C_SendData()).
-  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
-  *     I2C_SR2 register ((void)(I2Cx->SR2)).
-  *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
-  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
-  *     register  (I2C_SendData()).
-  * @retval None
-  */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
-  uint32_t flagpos = 0;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-  /* Get the I2C flag position */
-  flagpos = I2C_FLAG & FLAG_Mask;
-  /* Clear the selected I2C flag */
-  I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
-  * @brief  Checks whether the specified I2C interrupt has occurred or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_IT_SMBALERT: SMBus Alert flag
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
-  *     @arg I2C_IT_PECERR: PEC error in reception flag
-  *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
-  *     @arg I2C_IT_AF: Acknowledge failure flag
-  *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
-  *     @arg I2C_IT_BERR: Bus error flag
-  *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
-  *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
-  *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
-  *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
-  *     @arg I2C_IT_BTF: Byte transfer finished flag
-  *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
-  *                       Address matched flag (Slave mode)"ENDAD"
-  *     @arg I2C_IT_SB: Start bit flag (Master mode)
-  * @retval The new state of I2C_IT (SET or RESET).
-  */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_IT(I2C_IT));
-
-  /* Check if the interrupt source is enabled or not */
-  enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
-  
-  /* Get bit[23:0] of the flag */
-  I2C_IT &= FLAG_Mask;
-
-  /* Check the status of the specified I2C flag */
-  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
-  {
-    /* I2C_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the I2C_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the I2Cx’s interrupt pending bits.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
-  *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
-  *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
-  *     @arg I2C_IT_AF: Acknowledge failure interrupt
-  *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
-  *     @arg I2C_IT_BERR: Bus error interrupt
-  *   
-  * @note
-  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
-  *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
-  *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
-  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
-  *     byte of the address in I2C_DR register.
-  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
-  *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
-  *     read/write to I2C_DR register (I2C_SendData()).
-  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
-  *     I2C_SR2 register ((void)(I2Cx->SR2)).
-  *   - SB (Start Bit) is cleared by software sequence: a read operation to 
-  *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
-  *     I2C_DR register (I2C_SendData()).
-  * @retval None
-  */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  uint32_t flagpos = 0;
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-  /* Get the I2C flag position */
-  flagpos = I2C_IT & FLAG_Mask;
-  /* Clear the selected I2C flag */
-  I2Cx->SR1 = (uint16_t)~flagpos;
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
deleted file mode 100644
index c7cbf7e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_iwdg.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the IWDG firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_iwdg.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup IWDG 
-  * @brief IWDG driver modules
-  * @{
-  */ 
-
-/** @defgroup IWDG_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Defines
-  * @{
-  */ 
-
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-
-/* KR register bit mask */
-#define KR_KEY_Reload    ((uint16_t)0xAAAA)
-#define KR_KEY_Enable    ((uint16_t)0xCCCC)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup IWDG_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
-  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
-  * @retval None
-  */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
-  IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
-  * @brief  Sets IWDG Prescaler value.
-  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
-  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
-  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
-  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
-  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
-  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
-  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
-  * @retval None
-  */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
-  IWDG->PR = IWDG_Prescaler;
-}
-
-/**
-  * @brief  Sets IWDG Reload value.
-  * @param  Reload: specifies the IWDG Reload value.
-  *   This parameter must be a number between 0 and 0x0FFF.
-  * @retval None
-  */
-void IWDG_SetReload(uint16_t Reload)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_RELOAD(Reload));
-  IWDG->RLR = Reload;
-}
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None
-  * @retval None
-  */
-void IWDG_ReloadCounter(void)
-{
-  IWDG->KR = KR_KEY_Reload;
-}
-
-/**
-  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None
-  * @retval None
-  */
-void IWDG_Enable(void)
-{
-  IWDG->KR = KR_KEY_Enable;
-}
-
-/**
-  * @brief  Checks whether the specified IWDG flag is set or not.
-  * @param  IWDG_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
-  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
-  * @retval The new state of IWDG_FLAG (SET or RESET).
-  */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
-  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
deleted file mode 100644
index a5a5c57..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_pwr.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the PWR firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup PWR 
-  * @brief PWR driver modules
-  * @{
-  */ 
-
-/** @defgroup PWR_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Defines
-  * @{
-  */
-
-/* --------- PWR registers bit address in the alias region ---------- */
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of DBP bit */
-#define CR_OFFSET                (PWR_OFFSET + 0x00)
-#define DBP_BitNumber            0x08
-#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BitNumber           0x04
-#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of EWUP bit */
-#define CSR_OFFSET               (PWR_OFFSET + 0x04)
-#define EWUP_BitNumber           0x08
-#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void PWR_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
-  * @brief  Enables or disables access to the RTC and backup registers.
-  * @param  NewState: new state of the access to the RTC and backup registers.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Power Voltage Detector(PVD).
-  * @param  NewState: new state of the PVD.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_PVDCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  PWR_PVDLevel: specifies the PVD detection level
-  *   This parameter can be one of the following values:
-  *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
-  *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
-  *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
-  *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
-  *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
-  *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
-  *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
-  *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
-  * @retval None
-  */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-  tmpreg = PWR->CR;
-  /* Clear PLS[7:5] bits */
-  tmpreg &= CR_PLS_MASK;
-  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
-  tmpreg |= PWR_PVDLevel;
-  /* Store the new value */
-  PWR->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the WakeUp Pin functionality.
-  * @param  NewState: new state of the WakeUp Pin functionality.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_WakeUpPinCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enters STOP mode.
-  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
-  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
-  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
-  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-  
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tmpreg = PWR->CR;
-  /* Clear PDDS and LPDS bits */
-  tmpreg &= CR_DS_MASK;
-  /* Set LPDS bit according to PWR_Regulator value */
-  tmpreg |= PWR_Regulator;
-  /* Store the new value */
-  PWR->CR = tmpreg;
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-  
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
-}
-
-/**
-  * @brief  Enters STANDBY mode.
-  * @param  None
-  * @retval None
-  */
-void PWR_EnterSTANDBYMode(void)
-{
-  /* Clear Wake-up flag */
-  PWR->CR |= PWR_CR_CWUF;
-  /* Select STANDBY mode */
-  PWR->CR |= PWR_CR_PDDS;
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP;
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM   )
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief  Checks whether the specified PWR flag is set or not.
-  * @param  PWR_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_FLAG_WU: Wake Up flag
-  *     @arg PWR_FLAG_SB: StandBy flag
-  *     @arg PWR_FLAG_PVDO: PVD Output
-  * @retval The new state of PWR_FLAG (SET or RESET).
-  */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-  
-  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the PWR's pending flags.
-  * @param  PWR_FLAG: specifies the flag to clear.
-  *   This parameter can be one of the following values:
-  *     @arg PWR_FLAG_WU: Wake Up flag
-  *     @arg PWR_FLAG_SB: StandBy flag
-  * @retval None
-  */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-         
-  PWR->CR |=  PWR_FLAG << 2;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
deleted file mode 100644
index a29034b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
+++ /dev/null
@@ -1,1470 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_rcc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the RCC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RCC 
-  * @brief RCC driver modules
-  * @{
-  */ 
-
-/** @defgroup RCC_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_Defines
-  * @{
-  */
-
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of HSION bit */
-#define CR_OFFSET                 (RCC_OFFSET + 0x00)
-#define HSION_BitNumber           0x00
-#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber           0x18
-#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-#ifdef STM32F10X_CL
- /* Alias word address of PLL2ON bit */
- #define PLL2ON_BitNumber          0x1A
- #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
-
- /* Alias word address of PLL3ON bit */
- #define PLL3ON_BitNumber          0x1C
- #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
-#endif /* STM32F10X_CL */ 
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber           0x13
-#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-
-/* Alias word address of USBPRE bit */
-#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
-
-#ifndef STM32F10X_CL
- #define USBPRE_BitNumber          0x16
- #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
-#else
- #define OTGFSPRE_BitNumber        0x16
- #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
-#endif /* STM32F10X_CL */ 
-
-/* --- BDCR Register ---*/
-
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
-#define RTCEN_BitNumber           0x0F
-#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber           0x10
-#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of LSION bit */
-#define CSR_OFFSET                (RCC_OFFSET + 0x24)
-#define LSION_BitNumber           0x00
-#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-#ifdef STM32F10X_CL
-/* --- CFGR2 Register ---*/
-
- /* Alias word address of I2S2SRC bit */
- #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
- #define I2S2SRC_BitNumber         0x11
- #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
-
- /* Alias word address of I2S3SRC bit */
- #define I2S3SRC_BitNumber         0x12
- #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
-#endif /* STM32F10X_CL */
-
-/* ---------------------- RCC registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
-#define CR_HSEBYP_Set             ((uint32_t)0x00040000)
-#define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
-#define CR_HSEON_Set              ((uint32_t)0x00010000)
-#define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
-
-/* CFGR register bit mask */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
- #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
-#else
- #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
-#endif /* STM32F10X_CL */ 
-
-#define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
-#define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
-#define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
-#define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
-#define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
-#define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
-#define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
-#define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
-#define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
-#define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
-#define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
-#define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
-#define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
-
-/* CSR register bit mask */
-#define CSR_RMVF_Set              ((uint32_t)0x01000000)
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
-/* CFGR2 register bit mask */
- #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
- #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
-#endif
-#ifdef STM32F10X_CL
- #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
- #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
- #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
-#endif /* STM32F10X_CL */ 
-
-/* RCC Flag Mask */
-#define FLAG_Mask                 ((uint8_t)0x1F)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
-
-/* CFGR register byte 4 (Bits[31:24]) base address */
-#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
-
-/* BDCR register base address */
-#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Private_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Private_Variables
-  * @{
-  */ 
-
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @param  None
-  * @retval None
-  */
-void RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-
-}
-
-/**
-  * @brief  Configures the External High Speed oscillator (HSE).
-  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
-  * @param  RCC_HSE: specifies the new state of the HSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HSE_OFF: HSE oscillator OFF
-  *     @arg RCC_HSE_ON: HSE oscillator ON
-  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_HSEConfig(uint32_t RCC_HSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_HSE(RCC_HSE));
-  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
-  /* Reset HSEON bit */
-  RCC->CR &= CR_HSEON_Reset;
-  /* Reset HSEBYP bit */
-  RCC->CR &= CR_HSEBYP_Reset;
-  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
-  switch(RCC_HSE)
-  {
-    case RCC_HSE_ON:
-      /* Set HSEON bit */
-      RCC->CR |= CR_HSEON_Set;
-      break;
-      
-    case RCC_HSE_Bypass:
-      /* Set HSEBYP and HSEON bits */
-      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
-      break;
-      
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  Waits for HSE start-up.
-  * @param  None
-  * @retval An ErrorStatus enumuration value:
-  * - SUCCESS: HSE oscillator is stable and ready to use
-  * - ERROR: HSE oscillator not yet ready
-  */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
-  __IO uint32_t StartUpCounter = 0;
-  ErrorStatus status = ERROR;
-  FlagStatus HSEStatus = RESET;
-  
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
-    StartUpCounter++;  
-  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-  
-  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
-  {
-    status = SUCCESS;
-  }
-  else
-  {
-    status = ERROR;
-  }  
-  return (status);
-}
-
-/**
-  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
-  * @param  HSICalibrationValue: specifies the calibration trimming value.
-  *   This parameter must be a number between 0 and 0x1F.
-  * @retval None
-  */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
-  tmpreg = RCC->CR;
-  /* Clear HSITRIM[4:0] bits */
-  tmpreg &= CR_HSITRIM_Mask;
-  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
-  tmpreg |= (uint32_t)HSICalibrationValue << 3;
-  /* Store the new value */
-  RCC->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
-  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
-  * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_HSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the PLL clock source and multiplication factor.
-  * @note   This function must be used only when the PLL is disabled.
-  * @param  RCC_PLLSource: specifies the PLL entry clock source.
-  *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, 
-  *   this parameter can be one of the following values:
-  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
-  *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
-  *   For @b other_STM32_devices, this parameter can be one of the following values:
-  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
-  *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
-  *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry 
-  * @param  RCC_PLLMul: specifies the PLL multiplication factor.
-  *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
-  *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]  
-  * @retval None
-  */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
-  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
-  tmpreg = RCC->CFGR;
-  /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  tmpreg &= CFGR_PLL_Mask;
-  /* Set the PLL configuration bits */
-  tmpreg |= RCC_PLLSource | RCC_PLLMul;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the PLL.
-  * @note   The PLL can not be disabled if it is used as system clock.
-  * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLLCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
-/**
-  * @brief  Configures the PREDIV1 division factor.
-  * @note 
-  *   - This function must be used only when the PLL is disabled.
-  *   - This function applies only to STM32 Connectivity line and Value line 
-  *     devices.
-  * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
-  *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
-  * @note 
-  *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE  
-  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
-  *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
-  * @retval None
-  */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
-  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
-  tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
-  /* Set the PREDIV1 clock source and division factor */
-  tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-#endif
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Configures the PREDIV2 division factor.
-  * @note 
-  *   - This function must be used only when both PLL2 and PLL3 are disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
-  *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
-  * @retval None
-  */
-void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PREDIV2[3:0] bits */
-  tmpreg &= ~CFGR2_PREDIV2;
-  /* Set the PREDIV2 division factor */
-  tmpreg |= RCC_PREDIV2_Div;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-/**
-  * @brief  Configures the PLL2 multiplication factor.
-  * @note
-  *   - This function must be used only when the PLL2 is disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
-  *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
-  * @retval None
-  */
-void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PLL2Mul[3:0] bits */
-  tmpreg &= ~CFGR2_PLL2MUL;
-  /* Set the PLL2 configuration bits */
-  tmpreg |= RCC_PLL2Mul;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-
-/**
-  * @brief  Enables or disables the PLL2.
-  * @note 
-  *   - The PLL2 can not be disabled if it is used indirectly as system clock
-  *     (i.e. it is used as PLL clock entry that is used as System clock).
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLL2Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
-}
-
-
-/**
-  * @brief  Configures the PLL3 multiplication factor.
-  * @note 
-  *   - This function must be used only when the PLL3 is disabled.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
-  *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
-  * @retval None
-  */
-void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PLL3Mul[3:0] bits */
-  tmpreg &= ~CFGR2_PLL3MUL;
-  /* Set the PLL3 configuration bits */
-  tmpreg |= RCC_PLL3Mul;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-
-/**
-  * @brief  Enables or disables the PLL3.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLL3Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
-}
-#endif /* STM32F10X_CL */
-
-/**
-  * @brief  Configures the system clock (SYSCLK).
-  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
-  *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
-  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
-  * @retval None
-  */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-  tmpreg = RCC->CFGR;
-  /* Clear SW[1:0] bits */
-  tmpreg &= CFGR_SW_Mask;
-  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
-  tmpreg |= RCC_SYSCLKSource;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Returns the clock source used as system clock.
-  * @param  None
-  * @retval The clock source used as system clock. The returned value can
-  *   be one of the following:
-  *     - 0x00: HSI used as system clock
-  *     - 0x04: HSE used as system clock
-  *     - 0x08: PLL used as system clock
-  */
-uint8_t RCC_GetSYSCLKSource(void)
-{
-  return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
-}
-
-/**
-  * @brief  Configures the AHB clock (HCLK).
-  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
-  *   the system clock (SYSCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
-  *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
-  *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
-  *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
-  *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
-  *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
-  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
-  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
-  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
-  * @retval None
-  */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear HPRE[3:0] bits */
-  tmpreg &= CFGR_HPRE_Reset_Mask;
-  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
-  tmpreg |= RCC_SYSCLK;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the Low Speed APB clock (PCLK1).
-  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
-  *   the AHB clock (HCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
-  *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
-  *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
-  *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
-  *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
-  * @retval None
-  */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_PCLK(RCC_HCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear PPRE1[2:0] bits */
-  tmpreg &= CFGR_PPRE1_Reset_Mask;
-  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
-  tmpreg |= RCC_HCLK;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the High Speed APB clock (PCLK2).
-  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
-  *   the AHB clock (HCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
-  *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
-  *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
-  *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
-  *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
-  * @retval None
-  */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_PCLK(RCC_HCLK));
-  tmpreg = RCC->CFGR;
-  /* Clear PPRE2[2:0] bits */
-  tmpreg &= CFGR_PPRE2_Reset_Mask;
-  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
-  tmpreg |= RCC_HCLK << 3;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the specified RCC interrupts.
-  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
-  * 
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the 
-  *   following values        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *       
-  * @param  NewState: new state of the specified RCC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_IT(RCC_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
-  }
-  else
-  {
-    /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
-  }
-}
-
-#ifndef STM32F10X_CL
-/**
-  * @brief  Configures the USB clock (USBCLK).
-  * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
-  *   derived from the PLL output.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
-  *                                     clock source
-  *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
-  * @retval None
-  */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
-
-  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
-}
-#else
-/**
-  * @brief  Configures the USB OTG FS clock (OTGFSCLK).
-  *   This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
-  *   This clock is derived from the PLL output.
-  *   This parameter can be one of the following values:
-  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
-  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
-  * @retval None
-  */
-void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
-
-  *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
-}
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @brief  Configures the ADC clock (ADCCLK).
-  * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
-  *   the APB2 clock (PCLK2).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
-  *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
-  *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
-  *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
-  * @retval None
-  */
-void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
-  tmpreg = RCC->CFGR;
-  /* Clear ADCPRE[1:0] bits */
-  tmpreg &= CFGR_ADCPRE_Reset_Mask;
-  /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
-  tmpreg |= RCC_PCLK2;
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Configures the I2S2 clock source(I2S2CLK).
-  * @note
-  *   - This function must be called before enabling I2S2 APB clock.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
-  *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
-  * @retval None
-  */
-void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
-
-  *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
-}
-
-/**
-  * @brief  Configures the I2S3 clock source(I2S2CLK).
-  * @note
-  *   - This function must be called before enabling I2S3 APB clock.
-  *   - This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
-  *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
-  * @retval None
-  */
-void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
-
-  *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
-}
-#endif /* STM32F10X_CL */
-
-/**
-  * @brief  Configures the External Low Speed oscillator (LSE).
-  * @param  RCC_LSE: specifies the new state of the LSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_LSE_OFF: LSE oscillator OFF
-  *     @arg RCC_LSE_ON: LSE oscillator ON
-  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_LSEConfig(uint8_t RCC_LSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE(RCC_LSE));
-  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
-  /* Reset LSEON bit */
-  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-  /* Reset LSEBYP bit */
-  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
-  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
-  switch(RCC_LSE)
-  {
-    case RCC_LSE_ON:
-      /* Set LSEON bit */
-      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
-      break;
-      
-    case RCC_LSE_Bypass:
-      /* Set LSEBYP and LSEON bits */
-      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
-      break;            
-      
-    default:
-      break;      
-  }
-}
-
-/**
-  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_LSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Configures the RTC clock (RTCCLK).
-  * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
-  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
-  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
-  *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
-  * @retval None
-  */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-  /* Select the RTC clock source */
-  RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
-  * @brief  Enables or disables the RTC clock.
-  * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
-  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Returns the frequencies of different on chip clocks.
-  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
-  *         the clocks frequencies.
-  * @note   The result of this function could be not correct when using 
-  *         fractional value for HSE crystal.  
-  * @retval None
-  */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & CFGR_SWS_Mask;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
-      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { /* HSE oscillator clock selected as PREDIV1 clock entry */
-          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
-          RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-  }
-
-  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
-  /* Get HCLK prescaler */
-  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
-  tmp = tmp >> 4;
-  presc = APBAHBPrescTable[tmp];
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-  /* Get PCLK1 prescaler */
-  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
-  tmp = tmp >> 8;
-  presc = APBAHBPrescTable[tmp];
-  /* PCLK1 clock frequency */
-  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-  /* Get PCLK2 prescaler */
-  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
-  tmp = tmp >> 11;
-  presc = APBAHBPrescTable[tmp];
-  /* PCLK2 clock frequency */
-  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-  /* Get ADCCLK prescaler */
-  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
-  tmp = tmp >> 14;
-  presc = ADCPrescTable[tmp];
-  /* ADCCLK clock frequency */
-  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
-}
-
-/**
-  * @brief  Enables or disables the AHB peripheral clock.
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values:        
-  *     @arg RCC_AHBPeriph_DMA1
-  *     @arg RCC_AHBPeriph_DMA2
-  *     @arg RCC_AHBPeriph_SRAM
-  *     @arg RCC_AHBPeriph_FLITF
-  *     @arg RCC_AHBPeriph_CRC
-  *     @arg RCC_AHBPeriph_OTG_FS    
-  *     @arg RCC_AHBPeriph_ETH_MAC   
-  *     @arg RCC_AHBPeriph_ETH_MAC_Tx
-  *     @arg RCC_AHBPeriph_ETH_MAC_Rx
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the 
-  *   following values:        
-  *     @arg RCC_AHBPeriph_DMA1
-  *     @arg RCC_AHBPeriph_DMA2
-  *     @arg RCC_AHBPeriph_SRAM
-  *     @arg RCC_AHBPeriph_FLITF
-  *     @arg RCC_AHBPeriph_CRC
-  *     @arg RCC_AHBPeriph_FSMC
-  *     @arg RCC_AHBPeriph_SDIO
-  *   
-  * @note SRAM and FLITF clock can be disabled only during sleep mode.
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->AHBENR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBENR &= ~RCC_AHBPeriph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
-  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11     
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB2ENR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2ENR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
-  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
-  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
-  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB1ENR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1ENR &= ~RCC_APB1Periph;
-  }
-}
-
-#ifdef STM32F10X_CL
-/**
-  * @brief  Forces or releases AHB peripheral reset.
-  * @note   This function applies only to STM32 Connectivity line devices.
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_AHBPeriph_OTG_FS 
-  *     @arg RCC_AHBPeriph_ETH_MAC
-  * @param  NewState: new state of the specified peripheral reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->AHBRSTR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBRSTR &= ~RCC_AHBPeriph;
-  }
-}
-#endif /* STM32F10X_CL */ 
-
-/**
-  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
-  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
-  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
-  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
-  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
-  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
-  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11  
-  * @param  NewState: new state of the specified peripheral reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB2RSTR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2RSTR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
-  *   This parameter can be any combination of the following values:
-  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
-  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
-  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
-  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
-  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
-  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
-  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
-  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14  
-  * @param  NewState: new state of the specified peripheral clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB1RSTR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1RSTR &= ~RCC_APB1Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases the Backup domain reset.
-  * @param  NewState: new state of the Backup domain reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Enables or disables the Clock Security System.
-  * @param  NewState: new state of the Clock Security System..
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-/**
-  * @brief  Selects the clock source to output on MCO pin.
-  * @param  RCC_MCO: specifies the clock source to output.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:       
-  *     @arg RCC_MCO_NoClock: No clock selected
-  *     @arg RCC_MCO_SYSCLK: System clock selected
-  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
-  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
-  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-  *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected                     
-  *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected   
-  *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected  
-  *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected 
-  * 
-  *   For  @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_MCO_NoClock: No clock selected
-  *     @arg RCC_MCO_SYSCLK: System clock selected
-  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
-  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
-  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-  *   
-  * @retval None
-  */
-void RCC_MCOConfig(uint8_t RCC_MCO)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCO));
-
-  /* Perform Byte access to MCO bits to select the MCO source */
-  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
-}
-
-/**
-  * @brief  Checks whether the specified RCC flag is set or not.
-  * @param  RCC_FLAG: specifies the flag to check.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:
-  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
-  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
-  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
-  *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready      
-  *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready                           
-  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
-  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
-  *     @arg RCC_FLAG_PINRST: Pin reset
-  *     @arg RCC_FLAG_PORRST: POR/PDR reset
-  *     @arg RCC_FLAG_SFTRST: Software reset
-  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
-  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
-  *     @arg RCC_FLAG_LPWRRST: Low Power reset
-  * 
-  *   For @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
-  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
-  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
-  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
-  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
-  *     @arg RCC_FLAG_PINRST: Pin reset
-  *     @arg RCC_FLAG_PORRST: POR/PDR reset
-  *     @arg RCC_FLAG_SFTRST: Software reset
-  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
-  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
-  *     @arg RCC_FLAG_LPWRRST: Low Power reset
-  *   
-  * @retval The new state of RCC_FLAG (SET or RESET).
-  */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
-  uint32_t tmp = 0;
-  uint32_t statusreg = 0;
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RCC_FLAG(RCC_FLAG));
-
-  /* Get the RCC register index */
-  tmp = RCC_FLAG >> 5;
-  if (tmp == 1)               /* The flag to check is in CR register */
-  {
-    statusreg = RCC->CR;
-  }
-  else if (tmp == 2)          /* The flag to check is in BDCR register */
-  {
-    statusreg = RCC->BDCR;
-  }
-  else                       /* The flag to check is in CSR register */
-  {
-    statusreg = RCC->CSR;
-  }
-
-  /* Get the flag position */
-  tmp = RCC_FLAG & FLAG_Mask;
-  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC reset flags.
-  * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  * @param  None
-  * @retval None
-  */
-void RCC_ClearFlag(void)
-{
-  /* Set RMVF bit to clear the reset flags */
-  RCC->CSR |= CSR_RMVF_Set;
-}
-
-/**
-  * @brief  Checks whether the specified RCC interrupt has occurred or not.
-  * @param  RCC_IT: specifies the RCC interrupt source to check.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
-  *   following values:
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be one of the following values:        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  *   
-  * @retval The new state of RCC_IT (SET or RESET).
-  */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RCC_GET_IT(RCC_IT));
-
-  /* Check the status of the specified RCC interrupt */
-  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-
-  /* Return the RCC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC's interrupt pending bits.
-  * @param  RCC_IT: specifies the interrupt pending bit to clear.
-  *   
-  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
-  *   of the following values:
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
-  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * 
-  *   For @b other_STM32_devices, this parameter can be any combination of the
-  *   following values:        
-  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *     @arg RCC_IT_LSERDY: LSE ready interrupt
-  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *     @arg RCC_IT_HSERDY: HSE ready interrupt
-  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *   
-  *     @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval None
-  */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
-  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
-     pending bits */
-  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
deleted file mode 100644
index f05aef5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_rtc.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the RTC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_rtc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RTC 
-  * @brief RTC driver modules
-  * @{
-  */
-
-/** @defgroup RTC_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Defines
-  * @{
-  */
-#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
-#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified RTC interrupts.
-  * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @param  NewState: new state of the specified RTC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_IT(RTC_IT));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RTC->CRH |= RTC_IT;
-  }
-  else
-  {
-    RTC->CRH &= (uint16_t)~RTC_IT;
-  }
-}
-
-/**
-  * @brief  Enters the RTC configuration mode.
-  * @param  None
-  * @retval None
-  */
-void RTC_EnterConfigMode(void)
-{
-  /* Set the CNF flag to enter in the Configuration Mode */
-  RTC->CRL |= RTC_CRL_CNF;
-}
-
-/**
-  * @brief  Exits from the RTC configuration mode.
-  * @param  None
-  * @retval None
-  */
-void RTC_ExitConfigMode(void)
-{
-  /* Reset the CNF flag to exit from the Configuration Mode */
-  RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 
-}
-
-/**
-  * @brief  Gets the RTC counter value.
-  * @param  None
-  * @retval RTC counter value.
-  */
-uint32_t RTC_GetCounter(void)
-{
-  uint16_t tmp = 0;
-  tmp = RTC->CNTL;
-  return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
-}
-
-/**
-  * @brief  Sets the RTC counter value.
-  * @param  CounterValue: RTC counter new value.
-  * @retval None
-  */
-void RTC_SetCounter(uint32_t CounterValue)
-{ 
-  RTC_EnterConfigMode();
-  /* Set RTC COUNTER MSB word */
-  RTC->CNTH = CounterValue >> 16;
-  /* Set RTC COUNTER LSB word */
-  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Sets the RTC prescaler value.
-  * @param  PrescalerValue: RTC prescaler new value.
-  * @retval None
-  */
-void RTC_SetPrescaler(uint32_t PrescalerValue)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_PRESCALER(PrescalerValue));
-  
-  RTC_EnterConfigMode();
-  /* Set RTC PRESCALER MSB word */
-  RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
-  /* Set RTC PRESCALER LSB word */
-  RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Sets the RTC alarm value.
-  * @param  AlarmValue: RTC alarm new value.
-  * @retval None
-  */
-void RTC_SetAlarm(uint32_t AlarmValue)
-{  
-  RTC_EnterConfigMode();
-  /* Set the ALARM MSB word */
-  RTC->ALRH = AlarmValue >> 16;
-  /* Set the ALARM LSB word */
-  RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
-  RTC_ExitConfigMode();
-}
-
-/**
-  * @brief  Gets the RTC divider value.
-  * @param  None
-  * @retval RTC Divider value.
-  */
-uint32_t RTC_GetDivider(void)
-{
-  uint32_t tmp = 0x00;
-  tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
-  tmp |= RTC->DIVL;
-  return tmp;
-}
-
-/**
-  * @brief  Waits until last write operation on RTC registers has finished.
-  * @note   This function must be called before any write to RTC registers.
-  * @param  None
-  * @retval None
-  */
-void RTC_WaitForLastTask(void)
-{
-  /* Loop until RTOFF flag is set */
-  while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
-  {
-  }
-}
-
-/**
-  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
-  *   are synchronized with RTC APB clock.
-  * @note   This function must be called before any read operation after an APB reset
-  *   or an APB clock stop.
-  * @param  None
-  * @retval None
-  */
-void RTC_WaitForSynchro(void)
-{
-  /* Clear RSF flag */
-  RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
-  /* Loop until RSF flag is set */
-  while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
-  {
-  }
-}
-
-/**
-  * @brief  Checks whether the specified RTC flag is set or not.
-  * @param  RTC_FLAG: specifies the flag to check.
-  *   This parameter can be one the following values:
-  *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
-  *     @arg RTC_FLAG_OW: Overflow flag
-  *     @arg RTC_FLAG_ALR: Alarm flag
-  *     @arg RTC_FLAG_SEC: Second flag
-  * @retval The new state of RTC_FLAG (SET or RESET).
-  */
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 
-  
-  if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's pending flags.
-  * @param  RTC_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
-  *                        an APB reset or an APB Clock stop.
-  *     @arg RTC_FLAG_OW: Overflow flag
-  *     @arg RTC_FLAG_ALR: Alarm flag
-  *     @arg RTC_FLAG_SEC: Second flag
-  * @retval None
-  */
-void RTC_ClearFlag(uint16_t RTC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
-    
-  /* Clear the corresponding RTC flag */
-  RTC->CRL &= (uint16_t)~RTC_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified RTC interrupt has occurred or not.
-  * @param  RTC_IT: specifies the RTC interrupts sources to check.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @retval The new state of the RTC_IT (SET or RESET).
-  */
-ITStatus RTC_GetITStatus(uint16_t RTC_IT)
-{
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_IT(RTC_IT)); 
-  
-  bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
-  if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's interrupt pending bits.
-  * @param  RTC_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_OW: Overflow interrupt
-  *     @arg RTC_IT_ALR: Alarm interrupt
-  *     @arg RTC_IT_SEC: Second interrupt
-  * @retval None
-  */
-void RTC_ClearITPendingBit(uint16_t RTC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_IT(RTC_IT));  
-  
-  /* Clear the corresponding RTC pending bit */
-  RTC->CRL &= (uint16_t)~RTC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
deleted file mode 100644
index 4ec65b2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
+++ /dev/null
@@ -1,908 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_spi.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the SPI firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_spi.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup SPI 
-  * @brief SPI driver modules
-  * @{
-  */ 
-
-/** @defgroup SPI_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup SPI_Private_Defines
-  * @{
-  */
-
-/* SPI SPE mask */
-#define CR1_SPE_Set          ((uint16_t)0x0040)
-#define CR1_SPE_Reset        ((uint16_t)0xFFBF)
-
-/* I2S I2SE mask */
-#define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
-#define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
-
-/* SPI CRCNext mask */
-#define CR1_CRCNext_Set      ((uint16_t)0x1000)
-
-/* SPI CRCEN mask */
-#define CR1_CRCEN_Set        ((uint16_t)0x2000)
-#define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
-
-/* SPI SSOE mask */
-#define CR2_SSOE_Set         ((uint16_t)0x0004)
-#define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
-
-/* SPI registers Masks */
-#define CR1_CLEAR_Mask       ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
-
-/* SPI or I2S mode selection masks */
-#define SPI_Mode_Select      ((uint16_t)0xF7FF)
-#define I2S_Mode_Select      ((uint16_t)0x0800) 
-
-/* I2S clock source selection masks */
-#define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
-#define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
-#define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
-#define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the SPIx peripheral registers to their default
-  *         reset values (Affects also the I2Ss).
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  if (SPIx == SPI1)
-  {
-    /* Enable SPI1 reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
-    /* Release SPI1 from reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
-  }
-  else if (SPIx == SPI2)
-  {
-    /* Enable SPI2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
-    /* Release SPI2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
-  }
-  else
-  {
-    if (SPIx == SPI3)
-    {
-      /* Enable SPI3 reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
-      /* Release SPI3 from reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *         parameters in the SPI_InitStruct.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
-  *         contains the configuration information for the specified SPI peripheral.
-  * @retval None
-  */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
-  uint16_t tmpreg = 0;
-  
-  /* check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
-  
-  /* Check the SPI parameters */
-  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
-  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
-  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
-  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
-  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
-  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
-  /* Get the SPIx CR1 value */
-  tmpreg = SPIx->CR1;
-  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
-     master/salve mode, CPOL and CPHA */
-  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
-  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
-  /* Set LSBFirst bit according to SPI_FirstBit value */
-  /* Set BR bits according to SPI_BaudRatePrescaler value */
-  /* Set CPOL bit according to SPI_CPOL value */
-  /* Set CPHA bit according to SPI_CPHA value */
-  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
-                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
-                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
-                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
-  /* Write to SPIx CR1 */
-  SPIx->CR1 = tmpreg;
-  
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  SPIx->I2SCFGR &= SPI_Mode_Select;		
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
-  /* Write to SPIx CRCPOLY */
-  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *         parameters in the I2S_InitStruct.
-  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
-  *         (configured in I2S mode).
-  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
-  *         contains the configuration information for the specified SPI peripheral
-  *         configured in I2S mode.
-  * @note
-  *  The function calculates the optimal prescaler needed to obtain the most 
-  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
-  *  and the product configuration). But in case the prescaler value is greater 
-  *  than 511, the default value (0x02) will be configured instead.  *   
-  * @retval None
-  */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
-  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0;
-  RCC_ClocksTypeDef RCC_Clocks;
-  uint32_t sourceclock = 0;
-  
-  /* Check the I2S parameters */
-  assert_param(IS_SPI_23_PERIPH(SPIx));
-  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
-  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
-  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
-  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
-  SPIx->I2SPR = 0x0002;
-  
-  /* Get the I2SCFGR register value */
-  tmpreg = SPIx->I2SCFGR;
-  
-  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
-  {
-    i2sodd = (uint16_t)0;
-    i2sdiv = (uint16_t)2;   
-  }
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  else
-  {
-    /* Check the frame length (For the Prescaler computing) */
-    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 1;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2;
-    }
-
-    /* Get the I2S clock source mask depending on the peripheral number */
-    if(((uint32_t)SPIx) == SPI2_BASE)
-    {
-      /* The mask is relative to I2S2 */
-      tmp = I2S2_CLOCK_SRC;
-    }
-    else 
-    {
-      /* The mask is relative to I2S3 */      
-      tmp = I2S3_CLOCK_SRC;
-    }
-
-    /* Check the I2S clock source configuration depending on the Device:
-       Only Connectivity line devices have the PLL3 VCO clock */
-#ifdef STM32F10X_CL
-    if((RCC->CFGR2 & tmp) != 0)
-    {
-      /* Get the configuration bits of RCC PLL3 multiplier */
-      tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
-
-      /* Get the value of the PLL3 multiplier */      
-      if((tmp > 5) && (tmp < 15))
-      {
-        /* Multiplier is between 8 and 14 (value 15 is forbidden) */
-        tmp += 2;
-      }
-      else
-      {
-        if (tmp == 15)
-        {
-          /* Multiplier is 20 */
-          tmp = 20;
-        }
-      }      
-      /* Get the PREDIV2 value */
-      sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
-      
-      /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
-      sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); 
-    }
-    else
-    {
-      /* I2S Clock source is System clock: Get System Clock frequency */
-      RCC_GetClocksFreq(&RCC_Clocks);      
-      
-      /* Get the source clock value: based on System Clock value */
-      sourceclock = RCC_Clocks.SYSCLK_Frequency;
-    }        
-#else /* STM32F10X_HD */
-    /* I2S Clock source is System clock: Get System Clock frequency */
-    RCC_GetClocksFreq(&RCC_Clocks);      
-      
-    /* Get the source clock value: based on System Clock value */
-    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
-#endif /* STM32F10X_CL */    
-
-    /* Compute the Real divider depending on the MCLK output state with a floating point */
-    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    
-    /* Remove the floating point */
-    tmp = tmp / 10;  
-      
-    /* Check the parity of the divider */
-    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-   
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-   
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint16_t) (i2sodd << 8);
-  }
-  
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
-  {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
-  }
-
-  /* Write to SPIx I2SPR register the computed value */
-  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
- 
-  /* Configure the I2S with the SPI_InitStruct values */
-  tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
-                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
-                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
- 
-  /* Write to SPIx I2SCFGR */  
-  SPIx->I2SCFGR = tmpreg;   
-}
-
-/**
-  * @brief  Fills each SPI_InitStruct member with its default value.
-  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
-  /* Initialize the SPI_Direction member */
-  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  /* initialize the SPI_Mode member */
-  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
-  /* initialize the SPI_DataSize member */
-  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
-  /* Initialize the SPI_CPOL member */
-  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
-  /* Initialize the SPI_CPHA member */
-  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
-  /* Initialize the SPI_NSS member */
-  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
-  /* Initialize the SPI_BaudRatePrescaler member */
-  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  /* Initialize the SPI_FirstBit member */
-  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
-  /* Initialize the SPI_CRCPolynomial member */
-  SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
-  * @brief  Fills each I2S_InitStruct member with its default value.
-  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
-  /* Initialize the I2S_Mode member */
-  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-  
-  /* Initialize the I2S_Standard member */
-  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-  
-  /* Initialize the I2S_DataFormat member */
-  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-  
-  /* Initialize the I2S_MCLKOutput member */
-  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-  
-  /* Initialize the I2S_AudioFreq member */
-  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-  
-  /* Initialize the I2S_CPOL member */
-  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral */
-    SPIx->CR1 |= CR1_SPE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral */
-    SPIx->CR1 &= CR1_SPE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
-  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_23_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral (in I2S mode) */
-    SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral (in I2S mode) */
-    SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified SPI/I2S interrupts.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
-  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
-  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
-  * @param  NewState: new state of the specified SPI/I2S interrupt.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
-  uint16_t itpos = 0, itmask = 0 ;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
-  /* Get the SPI/I2S IT index */
-  itpos = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = (uint16_t)1 << (uint16_t)itpos;
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI/I2S interrupt */
-    SPIx->CR2 |= itmask;
-  }
-  else
-  {
-    /* Disable the selected SPI/I2S interrupt */
-    SPIx->CR2 &= (uint16_t)~itmask;
-  }
-}
-
-/**
-  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
-  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
-  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI/I2S DMA requests */
-    SPIx->CR2 |= SPI_I2S_DMAReq;
-  }
-  else
-  {
-    /* Disable the selected SPI/I2S DMA requests */
-    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
-  }
-}
-
-/**
-  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  Data : Data to be transmitted.
-  * @retval None
-  */
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Write in the DR register the data to be sent */
-  SPIx->DR = Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @retval The value of the received data.
-  */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Return the data in the DR register */
-  return SPIx->DR;
-}
-
-/**
-  * @brief  Configures internally by software the NSS pin for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
-  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
-  * @retval None
-  */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
-  {
-    /* Set NSS pin internally by software */
-    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
-  }
-  else
-  {
-    /* Reset NSS pin internally by software */
-    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the SS output for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx SS output. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI SS output */
-    SPIx->CR2 |= CR2_SSOE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI SS output */
-    SPIx->CR2 &= CR2_SSOE_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the data size for the selected SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_DataSize: specifies the SPI data size.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_DataSize_16b: Set data frame format to 16bit
-  *     @arg SPI_DataSize_8b: Set data frame format to 8bit
-  * @retval None
-  */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
-  /* Clear DFF bit */
-  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
-  /* Set new DFF bit value */
-  SPIx->CR1 |= SPI_DataSize;
-}
-
-/**
-  * @brief  Transmit the SPIx CRC value.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Enable the selected SPI CRC transmission */
-  SPIx->CR1 |= CR1_CRCNext_Set;
-}
-
-/**
-  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx CRC value calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI CRC calculation */
-    SPIx->CR1 |= CR1_CRCEN_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI CRC calculation */
-    SPIx->CR1 &= CR1_CRCEN_Reset;
-  }
-}
-
-/**
-  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_CRC: specifies the CRC register to be read.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_CRC_Tx: Selects Tx CRC register
-  *     @arg SPI_CRC_Rx: Selects Rx CRC register
-  * @retval The selected CRC register value..
-  */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
-  uint16_t crcreg = 0;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_CRC(SPI_CRC));
-  if (SPI_CRC != SPI_CRC_Rx)
-  {
-    /* Get the Tx CRC register */
-    crcreg = SPIx->TXCRCR;
-  }
-  else
-  {
-    /* Get the Rx CRC register */
-    crcreg = SPIx->RXCRCR;
-  }
-  /* Return the selected CRC register */
-  return crcreg;
-}
-
-/**
-  * @brief  Returns the CRC Polynomial register value for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @retval The CRC Polynomial register value.
-  */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Return the CRC polynomial register */
-  return SPIx->CRCPR;
-}
-
-/**
-  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
-  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
-  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
-  *     @arg SPI_Direction_Rx: Selects Rx receive direction
-  * @retval None
-  */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DIRECTION(SPI_Direction));
-  if (SPI_Direction == SPI_Direction_Tx)
-  {
-    /* Set the Tx only mode */
-    SPIx->CR1 |= SPI_Direction_Tx;
-  }
-  else
-  {
-    /* Set the Rx only mode */
-    SPIx->CR1 &= SPI_Direction_Rx;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified SPI/I2S flag is set or not.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
-  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
-  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
-  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
-  *     @arg SPI_FLAG_MODF: Mode Fault flag.
-  *     @arg SPI_FLAG_CRCERR: CRC Error flag.
-  *     @arg I2S_FLAG_UDR: Underrun Error flag.
-  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
-  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
-  */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-  /* Check the status of the specified SPI/I2S flag */
-  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
-  {
-    /* SPI_I2S_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
-  *   This function clears only CRCERR flag.
-  * @note
-  *   - OVR (OverRun error) flag is cleared by software sequence: a read 
-  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
-  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
-  *   - UDR (UnderRun error) flag is cleared by a read operation to 
-  *     SPI_SR register (SPI_I2S_GetFlagStatus()).
-  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
-  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
-  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
-  * @retval None
-  */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
-    
-    /* Clear the selected SPI CRC Error (CRCERR) flag */
-    SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  *   - 2 or 3 in I2S mode
-  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
-  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
-  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
-  *     @arg SPI_IT_MODF: Mode Fault interrupt.
-  *     @arg SPI_IT_CRCERR: CRC Error interrupt.
-  *     @arg I2S_IT_UDR: Underrun Error interrupt.
-  * @retval The new state of SPI_I2S_IT (SET or RESET).
-  */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
-  /* Get the SPI/I2S IT index */
-  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
-  /* Get the SPI/I2S IT mask */
-  itmask = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = 0x01 << itmask;
-
-  /* Get the SPI_I2S_IT enable bit status */
-  enablestatus = (SPIx->CR2 & itmask) ;
-
-  /* Check the status of the specified SPI/I2S interrupt */
-  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
-  {
-    /* SPI_I2S_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_IT status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
-  * @param  SPIx: where x can be
-  *   - 1, 2 or 3 in SPI mode 
-  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
-  *   This function clears only CRCERR interrupt pending bit.   
-  * @note
-  *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
-  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
-  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
-  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
-  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
-  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
-  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
-  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
-  *     the SPI).
-  * @retval None
-  */
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
-  uint16_t itpos = 0;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
-
-  /* Get the SPI IT index */
-  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
-  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
-  SPIx->SR = (uint16_t)~itpos;
-}
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
deleted file mode 100644
index bfb4dd1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
+++ /dev/null
@@ -1,2890 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_tim.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the TIM firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_tim.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup TIM 
-  * @brief TIM driver modules
-  * @{
-  */
-
-/** @defgroup TIM_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Defines
-  * @{
-  */
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_Mask               ((uint16_t)0x00FF) 
-#define CCMR_Offset                 ((uint16_t)0x0018)
-#define CCER_CCE_Set                ((uint16_t)0x0001)  
-#define	CCER_CCNE_Set               ((uint16_t)0x0004) 
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_FunctionPrototypes
-  * @{
-  */
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval None
-  */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
- 
-  if (TIMx == TIM1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
-  }     
-  else if (TIMx == TIM2)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
-  }
-  else if (TIMx == TIM3)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
-  }
-  else if (TIMx == TIM4)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
-  } 
-  else if (TIMx == TIM5)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
-  } 
-  else if (TIMx == TIM6)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
-  } 
-  else if (TIMx == TIM7)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
-  } 
-  else if (TIMx == TIM8)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
-  }
-  else if (TIMx == TIM9)
-  {      
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
-   }  
-  else if (TIMx == TIM10)
-  {      
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
-  }  
-  else if (TIMx == TIM11) 
-  {     
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
-  }  
-  else if (TIMx == TIM12)
-  {      
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
-  }  
-  else if (TIMx == TIM13) 
-  {       
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
-  }
-  else if (TIMx == TIM14) 
-  {       
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
-  }        
-  else if (TIMx == TIM15)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
-  } 
-  else if (TIMx == TIM16)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
-  } 
-  else
-  {
-    if (TIMx == TIM17)
-    {
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
-    }  
-  }
-}
-
-/**
-  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
-  *         the specified parameters in the TIM_TimeBaseInitStruct.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
-  *         structure that contains the configuration information for the 
-  *         specified TIM peripheral.
-  * @retval None
-  */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  uint16_t tmpcr1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
-  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
-  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
-  tmpcr1 = TIMx->CR1;  
-
-  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
-     (TIMx == TIM4) || (TIMx == TIM5)) 
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
-  }
- 
-  if((TIMx != TIM6) && (TIMx != TIM7))
-  {
-    /* Set the clock division */
-    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
- 
-  /* Set the Prescaler value */
-  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-    
-  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler and the Repetition counter
-     values immediately */
-  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
-}
-
-/**
-  * @brief  Initializes the TIMx Channel1 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
- /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-  
-  /* Set the Output State */
-  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-    
-  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
-     (TIMx == TIM16)|| (TIMx == TIM17))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
-    /* Set the Output N Polarity */
-    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
-    /* Set the Output N State */
-    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
- 
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel2 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-   /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-  
-  /* Get the TIMx CCER register value */  
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel3 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel4 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-    
-  if((TIMx == TIM1) || (TIMx == TIM8))
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    /* Reset the Output Compare IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */  
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
-  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
-  }
-  else
-  {
-    assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
-  }
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
-  {
-    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI3 Configuration */
-    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI4 Configuration */
-    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Configures the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
-  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Select the Opposite Input Polarity */
-  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
-  {
-    icoppositepolarity = TIM_ICPolarity_Falling;
-  }
-  else
-  {
-    icoppositepolarity = TIM_ICPolarity_Rising;
-  }
-  /* Select the Opposite Input */
-  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
-  {
-    icoppositeselection = TIM_ICSelection_IndirectTI;
-  }
-  else
-  {
-    icoppositeselection = TIM_ICSelection_DirectTI;
-  }
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI2 Configuration */
-    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  { 
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI1 Configuration */
-    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
-  *         the OSSR State and the AOE(automatic output enable).
-  * @param  TIMx: where x can be  1 or 8 to select the TIM 
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral.
-  * @retval None
-  */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
-  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
-  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
-  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
-  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
-             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
-             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
-             TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
-  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
-  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
-  *         structure which will be initialized.
-  * @retval None
-  */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  /* Set the default configuration */
-  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
-  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
-  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
-  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
-  * @brief  Fills each TIM_OCInitStruct member with its default value.
-  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  /* Set the default configuration */
-  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
-  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
-  TIM_OCInitStruct->TIM_Pulse = 0x0000;
-  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
-  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
-  * @brief  Fills each TIM_ICInitStruct member with its default value.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
-  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
-  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
-  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
-  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
-  *         will be initialized.
-  * @retval None
-  */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
-  /* Set the default configuration */
-  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
-  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
-  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
-  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
-  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
-  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
-  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified TIM peripheral.
-  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
-  * @param  NewState: new state of the TIMx peripheral.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Counter */
-    TIMx->CR1 |= TIM_CR1_CEN;
-  }
-  else
-  {
-    /* Disable the TIM Counter */
-    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIM peripheral Main Outputs.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
-  * @param  NewState: new state of the TIM peripheral Main Outputs.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Main Output */
-    TIMx->BDTR |= TIM_BDTR_MOE;
-  }
-  else
-  {
-    /* Disable the TIM Main Output */
-    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
-  }  
-}
-
-/**
-  * @brief  Enables or disables the specified TIM interrupts.
-  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
-  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note 
-  *   - TIM6 and TIM7 can only generate an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @param  NewState: new state of the TIM interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Interrupt sources */
-    TIMx->DIER |= TIM_IT;
-  }
-  else
-  {
-    /* Disable the Interrupt sources */
-    TIMx->DIER &= (uint16_t)~TIM_IT;
-  }
-}
-
-/**
-  * @brief  Configures the TIMx event to be generate by software.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_EventSource: specifies the event source.
-  *   This parameter can be one or more of the following values:	   
-  *     @arg TIM_EventSource_Update: Timer update Event source
-  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-  *     @arg TIM_EventSource_COM: Timer COM event source  
-  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
-  *     @arg TIM_EventSource_Break: Timer Break event source
-  * @note 
-  *   - TIM6 and TIM7 can only generate an update event. 
-  *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.      
-  * @retval None
-  */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-  
-  /* Set the event sources */
-  TIMx->EGR = TIM_EventSource;
-}
-
-/**
-  * @brief  Configures the TIMx's DMA interface.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
-  *   the TIM peripheral.
-  * @param  TIM_DMABase: DMA Base address.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
-  *          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
-  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
-  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
-  *          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
-  *          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
-  *          TIM_DMABase_DCR.
-  * @param  TIM_DMABurstLength: DMA Burst length.
-  *   This parameter can be one value between:
-  *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval None
-  */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
-  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-  /* Set the DMA Base and the DMA Burst Length */
-  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
-  * @brief  Enables or disables the TIMx's DMA Requests.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 
-  *   to select the TIM peripheral. 
-  * @param  TIM_DMASource: specifies the DMA Request sources.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_DMA_Update: TIM update Interrupt source
-  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *     @arg TIM_DMA_COM: TIM Commutation DMA source
-  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA sources */
-    TIMx->DIER |= TIM_DMASource; 
-  }
-  else
-  {
-    /* Disable the DMA sources */
-    TIMx->DIER &= (uint16_t)~TIM_DMASource;
-  }
-}
-
-/**
-  * @brief  Configures the TIMx internal Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
-  *         to select the TIM peripheral.
-  * @retval None
-  */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Disable slave mode to clock the prescaler directly with the internal clock */
-  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
-  * @brief  Configures the TIMx Internal Trigger as External Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ITRSource: Trigger source.
-  *   This parameter can be one of the following values:
-  * @param  TIM_TS_ITR0: Internal Trigger 0
-  * @param  TIM_TS_ITR1: Internal Trigger 1
-  * @param  TIM_TS_ITR2: Internal Trigger 2
-  * @param  TIM_TS_ITR3: Internal Trigger 3
-  * @retval None
-  */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-  /* Select the Internal Trigger */
-  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the TIMx Trigger as External Clock
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_TIxExternalCLKSource: Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
-  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
-  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
-  * @param  TIM_ICPolarity: specifies the TIx Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  ICFilter : specifies the filter value.
-  *   This parameter must be a value between 0x0 and 0xF.
-  * @retval None
-  */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
-                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
-  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
-  assert_param(IS_TIM_IC_FILTER(ICFilter));
-  /* Configure the Timer Input Clock Source */
-  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
-  {
-    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  else
-  {
-    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  /* Select the Trigger source */
-  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the External clock Mode1
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                             uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the SMS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  /* Select the External clock mode1 */
-  tmpsmcr |= TIM_SlaveMode_External1;
-  /* Select the Trigger selection : ETRF */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  tmpsmcr |= TIM_TS_ETRF;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the External clock Mode2
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
-                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  /* Enable the External clock mode2 */
-  TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                   uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the ETR Bits */
-  tmpsmcr &= SMCR_ETR_Mask;
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx Prescaler.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Prescaler: specifies the Prescaler Register value
-  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
-  *   This parameter can be one of the following values:
-  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
-  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
-  * @retval None
-  */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-  /* Set the Prescaler value */
-  TIMx->PSC = Prescaler;
-  /* Set or reset the UG Bit */
-  TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
-  * @brief  Specifies the TIMx Counter Mode to be used.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_CounterMode: specifies the Counter Mode to be used
-  *   This parameter can be one of the following values:
-  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
-  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
-  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
-  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
-  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
-  * @retval None
-  */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
-  uint16_t tmpcr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-  tmpcr1 = TIMx->CR1;
-  /* Reset the CMS and DIR Bits */
-  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-  /* Set the Counter Mode */
-  tmpcr1 |= TIM_CounterMode;
-  /* Write to TIMx CR1 register */
-  TIMx->CR1 = tmpcr1;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_InputTriggerSource: The Input Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TS_ITR0: Internal Trigger 0
-  *     @arg TIM_TS_ITR1: Internal Trigger 1
-  *     @arg TIM_TS_ITR2: Internal Trigger 2
-  *     @arg TIM_TS_ITR3: Internal Trigger 3
-  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *     @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  uint16_t tmpsmcr = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the TS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  /* Set the Input Trigger source */
-  tmpsmcr |= TIM_InputTriggerSource;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the TIMx Encoder Interface.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
-  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
-  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
-  *                                on the level of the other input.
-  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @retval None
-  */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
-                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
-  uint16_t tmpsmcr = 0;
-  uint16_t tmpccmr1 = 0;
-  uint16_t tmpccer = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
-  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  
-  /* Set the encoder Mode */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  tmpsmcr |= TIM_EncoderMode;
-  
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
-  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-  
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
-  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-  
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
-  * @retval None
-  */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
-  * @retval None
-  */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
-  * @retval None
-  */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC1M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
-  * @retval None
-  */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC2M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
-  * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx peripheral Preload register
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the ARR Preload Bit */
-    TIMx->CR1 |= TIM_CR1_ARPE;
-  }
-  else
-  {
-    /* Reset the ARR Preload Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
-  }
-}
-
-/**
-  * @brief  Selects the TIM peripheral Commutation event.
-  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
-  * @param  NewState: new state of the Commutation event.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the COM Bit */
-    TIMx->CR2 |= TIM_CR2_CCUS;
-  }
-  else
-  {
-    /* Reset the COM Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
-  }
-}
-
-/**
-  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
-  *         the TIM peripheral.
-  * @param  NewState: new state of the Capture Compare DMA source
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the CCDS Bit */
-    TIMx->CR2 |= TIM_CR2_CCDS;
-  }
-  else
-  {
-    /* Reset the CCDS Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
-  }
-}
-
-/**
-  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
-  * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15 
-  *         to select the TIMx peripheral
-  * @param  NewState: new state of the Capture Compare Preload Control bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the CCPC Bit */
-    TIMx->CR2 |= TIM_CR2_CCPC;
-  }
-  else
-  {
-    /* Reset the CCPC Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= TIM_OCPreload;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= TIM_OCPreload;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 1 Fast feature.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= TIM_OCFast;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 2 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
-  *         the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 3 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= TIM_OCFast;
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 4 Fast feature.
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF1 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Reset the OC1CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= TIM_OCClear;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF2 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF3 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= TIM_OCClear;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF4 signal on an external event
-  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx channel 1 polarity.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC1 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
-  tmpccer |= TIM_OCPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 1N polarity.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-   
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
-  tmpccer |= TIM_OCNPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 2 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC2 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 2N polarity.
-  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 3 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC3 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 3N polarity.
-  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-    
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 4 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC4 Polarity
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC4P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
-  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
-  * @retval None
-  */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_CCX(TIM_CCx));
-
-  tmp = CCER_CCE_Set << TIM_Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t)~ tmp;
-
-  /* Set or reset the CCxE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
-  *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
-  * @retval None
-  */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_CCXN(TIM_CCxN));
-
-  tmp = CCER_CCNE_Set << TIM_Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp;
-
-  /* Set or reset the CCxNE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
-  * @brief  Selects the TIM Output Compare Mode.
-  * @note   This function disables the selected channel before changing the Output
-  *         Compare Mode.
-  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCMode_Timing
-  *     @arg TIM_OCMode_Active
-  *     @arg TIM_OCMode_Toggle
-  *     @arg TIM_OCMode_PWM1
-  *     @arg TIM_OCMode_PWM2
-  *     @arg TIM_ForcedAction_Active
-  *     @arg TIM_ForcedAction_InActive
-  * @retval None
-  */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
-  uint32_t tmp = 0;
-  uint16_t tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_OCM(TIM_OCMode));
-
-  tmp = (uint32_t) TIMx;
-  tmp += CCMR_Offset;
-
-  tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
-
-  /* Disable the Channel: Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp1;
-
-  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
-  {
-    tmp += (TIM_Channel>>1);
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-   
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= TIM_OCMode;
-  }
-  else
-  {
-    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-    
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
-  }
-}
-
-/**
-  * @brief  Enables or Disables the TIMx Update event.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx UDIS bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the Update Disable Bit */
-    TIMx->CR1 |= TIM_CR1_UDIS;
-  }
-  else
-  {
-    /* Reset the Update Disable Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
-  }
-}
-
-/**
-  * @brief  Configures the TIMx Update Request Interrupt source.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_UpdateSource: specifies the Update source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
-                                       or the setting of UG bit, or an update generation
-                                       through the slave mode controller.
-  *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
-  * @retval None
-  */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-  if (TIM_UpdateSource != TIM_UpdateSource_Global)
-  {
-    /* Set the URS Bit */
-    TIMx->CR1 |= TIM_CR1_URS;
-  }
-  else
-  {
-    /* Reset the URS Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
-  }
-}
-
-/**
-  * @brief  Enables or disables the TIMx's Hall sensor interface.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx Hall sensor interface.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the TI1S Bit */
-    TIMx->CR2 |= TIM_CR2_TI1S;
-  }
-  else
-  {
-    /* Reset the TI1S Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
-  }
-}
-
-/**
-  * @brief  Selects the TIMx's One Pulse Mode.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_OPMode: specifies the OPM Mode to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OPMode_Single
-  *     @arg TIM_OPMode_Repetitive
-  * @retval None
-  */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-  /* Reset the OPM Bit */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
-  /* Configure the OPM Mode */
-  TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
-  * @brief  Selects the TIMx Trigger Output Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_TRGOSource: specifies the Trigger Output source.
-  *   This paramter can be one of the following values:
-  *
-  *  - For all TIMx
-  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
-  *
-  *  - For all TIMx except TIM6 and TIM7
-  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
-  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
-  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
-  *
-  * @retval None
-  */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST7_PERIPH(TIMx));
-  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-  /* Reset the MMS Bits */
-  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
-  /* Select the TRGO source */
-  TIMx->CR2 |=  TIM_TRGOSource;
-}
-
-/**
-  * @brief  Selects the TIMx Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
-  *                               the counter and triggers an update of the registers.
-  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
-  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
-  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
-  * @retval None
-  */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
- /* Reset the SMS Bits */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
-  /* Select the Slave Mode */
-  TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
-  * @brief  Sets or Resets the TIMx Master/Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
-  *                                      and its slaves (through TRGO).
-  *     @arg TIM_MasterSlaveMode_Disable: No action
-  * @retval None
-  */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-  /* Reset the MSM Bit */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-  
-  /* Set or Reset the MSM Bit */
-  TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
-  * @brief  Sets the TIMx Counter Register value
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Counter: specifies the Counter register new value.
-  * @retval None
-  */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Set the Counter Register value */
-  TIMx->CNT = Counter;
-}
-
-/**
-  * @brief  Sets the TIMx Autoreload Register value
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  Autoreload: specifies the Autoreload register new value.
-  * @retval None
-  */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Set the Autoreload Register value */
-  TIMx->ARR = Autoreload;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare1 Register value
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  Compare1: specifies the Capture Compare1 register new value.
-  * @retval None
-  */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  /* Set the Capture Compare1 Register value */
-  TIMx->CCR1 = Compare1;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare2 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  Compare2: specifies the Capture Compare2 register new value.
-  * @retval None
-  */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Set the Capture Compare2 Register value */
-  TIMx->CCR2 = Compare2;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare3 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  Compare3: specifies the Capture Compare3 register new value.
-  * @retval None
-  */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Set the Capture Compare3 Register value */
-  TIMx->CCR3 = Compare3;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare4 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  Compare4: specifies the Capture Compare4 register new value.
-  * @retval None
-  */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Set the Capture Compare4 Register value */
-  TIMx->CCR4 = Compare4;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 1 prescaler.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC1PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
-  /* Set the IC1PSC value */
-  TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 2 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC2PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
-  /* Set the IC2PSC value */
-  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 3 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC3PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
-  /* Set the IC3PSC value */
-  TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 4 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  /* Reset the IC4PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
-  /* Set the IC4PSC value */
-  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @brief  Sets the TIMx Clock Division value.
-  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select 
-  *   the TIM peripheral.
-  * @param  TIM_CKD: specifies the clock division value.
-  *   This parameter can be one of the following value:
-  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
-  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
-  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
-  * @retval None
-  */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-  /* Reset the CKD Bits */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
-  /* Set the CKD value */
-  TIMx->CR1 |= TIM_CKD;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 1 value.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @retval Capture Compare 1 Register value.
-  */
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
-  /* Get the Capture 1 Register value */
-  return TIMx->CCR1;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 2 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @retval Capture Compare 2 Register value.
-  */
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Get the Capture 2 Register value */
-  return TIMx->CCR2;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 3 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @retval Capture Compare 3 Register value.
-  */
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  /* Get the Capture 3 Register value */
-  return TIMx->CCR3;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 4 value.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @retval Capture Compare 4 Register value.
-  */
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  /* Get the Capture 4 Register value */
-  return TIMx->CCR4;
-}
-
-/**
-  * @brief  Gets the TIMx Counter value.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval Counter Register value.
-  */
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Get the Counter Register value */
-  return TIMx->CNT;
-}
-
-/**
-  * @brief  Gets the TIMx Prescaler value.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @retval Prescaler Register value.
-  */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  /* Get the Prescaler Register value */
-  return TIMx->PSC;
-}
-
-/**
-  * @brief  Checks whether the specified TIM flag is set or not.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 and TIM7 can have only one update flag. 
-  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
-  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @retval The new state of TIM_FLAG (SET or RESET).
-  */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{ 
-  ITStatus bitstatus = RESET;  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-  
-  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's pending flags.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 and TIM7 can have only one update flag. 
-  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
-  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.   
-  * @retval None
-  */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-   
-  /* Clear the flags */
-  TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
-  * @brief  Checks whether the TIM interrupt has occurred or not.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the TIM interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 and TIM7 can generate only an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.  
-  * @retval The new state of the TIM_IT(SET or RESET).
-  */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  ITStatus bitstatus = RESET;  
-  uint16_t itstatus = 0x0, itenable = 0x0;
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_IT(TIM_IT));
-   
-  itstatus = TIMx->SR & TIM_IT;
-  
-  itenable = TIMx->DIER & TIM_IT;
-  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's interrupt pending bits.
-  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM1 update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 and TIM7 can generate only an update interrupt.
-  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *      TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
-  * @retval None
-  */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-  /* Clear the IT pending Bit */
-  TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0;
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC1E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC1E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-  }
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 4);
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC2E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
-    tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC2E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
-  }
-  
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 8);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-    
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC3E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
-    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC3E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
-  }
-  
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
-   /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 12);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
-  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-  
-  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
-     (TIMx == TIM4) ||(TIMx == TIM5))
-  {
-    /* Select the Polarity and set the CC4E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
-    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-  }
-  else
-  {
-    /* Select the Polarity and set the CC4E Bit */
-    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
-    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
-  }
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
deleted file mode 100644
index e794eae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
+++ /dev/null
@@ -1,1058 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_usart.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the USART firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_usart.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup USART 
-  * @brief USART driver modules
-  * @{
-  */
-
-/** @defgroup USART_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Defines
-  * @{
-  */
-
-#define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
-#define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
-
-#define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
-
-#define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
-#define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
-#define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
-#define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
-#define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
-
-#define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
-#define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
-
-#define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
-#define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
-#define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */
-
-#define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
-#define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
-
-#define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
-#define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
-
-#define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
-#define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
-
-#define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
-#define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
-
-#define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
-#define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
-#define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
-#define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
-#define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
-
-/* USART OverSampling-8 Mask */
-#define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
-#define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
-
-/* USART One Bit Sampling Mask */
-#define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
-#define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values: 
-  *      USART1, USART2, USART3, UART4 or UART5.
-  * @retval None
-  */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-
-  if (USARTx == USART1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
-  }
-  else if (USARTx == USART2)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
-  }
-  else if (USARTx == USART3)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
-  }    
-  else if (USARTx == UART4)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
-  }    
-  else
-  {
-    if (USARTx == UART5)
-    { 
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral according to the specified
-  *         parameters in the USART_InitStruct .
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *         that contains the configuration information for the specified USART 
-  *         peripheral.
-  * @retval None
-  */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
-  uint32_t tmpreg = 0x00, apbclock = 0x00;
-  uint32_t integerdivider = 0x00;
-  uint32_t fractionaldivider = 0x00;
-  uint32_t usartxbase = 0;
-  RCC_ClocksTypeDef RCC_ClocksStatus;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
-  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
-  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
-  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
-  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
-  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-  /* The hardware flow control is available only for USART1, USART2 and USART3 */
-  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }
-
-  usartxbase = (uint32_t)USARTx;
-
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear STOP[13:12] bits */
-  tmpreg &= CR2_STOP_CLEAR_Mask;
-  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
-  /* Set STOP[13:12] bits according to USART_StopBits value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-  
-  /* Write to USART CR2 */
-  USARTx->CR2 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = USARTx->CR1;
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure the USART Word Length, Parity and mode ----------------------- */
-  /* Set the M bits according to USART_WordLength value */
-  /* Set PCE and PS bits according to USART_Parity value */
-  /* Set TE and RE bits according to USART_Mode value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
-            USART_InitStruct->USART_Mode;
-  /* Write to USART CR1 */
-  USARTx->CR1 = (uint16_t)tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/  
-  tmpreg = USARTx->CR3;
-  /* Clear CTSE and RTSE bits */
-  tmpreg &= CR3_CLEAR_Mask;
-  /* Configure the USART HFC -------------------------------------------------*/
-  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
-  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-  /* Write to USART CR3 */
-  USARTx->CR3 = (uint16_t)tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
-  /* Configure the USART Baud Rate -------------------------------------------*/
-  RCC_GetClocksFreq(&RCC_ClocksStatus);
-  if (usartxbase == USART1_BASE)
-  {
-    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
-  }
-  else
-  {
-    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
-  }
-  
-  /* Determine the integer part */
-  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
-  {
-    /* Integer part computing in case Oversampling mode is 8 Samples */
-    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    /* Integer part computing in case Oversampling mode is 16 Samples */
-    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  tmpreg = (integerdivider / 100) << 4;
-
-  /* Determine the fractional part */
-  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
-  /* Implement the fractional part in the register */
-  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
-  {
-    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
-  }
-  
-  /* Write to USART BRR */
-  USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_InitStruct member with its default value.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *         which will be initialized.
-  * @retval None
-  */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
-  /* USART_InitStruct members default value */
-  USART_InitStruct->USART_BaudRate = 9600;
-  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
-  USART_InitStruct->USART_StopBits = USART_StopBits_1;
-  USART_InitStruct->USART_Parity = USART_Parity_No ;
-  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral Clock according to the 
-  *          specified parameters in the USART_ClockInitStruct .
-  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *         structure that contains the configuration information for the specified 
-  *         USART peripheral.  
-  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
-  * @retval None
-  */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  uint32_t tmpreg = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
-  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
-  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
-  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-  
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
-  tmpreg &= CR2_CLOCK_CLEAR_Mask;
-  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
-  /* Set CLKEN bit according to USART_Clock value */
-  /* Set CPOL bit according to USART_CPOL value */
-  /* Set CPHA bit according to USART_CPHA value */
-  /* Set LBCL bit according to USART_LastBit value */
-  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
-                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
-  /* Write to USART CR2 */
-  USARTx->CR2 = (uint16_t)tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_ClockInitStruct member with its default value.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *         structure which will be initialized.
-  * @retval None
-  */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  /* USART_ClockInitStruct members default value */
-  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
-  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
-  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
-  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified USART peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *         This parameter can be one of the following values:
-  *           USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USARTx peripheral.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected USART by setting the UE bit in the CR1 register */
-    USARTx->CR1 |= CR1_UE_Set;
-  }
-  else
-  {
-    /* Disable the selected USART by clearing the UE bit in the CR1 register */
-    USARTx->CR1 &= CR1_UE_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified USART interrupts.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *     @arg USART_IT_IDLE: Idle line detection interrupt
-  *     @arg USART_IT_PE:   Parity Error interrupt
-  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @param  NewState: new state of the specified USARTx interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
-{
-  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
-  uint32_t usartxbase = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CONFIG_IT(USART_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  /* The CTS interrupt is not available for UART4 and UART5 */
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  usartxbase = (uint32_t)USARTx;
-
-  /* Get the USART register index */
-  usartreg = (((uint8_t)USART_IT) >> 0x05);
-
-  /* Get the interrupt position */
-  itpos = USART_IT & IT_Mask;
-  itmask = (((uint32_t)0x01) << itpos);
-    
-  if (usartreg == 0x01) /* The IT is in CR1 register */
-  {
-    usartxbase += 0x0C;
-  }
-  else if (usartreg == 0x02) /* The IT is in CR2 register */
-  {
-    usartxbase += 0x10;
-  }
-  else /* The IT is in CR3 register */
-  {
-    usartxbase += 0x14; 
-  }
-  if (NewState != DISABLE)
-  {
-    *(__IO uint32_t*)usartxbase  |= itmask;
-  }
-  else
-  {
-    *(__IO uint32_t*)usartxbase &= ~itmask;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART’s DMA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_DMAReq: specifies the DMA request.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_DMAReq_Tx: USART DMA transmit request
-  *     @arg USART_DMAReq_Rx: USART DMA receive request
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note The DMA mode is not available for UART5 except in the STM32
-  *       High density value line devices(STM32F10X_HD_VL).  
-  * @retval None
-  */
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 |= USART_DMAReq;
-  }
-  else
-  {
-    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
-  }
-}
-
-/**
-  * @brief  Sets the address of the USART node.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_Address: Indicates the address of the USART node.
-  * @retval None
-  */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_ADDRESS(USART_Address)); 
-    
-  /* Clear the USART address */
-  USARTx->CR2 &= CR2_Address_Mask;
-  /* Set the USART address node */
-  USARTx->CR2 |= USART_Address;
-}
-
-/**
-  * @brief  Selects the USART WakeUp method.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_WakeUp: specifies the USART wakeup method.
-  *   This parameter can be one of the following values:
-  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
-  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
-  * @retval None
-  */
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_WAKEUP(USART_WakeUp));
-  
-  USARTx->CR1 &= CR1_WAKE_Mask;
-  USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
-  * @brief  Determines if the USART is in mute mode or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART mute mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-    USARTx->CR1 |= CR1_RWU_Set;
-  }
-  else
-  {
-    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-    USARTx->CR1 &= CR1_RWU_Reset;
-  }
-}
-
-/**
-  * @brief  Sets the USART LIN Break detection length.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
-  *   This parameter can be one of the following values:
-  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
-  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
-  * @retval None
-  */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-  
-  USARTx->CR2 &= CR2_LBDL_Mask;
-  USARTx->CR2 |= USART_LINBreakDetectLength;  
-}
-
-/**
-  * @brief  Enables or disables the USART’s LIN mode.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART LIN mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-    USARTx->CR2 |= CR2_LINEN_Set;
-  }
-  else
-  {
-    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
-    USARTx->CR2 &= CR2_LINEN_Reset;
-  }
-}
-
-/**
-  * @brief  Transmits single data through the USARTx peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DATA(Data)); 
-    
-  /* Transmit Data */
-  USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
-  * @brief  Returns the most recent received data by the USARTx peripheral.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @retval The received data.
-  */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Receive Data */
-  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-/**
-  * @brief  Transmits break characters.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @retval None
-  */
-void USART_SendBreak(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Send break characters */
-  USARTx->CR1 |= CR1_SBK_Set;
-}
-
-/**
-  * @brief  Sets the specified USART guard time.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
-  * @param  USART_GuardTime: specifies the guard time.
-  * @note The guard time bits are not available for UART4 and UART5.   
-  * @retval None
-  */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  
-  /* Clear the USART Guard time */
-  USARTx->GTPR &= GTPR_LSB_Mask;
-  /* Set the USART guard time */
-  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
-  * @brief  Sets the system clock prescaler.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_Prescaler: specifies the prescaler clock.  
-  * @note   The function is used for IrDA mode with UART4 and UART5.
-  * @retval None
-  */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{ 
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Clear the USART prescaler */
-  USARTx->GTPR &= GTPR_MSB_Mask;
-  /* Set the USART prescaler */
-  USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
-  * @brief  Enables or disables the USART’s Smart Card mode.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
-  * @param  NewState: new state of the Smart Card mode.
-  *   This parameter can be: ENABLE or DISABLE.     
-  * @note The Smart Card mode is not available for UART4 and UART5. 
-  * @retval None
-  */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
-    USARTx->CR3 |= CR3_SCEN_Set;
-  }
-  else
-  {
-    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
-    USARTx->CR3 &= CR3_SCEN_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables NACK transmission.
-  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral. 
-  * @param  NewState: new state of the NACK transmission.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @note The Smart Card mode is not available for UART4 and UART5.
-  * @retval None
-  */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_123_PERIPH(USARTx));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
-    USARTx->CR3 |= CR3_NACK_Set;
-  }
-  else
-  {
-    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
-    USARTx->CR3 &= CR3_NACK_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART’s Half Duplex communication.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART Communication.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-    USARTx->CR3 |= CR3_HDSEL_Set;
-  }
-  else
-  {
-    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
-    USARTx->CR3 &= CR3_HDSEL_Reset;
-  }
-}
-
-
-/**
-  * @brief  Enables or disables the USART's 8x oversampling mode.
-  * @param  USARTx: Select the USART or the UART peripheral.
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART one bit sampling method.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *     This function has to be called before calling USART_Init()
-  *     function in order to have correct baudrate Divider value.   
-  * @retval None
-  */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
-    USARTx->CR1 |= CR1_OVER8_Set;
-  }
-  else
-  {
-    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
-    USARTx->CR1 &= CR1_OVER8_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's one bit sampling method.
-  * @param  USARTx: Select the USART or the UART peripheral.
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the USART one bit sampling method.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
-    USARTx->CR3 |= CR3_ONEBITE_Set;
-  }
-  else
-  {
-    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
-    USARTx->CR3 &= CR3_ONEBITE_Reset;
-  }
-}
-
-/**
-  * @brief  Configures the USART's IrDA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IrDAMode: specifies the IrDA mode.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IrDAMode_LowPower
-  *     @arg USART_IrDAMode_Normal
-  * @retval None
-  */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-    
-  USARTx->CR3 &= CR3_IRLP_Mask;
-  USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
-  * @brief  Enables or disables the USART's IrDA interface.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  NewState: new state of the IrDA mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-    
-  if (NewState != DISABLE)
-  {
-    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-    USARTx->CR3 |= CR3_IREN_Set;
-  }
-  else
-  {
-    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
-    USARTx->CR3 &= CR3_IREN_Reset;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified USART flag is set or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag
-  *     @arg USART_FLAG_TXE:  Transmit data register empty flag
-  *     @arg USART_FLAG_TC:   Transmission Complete flag
-  *     @arg USART_FLAG_RXNE: Receive data register not empty flag
-  *     @arg USART_FLAG_IDLE: Idle Line detection flag
-  *     @arg USART_FLAG_ORE:  OverRun Error flag
-  *     @arg USART_FLAG_NE:   Noise Error flag
-  *     @arg USART_FLAG_FE:   Framing Error flag
-  *     @arg USART_FLAG_PE:   Parity Error flag
-  * @retval The new state of USART_FLAG (SET or RESET).
-  */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_FLAG(USART_FLAG));
-  /* The CTS flag is not available for UART4 and UART5 */
-  if (USART_FLAG == USART_FLAG_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }  
-  
-  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the USARTx's pending flags.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
-  *     @arg USART_FLAG_TC:   Transmission Complete flag.
-  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note
-  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *     error) and IDLE (Idle line detected) flags are cleared by software 
-  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
-  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
-  *   - RXNE flag can be also cleared by a read to the USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - TC flag can be also cleared by software sequence: a read operation to 
-  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
-  *     to USART_DR register (USART_SendData()).
-  *   - TXE flag is cleared only by a write to the USART_DR register 
-  *     (USART_SendData()).
-  * @retval None
-  */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-  /* The CTS flag is not available for UART4 and UART5 */
-  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  } 
-   
-  USARTx->SR = (uint16_t)~USART_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the USART interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *     @arg USART_IT_IDLE: Idle line detection interrupt
-  *     @arg USART_IT_ORE:  OverRun Error interrupt
-  *     @arg USART_IT_NE:   Noise Error interrupt
-  *     @arg USART_IT_FE:   Framing Error interrupt
-  *     @arg USART_IT_PE:   Parity Error interrupt
-  * @retval The new state of USART_IT (SET or RESET).
-  */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
-  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_GET_IT(USART_IT));
-  /* The CTS interrupt is not available for UART4 and UART5 */ 
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  /* Get the USART register index */
-  usartreg = (((uint8_t)USART_IT) >> 0x05);
-  /* Get the interrupt position */
-  itmask = USART_IT & IT_Mask;
-  itmask = (uint32_t)0x01 << itmask;
-  
-  if (usartreg == 0x01) /* The IT  is in CR1 register */
-  {
-    itmask &= USARTx->CR1;
-  }
-  else if (usartreg == 0x02) /* The IT  is in CR2 register */
-  {
-    itmask &= USARTx->CR2;
-  }
-  else /* The IT  is in CR3 register */
-  {
-    itmask &= USARTx->CR3;
-  }
-  
-  bitpos = USART_IT >> 0x08;
-  bitpos = (uint32_t)0x01 << bitpos;
-  bitpos &= USARTx->SR;
-  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  
-  return bitstatus;  
-}
-
-/**
-  * @brief  Clears the USARTx's interrupt pending bits.
-  * @param  USARTx: Select the USART or the UART peripheral. 
-  *   This parameter can be one of the following values:
-  *   USART1, USART2, USART3, UART4 or UART5.
-  * @param  USART_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt
-  *     @arg USART_IT_TC:   Transmission complete interrupt. 
-  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
-  *   
-  * @note
-  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *     error) and IDLE (Idle line detected) pending bits are cleared by 
-  *     software sequence: a read operation to USART_SR register 
-  *     (USART_GetITStatus()) followed by a read operation to USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - RXNE pending bit can be also cleared by a read to the USART_DR register 
-  *     (USART_ReceiveData()).
-  *   - TC pending bit can be also cleared by software sequence: a read 
-  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
-  *     operation to USART_DR register (USART_SendData()).
-  *   - TXE pending bit is cleared only by a write to the USART_DR register 
-  *     (USART_SendData()).
-  * @retval None
-  */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
-{
-  uint16_t bitpos = 0x00, itmask = 0x00;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_IT(USART_IT));
-  /* The CTS interrupt is not available for UART4 and UART5 */
-  if (USART_IT == USART_IT_CTS)
-  {
-    assert_param(IS_USART_123_PERIPH(USARTx));
-  }   
-  
-  bitpos = USART_IT >> 0x08;
-  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
-  USARTx->SR = (uint16_t)~itmask;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
deleted file mode 100644
index 4a901e4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x_wwdg.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the WWDG firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_wwdg.h"
-#include "stm32f10x_rcc.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup WWDG 
-  * @brief WWDG driver modules
-  * @{
-  */
-
-/** @defgroup WWDG_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Defines
-  * @{
-  */
-
-/* ----------- WWDG registers bit address in the alias region ----------- */
-#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
-
-/* Alias word address of EWI bit */
-#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
-#define EWI_BitNumber     0x09
-#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
-
-/* --------------------- WWDG registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_WDGA_Set       ((uint32_t)0x00000080)
-
-/* CFR register bit mask */
-#define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
-#define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
-#define BIT_Mask          ((uint8_t)0x7F)
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_FunctionPrototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void WWDG_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
-  * @brief  Sets the WWDG Prescaler.
-  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
-  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
-  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
-  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
-  * @retval None
-  */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
-  /* Clear WDGTB[1:0] bits */
-  tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
-  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
-  tmpreg |= WWDG_Prescaler;
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Sets the WWDG window value.
-  * @param  WindowValue: specifies the window value to be compared to the downcounter.
-  *   This parameter value must be lower than 0x80.
-  * @retval None
-  */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
-  /* Clear W[6:0] bits */
-
-  tmpreg = WWDG->CFR & CFR_W_Mask;
-
-  /* Set W[6:0] bits according to WindowValue value */
-  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
-
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
-  * @param  None
-  * @retval None
-  */
-void WWDG_EnableIT(void)
-{
-  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Sets the WWDG counter value.
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F.
-  * @retval None
-  */
-void WWDG_SetCounter(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  /* Write to T[6:0] bits to configure the counter value, no need to do
-     a read-modify-write; writing a 0 to WDGA bit does nothing */
-  WWDG->CR = Counter & BIT_Mask;
-}
-
-/**
-  * @brief  Enables WWDG and load the counter value.                  
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F.
-  * @retval None
-  */
-void WWDG_Enable(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  WWDG->CR = CR_WDGA_Set | Counter;
-}
-
-/**
-  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
-  * @param  None
-  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
-  */
-FlagStatus WWDG_GetFlagStatus(void)
-{
-  return (FlagStatus)(WWDG->SR);
-}
-
-/**
-  * @brief  Clears Early Wakeup interrupt flag.
-  * @param  None
-  * @retval None
-  */
-void WWDG_ClearFlag(void)
-{
-  WWDG->SR = (uint32_t)RESET;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
deleted file mode 100644
index fe7d71e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/3ADCs_DMA/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_3ADCs_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ADC1_DR_Address    ((uint32_t)0x4001244C)
-#define ADC3_DR_Address    ((uint32_t)0x40013C4C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-ADC_InitTypeDef ADC_InitStructure;
-DMA_InitTypeDef DMA_InitStructure;
-__IO uint16_t ADC1ConvertedValue = 0, ADC3ConvertedValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* DMA1 channel1 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel1);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC1ConvertedValue;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 1;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA1_Channel1, &DMA_InitStructure);  
-  /* Enable DMA1 channel1 */
-  DMA_Cmd(DMA1_Channel1, ENABLE);
-
-  /* DMA2 channel5 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA2_Channel5);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC3_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC3ConvertedValue;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 1;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA2_Channel5, &DMA_InitStructure);  
-  /* Enable DMA2 channel5 */
-  DMA_Cmd(DMA2_Channel5, ENABLE);
-
-  /* ADC1 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
-  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 1;
-  ADC_Init(ADC1, &ADC_InitStructure);
-  /* ADC1 regular channels configuration */ 
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_28Cycles5);    
-  /* Enable ADC1 DMA */
-  ADC_DMACmd(ADC1, ENABLE);
-
-  /* ADC2 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
-  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 1;
-  ADC_Init(ADC2, &ADC_InitStructure);
-  /* ADC2 regular channels configuration */ 
-  ADC_RegularChannelConfig(ADC2, ADC_Channel_13, 1, ADC_SampleTime_28Cycles5);
-  /* Enable ADC2 EOC interrupt */
-  ADC_ITConfig(ADC2, ADC_IT_EOC, ENABLE);
-
-  /* ADC3 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
-  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 1;
-  ADC_Init(ADC3, &ADC_InitStructure);
-  /* ADC3 regular channel14 configuration */ 
-  ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_28Cycles5);
-  /* Enable ADC3 DMA */
-  ADC_DMACmd(ADC3, ENABLE);
-
-  /* Enable ADC1 */
-  ADC_Cmd(ADC1, ENABLE);
-
-  /* Enable ADC1 reset calibration register */   
-  ADC_ResetCalibration(ADC1);
-  /* Check the end of ADC1 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC1));
-
-  /* Start ADC1 calibration */
-  ADC_StartCalibration(ADC1);
-  /* Check the end of ADC1 calibration */
-  while(ADC_GetCalibrationStatus(ADC1));
-
-  /* Enable ADC2 */
-  ADC_Cmd(ADC2, ENABLE);
-
-  /* Enable ADC2 reset calibration register */   
-  ADC_ResetCalibration(ADC2);
-  /* Check the end of ADC2 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC2));
-
-  /* Start ADC2 calibration */
-  ADC_StartCalibration(ADC2);
-  /* Check the end of ADC2 calibration */
-  while(ADC_GetCalibrationStatus(ADC2));
-
-  /* Enable ADC3 */
-  ADC_Cmd(ADC3, ENABLE);
-
-  /* Enable ADC3 reset calibration register */   
-  ADC_ResetCalibration(ADC3);
-  /* Check the end of ADC3 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC3));
-
-  /* Start ADC3 calibration */
-  ADC_StartCalibration(ADC3);
-  /* Check the end of ADC3 calibration */
-  while(ADC_GetCalibrationStatus(ADC3));
-
-  /* Start ADC1 Software Conversion */ 
-  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-  /* Start ADC2 Software Conversion */ 
-  ADC_SoftwareStartConvCmd(ADC2, ENABLE);
-  /* Start ADC3 Software Conversion */ 
-  ADC_SoftwareStartConvCmd(ADC3, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* ADCCLK = PCLK2/4 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div4); 
-    
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* Enable DMA1 and DMA2 clocks */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);
-
-  /* Enable ADC1, ADC2, ADC3 and GPIOC clocks */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 |
-                         RCC_APB2Periph_ADC3 | RCC_APB2Periph_GPIOC, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure PC.02, PC.03 and PC.04 (ADC Channel12, ADC Channel13 and 
-     ADC Channel14) as analog inputs */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures Vector Table base location.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure and enable ADC interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h
deleted file mode 100644
index 02db464..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/3ADCs_DMA/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
deleted file mode 100644
index 3dd4e41..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/3ADCs_DMA/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_3ADCs_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint16_t ADC2ConvertedValue;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
- 
-/**
-  * @brief  This function handles ADC1 and ADC2 global interrupts requests.
-  * @param  None
-  * @retval None
-  */
-void ADC1_2_IRQHandler(void)
-{
-  /* Get injected channel13 converted value */
-  ADC2ConvertedValue = ADC_GetConversionValue(ADC2);
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h
deleted file mode 100644
index fc8479d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/3ADCs_DMA/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void ADC1_2_IRQHandler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
deleted file mode 100644
index f41af14..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/3ADCs_DMA/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
- #define SYSCLK_FREQ_56MHz  56000000
-/* #define SYSCLK_FREQ_72MHz  72000000 */
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
deleted file mode 100644
index bc9bd02..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ADC1_DMA/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_ADC1_DMA
-  * @{
-  */ 
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ADC1_DR_Address    ((uint32_t)0x4001244C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-ADC_InitTypeDef ADC_InitStructure;
-DMA_InitTypeDef DMA_InitStructure;
-__IO uint16_t ADCConvertedValue;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* DMA1 channel1 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel1);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADCConvertedValue;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 1;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA1_Channel1, &DMA_InitStructure);
-  
-  /* Enable DMA1 channel1 */
-  DMA_Cmd(DMA1_Channel1, ENABLE);
-  
-  /* ADC1 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
-  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 1;
-  ADC_Init(ADC1, &ADC_InitStructure);
-
-  /* ADC1 regular channel14 configuration */ 
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);
-
-  /* Enable ADC1 DMA */
-  ADC_DMACmd(ADC1, ENABLE);
-  
-  /* Enable ADC1 */
-  ADC_Cmd(ADC1, ENABLE);
-
-  /* Enable ADC1 reset calibration register */   
-  ADC_ResetCalibration(ADC1);
-  /* Check the end of ADC1 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC1));
-
-  /* Start ADC1 calibration */
-  ADC_StartCalibration(ADC1);
-  /* Check the end of ADC1 calibration */
-  while(ADC_GetCalibrationStatus(ADC1));
-     
-  /* Start ADC1 Software Conversion */ 
-  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  /* ADCCLK = PCLK2/2 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div2); 
-#else
-  /* ADCCLK = PCLK2/4 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div4); 
-#endif
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* Enable DMA1 clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-
-  /* Enable ADC1 and GPIOC clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOC, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure PC.04 (ADC Channel14) as analog input -------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt
deleted file mode 100644
index 19d9a7d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
-  @page ADC_ADC1_DMA ADC1 DMA example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    ADC/ADC1_DMA/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the ADC1 DMA example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to use the ADC1 and DMA to transfer continuously 
-converted data from ADC1 to memory.
-The ADC1 is configured to convert continuously channel14.
-Each time an end of conversion occurs the DMA transfers, in circular mode, the
-converted data from ADC1 DR register to the ADCConvertedValue variable.
-The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other 
-devices.
-
-@par Directory contents 
-
-  - ADC/ADC1_DMA/stm32f10x_conf.h     Library Configuration file
-  - ADC/ADC1_DMA/stm32f10x_it.c       Interrupt handlers
-  - ADC/ADC1_DMA/stm32f10x_it.h       Interrupt handlers header file
-  - ADC/ADC1_DMA/system_stm32f10x.c   STM32F10x system source file
-  - ADC/ADC1_DMA/main.c               Main program
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and 
-    STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored 
-    to any other supported device and development board.
-
-  - STM32100E-EVAL Set-up
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV2)
-      
-  - STM32100B-EVAL Set-up
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV1)
-
-  - STM3210C-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV1)
-
-  - STM3210E-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV1)
-
-  - STM3210B-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV1)
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c
deleted file mode 100644
index 1c69e80..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ADC1_DMA/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_ADC1_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h
deleted file mode 100644
index 658cd79..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ADC1_DMA/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c
deleted file mode 100644
index c2c3659..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ADC1_DMA/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
- #define SYSCLK_FREQ_56MHz  56000000 
-/* #define SYSCLK_FREQ_72MHz  72000000 */
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h
deleted file mode 100644
index de24e23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/AnalogWatchdog/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c
deleted file mode 100644
index d482d69..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/AnalogWatchdog/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_AnalogWatchdog
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles ADC1 and ADC2 global interrupts requests.
-  * @param  None
-  * @retval None
-  */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void ADC1_IRQHandler(void)
-#else
-void ADC1_2_IRQHandler(void)
-#endif
-{
-  /* Toggle LED1 */
-  STM_EVAL_LEDOn(LED1);
-  STM_EVAL_LEDOff(LED1);
-  
-  /* Clear ADC1 AWD pending interrupt bit */
-  ADC_ClearITPendingBit(ADC1, ADC_IT_AWD);
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h
deleted file mode 100644
index 59a502e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/AnalogWatchdog/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void ADC1_IRQHandler(void);
-#else
-void ADC1_2_IRQHandler(void);
-#endif
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c
deleted file mode 100644
index 64f1272..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/AnalogWatchdog/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
- #define SYSCLK_FREQ_56MHz  56000000
-/* #define SYSCLK_FREQ_72MHz  72000000 */
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
deleted file mode 100644
index 8118c04..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ExtLinesTrigger/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_ExtLinesTrigger
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ADC1_DR_Address    ((uint32_t)0x4001244C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-ADC_InitTypeDef   ADC_InitStructure;
-DMA_InitTypeDef   DMA_InitStructure;
-__IO uint16_t ADC_RegularConvertedValueTab[64], ADC_InjectedConvertedValueTab[32];
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-void EXTI_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* EXTI configuration ------------------------------------------------------*/
-  EXTI_Configuration();
-
-  /* DMA1 channel1 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel1);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC_RegularConvertedValueTab;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 64;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA1_Channel1, &DMA_InitStructure);
-  
-  /* Enable DMA1 channel1 */
-  DMA_Cmd(DMA1_Channel1, ENABLE);
-  
-  /* ADC1 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
-  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 2;
-  ADC_Init(ADC1, &ADC_InitStructure);
-
-  /* ADC1 regular channels configuration */ 
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_28Cycles5);
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 2, ADC_SampleTime_28Cycles5);
-
-  /* Regular discontinuous mode channel number configuration */
-  ADC_DiscModeChannelCountConfig(ADC1, 1);
-  /* Enable regular discontinuous mode */
-  ADC_DiscModeCmd(ADC1, ENABLE);
-
-  /* Enable ADC1 external trigger conversion */ 
-  ADC_ExternalTrigConvCmd(ADC1, ENABLE);
-
-  /* Set injected sequencer length */
-  ADC_InjectedSequencerLengthConfig(ADC1, 2);
-  /* ADC1 injected channel configuration */ 
-  ADC_InjectedChannelConfig(ADC1, ADC_Channel_11, 1, ADC_SampleTime_28Cycles5);
-  ADC_InjectedChannelConfig(ADC1, ADC_Channel_12, 2, ADC_SampleTime_28Cycles5);
-  /* ADC1 injected external trigger configuration */
-  ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4);
-  /* Enable ADC1 injected external trigger conversion */
-  ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE);
-
-  /* Enable JEOC interrupt */
-  ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
-
-  /* Enable ADC1 DMA */
-  ADC_DMACmd(ADC1, ENABLE);
-  
-  /* Enable ADC1 */
-  ADC_Cmd(ADC1, ENABLE);  
-
-  /* Enable ADC1 reset calibration register */   
-  ADC_ResetCalibration(ADC1);
-  /* Check the end of ADC1 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC1));
-
-  /* Start ADC1 calibration */
-  ADC_StartCalibration(ADC1);
-  /* Check the end of ADC1 calibration */
-  while(ADC_GetCalibrationStatus(ADC1));
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  /* ADCCLK = PCLK2/2 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div2);
-#else
-  /* ADCCLK = PCLK2/4 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div4); 
-#endif
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* Enable DMA1 clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-
-  /* Enable GPIOs and ADC1 clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | 
-                         RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO |
-                         RCC_APB2Periph_ADC1, ENABLE);
-}
-
-/**
-  * @brief  Configures the different EXTI lines.
-  * @param  None
-  * @retval None
-  */
-void EXTI_Configuration(void)
-{
-  EXTI_InitTypeDef EXTI_InitStructure;
-#ifdef STM32F10X_HD_VL
-  /* Select the EXTI Line11 the GPIO pin source */
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOF, GPIO_PinSource11);
-#else
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOE, GPIO_PinSource11);
-#endif
-
-  /* EXTI line11 configuration -----------------------------------------------*/  
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
-  EXTI_InitStructure.EXTI_Line = EXTI_Line11;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  /* Select the EXTI Line15 the GPIO pin source */
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOE, GPIO_PinSource15);
-  /* EXTI line15 configuration -----------------------------------------------*/  
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
-  EXTI_InitStructure.EXTI_Line = EXTI_Line15;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure PC.01, PC.02 and PC.04 (ADC Channel11, Channel12 and Channel14)
-   as analog input -----------------------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  /* Configure PA.04 (ADC Channel4) as analog input --------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* Configure EXTI line11 ---------------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-#ifdef STM32F10X_HD_VL 
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-#else
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-#endif
-
-  /* Configure EXTI line15 ---------------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures NVIC and Vector Table base location.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-    /* Configure and enable ADC interrupt */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  NVIC_InitStructure.NVIC_IRQChannel = ADC1_IRQn;
-#else
-  NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
-#endif
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt
deleted file mode 100644
index 2a57195..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
-  @page ADC_ExtLinesTrigger ADC external lines trigger example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    ADC/ExtLinesTrigger/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the ADC external lines trigger example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to trigger ADC regular and injected groups channels 
-conversion using two external line events. Discontinuous mode is enabled for regular
-group channel conversion and configured to convert one regular channel on each 
-external trigger.
-
-ADC1 is configured to start regular group channel conversion on EXTI11 event.
-On detection of the first rising edge on PE.11 pin (PF.11 pin for High-Density Value line),
-the conversion of the first regular channel (ADC channel4) is done and its converted 
-value is transferred by DMA to ADC_RegularConvertedValueTab table. On the following edge 
-detection, the second regular channel (ADC channel14) is automatically converted and 
-its converted value is stored by DMA in the same table. The number of transmitted data 
-by DMA, in this example is limited to 64 data.
-
-The procedure is repeated for both regular channels on each EXTI11 event.
-ADC1 is configured to start injected group channel conversion on EXTI15 event.
-On detection of the first rising edge on PE.15 pin all selected injected channels, which
-are two in this example (ADC channel11 and channel12), are converted and an interrupt 
-is generated on JEOC flag rising at the end of all injected channels conversion. 
-Both injected channels converted results are stored in ADC_InjectedConvertedValueTab 
-table inside the interrupt routine.
-The procedure is repeated for injected channels on each EXTI15 event.
-The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other 
-devices.
-
-@par Directory contents 
-
-  - ADC/ExtLinesTrigger/stm32f10x_conf.h     Library Configuration file
-  - ADC/ExtLinesTrigger/stm32f10x_it.c       Interrupt handlers
-  - ADC/ExtLinesTrigger/stm32f10x_it.h       Interrupt handlers header file
-  - ADC/ExtLinesTrigger/system_stm32f10x.c   STM32F10x system source file  
-  - ADC/ExtLinesTrigger/main.c               Main program
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density
-    Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and
-    XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily
-    tailored to any other supported device and development board.
-
-  - STM32100B-EVAL Set-up
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV2), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-    @note Make shure that jumper JP3 is open.
-    
-  - STM32100E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PF.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210C-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210B-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).              
-   
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.  
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h
deleted file mode 100644
index fc282f0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ExtLinesTrigger/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
deleted file mode 100644
index fa7bccc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ExtLinesTrigger/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_ExtLinesTrigger
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint16_t ADC_InjectedConvertedValueTab[32];
-uint32_t Index = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles ADC1 and ADC2 global interrupts requests.
-  * @param  None
-  * @retval None
-  */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void ADC1_IRQHandler(void)
-#else
-void ADC1_2_IRQHandler(void)
-#endif
-{
-  /* Clear ADC1 JEOC pending interrupt bit */
-  ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC);
-  
-  /* Get injected channel11 and channel12 converted value */
-  ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1);
-  ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_2);
-  
-  if (Index == 32)
-  {
-    Index = 0;
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h
deleted file mode 100644
index 2a0c5b1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ExtLinesTrigger/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
-void ADC1_IRQHandler(void);
-#else
-void ADC1_2_IRQHandler(void);
-#endif
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c
deleted file mode 100644
index 7770570..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/ExtLinesTrigger/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
- #define SYSCLK_FREQ_56MHz  56000000
-/* #define SYSCLK_FREQ_72MHz  72000000 */
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
deleted file mode 100644
index c6d474d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/RegSimul_DualMode/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_RegSimul_DualMode
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ADC1_DR_Address    ((uint32_t)0x4001244C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-ADC_InitTypeDef ADC_InitStructure;
-DMA_InitTypeDef DMA_InitStructure;
-__IO uint32_t ADC_DualConvertedValueTab[16];
-    
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-  
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* DMA1 channel1 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel1);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC1_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC_DualConvertedValueTab;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 16;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA1_Channel1, &DMA_InitStructure);
-  /* Enable DMA1 Channel1 */
-  DMA_Cmd(DMA1_Channel1, ENABLE);
-
-  /* ADC1 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_RegSimult;
-  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 2;
-  ADC_Init(ADC1, &ADC_InitStructure);
-  /* ADC1 regular channels configuration */ 
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_239Cycles5);    
-  ADC_RegularChannelConfig(ADC1, ADC_Channel_17, 2, ADC_SampleTime_239Cycles5);
-  /* Enable ADC1 DMA */
-  ADC_DMACmd(ADC1, ENABLE);
-
-  /* ADC2 configuration ------------------------------------------------------*/
-  ADC_InitStructure.ADC_Mode = ADC_Mode_RegSimult;
-  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
-  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
-  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
-  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-  ADC_InitStructure.ADC_NbrOfChannel = 2;
-  ADC_Init(ADC2, &ADC_InitStructure);
-  /* ADC2 regular channels configuration */ 
-  ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_239Cycles5);
-  ADC_RegularChannelConfig(ADC2, ADC_Channel_12, 2, ADC_SampleTime_239Cycles5);
-  /* Enable ADC2 external trigger conversion */
-  ADC_ExternalTrigConvCmd(ADC2, ENABLE);
-
-  /* Enable ADC1 */
-  ADC_Cmd(ADC1, ENABLE);
-  /* Enable Vrefint channel17 */
-  ADC_TempSensorVrefintCmd(ENABLE);
-
-  /* Enable ADC1 reset calibration register */   
-  ADC_ResetCalibration(ADC1);
-  /* Check the end of ADC1 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC1));
-
-  /* Start ADC1 calibration */
-  ADC_StartCalibration(ADC1);
-  /* Check the end of ADC1 calibration */
-  while(ADC_GetCalibrationStatus(ADC1));
-
-  /* Enable ADC2 */
-  ADC_Cmd(ADC2, ENABLE);
-
-  /* Enable ADC2 reset calibration register */   
-  ADC_ResetCalibration(ADC2);
-  /* Check the end of ADC2 reset calibration register */
-  while(ADC_GetResetCalibrationStatus(ADC2));
-
-  /* Start ADC2 calibration */
-  ADC_StartCalibration(ADC2);
-  /* Check the end of ADC2 calibration */
-  while(ADC_GetCalibrationStatus(ADC2));
-
-  /* Start ADC1 Software Conversion */ 
-  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-
-  /* Test on DMA1 channel1 transfer complete flag */
-  while(!DMA_GetFlagStatus(DMA1_FLAG_TC1));
-  /* Clear DMA1 channel1 transfer complete flag */
-  DMA_ClearFlag(DMA1_FLAG_TC1);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* ADCCLK = PCLK2/4 */
-  RCC_ADCCLKConfig(RCC_PCLK2_Div4);
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* Enable DMA1 clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-
-  /* Enable ADC1, ADC2 and GPIOC clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 |
-                         RCC_APB2Periph_GPIOC, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure PC.01, PC.02 and PC.04 (ADC Channel11, Channel12 and Channel14)
-    as analog input ----------------------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h
deleted file mode 100644
index 7239750..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/RegSimul_DualMode/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c
deleted file mode 100644
index ec6e131..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/RegSimul_DualMode/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_RegSimul_DualMode
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h
deleted file mode 100644
index 9e9b0b8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/RegSimul_DualMode/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt
deleted file mode 100644
index ae21baa..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
-  @page ADC_TIMTrigger_AutoInjection ADC TIM trigger and auto-injection example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    ADC/TIMTrigger_AutoInjection/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the ADC TIM trigger and auto-injection example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to convert ADC regular group channels continuously using
-TIM1 external trigger and injected group channels using the auto-injected feature.
-
-ADC1 is configured to convert on each TIM1 capture compare event ADC channel14.
-Each time an end of regular conversion occurs the DMA transfers the converted data 
-from ADC1 DR register to the ADC_RegularConvertedValueTab table. 
-Enabling the auto-injected feature, allows to convert automatically the injected 
-channel ADC channel11 after the end of the regular channel14. An ADC interrupt is 
-generated then by JEOC flag at the end of the injected channel conversion and in 
-the interrupt routine the result is stored in the ADC_InjectedConvertedValueTab table.
-The procedure is repeated 32 times then the TIM1 peripheral is disabled and thus, 
-no conversion will be done neither regular nor injected.
-TIM1 start conversion triggers can be visualized on oscilloscope on PA.08 and at the
-same time the toggle of pin PC.06 which indicates the automatic auto-injection conversion.
-
-The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other 
-devices.
-
-@par Directory contents 
-
-  - ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h     Library Configuration file
-  - ADC/TIMTrigger_AutoInjection/stm32f10x_it.c       Interrupt handlers
-  - ADC/TIMTrigger_AutoInjection/stm32f10x_it.h       Interrupt handlers header file
-  - ADC/TIMTrigger_AutoInjection/system_stm32f10x.c   STM32F10x system source file  
-  - ADC/TIMTrigger_AutoInjection/main.c               Main program
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line,
-    Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value 
-    line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL(High-Density 
-    Value line) STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity
-    line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device and development 
-    board.
-
-  - STM32100E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
-    - Connect PA.08 and PC.06 pins to an oscilloscope
-    
-  - STM32100B-EVAL Set-up
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
-      (potentiometer RV2) and ADC Channel11 mapped on pin PC.01
-    - Connect PA.08 and PC.06 pins to an oscilloscope
-
-  - STM3210C-EVAL Set-up
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
-    - Connect PA.08 and PC.06 pins to an oscilloscope
-    
-  - STM3210E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
-    - Connect PA.08 and PC.06 pins to an oscilloscope
-
-  - STM3210B-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
-    - Connect PA.08 and PC.06 pins to an oscilloscope        
-      
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.  
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
- 
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
deleted file mode 100644
index 9650010..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
deleted file mode 100644
index 9780049..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup ADC_TIMTrigger_AutoInjection
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint16_t ADC_InjectedConvertedValueTab[32];
-__IO uint32_t Index;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles ADC1 and ADC2 global interrupts requests.
-  * @param  None
-  * @retval None
-  */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void ADC1_IRQHandler(void)
-#else
-void ADC1_2_IRQHandler(void)
-#endif
-{
-  /* Set PC.06 pin */
-  GPIO_WriteBit(GPIOC, GPIO_Pin_6, Bit_SET);
-  /* Get injected channel11 converted value */
-  ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1);
-  /* Clear ADC1 JEOC pending interrupt bit */
-  ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC);
-  /* Reset PC.06 pin */
-  GPIO_WriteBit(GPIOC, GPIO_Pin_6, Bit_RESET);
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
deleted file mode 100644
index 90aa163..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
-void ADC1_IRQHandler(void);
-#else
-void ADC1_2_IRQHandler(void);
-#endif
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt
deleted file mode 100644
index fc4cf9b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
-  @page BKP_Backup_Data Backup Data example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    BKP/Backup_Data/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the Backup Data example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to store user data in the Backup data registers.
-As the Backup (BKP) domain still powered by VBAT when VDD is switched off, its
-contents are not lost if a battery is connected to VBAT pin.
-
-The program behaves as follows:
-
-1. After startup the program checks if the board has been powered up. If yes, 
-the values in the BKP data registers are checked:
-   - if a battery is connected to the VBAT pin, the values in the BKP data registers
-     are retained
-   - if no battery is connected to the VBAT pin, the values in the BKP data registers
-     are lost
-     
-2. After an external reset, the BKP data registers contents are not checked.
-
-Four LEDs are used to monitor the system state as follows:
-1. LD3 on / LD1 on: a Power On Reset occurred and the values in the BKP data
-   registers are correct
-   
-2. LD3 on / LD2 on: a Power On Reset occurred and the values in the BKP data
-   registers are not correct or they have not yet been programmed (if it is the
-   first time the program is executed)
-   
-3. LD3 off / LD1 off / LD2 off: no Power On Reset occurred
-
-4. LD4 on: program running
-
-@par Directory contents 
-
-  - BKP/Backup_Data/stm32f10x_conf.h     Library Configuration file
-  - BKP/Backup_Data/stm32f10x_it.c       Interrupt handlers
-  - BKP/Backup_Data/stm32f10x_it.h       Header for stm32f10x_it.c
-  - BKP/Backup_Data/system_stm32f10x.c   STM32F10x system source file  
-  - BKP/Backup_Data/main.c               Main program
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and 
-    STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored 
-    to any other supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use 3V battery on VBAT pin (set jumper JP9 in position 1-2)  
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins  
-    - Use 3V battery on VBAT pin (set jumper JP24 in position 1-2)  
-
-  - STM3210E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use 3V battery on VBAT pin (set jumper JP1 in position 1-2)  
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use 3V battery on VBAT pin (set jumper JP11 in position 1-2)  
-
-  - STM32100E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use 3V battery on VBAT pin (set jumper JP1 in position 1-2) 
-	
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
- - Power on/off the board and check that the BKP contents are not lost
-   
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h
deleted file mode 100644
index a1f8a0d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c
deleted file mode 100644
index c17e8dc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup BKP_Backup_Data
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h
deleted file mode 100644
index 7932911..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
deleted file mode 100644
index 781b64b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Backup_Data/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
deleted file mode 100644
index c6ba787..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Tamper/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup BKP_Tamper
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
-  #define BKP_DR_NUMBER              10   
-#else
-  #define BKP_DR_NUMBER              42
-#endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-#if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
-uint16_t BKPDataReg[BKP_DR_NUMBER] =
-  {
-    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
-    BKP_DR9, BKP_DR10
-  };
-#else
-uint16_t BKPDataReg[BKP_DR_NUMBER] =
-  {
-    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
-    BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
-    BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
-    BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
-    BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
-    BKP_DR41, BKP_DR42
-  };  
-#endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
-
-/* Private function prototypes -----------------------------------------------*/
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-void WriteToBackupReg(uint16_t FirstBackupData);
-uint32_t CheckBackupReg(uint16_t FirstBackupData);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* NVIC configuration */
-  NVIC_Configuration();
-    
-  /* Initialize Leds mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Enable PWR and BKP clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Enable write access to Backup domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Disable Tamper pin */
-  BKP_TamperPinCmd(DISABLE);
-  
-  /* Disable Tamper interrupt */
-  BKP_ITConfig(DISABLE);
-
-  /* Tamper pin active on low level */
-  BKP_TamperPinLevelConfig(BKP_TamperPinLevel_Low);
-
-  /* Clear Tamper pin Event(TE) pending flag */
-  BKP_ClearFlag();
-
-  /* Enable Tamper interrupt */
-  BKP_ITConfig(ENABLE);
-
-  /* Enable Tamper pin */
-  BKP_TamperPinCmd(ENABLE);
-   
-  /* Write data to Backup DRx registers */
-  WriteToBackupReg(0xA53C);
-  
-  /* Check if the written data are correct */
-  if(CheckBackupReg(0xA53C) == 0x00)
-  {
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  {
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-        
-  while (1)
-  {    
-  }
-}
-
-/**
-  * @brief  Configures NVIC and Vector Table base location.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable TAMPER IRQChannel */
-  NVIC_InitStructure.NVIC_IRQChannel = TAMPER_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Writes data Backup DRx registers.
-  * @param  FirstBackupData: data to be written to Backup data registers.
-  * @retval None
-  */
-void WriteToBackupReg(uint16_t FirstBackupData)
-{
-  uint32_t index = 0;
-
-  for (index = 0; index < BKP_DR_NUMBER; index++)
-  {
-    BKP_WriteBackupRegister(BKPDataReg[index], FirstBackupData + (index * 0x5A));
-  }  
-}
-
-/**
-  * @brief  Checks if the Backup DRx registers values are correct or not.
-  * @param  FirstBackupData: data to be compared with Backup data registers.
-  * @retval 
-  *         - 0: All Backup DRx registers values are correct
-  *         - Value different from 0: Number of the first Backup register
-  *           which value is not correct
-  */
-uint32_t CheckBackupReg(uint16_t FirstBackupData)
-{
-  uint32_t index = 0;
-
-  for (index = 0; index < BKP_DR_NUMBER; index++)
-  {
-    if (BKP_ReadBackupRegister(BKPDataReg[index]) != (FirstBackupData + (index * 0x5A)))
-    {
-      return (index + 1);
-    }
-  }
-
-  return 0;  
-}
-
-/**
-  * @brief  Checks if the Backup DRx registers are reset or not.
-  * @param  None
-  * @retval 
-  *          - 0: All Backup DRx registers are reset
-  *          - Value different from 0: Number of the first Backup register
-  *            not reset
-  */
-uint32_t IsBackupRegReset(void)
-{
-  uint32_t index = 0;
-
-  for (index = 0; index < BKP_DR_NUMBER; index++)
-  {
-    if (BKP_ReadBackupRegister(BKPDataReg[index]) != 0x0000)
-    {
-      return (index + 1);
-    }
-  }
-
-  return 0;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h
deleted file mode 100644
index e4015fe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Tamper/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-uint32_t IsBackupRegReset(void);
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt
deleted file mode 100644
index 49d3c67..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  @page BKP_Tamper BKP Tamper example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    BKP/Tamper/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the BKP Tamper example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to write/read data to/from Backup data registers and 
-demonstrates the Tamper detection feature.
-
-The associated firmware performs the following:
-
-1. It configures the ANTI_TAMP pin to be active low, and enables the Tamper interrupt.
-
-2. It writes the data to all Backup data registers, then check whether the data were
-correctly written. If yes, LED1 turns on, otherwise LED2 turns on.
-
-3. On applying a low level on the ANTI_TAMP pin (PC.13), the Backup data registers
-are reset and the Tamper interrupt is generated. The corresponding ISR then checks
-whether the Backup data registers are cleared. If yes, LED3 on, otherwise LED4
-turns on.
-
-
-@par Directory contents 
-
-  - BKP/Tamper/stm32f10x_conf.h    Library Configuration file
-  - BKP/Tamper/stm32f10x_it.h      Interrupt handlers header file
-  - BKP/Tamper/stm32f10x_it.c      Interrupt handlers
-  - BKP/Tamper/main.h              Main header file
-  - BKP/Tamper/main.c              Main program
-  - BKP/Tamper/system_stm32f10x.c  STM32F10x system source file
-
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    High-Density Value line, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins  
-    - Use the Tamper push-button connected to pin PC.13 (set jumper JP1 in position 2-3). 
-      PC13 is already connected to VDD on the eval board.
-    
-  - STM3210E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.   
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.
-	  
-  - STM32100E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.   
-         
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-   
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h
deleted file mode 100644
index 48e5a4f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Tamper/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c
deleted file mode 100644
index 9bb6e44..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    BKP/Tamper/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
deleted file mode 100644
index f38297f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/DualCAN/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-#include "stm3210c_eval_lcd.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_DualCAN
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CAN_BAUDRATE  1000      /* 1MBps   */
-/* #define CAN_BAUDRATE  500*/  /* 500kBps */
-/* #define CAN_BAUDRATE  250*/  /* 250kBps */
-/* #define CAN_BAUDRATE  125*/  /* 125kBps */
-/* #define CAN_BAUDRATE  100*/  /* 100kBps */ 
-/* #define CAN_BAUDRATE  50*/   /* 50kBps  */ 
-/* #define CAN_BAUDRATE  20*/   /* 20kBps  */ 
-/* #define CAN_BAUDRATE  10*/   /* 10kBps  */ 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CAN_InitTypeDef        CAN_InitStructure;
-CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-CanTxMsg TxMessage;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Config(void);
-void CAN_Config(void);
-void LED_Display(uint8_t Ledstatus);
-void Init_RxMes(CanRxMsg *RxMessage);
-void Delay(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-        
-  /* NVIC configuration */
-  NVIC_Config();
-
-  /* Configures LED 1..4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* LCD Initialization */
-  STM3210C_LCD_Init();
-  LCD_Clear(LCD_COLOR_WHITE);
-
-  /* Set the LCD Back Color */
-  LCD_SetBackColor(LCD_COLOR_RED);
-  /* Set the LCD Text Color */
-  LCD_SetTextColor(LCD_COLOR_GREEN);
-  
-  LCD_DisplayStringLine(LCD_LINE_0, "   STM3210C-EVAL    ");
-  LCD_DisplayStringLine(LCD_LINE_1, " STM32F10x Dual CAN ");
-  LCD_DisplayStringLine(LCD_LINE_2, "To start Press on:  ");
-  LCD_DisplayStringLine(LCD_LINE_3, "Key or Tamper Button");
-
-  /* Set the LCD Back Color */
-  LCD_SetBackColor(LCD_COLOR_BLUE);
-
-#if CAN_BAUDRATE == 1000 /* 1MBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 1MBps   ");
-#elif CAN_BAUDRATE == 500 /* 500KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 500kBps   ");
-#elif CAN_BAUDRATE == 250 /* 250KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 250kBps   ");
-#elif CAN_BAUDRATE == 125 /* 125KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 125kBps   ");
-#elif  CAN_BAUDRATE == 100 /* 100KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 100kBps   ");
-#elif  CAN_BAUDRATE == 50 /* 50KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 50kBps   ");
-#elif  CAN_BAUDRATE == 20 /* 20KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 20kBps   ");
-#elif  CAN_BAUDRATE == 10 /* 10KBps */
-  LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 10kBps   ");
-#endif
-  /* Set the LCD Text Color */
-  LCD_SetTextColor(LCD_COLOR_WHITE);   
-    
-  /* Configure BUTTON_KEY */
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); 
-  
-  /* Configure BUTTON_TAMPER */
-  STM_EVAL_PBInit(BUTTON_TAMPER, BUTTON_MODE_GPIO); 
-   
-  /* CANs configuration */
-  CAN_Config();
-
-  /* IT Configuration for CAN1 */  
-  CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
-
-  /* IT Configuration for CAN2 */  
-  CAN_ITConfig(CAN2, CAN_IT_FMP0, ENABLE);
-
-  /* turn off all leds*/
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
- 
-  /* Infinite loop */
-  while(1)
-  {
-    if(STM_EVAL_PBGetState(BUTTON_KEY)== RESET)
-    {
-      /* Turn On LED1 */
-      LED_Display(0x01);
-      TxMessage.Data[0] = 0x55;
-      CAN_Transmit(CAN1, &TxMessage);
-
-      /* Loop while KEY button is pressed */
-      while(STM_EVAL_PBGetState(BUTTON_KEY)== RESET)
-      {
-      }
-    }
-    if(STM_EVAL_PBGetState(BUTTON_TAMPER)== RESET)
-    {
-      /* Turn On LED2 */
-      LED_Display(0x2);
-      TxMessage.Data[0] = 0xAA;
-      CAN_Transmit(CAN2, &TxMessage);
-
-      /* Loop while TAMPER button is pressed */
-      while(STM_EVAL_PBGetState(BUTTON_TAMPER)== RESET)
-      {
-      }
-    }
-  }
-}
-
-/**
-  * @brief  Configures CAN1 and CAN2.
-  * @param  None
-  * @retval None
-  */
-void CAN_Config(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /* Configure CAN1 and CAN2 IOs **********************************************/
-  /* GPIOB, GPIOD and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOB, ENABLE);
-     
-  /* Configure CAN1 RX pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-   
-  /* Configure CAN2 RX pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* Configure CAN1 TX pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  /* Configure CAN2 TX pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* Remap CAN1 and CAN2 GPIOs */
-  GPIO_PinRemapConfig(GPIO_Remap2_CAN1 , ENABLE);
-  GPIO_PinRemapConfig(GPIO_Remap_CAN2, ENABLE);
-
-  /* Configure CAN1 and CAN2 **************************************************/  
-  /* CAN1 and CAN2 Periph clocks enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 | RCC_APB1Periph_CAN2, ENABLE);  
-  
-   /* CAN1 and CAN2 register init */
-  CAN_DeInit(CAN1);
-  CAN_DeInit(CAN2);
-
-  /* Struct init*/
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN1 and CAN2  cell init */
-  CAN_InitStructure.CAN_TTCM = DISABLE;
-  CAN_InitStructure.CAN_ABOM = DISABLE;
-  CAN_InitStructure.CAN_AWUM = DISABLE;
-  CAN_InitStructure.CAN_NART = DISABLE;
-  CAN_InitStructure.CAN_RFLM = DISABLE;
-  CAN_InitStructure.CAN_TXFP = ENABLE;
-  CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
-  CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;  
-  CAN_InitStructure.CAN_BS1 = CAN_BS1_3tq;
-  CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
- 
-#if CAN_BAUDRATE == 1000 /* 1MBps */
-  CAN_InitStructure.CAN_Prescaler =6;
-#elif CAN_BAUDRATE == 500 /* 500KBps */
-  CAN_InitStructure.CAN_Prescaler =12;
-#elif CAN_BAUDRATE == 250 /* 250KBps */
-  CAN_InitStructure.CAN_Prescaler =24;
-#elif CAN_BAUDRATE == 125 /* 125KBps */
-  CAN_InitStructure.CAN_Prescaler =48;
-#elif  CAN_BAUDRATE == 100 /* 100KBps */
-  CAN_InitStructure.CAN_Prescaler =60;
-#elif  CAN_BAUDRATE == 50 /* 50KBps */
-  CAN_InitStructure.CAN_Prescaler =120;
-#elif  CAN_BAUDRATE == 20 /* 20KBps */
-  CAN_InitStructure.CAN_Prescaler =300;
-#elif  CAN_BAUDRATE == 10 /* 10KBps */
-  CAN_InitStructure.CAN_Prescaler =600;
-#else
-   #error "Please select first the CAN Baudrate in Private defines in main.c "
-#endif  /* CAN_BAUDRATE == 1000 */
-
-  
-  /*Initializes the CAN1  and CAN2 */
-  CAN_Init(CAN1, &CAN_InitStructure);
-  CAN_Init(CAN2, &CAN_InitStructure);
-
-  /* CAN1 filter init */
-  CAN_FilterInitStructure.CAN_FilterNumber = 1;
-  CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh = 0x6420;
-  CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
-  CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-  
-  /* CAN2 filter init */
-  CAN_FilterInitStructure.CAN_FilterIdHigh =0x2460;
-  CAN_FilterInitStructure.CAN_FilterNumber = 15;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-  
-  /* Transmit */
-  TxMessage.StdId = 0x321;
-  TxMessage.ExtId = 0x01;
-  TxMessage.RTR = CAN_RTR_DATA;
-  TxMessage.IDE = CAN_ID_STD;
-  TxMessage.DLC = 1;  
-}
-
-/**
-  * @brief  Initializes a Rx Message.
-  * @param  CanRxMsg *RxMessage.
-  * @retval None
-  */
-void Init_RxMes(CanRxMsg *RxMessage)
-{
-  uint8_t i = 0;
-
-  RxMessage->StdId = 0;
-  RxMessage->ExtId = 0;
-  RxMessage->IDE = CAN_ID_STD;
-  RxMessage->DLC = 0;
-  RxMessage->FMI = 0;
-  for (i = 0; i < 8; i++)
-  {
-    RxMessage->Data[i] = 0;
-  }
-}
-
-/**
-  * @brief  Configures the NVIC for CAN.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Config(void)
-{
-  NVIC_InitTypeDef  NVIC_InitStructure;
-
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
- 
-  NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Turn ON/OFF the dedicate led.
-  * @param  Ledstatus: Communication status. 
-  * @retval None
-  */
-void LED_Display(uint8_t Ledstatus)
-{
-
-
-  switch(Ledstatus)
-  {
-    case(1): 
-      STM_EVAL_LEDOn(LED1);
-      LCD_DisplayStringLine(LCD_LINE_5, "CAN1 send Frame     ");
-      LCD_DisplayStringLine(LCD_LINE_6, "                    ");
-      break;
-   
-    case(2): 
-      STM_EVAL_LEDOn(LED2);
-      LCD_DisplayStringLine(LCD_LINE_5, "                    ");
-      LCD_DisplayStringLine(LCD_LINE_6, "CAN2 send Frame     ");
-      break;
-            
-    case(3): 
-      STM_EVAL_LEDOff(LED1);
-      STM_EVAL_LEDOn(LED3);
-      LCD_DisplayStringLine(LCD_LINE_5, "CAN1 receive Passed ");
-      break;
-     
-    case(4): 
-      STM_EVAL_LEDOff(LED2);
-      STM_EVAL_LEDOn(LED4);
-      LCD_DisplayStringLine(LCD_LINE_6, "CAN2 receive Passed ");
-      break;
-
-    case(5): 
-      STM_EVAL_LEDOff(LED1);
-      STM_EVAL_LEDOff(LED3);
-      LCD_DisplayStringLine(LCD_LINE_7, "Communication Failed ");
-      break;
-
-    case(6): 
-      STM_EVAL_LEDOff(LED2);
-      STM_EVAL_LEDOff(LED4);
-      LCD_DisplayStringLine(LCD_LINE_7, "Communication Failed ");
-      break;
-      
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  Delay
-  * @param  None
-  * @retval None
-  */
-void Delay(void)
-{
-  uint16_t nTime = 0x0000;
-
-  for(nTime = 0; nTime <0xFFF; nTime++)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt
deleted file mode 100644
index 3473f5d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
-  @page CAN_DualCAN Dual CAN example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CAN/DualCAN/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the Dual CAN example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the CAN1 and CAN2 peripherals to send and 
-receive CAN frames in normal mode. The sent frames are used to control Leds by 
-pressing KEY or TAMPER push buttons:
- - When KEY button is pressed, LED1 is turned ON and CAN1 sends a message to CAN2,
-   when CAN2 receives correctly this message LED4 is turned ON. 
- - When TAMPER button is pressed, LED2 is turned ON and CAN2 sends a message to CAN1,
-   when CAN1 receives correctly this message LED3 is turned ON. 
-
-The CAN1 and CAN2 are configured as follow:
-    - Bit Rate   = 1 Mbit/s  
-    - CAN Clock  = external clock (HSE)
-    - ID Filter  = All identifiers are allowed
-    - RTR = Data
-    - DLC = 1 byte
-    - Data: Led number that should be turned ON
-@note 
-  user can select one from the preconfigured CAN baud rates from the private 
-  defines in main.c by uncommenting the desired define: 
-
-@code
-  #define CAN_BAUDRATE  1000      /* CAN baudrate = 1MBps   */
-/* #define CAN_BAUDRATE  500*/  /* CAN baudrate = 500kBps */
-/* #define CAN_BAUDRATE  250*/  /* CAN baudrate = 250kBps */
-/* #define CAN_BAUDRATE  125*/  /* CAN baudrate = 125kBps */
-/* #define CAN_BAUDRATE  100*/  /* CAN baudrate = 100kBps */ 
-/* #define CAN_BAUDRATE  50*/   /* CAN baudrate = 50kBps  */ 
-/* #define CAN_BAUDRATE  20*/   /* CAN baudrate = 20kBps  */ 
-/* #define CAN_BAUDRATE  10*/   /* CAN baudrate = 10kBps  */
-@endcode
-
-@par Directory contents 
-
-  - CAN/DualCAN/stm32f10x_conf.h     Library Configuration file
-  - CAN/DualCAN/stm32f10x_it.c       Interrupt handlers
-  - CAN/DualCAN/stm32f10x_it.h       Interrupt handlers header file
-  - CAN/DualCAN/main.c               Main program
-  - CAN/DualCAN/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210C-EVAL (STM32F10x 
-    Connectivity line) evaluation board and can be easily tailored to any other 
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file  
-
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - Use Key Push Button connected to PB9
-    - Use Tamper Push Button connected to PC13    
-    - Connect a female/female CAN cable between the CAN connectors 
-      (CN4 and CN3 on STM3210C-EVAL boards)
-    - Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2  (CAN_L)
-    - Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5  ( GND )
-    - Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7  (CAN_H) 
-    - JP6 or JP5 must be fitted.
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h
deleted file mode 100644
index 0f04fd0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/DualCAN/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
deleted file mode 100644
index 322d003..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/DualCAN/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_DualCAN
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CanRxMsg RxMessage;
-extern void LED_Display(uint8_t Ledstatus);
- 
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief   This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-
-/**
-  * @brief  This function handles CAN1 RX0 Handler.
-  * @param  None
-  * @retval None
-  */
-void CAN1_RX0_IRQHandler(void)
-{
-  CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
-
-  if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD)&&(RxMessage.DLC == 1)&&(RxMessage.Data[0] == 0xAA))
-  {
-    /* Turn On LED3 */
-    LED_Display(0x03); /* OK */
-  }
-  else
-  {
-    /* Turn Off LED3 */
-    LED_Display(0x05); /* Error */
-  }
-}
-
-/**
-  * @brief  This function handles CAN2 RX0 Handler.
-  * @param  None
-  * @retval None
-  */
-
-void CAN2_RX0_IRQHandler(void)
-{
-  CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
-
-  if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD)&&(RxMessage.DLC == 1)&&(RxMessage.Data[0] == 0x55))
-  {
-    /* Turn On LED4 */
-    LED_Display(0x04); /* OK */
-  }
-  else
-  {
-    /* Turn Off LED4 */
-    LED_Display(0x06); /* Error */
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
deleted file mode 100644
index 20cb493..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/DualCAN/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void CAN1_RX0_IRQHandler(void);
-void CAN2_RX0_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c
deleted file mode 100644
index 6dea15f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/DualCAN/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
deleted file mode 100644
index 6651d04..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_LoopBack
-  * @{
-  */ 
-
-
-
-/* Private define ------------------------------------------------------------*/
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/   /* Please check that you device is 
-                                Connectivity line when using CAN2 */
-
-#ifdef  __CAN1_USED__
-  #define CANx CAN1
-#else /*__CAN2_USED__*/
-  #define CANx CAN2
-#endif  /* __CAN1_USED__ */
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t ret = 0; /* for return of the interrupt handling */
-volatile TestStatus TestRx;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-TestStatus CAN_Polling(void);
-TestStatus CAN_Interrupt(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-
-
-#ifdef  __CAN1_USED__
-  /* CANx Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  /* CAN1 & 2  Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-  
-  /* Configures LED 1..4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  
-  /* Turns selected LED Off */  
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
-  
-  /* CAN transmit at 125Kb/s and receive by polling in loopback mode */
-  TestRx = CAN_Polling();
-
-  if (TestRx == FAILED)
-  {
-    /* Turn on led LD3 */
-    STM_EVAL_LEDOn(LED3);
-  }
-  else
-  {
-    /* Turn on led LD1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-
-  /* CAN transmit at 500Kb/s and receive by interrupt in loopback mode */
-  TestRx = CAN_Interrupt();
-
-  if (TestRx == FAILED)
-  {
-    /* Turn on led LD4 */
-    STM_EVAL_LEDOn(LED4);
-  }
-  else
-  {
-    /* Turn on led LD2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the CAN, transmit and receive by polling
-  * @param  None
-  * @retval PASSED if the reception is well done, FAILED in other case
-  */
-TestStatus CAN_Polling(void)
-{
-  CAN_InitTypeDef        CAN_InitStructure;
-  CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-  CanTxMsg TxMessage;
-  CanRxMsg RxMessage;
-  uint32_t i = 0;
-  uint8_t TransmitMailbox = 0;
-
-  /* CAN register init */
-  CAN_DeInit(CANx);
-
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM=DISABLE;
-  CAN_InitStructure.CAN_ABOM=DISABLE;
-  CAN_InitStructure.CAN_AWUM=DISABLE;
-  CAN_InitStructure.CAN_NART=DISABLE;
-  CAN_InitStructure.CAN_RFLM=DISABLE;
-  CAN_InitStructure.CAN_TXFP=DISABLE;
-  CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
-  
-  /* Baudrate = 125kbps*/
-  CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
-  CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
-  CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
-  CAN_InitStructure.CAN_Prescaler=48;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber=0;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber=14;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;  
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment=0;
-
-
-  CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-
-  /* transmit */
-  TxMessage.StdId=0x11;
-  TxMessage.RTR=CAN_RTR_DATA;
-  TxMessage.IDE=CAN_ID_STD;
-  TxMessage.DLC=2;
-  TxMessage.Data[0]=0xCA;
-  TxMessage.Data[1]=0xFE;
-
-  TransmitMailbox=CAN_Transmit(CANx, &TxMessage);
-  i = 0;
-  while((CAN_TransmitStatus(CANx, TransmitMailbox) != CANTXOK) && (i != 0xFFFF))
-  {
-    i++;
-  }
-
-  i = 0;
-  while((CAN_MessagePending(CANx, CAN_FIFO0) < 1) && (i != 0xFFFF))
-  {
-    i++;
-  }
-
-  /* receive */
-  RxMessage.StdId=0x00;
-  RxMessage.IDE=CAN_ID_STD;
-  RxMessage.DLC=0;
-  RxMessage.Data[0]=0x00;
-  RxMessage.Data[1]=0x00;
-  CAN_Receive(CANx, CAN_FIFO0, &RxMessage);
-
-  if (RxMessage.StdId!=0x11)
-  {
-    return FAILED;  
-  }
-
-  if (RxMessage.IDE!=CAN_ID_STD)
-  {
-    return FAILED;
-  }
-
-  if (RxMessage.DLC!=2)
-  {
-    return FAILED;  
-  }
-
-  if ((RxMessage.Data[0]<<8|RxMessage.Data[1])!=0xCAFE)
-  {
-    return FAILED;
-  }
-  
-  return PASSED; /* Test Passed */
-}
-
-/**
-  * @brief  Configures the CAN, transmit and receive using interrupt.
-  * @param  None
-  * @retval PASSED if the reception is well done, FAILED in other case
-  */
-TestStatus CAN_Interrupt(void)
-{
-  CAN_InitTypeDef        CAN_InitStructure;
-  CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-  CanTxMsg TxMessage;
-  uint32_t i = 0;
-
-  /* CAN register init */
-  CAN_DeInit(CANx);
-
-
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM=DISABLE;
-  CAN_InitStructure.CAN_ABOM=DISABLE;
-  CAN_InitStructure.CAN_AWUM=DISABLE;
-  CAN_InitStructure.CAN_NART=DISABLE;
-  CAN_InitStructure.CAN_RFLM=DISABLE;
-  CAN_InitStructure.CAN_TXFP=DISABLE;
-  CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
-  CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
-  
-  /* Baudrate = 500 Kbps */
-  CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
-  CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
-  CAN_InitStructure.CAN_Prescaler=12;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber=1;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber=15;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
-  CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-
-  /* CAN FIFO0 message pending interrupt enable */ 
-  CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
-
-  /* transmit 1 message */
-  TxMessage.StdId=0;
-  TxMessage.ExtId=0x1234;
-  TxMessage.IDE=CAN_ID_EXT;
-  TxMessage.RTR=CAN_RTR_DATA;
-  TxMessage.DLC=2;
-  TxMessage.Data[0]=0xDE;
-  TxMessage.Data[1]=0xCA;
-  CAN_Transmit(CANx, &TxMessage);
-
-  /* initialize the value that will be returned */
-  ret = 0xFF;
-       
-  /* receive message with interrupt handling */
-  i=0;
-  while((ret == 0xFF) && (i < 0xFFF))
-  {
-    i++;
-  }
-  
-  if (i == 0xFFF)
-  {
-    ret=0;  
-  }
-
-  /* disable interrupt handling */
-  CAN_ITConfig(CANx, CAN_IT_FMP0, DISABLE);
-
-  return (TestStatus)ret;
-}
-
-/**
-  * @brief  Configures the NVIC and Vector Table base address.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable CANx RX0 interrupt IRQ channel */
-#ifndef STM32F10X_CL
-
-#ifdef  __CAN1_USED__
-  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  /* CAN2 is not implemented in the device */
-   #error "CAN2 is implemented only in Connectivity line devices"
-  
-#endif /*__CAN1_USED__*/
-#else
-#ifdef  __CAN1_USED__ 
-  NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
-#endif /*__CAN1_USED__*/
-
-#endif /* STM32F10X_CL*/
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt
deleted file mode 100644
index e662598..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
-  @page CAN_LoopBack CAN LoopBack example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CAN/LoopBack/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the CAN LoopBack example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to set a communication with the CAN
-in loopback mode.
-
-The CAN cell first performs a transmission and a reception of a standard data
-frame by polling at 125 Kbps. The received frame is checked and some LEDs light
-up to indicate whether the communication was successful. Then, an extended data
-frame is transmitted at 500 Kbps. Reception is done in the interrupt handler
-when the message becomes pending in the FIFO. Finally, the LEDs indicate if both
-transmission and reception have been successful.
-
-User can select CAN1 or CAN2 cell using the private defines in main.c :
-
-@code
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/   
-@endcode
-
-@note When using CAN2, please check that your device is Connectivity line.
-
-@par Directory contents 
-
-  - CAN/LoopBack/stm32f10x_conf.h     Library Configuration file
-  - CAN/LoopBack/stm32f10x_it.c       Interrupt handlers
-  - CAN/LoopBack/stm32f10x_it.h       Interrupt handlers header file
-  - CAN/LoopBack/main.c               Main program
-  - CAN/LoopBack/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density and Low-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line),
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
-    evaluation boards and can be easily tailored to any other supported device and
-    development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file   
-
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-      
-  - STM3210E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
- 
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h
deleted file mode 100644
index ecf7661..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
deleted file mode 100644
index 28dec5c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_LoopBack
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint32_t ret;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief   This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles CAN1 Handler.
-  * @param  None
-  * @retval None
-  */
-#ifndef STM32F10X_CL
-void USB_LP_CAN1_RX0_IRQHandler(void)
-#else
-void CAN1_RX0_IRQHandler(void)
-#endif
-{
-  CanRxMsg RxMessage;
-
-  RxMessage.StdId=0x00;
-  RxMessage.ExtId=0x00;
-  RxMessage.IDE=0;
-  RxMessage.DLC=0;
-  RxMessage.FMI=0;
-  RxMessage.Data[0]=0x00;
-  RxMessage.Data[1]=0x00;
-
-  CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
-
-  if((RxMessage.ExtId==0x1234) && (RxMessage.IDE==CAN_ID_EXT)
-     && (RxMessage.DLC==2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8)==0xDECA))
-  {
-    ret = 1; 
-  }
-  else
-  {
-    ret = 0; 
-  }
-}
-
-/**
-  * @brief  This function handles CAN2 Handler.
-  * @param  None
-  * @retval None
-  */
-#ifdef STM32F10X_CL
-void CAN2_RX0_IRQHandler(void)
-
-{
-  CanRxMsg RxMessage;
-
-  RxMessage.StdId=0x00;
-  RxMessage.ExtId=0x00;
-  RxMessage.IDE=0;
-  RxMessage.DLC=0;
-  RxMessage.FMI=0;
-  RxMessage.Data[0]=0x00;
-  RxMessage.Data[1]=0x00;
-
-  CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
-
-  if((RxMessage.ExtId==0x1234) && (RxMessage.IDE==CAN_ID_EXT)
-     && (RxMessage.DLC==2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8)==0xDECA))
-  {
-    ret = 1; 
-  }
-  else
-  {
-    ret = 0; 
-  }
-}
-#endif
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h
deleted file mode 100644
index c0dce57..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#ifdef STM32F10X_CL
-void CAN1_RX0_IRQHandler(void);
-#else
-void USB_LP_CAN1_RX0_IRQHandler(void);
-#endif
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c
deleted file mode 100644
index 4b8b7a9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
deleted file mode 100644
index fca0acd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_Networking
-  * @{
-  */ 
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/
-
-#ifdef  __CAN1_USED__
-  #define CANx                       CAN1
-  #define GPIO_CAN                   GPIO_CAN1
-  #define GPIO_Remapping_CAN         GPIO_Remapping_CAN1
-  #define GPIO_CAN                   GPIO_CAN1
-  #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN1_RX
-  #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN1_TX
-#else /*__CAN2_USED__*/
-  #define CANx                       CAN2
-  #define GPIO_CAN                   GPIO_CAN2
-  #define GPIO_Remapping_CAN             GPIO_Remap_CAN2
-  #define GPIO_CAN                   GPIO_CAN2
-  #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN2_RX
-  #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN2_TX
-#endif  /* __CAN1_USED__ */
-
-#define KEY_PRESSED     0x01
-#define KEY_NOT_PRESSED 0x00
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CAN_InitTypeDef        CAN_InitStructure;
-CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-CanTxMsg TxMessage;
-uint8_t KeyNumber = 0x0;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Config(void);
-void CAN_Config(void);
-void LED_Display(uint8_t Ledstatus);
-void Init_RxMes(CanRxMsg *RxMessage);
-void Delay(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* NVIC configuration */
-  NVIC_Config();
-
-  /* Configures LED 1..4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  
-  /* Configure Push button key */
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); 
-   
-  /* CAN configuration */
-  CAN_Config();
-  
-  CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
-
-  /* turn off all leds*/
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
- 
-  /* Infinite loop */
-  while(1)
-  {
-    while(STM_EVAL_PBGetState(BUTTON_KEY) == KEY_PRESSED)
-    {
-      if(KeyNumber == 0x4) 
-      {
-        KeyNumber = 0x00;
-      }
-      else
-      {
-        LED_Display(++KeyNumber);
-        TxMessage.Data[0] = KeyNumber;
-        CAN_Transmit(CANx, &TxMessage);
-        Delay();
-        
-        while(STM_EVAL_PBGetState(BUTTON_KEY) != KEY_NOT_PRESSED)
-        {
-        }
-      }
-    }
-  }
-}
-
-/**
-  * @brief  Configures the CAN.
-  * @param  None
-  * @retval None
-  */
-void CAN_Config(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* GPIO clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-#ifdef  __CAN1_USED__
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-  /* Configure CAN pin: RX */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_RX;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
-  
-  /* Configure CAN pin: TX */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_TX;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
-  
-  GPIO_PinRemapConfig(GPIO_Remapping_CAN , ENABLE);
-  
-  /* CANx Periph clock enable */
-#ifdef  __CAN1_USED__
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-  
-  
-  /* CAN register init */
-  CAN_DeInit(CANx);
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM = DISABLE;
-  CAN_InitStructure.CAN_ABOM = DISABLE;
-  CAN_InitStructure.CAN_AWUM = DISABLE;
-  CAN_InitStructure.CAN_NART = DISABLE;
-  CAN_InitStructure.CAN_RFLM = DISABLE;
-  CAN_InitStructure.CAN_TXFP = DISABLE;
-  CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
-  
-  /* CAN Baudrate = 1MBps*/
-  CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
-  CAN_InitStructure.CAN_BS1 = CAN_BS1_3tq;
-  CAN_InitStructure.CAN_BS2 = CAN_BS2_5tq;
-  CAN_InitStructure.CAN_Prescaler = 4;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber = 0;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber = 14;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
-  CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-  
-  /* Transmit */
-  TxMessage.StdId = 0x321;
-  TxMessage.ExtId = 0x01;
-  TxMessage.RTR = CAN_RTR_DATA;
-  TxMessage.IDE = CAN_ID_STD;
-  TxMessage.DLC = 1;
-}
-
-/**
-  * @brief  Configures the NVIC for CAN.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Config(void)
-{
-  NVIC_InitTypeDef  NVIC_InitStructure;
-
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-  
-#ifndef STM32F10X_CL
-#ifdef  __CAN1_USED__
-  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  /* CAN2 is not implemented in the device */
-   #error "CAN2 is implemented only in Connectivity line devices"
-#endif /*__CAN1_USED__*/
-#else
-#ifdef  __CAN1_USED__ 
-  NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
-#endif /*__CAN1_USED__*/
-
-#endif /* STM32F10X_CL*/
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Initializes a Rx Message.
-  * @param  CanRxMsg *RxMessage
-  * @retval None
-  */
-void Init_RxMes(CanRxMsg *RxMessage)
-{
-  uint8_t i = 0;
-
-  RxMessage->StdId = 0x00;
-  RxMessage->ExtId = 0x00;
-  RxMessage->IDE = CAN_ID_STD;
-  RxMessage->DLC = 0;
-  RxMessage->FMI = 0;
-  for (i = 0;i < 8;i++)
-  {
-    RxMessage->Data[i] = 0x00;
-  }
-}
-
-/**
-  * @brief  Turn ON/OFF the dedicate led
-  * @param  Ledstatus: Led number from 0 to 3.
-  * @retval None
-  */
-void LED_Display(uint8_t Ledstatus)
-{
-  /* Turn off all leds */
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
-  
-  switch(Ledstatus)
-  {
-    case(1): 
-      STM_EVAL_LEDOn(LED1);
-      break;
-   
-    case(2): 
-      STM_EVAL_LEDOn(LED2);
-      break;
- 
-    case(3): 
-      STM_EVAL_LEDOn(LED3);
-      break;
-
-    case(4): 
-      STM_EVAL_LEDOn(LED4);
-      break;
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  Delay
-  * @param  None
-  * @retval None
-  */
-void Delay(void)
-{
-  uint16_t nTime = 0x0000;
-
-  for(nTime = 0; nTime <0xFFF; nTime++)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/platform_config.h
deleted file mode 100644
index 68680e2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/platform_config.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- #define USE_STM3210C_EVAL
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#ifdef USE_STM3210B_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
-  #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
-  #define GPIO_CAN1                   GPIOD  
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
-
-#elif defined USE_STM3210E_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOB
-  #define GPIO_Remapping_CAN1         GPIO_Remap1_CAN1
-  #define GPIO_CAN1                   GPIOB
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_8
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_9
-
-#elif defined USE_STM3210C_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
-  #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
-  #define GPIO_CAN1                   GPIOD  
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
-  
-  #define RCC_APB2Periph_GPIO_CAN2    RCC_APB2Periph_GPIOB
-  #define GPIO_Remapping_CAN2         GPIO_Remap_CAN2
-  #define GPIO_CAN2                   GPIOB  
-  #define GPIO_Pin_CAN2_RX            GPIO_Pin_5
-  #define GPIO_Pin_CAN2_TX            GPIO_Pin_6
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt
deleted file mode 100644
index 1533e0f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt
+++ /dev/null
@@ -1,152 +0,0 @@
-/**
-  @page CAN_Networking CAN Networking example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CAN/Networking/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the CAN Networking example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the CAN peripheral to send and receive 
-CAN frames in normal mode. The sent frames are used to control Leds by pressing  
-key push button.
-	
-The CAN serial communication link is a bus to which a number of units may be
-connected. This number has no theoretical limit. Practically the total number
-of units will be limited by delay times and/or electrical loads on the bus line.
-
-This program behaves as follows:
-  - After reset LED1 is ON
-  - By Pressing on KEY Button : LED2 turns ON and all other Leds are OFF, on the N
-    eval boards connected to the bus. 
-  - Press on KEY Button again to send CAN Frame to command LEDn+1 ON, all other Leds 
-    are OFF on the N eval boards.
-    
-@note This example is tested with a bus of 3 units. The same program example is 
-      loaded in all units to send and receive frames.
-@note Any unit in the CAN bus may play the role of sender (by pressing KEY button)
-      or receiver.
-	
-	The CAN is configured as follow:
-    - Bit Rate   = 1 Mbit/s  
-    - CAN Clock  = external clock (HSE)
-		- ID Filter  = All identifiers are allowed
-		- RTR = Data
-		- DLC = 1 byte
-		- Data: Led number that should be turned ON
-
-
-User can select CAN1 or CAN2 cell using the private defines in main.c :
-
-@code
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/
-@endcode
-   
-@note When using CAN2, please check that you device is Connectivity line.
-
-
-@par Directory contents 
-
-  - CAN/Networking/platform_config.h    Hardware configuration header file
-  - CAN/Networking/stm32f10x_conf.h     Library Configuration file
-  - CAN/Networking/stm32f10x_it.c       Interrupt handlers
-  - CAN/Networking/stm32f10x_it.h       Interrupt handlers header file
-  - CAN/Networking/main.c               Main program
-  - CAN/Networking/system_stm32f10x.c   STM32F10x system source file
-  
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density and Low-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line),
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
-    evaluation boards and can be easily tailored to any other supported device and
-    development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in CAN/Networking/platform_config.h or stm32_eval.h file  
-
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - Use Key Push Button connected to PB9
-    - Connect a female/female CAN cable between at least 2 EVAL CAN connectors 
-      (on STM3210E-EVAL (CN2)/ STM3210C-EVAL (CN3 or CN4) boards)
-       - Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2  (CAN_L)
-		   - Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5  ( GND )
-		   - Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7  (CAN_H) 
-		  @note JP6 or JP5 must be fitted.
-       
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LD2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-    - Use Key Push Button connected to PG8
-    - Connect a female/female CAN cable between at least 2 EVAL CAN connectors 
-      (on STM3210B-EVAL (CN2)/ STM3210E-EVAL (CN4) boards)
-       - Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2  (CAN_L)
-		   - Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5  ( GND )
-		   - Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7  (CAN_H) 
-		  @note JP6 must be fitted.
-		  
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-    - Use Key Push Button connected to PB9      
-    - Connect a female/female CAN cable between at least 2 EVAL CAN connectors 
-      (on STM3210B-EVAL (CN2)/ STM3210E-EVAL (CN4) boards) 
-      - Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2  (CAN_L)
-		  - Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5  ( GND )
-		  - Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7  (CAN_H) 
-		  @note JP3 must be fitted.
-		  
-@note Any unit in the CAN bus may play the role of sender (by pressing on the 
-      key) or receiver.
-      
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
- - In the first time the all leds are OFF.
- - By Pressing on Key Button : LED1 turn ON and all other Leds are OFF, on the N
-   eval-boards connected to the bus. 
- - Press on Key Button again to send CAN Frame to command LEDn+1 ON, all other Leds 
-   are OFF on the N eval-boards.
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h
deleted file mode 100644
index 0afac1b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
deleted file mode 100644
index 3008991..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_Networking
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CanRxMsg RxMessage;
-extern uint8_t KeyNumber;
-extern void LED_Display(uint8_t Ledstatus);
- 
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles CAN1 Handler.
-  * @param  None
-  * @retval None
-  */
-#ifndef STM32F10X_CL
-void USB_LP_CAN1_RX0_IRQHandler(void)
-#else
-void CAN1_RX0_IRQHandler(void)
-#endif
-{
-  CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
-  if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1))
-  {
-    LED_Display(RxMessage.Data[0]);
-    KeyNumber = RxMessage.Data[0];
-  }
-}
-
-/**
-  * @brief  This function handles CAN2 Handler.
-  * @param  None
-  * @retval None
-  */
-#ifdef STM32F10X_CL
-void CAN2_RX0_IRQHandler(void)
-{
-  CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
-  if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1))
-  {
-    LED_Display(RxMessage.Data[0]);
-    KeyNumber = RxMessage.Data[0];
-  }
-}
-#endif
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h
deleted file mode 100644
index a897363..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#ifndef STM32F10X_CL
-void USB_LP_CAN1_RX0_IRQHandler(void);
-#else
-void CAN1_RX0_IRQHandler(void);
-#endif
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c
deleted file mode 100644
index d495771..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
deleted file mode 100644
index bc2b6ee..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CEC_DataExchangeInterrupt
-  * @{
-  */  
-
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CEC_InitTypeDef CEC_InitStructure;
-
-uint8_t ByteNumber = 10;
-volatile TestStatus TransferStatus = FAILED;
-extern uint8_t TransmitBuffer[10];
-extern uint8_t ReceiveBuffer[10];
-extern __IO uint8_t ReceivedFrame;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void NVIC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-  
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* RCC configuration */
-  RCC_Configuration();
-
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  /* GPIO configuration */
-  GPIO_Configuration();
-
-  /* Configure the CEC peripheral */
-  CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
-  CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
-  CEC_Init(&CEC_InitStructure);
-
-  /* Set Prescaler value for APB1 clock PCLK1 = 24MHz */ 
-  CEC_SetPrescaler(0x4AF);
-
-  /* Set the CEC initiator address */
-  CEC_OwnAddressConfig(MY_DEVICE_ADDRESS);
-  
-  /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
-  CEC_ITConfig(ENABLE);
-
-  /* Enable CEC */
-  CEC_Cmd(ENABLE);
-
-  /* If a frame has been received */
-  while(ReceivedFrame == 0)
-  {
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus = Buffercmp(TransmitBuffer, ReceiveBuffer, ByteNumber);
-  /* TransferStatus = PASSED, if the data transmitted from CEC Device1 and  
-     received by CEC Device2 are the same */
-  /* TransferStatus = FAILED, if the data transmitted from CEC Device1 and 
-     received by CEC Device2 are different */
- 
-  if (TransferStatus == PASSED)
-  { 
-    /* OK */
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  { 
-    /* KO */
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-  while(1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* Enable CEC clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
-
-  /* Initialize LEDs and Key Button available on STM32F100B-EVAL board ***/
-  /* Configure LED1, LED2, LED3 and LED4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Configure the Key Push button and its associated EXTI Line */
-  STM_EVAL_PBInit(Button_KEY, Mode_EXTI);
-}
-
-/**
-  * @brief  Configures the different NVIC interrupts.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure two bits for preemption priority */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-
-  /* Enable the CEC global Interrupt (with higher priority) */
-  NVIC_InitStructure.NVIC_IRQChannel = CEC_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIOB  clocks */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
- 
-  /* Configure GPIOB Pin 8 (CEC line) as Output open drain */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt
deleted file mode 100644
index 6832fc5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  @page CEC_DataExchangeInterrupt CEC Data Exchange using Interrupt example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CEC/DataExchangeInterrupt/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the CEC Data Exchange using Interrupt example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Description 
-
-This example provides a basic communication between two HDMI-CEC devices using 
-interrupts. 
-The first and second CEC device send TransmitBuffer to the CEC other device. 
-The data received by the first and second CEC device  are stored respectively in 
-ReceiveBuffer. The data transfer is managed in CEC_IRQHandler in 
-stm32f10x_it.c file.
-
-The example illustrates the use of the CEC communication between two devices 
-(2 x STM32100B-EVAL boards).
-Each device can send a frame to the other device by pressing the user key 
-button on the EVAL board. 
-
-- Edit CEC/stm32f10x_conf.h to select the the corresponding device (CEC_DEVICE1,
-CEC_DEVICE2).
- 
-@par Directory contents 
-
-  - CEC/DataExchangeInterrupt/stm32f10x_conf.h    Library Configuration file
-  - CEC/DataExchangeInterrupt/stm32f10x_it.h      Interrupt handlers header file
-  - CEC/DataExchangeInterrupt/stm32f10x_it.c      Interrupt handlers
-  - CEC/DataExchangeInterrupt/main.c              Main program
-  - CEC/DataExchangeInterrupt/system_stm32f10x.c  STM32F10x system source file
-           
-@par Hardware and Software environment
-
-  - This example runs on STM32F10x High-Density Value line, Medium-Density Value 
-    line and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL 
-    (STM32F10x High-Density Value line), STM32100B-EVAL 
-    (STM32F10x Medium-Density Value line) evaluation boards and can be easily 
-    tailored to any other supported device and development board.
-    
-  - Connect the boards by using one of the two following alternatives:
-  - A HDMI Cables between all boards HDMI-CEC connectors (CN15 or CN16) on 
-    STM32100B-EVAL or between connectors (CN3 or CN4) on STM32100E-EVAL board. 
-  - Use a simple wire between all devices CEC Lines (PB.08), in this case don't 
-    forget to connect all boards grounds together.
-   
-@note
- - You can also use more than two CEC devices as much as you want by changing 
-   only the Device address and selecting the corresponding followers.
- - You can use also the STM3210B-EVAL with the UM0685 associated firmware as a
-   CEC device. This configuration is available only when use a simple wire connected
-   between STM3210B-EVAL PA.00 and STM32100B-EVAL PB.08 or STM32100E-EVAL PB.08 
-   pins. Don't forget to add a 27KOhm pull-up resistor on the STM3210B-EVAL PA.00 
-   and to to connect all boards grounds together.
-
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Load the project image of First_Device (choose CEC_DEVICE1 when compiling) to 
-   the first board.
- - Load the project image of Second_Device (choose CEC_DEVICE2 when compiling) to 
-   the second board.
- - Run the example      
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
deleted file mode 100644
index 2612de7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-#if !defined (CEC_DEVICE1) && !defined (CEC_DEVICE2)
-  #define CEC_DEVICE1  1
-  /* #define CEC_DEVICE2  2 */
-#endif
-
-#ifdef CEC_DEVICE1
- #define MY_DEVICE_ADDRESS  0x01 /* My device address: is my initiator address
-                                    in case of transmit and the follower address
-                                    in case of receive */ 
- #define FOLLOWER           0x02                                
-#elif defined  CEC_DEVICE2
- #define MY_DEVICE_ADDRESS  0x02 /* My device address: is my initiator address
-                                    in case of transmit and the follower address
-                                    in case of receive */
- #define FOLLOWER           0x01                                                                           
-#endif                                 
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
deleted file mode 100644
index 07e58f3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CEC_DataExchangeInterrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Receive buffer */
-uint8_t ReceiveBuffer[10];
-/* Transmit buffer */
-uint8_t TransmitBuffer[10] = {0xDF, 0x12, 0xD3, 0x56, 0x97, 
-                              0xA1, 0xEC, 0x7B, 0x4F, 0x22};
-__IO uint8_t ReceivedFrame = 0;
-uint8_t send_inc = 0, rcv_inc = 0;
-uint8_t HeaderBlockValueToSend = 0;
-uint8_t InitiatorAddress = 0;
-uint8_t TransErrorCode = 0;
-uint8_t RecepErrorCode = 0;
-extern uint8_t ByteNumber;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief   This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles EXTI Lines 9 to 5 interrupts requests.
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_IRQHandler(void)
-{
-  /* Generate rising edge on Key button to detect when we push key button to initiate 
-     transmission */
-  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
-  {
-    /* Turn on LED3 */
-    STM_EVAL_LEDOn(LED3);
-
-    /* Build the Header block to send */
-    HeaderBlockValueToSend = (((MY_DEVICE_ADDRESS & 0xF) << 4) | (FOLLOWER & 0xF));
-
-    /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
-    CEC_SendDataByte(HeaderBlockValueToSend);
-
-    /* Initiate Message Transmission */
-    CEC_StartOfMessage();
-
-    /* Clear Key Button EXTI line pending bit */
-    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
-  }
-}
-
-/**
-  * @brief  This function handles CEC global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void CEC_IRQHandler(void)
-{
-  /* Turn on LED4 */
-  STM_EVAL_LEDOn(LED4);
-/********************** Reception *********************************************/
-  /* Check if a reception error occurred */
-  if (CEC_GetFlagStatus(CEC_FLAG_RERR))
-  {
-    /* Set receive status bit (Error) */
-    RecepErrorCode = CEC->ESR;
-    CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
-  }
-  else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
-  {
-    /* Check if the byte received is the last one of the message */
-    if (CEC_GetFlagStatus(CEC_FLAG_REOM))
-    {
-      ReceiveBuffer[rcv_inc] = CEC_ReceiveDataByte();
-      rcv_inc++;
-      ReceivedFrame = 1;
-    }
-    /* Check if the byte received is a Header */
-    else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
-    {
- 
-      InitiatorAddress = ((CEC_ReceiveDataByte() >> 4) & 0x0F);
-      rcv_inc = 0;
-    }
-    /* Receive each byte except header in the reception buffer */
-    else 
-    {
-      ReceiveBuffer[rcv_inc] = CEC_ReceiveDataByte();
-      rcv_inc++;
-    }
-    /* Clear all reception flags */
-    CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
-  }
-
-/********************** Transmission ******************************************/
-  /* Check if a transmission error occurred */
-  if (CEC_GetFlagStatus(CEC_FLAG_TERR))
-  {
-    TransErrorCode = CEC->ESR;
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-   
-  }
-  /* Check if end of message bit is set in the data to be transmitted */
-  else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
-  {
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-  /* Check if data byte has been sent */
-  else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
-  {
-    /* Set EOM bit if the byte to be transmitted is the last one of the Transmit Buffer */
-    if (send_inc == (ByteNumber - 1))
-    {
-      CEC_SendDataByte(TransmitBuffer[send_inc]);
-      send_inc++;
-      CEC_ClearFlag(CEC_FLAG_TBTRF);
-      CEC_EndOfMessageCmd(ENABLE);
-    }
-    else
-    {
-      /* Put the byte in the TX Buffer */
-      CEC_SendDataByte(TransmitBuffer[send_inc]);
-      send_inc++;
-      CEC_ClearFlag(CEC_FLAG_TBTRF);
-    }
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
deleted file mode 100644
index 02e3af3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI9_5_IRQHandler(void);
-void CEC_IRQHandler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c
deleted file mode 100644
index 2067bfb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
deleted file mode 100644
index 0646e17..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CRC_Calculation
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BUFFER_SIZE    114
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static const uint32_t DataBuffer[BUFFER_SIZE] =
-  {
-    0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c,
-    0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318,
-    0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485,
-    0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7,
-    0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886,
-    0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b,
-    0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58,
-    0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec,
-    0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f,
-    0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d,
-    0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da,
-    0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea,
-    0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424,
-    0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0,
-    0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865,
-    0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb,
-    0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa,
-    0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e,
-    0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0
-  };
-
-__IO uint32_t CRCValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Enable CRC clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
-
-  /* Compute the CRC of "DataBuffer" */
-  CRCValue = CRC_CalcBlockCRC((uint32_t *)DataBuffer, BUFFER_SIZE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt
deleted file mode 100644
index ff4a85b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  @page CRC_Calculation CRC Calculation example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CRC/CRC_Calculation/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the CRC Calculation example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to use CRC (cyclic redundancy check) calculation unit to 
-get a CRC code of a given buffer of data word(32-bit), based on a fixed generator
-polynomial(0x4C11DB7).
-
-
-@par Directory contents 
-
-  - CRC/CRC_Calculation/stm32f10x_conf.h    Library Configuration file
-  - CRC/CRC_Calculation/stm32f10x_it.c      Interrupt handlers
-  - CRC/CRC_Calculation/stm32f10x_it.h      Header for stm32f10x_it.c
-  - CRC/CRC_Calculation/main.c              Main program
-  - CRC/CRC_Calculation/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    High-Density Value line, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and 
-    STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored 
-    to any other supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h
deleted file mode 100644
index a54a62f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
deleted file mode 100644
index cd3a452..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CRC_Calculation
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h
deleted file mode 100644
index be90925..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c
deleted file mode 100644
index 6b66ab0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
deleted file mode 100644
index 3074221..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/BitBand/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_BitBand
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define RAM_BASE       0x20000000
-#define RAM_BB_BASE    0x22000000
- 
-/* Private macro -------------------------------------------------------------*/
-#define  Var_ResetBit_BB(VarAddr, BitNumber)    \
-          (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
-   
-#define Var_SetBit_BB(VarAddr, BitNumber)       \
-          (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)
-
-#define Var_GetBit_BB(VarAddr, BitNumber)       \
-          (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
-   
-/* Private variables ---------------------------------------------------------*/
-
-__IO uint32_t Var, VarAddr = 0, VarBitValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-         
-  Var = 0x00005AA5;
-
-/* A mapping formula shows how to reference each word in the alias region to a 
-   corresponding bit in the bit-band region. The mapping formula is:
-   bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number + 4)
-
-where:
-   - bit_word_addr: is the address of the word in the alias memory region that 
-                    maps to the targeted bit.
-   - bit_band_base is the starting address of the alias region
-   - byte_offset is the number of the byte in the bit-band region that contains 
-     the targeted bit
-   - bit_number is the bit position (0-7) of the targeted bit */
-
-/* Get the variable address --------------------------------------------------*/ 
-  VarAddr = (uint32_t)&Var; 
-
-/* Modify variable bit using bit-band access ---------------------------------*/
-  /* Modify Var variable bit 0 -----------------------------------------------*/
-  Var_ResetBit_BB(VarAddr, 0);  /* Var = 0x00005AA4 */
-  Var_SetBit_BB(VarAddr, 0);    /* Var = 0x00005AA5 */
-  
-  /* Modify Var variable bit 11 ----------------------------------------------*/
-  Var_ResetBit_BB(VarAddr, 11);             /* Var = 0x000052A5 */
-  /* Get Var variable bit 11 value */
-  VarBitValue = Var_GetBit_BB(VarAddr, 11); /* VarBitValue = 0x00000000 */
-  
-  Var_SetBit_BB(VarAddr, 11);               /* Var = 0x00005AA5 */
-  /* Get Var variable bit 11 value */
-  VarBitValue = Var_GetBit_BB(VarAddr, 11);    /* VarBitValue = 0x00000001 */
-  
-  /* Modify Var variable bit 31 ----------------------------------------------*/
-  Var_SetBit_BB(VarAddr, 31);               /* Var = 0x80005AA5 */
-  /* Get Var variable bit 31 value */
-  VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000001 */
-    
-  Var_ResetBit_BB(VarAddr, 31);             /* Var = 0x00005AA5 */
-  /* Get Var variable bit 31 value */
-  VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000000 */
-        
-  while (1)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/readme.txt
deleted file mode 100644
index 560b636..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/readme.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
-  @page CortexM3_BitBand CortexM3 BitBand example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CortexM3/BitBand/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the CortexM3 BitBand example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to use CortexM3 Bit-Band access to perform atomic 
-read-modify-write and read operations on a variable in SRAM.
-
-@par Directory contents 
-
-  - CortexM3/BitBand/stm32f10x_conf.h    Library Configuration file
-  - CortexM3/BitBand/stm32f10x_it.c      Interrupt handlers
-  - CortexM3/BitBand/stm32f10x_it.h      Header for stm32f10x_it.c
-  - CortexM3/BitBand/main.c              Main program
-  - CortexM3/BitBand/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h
deleted file mode 100644
index edeeb40..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/BitBand/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c
deleted file mode 100644
index 31da44f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/BitBand/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_BitBand
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h
deleted file mode 100644
index cd40698..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/BitBand/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c
deleted file mode 100644
index 6ebd060..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/BitBand/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld
deleted file mode 100644
index edc22c0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
-Default linker script for STM32F10xx_1024K_96K
-Copyright RAISONANCE S.A.S. 2008
-*/
-
-/* include the common STM32F10xx  sub-script */
-
-/* Common part of the linker scripts for STM32F devices*/
-
-
-/* default stack sizes. 
-
-These are used by the startup in order to allocate stacks for the different modes.
-*/
-
-__Stack_Size = 1024 ;
-
-PROVIDE ( _Stack_Size = __Stack_Size ) ;
-
-__Stack_Init = _estack  - __Stack_Size ;
-
-/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
-PROVIDE ( _Stack_Init = __Stack_Init ) ;
-
-/*
-There will be a link error if there is not this amount of RAM free at the end.
-*/
-_Minimum_Stack_Size = 0x100 ;
-
-
-/* include the memory spaces definitions sub-script */
-/*
-Linker subscript for STM32F10xx definitions with 1024 Flash and 96 Onchip SRAM */
-
-/* Memory Spaces Definitions */
-
-MEMORY
-{
-  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
-  FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
-  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  MEMORY_ARRAY (xrw)  : ORIGIN = 0x20002000, LENGTH = 32
-}
-
-/* higher address of the user mode stack */
-_estack = 0x20018000;
-
-
-
-/* include the sections management sub-script for FLASH mode */
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
-    .isr_vector :
-    {
-	. = ALIGN(4);
-        KEEP(*(.isr_vector))            /* Startup code */
-	. = ALIGN(4);
-    } >FLASH
- 
-    /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
-    .flashtext :
-    {
-	. = ALIGN(4);
-        *(.flashtext)            /* Startup code */
-	. = ALIGN(4);
-    } >FLASH
- 
-    
-    /* the program code is stored in the .text section, which goes to Flash */
-    .text :
-    {
-	    . = ALIGN(4);
-	    
-        *(.text)                   /* remaining code */
-        *(.text.*)                   /* remaining code */
-        *(.rodata)                 /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-
-	    . = ALIGN(4);
-   	 _etext = .;
-	    /* This is used by the startup in order to initialize the .data secion */
-   	 _sidata = _etext;
-    } >FLASH
-    
-    /* MEMORY_ARRAY */
-    .ROarraySection :
-    {
-            *(.ROarraySection)                          
-    } >MEMORY_ARRAY
-     
-
-    /* This is the initialized data section
-    The program executes knowing that the data is in the RAM
-    but the loader puts the initial values in the FLASH (inidata).
-    It is one task of the startup to copy the initial values from FLASH to RAM. */
-    .data  : AT ( _sidata )
-    {
-	    . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _sdata = . ;
-        
-        *(.data)
-        *(.data.*)
-
-	    . = ALIGN(4);
-	    /* This is used by the startup in order to initialize the .data secion */
-   	 _edata = . ;
-    } >RAM
-    
-    
-
-    /* This is the uninitialized data section */
-    .bss :
-    {
-	    . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _sbss = .;
-        
-        *(.bss)
-        *(COMMON)
-        
-	    . = ALIGN(4);
-	    /* This is used by the startup in order to initialize the .bss secion */
-   	 _ebss = . ;
-    } >RAM
-    
-    PROVIDE ( end = _ebss );
-    PROVIDE ( _end = _ebss );
-    
-    /* This is the user stack section 
-    This is just to check that there is enough RAM left for the User mode stack
-    It should generate an error if it's full.
-     */
-    ._usrstack :
-    {
-	    . = ALIGN(4);
-        _susrstack = . ;
-        
-        . = . + _Minimum_Stack_Size ;
-        
-	    . = ALIGN(4);
-        _eusrstack = . ;
-    } >RAM
-    
-
-   
-    /* this is the FLASH Bank1 */
-    /* the C or assembly source must explicitly place the code or data there
-    using the "section" attribute */
-    .b1text :
-    {
-        *(.b1text)                   /* remaining code */
-        *(.b1rodata)                 /* read-only data (constants) */
-        *(.b1rodata*)
-    } >FLASHB1
-    
-    /* this is the EXTMEM */
-    /* the C or assembly source must explicitly place the code or data there
-    using the "section" attribute */
-    
-    /* EXTMEM Bank0 */
-    .eb0text :
-    {
-        *(.eb0text)                   /* remaining code */
-        *(.eb0rodata)                 /* read-only data (constants) */
-        *(.eb0rodata*)
-    } >EXTMEMB0
-    
-    /* EXTMEM Bank1 */
-    .eb1text :
-    {
-        *(.eb1text)                   /* remaining code */
-        *(.eb1rodata)                 /* read-only data (constants) */
-        *(.eb1rodata*)
-    } >EXTMEMB1
-    
-    /* EXTMEM Bank2 */
-    .eb2text :
-    {
-        *(.eb2text)                   /* remaining code */
-        *(.eb2rodata)                 /* read-only data (constants) */
-        *(.eb2rodata*)
-    } >EXTMEMB2
-    
-    /* EXTMEM Bank0 */
-    .eb3text :
-    {
-        *(.eb3text)                   /* remaining code */
-        *(.eb3rodata)                 /* read-only data (constants) */
-        *(.eb3rodata*)
-    } >EXTMEMB3
-   
-
-    
-    /* after that it's only debugging information. */
-    
-    /* remove the debugging information from the standard libraries */
-    DISCARD :
-    {
-     libc.a ( * )
-     libm.a ( * )
-     libgcc.a ( * )
-     }
-  
-  
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }    
-    
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32f10x_flash_ROArray.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32f10x_flash_ROArray.ld
deleted file mode 100644
index 357cd39..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32f10x_flash_ROArray.ld
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32f10x_flash_ROArray.ld
-**
-**  Abstract    : Linker script for stm32f10x_xl Device with
-**                1024KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of 96K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x80;  /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-  MEMORY_ARRAY (rw)  : ORIGIN = 0x20002000, LENGTH = 32
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-	*(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-  
-  .ROarraySection : {*(.ROarraySection)} >MEMORY_ARRAY
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c
deleted file mode 100644
index 50875b0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/accesspermission.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Access rights configuration using Cortex-M3 MPU regions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_MPU
-  * @{
-  */
-  
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ARRAY_ADDRESS_START    (0x20002000UL)
-#define ARRAY_SIZE             (0x09UL << 0UL)
-#define ARRAY_REGION_NUMBER    (0x03UL << MPU_RNR_REGION_Pos) 
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-#if defined ( __CC_ARM   )
-uint8_t privilegedreadonlyarray[32] __attribute__((at(0x20002000)));
-
-#elif defined ( __ICCARM__ )
-#pragma location=0x20002000
-__no_init uint8_t privilegedreadonlyarray[32];
-
-#elif defined   (  __GNUC__  )
-uint8_t privilegedreadonlyarray[32] __attribute__((section(".ROarraySection")));
-
-#elif defined   (  __TASKING__  )
-uint8_t privilegedreadonlyarray[32] __at(0x20002000);
-#endif
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  This function configure the access right using Cortex-M3 MPU regions.
-  * @param  None
-  * @retval None
-  */
-void accesspermission(void)
-{
- uint8_t a; 
-  
-  /* Configure region for privilegedreadonlyarray as REGION NÝ3, 32byte and R 
-     only in privileged mode */
-  MPU->RNR  = ARRAY_REGION_NUMBER;
-  MPU->RBAR |= ARRAY_ADDRESS_START;
-  MPU->RASR |= ARRAY_SIZE | portMPU_REGION_PRIVILEGED_READ_ONLY;
-  
-  /* Read from privilegedreadonlyarray. This will not generate error */
-  a = privilegedreadonlyarray[0];
-  
-  /* Uncomment the following line to write to privilegedreadonlyarray. This will
-     generate error */
-  //privilegedreadonlyarray[0] = 'e';
-  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
deleted file mode 100644
index 8fb838f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "main.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_MPU
-  * @{
-  */
-  
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ACCESS_PERMISSION
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-void MPU_SETUP(void);
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */  
- 
-  /* Configure LED1 and LED2 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  
-  /* Set MPU regions */
-  MPU_SETUP();
-
-  #ifdef ACCESS_PERMISSION
-    accesspermission();
-  #endif  
-
-  /* Infinite loop */
-  while (1)
-  {
-    /* Turn On LED1 */
-    STM_EVAL_LEDOn(LED1); 
-  }
-}
-
-/**
-  * @brief  Configures the main MPU regions.
-  * @param  None
-  * @retval None
-  */
-void MPU_SETUP(void)
-{
-  /* Disable MPU */
-  MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-  
-  /* Configure RAM region as Region NÝ0, 8kB of size and R/W region */
-  MPU->RNR  = RAM_REGION_NUMBER;
-  MPU->RBAR = RAM_ADDRESS_START;
-  MPU->RASR = RAM_SIZE | portMPU_REGION_READ_WRITE;
-  
-  /* Configure FLASH region as REGION NÝ1, 1MB of size and R/W region */
-  MPU->RNR  = FLASH_REGION_NUMBER;
-  MPU->RBAR = FLASH_ADDRESS_START;
-  MPU->RASR = FLASH_SIZE | portMPU_REGION_READ_WRITE;
-  
-  /* Configure Peripheral region as REGION NÝ2, 0.5GB of size, R/W and Execute
-  Never region */
-  MPU->RNR  = PERIPH_REGION_NUMBER;  
-  MPU->RBAR = PERIPH_ADDRESS_START;
-  MPU->RASR = PERIPH_SIZE |portMPU_REGION_READ_WRITE | MPU_RASR_XN_Msk;
-  
-  /* Enable the memory fault exception */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-   
-  /* Enable MPU */
-  MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h
deleted file mode 100644
index 925cfb1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Public macro --------------------------------------------------------------*/
-/* Public define -------------------------------------------------------------*/
-#define RAM_ADDRESS_START                        (0x20000000UL)
-#define RAM_SIZE                                 (0x19UL << 0UL)
-#define PERIPH_ADDRESS_START                     (0x40000000)
-#define PERIPH_SIZE                              (0x39UL << 0UL)
-#define FLASH_ADDRESS_START                      (0x08000000)
-#define FLASH_SIZE                               (0x27UL << 0UL)
-#define portMPU_REGION_READ_WRITE                (0x03UL << MPU_RASR_AP_Pos)
-#define portMPU_REGION_PRIVILEGED_READ_ONLY      (0x05UL << MPU_RASR_AP_Pos)
-#define portMPU_REGION_READ_ONLY                 (0x06UL << MPU_RASR_AP_Pos)
-#define portMPU_REGION_PRIVILEGED_READ_WRITE     (0x01UL << MPU_RASR_AP_Pos)
-#define RAM_REGION_NUMBER                        (0x00UL << MPU_RNR_REGION_Pos)
-#define FLASH_REGION_NUMBER                      (0x01UL << MPU_RNR_REGION_Pos)
-#define PERIPH_REGION_NUMBER                     (0x02UL << MPU_RNR_REGION_Pos)
-
-/* Exported functions ------------------------------------------------------- */
-void accesspermission(void);
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h
deleted file mode 100644
index 7e3ff4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c
deleted file mode 100644
index b341b17..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_MPU
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  while (1)
-  {
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h
deleted file mode 100644
index d4790c5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c
deleted file mode 100644
index 25cae00..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h
deleted file mode 100644
index e9b6cd4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/Mode_Privilege/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c
deleted file mode 100644
index 607e36c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/Mode_Privilege/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_Mode_Privilege
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-  /* Switch back Thread mode to privileged */
-  __set_CONTROL(2);
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h
deleted file mode 100644
index 4910999..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/Mode_Privilege/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt
deleted file mode 100644
index 1e5c19e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
-  @page DAC_DualModeDMA_SineWave DAC dual mode sine wave example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DAC/DualModeDMA_SineWave/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DAC dual mode sine wave example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to use DAC dual channel mode with DMA to generate sine
-waves on both DAC channels outputs.
-
-Both DAC channels conversions are configured to be triggered by TIM2 TRGO triggers
-and without noise/triangle wave generation. 12bit right data alignment is selected
-since we choose to access DAC_DHR12RD register. DMA2 channel4 is configured to
-transfer continuously, word by word, a 32-word buffer to the dual DAC register
-DAC_DHR12RD.
-
-The transferred 32buffer is made to have a sine wave generation on each DAC channel 
-output. Both DAC channels are then enabled. Only DAC channel2 DMA capability is enabled.
-
-Once TIM2 is enabled, each TIM2 TRGO update event generate a DMA request which
-transfer data to the dual DAC register and DAC conversion is started. The sine
-waves can be visualized by connecting both PA.04 and PA.05 pins to an oscilloscope.
-
-
-@par Directory contents 
-
-  - DAC/DualModeDMA_SineWave/stm32f10x_conf.h     Library Configuration file
-  - DAC/DualModeDMA_SineWave/stm32f10x_it.c       Interrupt handlers
-  - DAC/DualModeDMA_SineWave/stm32f10x_it.h       Header for stm32f10x_it.c
-  - DAC/DualModeDMA_SineWave/main.c               Main program
-  - DAC/DualModeDMA_SineWave/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, XL-Density, Medium-Density Value line and Low-Density Value line 
-    Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL 
-    (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), 
-    STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and XL-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board. 
-
-  - STM32100E-EVAL Set-up 
-    - Connect PA.04 and PA.05 pins to an oscilloscope 
-    
-  - STM32100B-EVAL Set-up 
-    - Connect PA.04 and PA.05 pins to an oscilloscope 
-    
-  - STM3210C-EVAL Set-up  
-    - Only PA.04 can be monitored on an oscilloscope, PA.05 is used by other
-      module (Motor control connector) that prevents to have DAC channel output
-      on it. However, if you don't use Motor control connector, you can remove
-      the 0ohm resistor R84 and thus PA.05 can be used for DAC output.
-    @note Make shure that jumper JP15 is open.
-        
-  - STM3210E-EVAL Set-up 
-    - Connect PA.04 and PA.05 pins to an oscilloscope    
-
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h
deleted file mode 100644
index 9f785ca..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/DualModeDMA_SineWave/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c
deleted file mode 100644
index fb01774..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/DualModeDMA_SineWave/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
deleted file mode 100644
index e445ebb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/OneChannelDMA_Escalator/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DAC_OneChannelDMA_Escalator
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define DAC_DHR8R1_Address      0x40007410
-
-/* Init Structure definition */
-DAC_InitTypeDef            DAC_InitStructure;
-DMA_InitTypeDef            DMA_InitStructure;
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-const uint8_t Escalator8bit[6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF};
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();   
-
-  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
-     connected to the DAC converter. In order to avoid parasitic consumption, 
-     the GPIO pin should be configured in analog */
-  GPIO_Configuration();
-
-  /* TIM6 Configuration */
-  TIM_PrescalerConfig(TIM6, 0xF, TIM_PSCReloadMode_Update);
-  TIM_SetAutoreload(TIM6, 0xFF);
-  /* TIM6 TRGO selection */
-  TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);
-
-  /* DAC channel1 Configuration */
-  DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
-  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
-  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
-  DAC_Init(DAC_Channel_1, &DAC_InitStructure);
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
-  /* DMA2 channel3 configuration */
-  DMA_DeInit(DMA2_Channel3);
-#else
-  /* DMA1 channel3 configuration */
-  DMA_DeInit(DMA1_Channel3);
-#endif
-
-  DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR8R1_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&Escalator8bit;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = 6;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
-  DMA_Init(DMA2_Channel3, &DMA_InitStructure);
-  /* Enable DMA2 Channel3 */
-  DMA_Cmd(DMA2_Channel3, ENABLE);
-#else
-  DMA_Init(DMA1_Channel3, &DMA_InitStructure);
-  /* Enable DMA1 Channel3 */
-  DMA_Cmd(DMA1_Channel3, ENABLE);
-#endif
-
-  /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is 
-     automatically connected to the DAC converter. */
-  DAC_Cmd(DAC_Channel_1, ENABLE);
-
-  /* Enable DMA for DAC Channel1 */
-  DAC_DMACmd(DAC_Channel_1, ENABLE);
-
-  /* TIM6 enable counter */
-  TIM_Cmd(TIM6, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable peripheral clocks ------------------------------------------------*/
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
-  /* DMA2 clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
-#else
-  /* DMA1 clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-#endif
-  /* GPIOA Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-  /* DAC Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
-  /* TIM6 Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
-     connected to the DAC converter. In order to avoid parasitic consumption, 
-     the GPIO pin should be configured in analog */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt
deleted file mode 100644
index 90fd74a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
-  @page DAC_OneChannelDMA_Escalator DAC one channel DMA escalator example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DAC/OneChannelDMA_Escalator/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DAC one channel DMA escalator example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to use one DAC channel mode with DMA to generate an
-escalator signal on DAC channel1 output.
-
-DAC channel1 conversion is configured to be triggered by TIM6 TRGO triggers and
-without noise/triangle wave generation. 8bit right data alignment is selected
-since we choose to access DAC_DHR8R1 register.
-DMA2 channel3 is configured to transfer continuously, byte by byte, a 6-byte
-buffer to the DAC1 register DAC_DHR8R1.
-
-The transferred 6bytes buffer is made to have an escalator signal on DAC channel1
-output. DAC channel1 is then enabled. Once TIM6 is enabled, each TIM6 TRGO update
-event generate a DMA request which transfer data  to the DAC1 register and DAC
-conversion is started. The escalator signal can be visualized by connecting PA.04
-pin to an oscilloscope.
-
-@par Directory contents 
-
-  - DAC/OneChannelDMA_Escalator/stm32f10x_conf.h     Library Configuration file
-  - DAC/OneChannelDMA_Escalator/stm32f10x_it.c       Interrupt handlers
-  - DAC/OneChannelDMA_Escalator/stm32f10x_it.h       Header for stm32f10x_it.c
-  - DAC/OneChannelDMA_Escalator/main.c               Main program
-  - DAC/OneChannelDMA_Escalator/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, XL-Density,
-    High-Density Value line, Medium-Density Value line and Low-Density Value 
-    line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100B-EVAL 
-    (Medium-Density Value line),STM32100E-EVAL (High-Density Value line),
-     STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and 
-     XL-Density) evaluation boards and can be easily tailored to any other 
-     supported device and development board.   
-
-  - STM32100B-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope 
-    @note Make shure that jumper JP2 is open.
-    
-  - STM3210C-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-    @note Make shure that jumper JP15 is open.
-        
-  - STM3210E-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-	
-  - STM32100E-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c
deleted file mode 100644
index 896dc50..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/OneChannel_NoiseWave/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DAC_OneChannel_NoiseWave
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Init Structure definition */
-DAC_InitTypeDef            DAC_InitStructure;
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();   
-
-  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
-     connected to the DAC converter. In order to avoid parasitic consumption, 
-     the GPIO pin should be configured in analog */
-  GPIO_Configuration();
-
-  /* DAC channel1 Configuration */
-  DAC_InitStructure.DAC_Trigger = DAC_Trigger_Software;
-  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Noise;
-  DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bits8_0;
-  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-  DAC_Init(DAC_Channel_1, &DAC_InitStructure);
-
-  /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is 
-     automatically connected to the DAC converter. */
-  DAC_Cmd(DAC_Channel_1, ENABLE);
-
-  /* Set DAC Channel1 DHR12L register */
-  DAC_SetChannel1Data(DAC_Align_12b_L, 0x7FF0);
-
-  while (1)
-  {
-    /* Start DAC Channel1 conversion by software */
-    DAC_SoftwareTriggerCmd(DAC_Channel_1, ENABLE);
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* GPIOA Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-  /* DAC Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
-     connected to the DAC converter. In order to avoid parasitic consumption, 
-     the GPIO pin should be configured in analog */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt
deleted file mode 100644
index 80d045b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
-  @page DAC_OneChannel_NoiseWave DAC one channel noise wave example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DAC/OneChannel_NoiseWave/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DAC one channel noise wave example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to use one DAC channel to generate a signal with noise
-waves on DAC Channel1 output.
-
-DAC channel1 conversion are configured to be triggered by software with noise wave 
-generation.12bit left data alignment is selected since we choose to access DAC_DHR12L1
-register. Bits 0 to 8 are masked for the Linear feedback shift register. 
-DAC channel1 is then enabled. DAC Channel1 DHR12L1 register is configured to have
-an output voltage of VREF/2.
-
-Software triggers are generated continuously in an infinite loop, and on each
-trigger the DAC channel1 start the conversion and calculate the noise value to
-apply on the DAC channel1 output.
-
-The output signal with noise waves can be visualized by connecting PA.04 pin to
-an oscilloscope.
-
-@par Directory contents 
-
-  - DAC/OneChannel_NoiseWave/stm32f10x_conf.h     Library Configuration file
-  - DAC/OneChannel_NoiseWave/stm32f10x_it.c       Interrupt handlers
-  - DAC/OneChannel_NoiseWave/stm32f10x_it.h       Header for stm32f10x_it.c
-  - DAC/OneChannel_NoiseWave/main.c               Main program
-  - DAC/OneChannel_NoiseWave/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, XL-Density,
-    High-Density Value line, Medium-Density Value line and Low-Density Value 
-    line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100B-EVAL 
-    (Medium-Density Value line),STM32100E-EVAL (High-Density Value line),
-    STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and 
-    XL-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.   
-    
-  - STM32100B-EVAL Set-up  
-    - Connect PA.04 pin to an oscilloscope
-    @note JP2 should be open
-      
-  - STM3210C-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-    
-  - STM3210E-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-
-  - STM32100E-EVAL Set-up 
-    - Connect PA.04 pin to an oscilloscope
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h
deleted file mode 100644
index b418306..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/OneChannel_NoiseWave/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c
deleted file mode 100644
index 927e739..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/OneChannel_NoiseWave/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h
deleted file mode 100644
index 0fb1fe6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/TwoChannels_TriangleWave/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h
deleted file mode 100644
index df6a0ee..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/TwoChannels_TriangleWave/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c
deleted file mode 100644
index c68050a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/TwoChannels_TriangleWave/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt
deleted file mode 100644
index dd93e41..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
-  @page DMA_ADC_TIM1 DMA ADC1 TIM1 example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/ADC_TIM1/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DMA ADC1 TIM1 example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use a DMA channel to transfer
-continuously a data from a peripheral (ADC1) to another peripheral (TIM1) supporting
-DMA transfer.
-The ADC channel14 is configured to be converted continuously. TIM1_CH1 is configured
-to generate a PWM signal on its output.
-The dedicated DMA1 channel5 is configured to transfer in circular mode the last ADC 
-channel14 converted value to the TIM1_CCR1 register. The DMA channel request is driven
-by the TIM1 update event. The duty cycle of TIM1_CH1 output signal is then changed
-each time the input voltage value on ADC channel14 pin is modified.
-The duty cycle variation can be visualized on oscilloscope on the TIM1_CH1 pin
-PA.08 while changing the analog input on ADC channel14 using the potentiometer.
-
-@par Directory contents 
-
-  - DMA/ADC_TIM1/stm32f10x_conf.h    Library Configuration file
-  - DMA/ADC_TIM1/stm32f10x_it.c      Interrupt handlers
-  - DMA/ADC_TIM1/stm32f10x_it.h      Interrupt handlers header file
-  - DMA/ADC_TIM1/main.c              Main program
-  - DMA/ADC_TIM1/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density
-    Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and
-    XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily
-    tailored to any other supported device and development board.
-
-  - STM32100B-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV2)
-    - Connect an oscilloscope to TIM1_CH1 (PA.08) pin 
-    
-  - STM3210C-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1)
-    - Connect an oscilloscope to TIM1_CH1 (PA.08) pin  
-
-  - STM3210E-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1)
-    - Connect an oscilloscope to TIM1_CH1 (PA.08) pin  
-
-  - STM3210B-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1)
-    - Connect an oscilloscope to TIM1_CH1 (PA.08) pin       
-
-  - STM32100E-EVAL Set-up 
-    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1)
-    - Connect an oscilloscope to TIM1_CH1 (PA.08) pin  
-	
-	
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h
deleted file mode 100644
index 8e13530..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/ADC_TIM1/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c
deleted file mode 100644
index 7d9f58e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/ADC_TIM1/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_ADC_TIM1
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h
deleted file mode 100644
index 5f0cc04..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/ADC_TIM1/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c
deleted file mode 100644
index 2670e7b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/ADC_TIM1/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt
deleted file mode 100644
index 5ef0865..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
-  @page DMA_EXAMPLES DMA_EXAMPLES
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   STM32F10x Standard Peripherals DMA Examples List.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-   
-In addition to these examples, there are other examples using the DMA peripheral:
-
-  * <ul>
-  * <li><B>  Complet List of DMA Examples </B>
-  * - @subpage ADC_3ADCs_DMA
-  * - @subpage ADC_ADC1_DMA
-  * - @subpage ADC_ExtLinesTrigger
-  * - @subpage ADC_RegSimul_DualMode 
-  * - @subpage ADC_TIMTrigger_AutoInjection
-  * - @subpage DAC_DualModeDMA_SineWave 
-  * - @subpage DAC_OneChannelDMA_Escalator     
-  * - @subpage I2C_EEPROM
-  * - @subpage I2C_TSENSOR
-  * - @subpage IOExpander_Example
-  * - @subpage NVIC_DMA_WFIMode 
-  * - @subpage SDIO_Example   
-  * - @subpage SPI_DMA
-  * - @subpage TIM_DMA 
-  * - @subpage USART_DMA_Interrupt
-  * - @subpage USART_DMA_Polling 
-  * </ul>  
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */ 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h
deleted file mode 100644
index 474afcc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file DMA/FLASH_RAM/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
deleted file mode 100644
index 4288f07..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/FLASH_RAM/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_FLASH_RAM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint16_t CurrDataCounterEnd;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles DMA1 Channel 6 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void DMA1_Channel6_IRQHandler(void)
-{
-  /* Test on DMA1 Channel6 Transfer Complete interrupt */
-  if(DMA_GetITStatus(DMA1_IT_TC6))
-  {
-    /* Get Current Data Counter value after complete transfer */
-    CurrDataCounterEnd = DMA_GetCurrDataCounter(DMA1_Channel6);
-    /* Clear DMA1 Channel6 Half Transfer, Transfer Complete and Global interrupt pending bits */
-    DMA_ClearITPendingBit(DMA1_IT_GL6);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h
deleted file mode 100644
index e90099f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file DMA/FLASH_RAM/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void DMA1_Channel6_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
deleted file mode 100644
index d982167..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/FSMC/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#ifdef STM32F10X_HD_VL /* High-density Value line devices */
- #include "stm32100e_eval_fsmc_sram.h"
-#else /* High- and XL-density */
- #include "stm3210e_eval_fsmc_sram.h"
-#endif
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_FSMC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize  32
-#define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-DMA_InitTypeDef    DMA_InitStructure;
-volatile TestStatus TransferStatus;
-const uint32_t SRC_Const_Buffer[BufferSize]= {
-                            0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
-                            0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
-                            0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
-                            0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
-                            0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
-                            0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
-                            0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
-                            0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
-uint8_t DST_Buffer[4*BufferSize];
-uint32_t Idx = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* FSMC for SRAM and SRAM pins configuration */
-  SRAM_Init();
-
-  /* Write to FSMC -----------------------------------------------------------*/
-  /* DMA2 channel5 configuration */
-  DMA_DeInit(DMA2_Channel5);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;    
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 32;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
-  DMA_Init(DMA2_Channel5, &DMA_InitStructure);
-
-  /* Enable DMA2 channel5 */
-  DMA_Cmd(DMA2_Channel5, ENABLE);
-
-  /* Check if DMA2 channel5 transfer is finished */
-  while(!DMA_GetFlagStatus(DMA2_FLAG_TC5));
-
-  /* Clear DMA2 channel5 transfer complete flag bit */
-  DMA_ClearFlag(DMA2_FLAG_TC5);
-
-  /* Read from FSMC ----------------------------------------------------------*/
-  /* Destination buffer initialization */ 
-  for(Idx=0; Idx<128; Idx++) DST_Buffer[Idx]=0;
-
-  /* DMA1 channel3 configuration */
-  DMA_DeInit(DMA1_Channel3);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;  
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 128;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
-  DMA_Init(DMA1_Channel3, &DMA_InitStructure);
-
-  /* Enable DMA1 channel3 */
-  DMA_Cmd(DMA1_Channel3, ENABLE);
-
-  /* Check if DMA1 channel3 transfer is finished */
-  while(!DMA_GetFlagStatus(DMA1_FLAG_TC3));
-
-  /* Clear DMA1 channel3 transfer complete flag bit */
-  DMA_ClearFlag(DMA1_FLAG_TC3);
-
-  /* Check if the transmitted and received data are equal */
-  TransferStatus = Buffercmp(SRC_Const_Buffer, (uint32_t*)DST_Buffer, BufferSize);
-  /* TransferStatus = PASSED, if the transmitted and received data 
-     are the same */
-  /* TransferStatus = FAILED, if the transmitted and received data 
-     are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* DMA1 and DMA2 clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);
-  /* FSMC clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer, pBuffer1: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer identical to pBuffer1
-  *         FAILED: pBuffer differs from pBuffer1
-  */
-TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer != *pBuffer1)
-    {
-      return FAILED;
-    }
-    
-    pBuffer++;
-    pBuffer1++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c
deleted file mode 100644
index b5ab495..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/FSMC/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_FSMC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h
deleted file mode 100644
index 7de2e62..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/FSMC/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
deleted file mode 100644
index 56a6480..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/I2C_RAM/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_I2C_RAM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define I2C1_DR_Address        0x40005410
-#define I2C2_DR_Address        0x40005810
-#define I2C1_SLAVE_ADDRESS7    0x30
-#define I2C2_SLAVE_ADDRESS7    0x30
-#define BufferSize             8
-#define ClockSpeed             100000
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-I2C_InitTypeDef  I2C_InitStructure;
-DMA_InitTypeDef  DMA_InitStructure;
-uint8_t I2C1_Buffer_Tx[BufferSize] = {1, 2, 3, 4, 5, 6, 7, 8};
-uint8_t I2C2_Buffer_Rx[BufferSize];
-uint8_t Tx_Idx = 0, Rx_Idx = 0;
-volatile TestStatus TransferStatus;
-    
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength);
-    
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-       
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* DMA1 channel5 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel5);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)I2C2_Buffer_Rx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = BufferSize;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA1_Channel5, &DMA_InitStructure);
-
-  /* DMA1 channel6 configuration ----------------------------------------------*/
-  DMA_DeInit(DMA1_Channel6);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)I2C1_Buffer_Tx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_Init(DMA1_Channel6, &DMA_InitStructure);
-
-  /* Enable I2C1 and I2C2 ----------------------------------------------------*/
-  I2C_Cmd(I2C1, ENABLE);
-  I2C_Cmd(I2C2, ENABLE);
-
-  /* I2C1 configuration ------------------------------------------------------*/
-  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
-  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
-  I2C_InitStructure.I2C_OwnAddress1 = I2C1_SLAVE_ADDRESS7;
-  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
-  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-  I2C_InitStructure.I2C_ClockSpeed = ClockSpeed;
-  I2C_Init(I2C1, &I2C_InitStructure);
-  /* I2C2 configuration ------------------------------------------------------*/
-  I2C_InitStructure.I2C_OwnAddress1 = I2C2_SLAVE_ADDRESS7;
-  I2C_Init(I2C2, &I2C_InitStructure);
-  
-  /*----- Transmission Phase -----*/
-  /* Send I2C1 START condition */
-  I2C_GenerateSTART(I2C1, ENABLE);
-  /* Test on I2C1 EV5 and clear it */
-  while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT));  
-  /* Send I2C2 slave Address for write */
-  I2C_Send7bitAddress(I2C1, I2C2_SLAVE_ADDRESS7, I2C_Direction_Transmitter);
-  /* Test on I2C2 EV1 and clear it */
-  while(!I2C_CheckEvent(I2C2, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED));  
-  /* Test on I2C1 EV6 and clear it */
-  while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));  
-
-  /* Enable I2C2 DMA */
-  I2C_DMACmd(I2C2, ENABLE);
-  /* Enable I2C1 DMA */
-  I2C_DMACmd(I2C1, ENABLE);
-
-  /* Enable DMA1 Channel5 */
-  DMA_Cmd(DMA1_Channel5, ENABLE);
-  /* Enable DMA1 Channel6 */
-  DMA_Cmd(DMA1_Channel6, ENABLE);
-
-  /* DMA1 Channel5 transfer complete test */
-  while(!DMA_GetFlagStatus(DMA1_FLAG_TC5));
-  /* DMA1 Channel6 transfer complete test */
-  while(!DMA_GetFlagStatus(DMA1_FLAG_TC6));
-
-  /* Send I2C1 STOP Condition */
-  I2C_GenerateSTOP(I2C1, ENABLE);
-  /* Test on I2C2 EV4 */
-  while(!I2C_CheckEvent(I2C2, I2C_EVENT_SLAVE_STOP_DETECTED)); 
-  /* Clear I2C2 STOPF flag: read operation to I2C_SR1 followed by a 
-  write operation to I2C_CR1 */
-  (void)(I2C_GetFlagStatus(I2C2, I2C_FLAG_STOPF));
-  I2C_Cmd(I2C2, ENABLE);
-
-
-  /* Check if the transmitted and received data are equal */
-  TransferStatus = Buffercmp(I2C1_Buffer_Tx, I2C2_Buffer_Rx, BufferSize);
-  /* TransferStatus = PASSED, if the transmitted and received data 
-     are the same */
-  /* TransferStatus = FAILED, if the transmitted and received data 
-     are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* Enable DMA1 clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-  /* Enable GPIOB clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-  /* Enable I2C1 and I2C2 clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1 | RCC_APB1Periph_I2C2, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure I2C1 pins: SCL and SDA */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* Configure I2C2 pins: SCL and SDA */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer, pBuffer1: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer identical to pBuffer1
-  *         FAILED: pBuffer differs from pBuffer1
-  */
-TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer != *pBuffer1)
-    {
-      return FAILED;
-    }
-    
-    pBuffer++;
-    pBuffer1++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt
deleted file mode 100644
index f5118ec..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  @page DMA_I2C_RAM DMA I2C to RAM example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/I2C_RAM/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DMA I2C to RAM example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use two DMA channels to transfer a 
-data buffer from memory to I2C2 through I2C1.
-
-I2C1 is set as the master transmitter and I2C2 as the slave receiver. DMA1 Channel5 is
-configured to store the data received from I2C2 into the Rx buffer (reception buffer).
-DMA1 Channel6 is configured to transfer data from the Tx buffer (transmission buffer)
-to the I2C1 DR register. After the generation of the Start condition and once the slave
-address has been acknowledged, DMA capability is enabled for both I2C1 and I2C2. 
-As soon as the two I2C DMAEN bits are set in the I2C1_CR2 and I2C2_CR2 registers, 
-the transmission of the Tx buffer is started by DMA1 Channel5 and at the same time the
-data received on I2C2 is stored in Rx buffer using DMA1 Channel6 .
-The transmitted and the received buffers are compared to check that all data have been
-correctly transferred.
-
-
-@par Directory contents 
-
-  - DMA/I2C_RAM/stm32f10x_conf.h    Library Configuration file
-  - DMA/I2C_RAM/stm32f10x_it.c      Interrupt handlers
-  - DMA/I2C_RAM/stm32f10x_it.h      Interrupt handlers header file
-  - DMA/I2C_RAM/main.c              Main program
-  - DMA/I2C_RAM/system_stm32f10x.c  STM32F10x system source file
-  
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can 
-    be easily tailored to any other supported device and development board.
-    This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x 
-    Connectivity-Line) evaluation boards since the I2C2 pins (PB10 and PB11) are 
-    already used by Ethernet PHY module. 
-    This example can't be tested with STMicroelectronics STM32100B-EVAL (STM32F10x 
-    Medium-Density Value line) and STM32100E-EVAL (High-Density Value line) 
-    evaluation boards since the I2C1/I2C2 pins (PB6/PB10 and PB7/PB11) are already 
-    used by HDMI-CEC module.     
-
-  - STM3210E-EVAL Set-up 
-    - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
-    - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin	(PB.11)
-    - Check that a pull-up resistor is connected on one I2C SDA pin
-    - Check that a pull-up resistor is connected on one I2C SCL pin
-
-  - STM3210B-EVAL Set-up 
-    - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
-    - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin	(PB.11)
-    - Check that a pull-up resistor is connected on one I2C SDA pin
-    - Check that a pull-up resistor is connected on one I2C SCL pin    
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c
deleted file mode 100644
index f281d1a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/I2C_RAM/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
deleted file mode 100644
index 2448236..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/SPI_RAM/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup DMA_SPI_RAM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize         32
-#define CRCPolynomial      7
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SPI_InitTypeDef    SPI_InitStructure;
-DMA_InitTypeDef    DMA_InitStructure;
-uint8_t SPI_MASTER_Buffer_Rx[BufferSize], SPI_SLAVE_Buffer_Rx[BufferSize];
-volatile uint8_t SPI_MASTERCRCValue = 0, SPI_SLAVECRCValue = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-
-uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,
-                                            0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,
-                                            0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,
-                                            0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20};
-
-uint8_t SPI_SLAVE_Buffer_Tx[BufferSize] = {0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,
-                                           0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,
-                                           0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,
-                                           0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70};
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-  
-  /* Configure the STM32_EVAL LED */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  /* Turn Off LED1 and LED2 */
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);     
-  
-  /* System Clocks Configuration */
-  RCC_Configuration();
-       
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* SPI_MASTER configuration ------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = CRCPolynomial;
-  SPI_Init(SPI_MASTER, &SPI_InitStructure);
-  
-  /* SPI_SLAVE configuration -------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPI_SLAVE, &SPI_InitStructure);
-
-  /* SPI_MASTER_Rx_DMA_Channel configuration ---------------------------------*/
-  DMA_DeInit(SPI_MASTER_Rx_DMA_Channel);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Rx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = BufferSize;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(SPI_MASTER_Rx_DMA_Channel, &DMA_InitStructure);
-
-  /* SPI_MASTER_Tx_DMA_Channel configuration ---------------------------------*/
-  DMA_DeInit(SPI_MASTER_Tx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Tx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
-  DMA_Init(SPI_MASTER_Tx_DMA_Channel, &DMA_InitStructure);
-
-  /* SPI_SLAVE_Rx_DMA_Channel configuration ----------------------------------*/
-  DMA_DeInit(SPI_SLAVE_Rx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Rx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  DMA_Init(SPI_SLAVE_Rx_DMA_Channel, &DMA_InitStructure);
-
-  /* SPI_SLAVE_Tx_DMA_Channel configuration ----------------------------------*/
-  DMA_DeInit(SPI_SLAVE_Tx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Tx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
-  DMA_Init(SPI_SLAVE_Tx_DMA_Channel, &DMA_InitStructure);
-
-  /* Enable SPI_MASTER DMA Tx request */
-  SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Tx, ENABLE);
-  /* Enable SPI_MASTER DMA Rx request */
-  SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Rx, ENABLE);
-  /* Enable SPI_SLAVE DMA Tx request */
-  SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Tx, ENABLE);
-  /* Enable SPI_SLAVE DMA Rx request */
-  SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Rx, ENABLE);
- 
-  /* Enable SPI_MASTER CRC calculation */
-  SPI_CalculateCRC(SPI_MASTER, ENABLE);
-  /* Enable SPI_SLAVE CRC calculation */
-  SPI_CalculateCRC(SPI_SLAVE, ENABLE);
-
-  /* Enable SPI_SLAVE */
-  SPI_Cmd(SPI_SLAVE, ENABLE);
-  /* Enable SPI_MASTER */
-  SPI_Cmd(SPI_MASTER, ENABLE);
-
-  /* Enable DMA channels */
-  DMA_Cmd(SPI_MASTER_Rx_DMA_Channel, ENABLE);
-  DMA_Cmd(SPI_SLAVE_Rx_DMA_Channel, ENABLE);
-  DMA_Cmd(SPI_SLAVE_Tx_DMA_Channel, ENABLE);
-  DMA_Cmd(SPI_MASTER_Tx_DMA_Channel, ENABLE);
-   
-  /* Transfer complete */
-  while(!DMA_GetFlagStatus(SPI_MASTER_Rx_DMA_FLAG));
-  while(!DMA_GetFlagStatus(SPI_SLAVE_Rx_DMA_FLAG));
-  while(!DMA_GetFlagStatus(SPI_SLAVE_Tx_DMA_FLAG));
-  while(!DMA_GetFlagStatus(SPI_MASTER_Tx_DMA_FLAG));
-
-  /* Wait for SPI_MASTER data reception: CRC transmitted by SPI_SLAVE */
-  while(SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Wait for SPI_SLAVE data reception: CRC transmitted by SPI_MASTER */
-  while(SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_I2S_FLAG_RXNE) == RESET);
-
-  /* Check the correctness of written dada */
-  TransferStatus1 = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
-  TransferStatus2 = Buffercmp(SPI_MASTER_Buffer_Rx, SPI_SLAVE_Buffer_Tx, BufferSize);
-  /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received 
-     are correct */
-  /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received  
-     are different */
-
-  /* Test on the SPI_MASTER CRCR ERROR flag */
-  if ((SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_FLAG_CRCERR)) != RESET)
-  {
-    TransferStatus1 = FAILED;
-  }
-  /* Test on the SPI_SLAVE CRCR ERROR flag */
-  if ((SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_FLAG_CRCERR)) != RESET)
-  {
-    TransferStatus2 = FAILED;
-  } 
-
-  /* Read SPI_MASTER received CRC value */
-  SPI_MASTERCRCValue = SPI_I2S_ReceiveData(SPI_MASTER);
-  /* Read SPI_SLAVE received CRC value */
-  SPI_SLAVECRCValue = SPI_I2S_ReceiveData(SPI_SLAVE);
-
-  if (TransferStatus1 != FAILED)
-  {
-    /* OK */
-    /* Turn on LD1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  { 
-    /* KO */
-    /* Turn Off LD1 */
-    STM_EVAL_LEDOff(LED1);
-  }
-    
-  if (TransferStatus2 != FAILED)
-  {	
-    /* OK */
-    /* Turn on LD2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-  else
-  { 
-    /* KO */
-    /* Turn Off LD2 */
-    STM_EVAL_LEDOff(LED2);
-  }
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK2 = HCLK/2 */
-  RCC_PCLK2Config(RCC_HCLK_Div2); 
-
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* Enable DMA1 or/and DMA2 clock */
-  RCC_AHBPeriphClockCmd(SPI_MASTER_DMA_CLK | SPI_SLAVE_DMA_CLK, ENABLE);
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
-  RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
-  RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable SPI_MASTER Periph clock */
-  RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
-                           
-#else
-  /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
-  RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
-                         SPI_MASTER_CLK, ENABLE);
-#endif
-  /* Enable SPI_SLAVE Periph clock */
-  RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable SPI3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
-#endif
-
-  /* Configure SPI_MASTER pins: SCK and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
-  /* Configure SPI_MASTER pins:  MISO */
-  GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_MISO;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
-
-  /* Configure SPI_SLAVE pins: SCK and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_SCK | SPI_SLAVE_PIN_MOSI;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
-  /* Configure SPI_SLAVE pins: MISO  */
-  GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_MISO ;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer, pBuffer1: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer identical to pBuffer1
-  *         FAILED: pBuffer differs from pBuffer1
-  */
-TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer != *pBuffer1)
-    {
-      return FAILED;
-    }
-    
-    pBuffer++;
-    pBuffer1++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h
deleted file mode 100644
index a9e96a5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/SPI_RAM/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100E_EVAL) && !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined(USE_STM32100B_EVAL) || defined (USE_STM32100E_EVAL)
-  #define SPI_MASTER                   SPI1
-  #define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
-  #define SPI_MASTER_GPIO              GPIOA
-  #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA  
-  #define SPI_MASTER_PIN_SCK           GPIO_Pin_5
-  #define SPI_MASTER_PIN_MISO          GPIO_Pin_6
-  #define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
-  #define SPI_MASTER_DMA               DMA1
-  #define SPI_MASTER_DMA_CLK           RCC_AHBPeriph_DMA1  
-  #define SPI_MASTER_Rx_DMA_Channel    DMA1_Channel2
-  #define SPI_MASTER_Rx_DMA_FLAG       DMA1_FLAG_TC2
-  #define SPI_MASTER_Tx_DMA_Channel    DMA1_Channel3
-  #define SPI_MASTER_Tx_DMA_FLAG       DMA1_FLAG_TC3  
-  #define SPI_MASTER_DR_Base           0x4001300C
-  
-  #define SPI_SLAVE                    SPI2
-  #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
-  #define SPI_SLAVE_GPIO               GPIOB
-  #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB 
-  #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
-  #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
-  #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15 
-  #define SPI_SLAVE_DMA                DMA1
-  #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1  
-  #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
-  #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
-  #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
-  #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5  
-  #define SPI_SLAVE_DR_Base            0x4000380C
-          
-#elif defined (USE_STM3210C_EVAL)
-  #define SPI_MASTER                   SPI3   /* SPI pins are remapped by software */
-  #define SPI_MASTER_CLK               RCC_APB1Periph_SPI3
-  #define SPI_MASTER_GPIO              GPIOC
-  #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOC  
-  #define SPI_MASTER_PIN_SCK           GPIO_Pin_10
-  #define SPI_MASTER_PIN_MISO          GPIO_Pin_11
-  #define SPI_MASTER_PIN_MOSI          GPIO_Pin_12
-  #define SPI_MASTER_DMA               DMA2
-  #define SPI_MASTER_DMA_CLK           RCC_AHBPeriph_DMA2  
-  #define SPI_MASTER_Rx_DMA_Channel    DMA2_Channel1
-  #define SPI_MASTER_Rx_DMA_FLAG       DMA2_FLAG_TC1
-  #define SPI_MASTER_Tx_DMA_Channel    DMA2_Channel2
-  #define SPI_MASTER_Tx_DMA_FLAG       DMA2_FLAG_TC2  
-  #define SPI_MASTER_DR_Base           0x40003C0C
-  
-  #define SPI_SLAVE                    SPI2
-  #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
-  #define SPI_SLAVE_GPIO               GPIOB
-  #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
-  #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
-  #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
-  #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
-  #define SPI_SLAVE_DMA                DMA1
-  #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
-  #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
-  #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
-  #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
-  #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5  
-  #define SPI_SLAVE_DR_Base            0x4000380C 
-
-#endif
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt
deleted file mode 100644
index 7bcbeb8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
-  @page DMA_SPI_RAM DMA SPI to RAM example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/SPI_RAM/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DMA SPI to RAM example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use four DMA channels to transfer
-a data buffer from memory to SPI_SLAVE through SPI_MASTER and a second data buffer
-from memory to SPI_MASTER through SPI_SLAVE in full-duplex mode.
-SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the
-STMicroelectronics EVAL board you are using.
-
-For each SPI the NSS pin is configured by software (thus NSS pin is free for GPIO use)
-and DMA Tx/Rx requests are enabled. 
-
-In this example both transmission and reception are managed through DMA and the
-received data are stored into buffers declared in the SRAM. The DMA channels 
-involved in this transfer depend on the used SPIs (for more details please refer
-to platform_config.h file).
-
-A polling on all Transfer complete flags are done for all used DMA channels to
-check the end of all DMA channels transfers. The last received data on SPI_MASTER
-and SPI_SLAVE are the CRC values sent by each SPI to the other.
-The transmitted and received buffers are compared to check that all data have
-been correctly transferred.
-
-
-@par Directory contents 
-
-  - DMA/SPI_RAM/platform_config.h   Evaluation board specific configuration file
-  - DMA/SPI_RAM/stm32f10x_conf.h    Library Configuration file
-  - DMA/SPI_RAM/stm32f10x_it.c      Interrupt handlers
-  - DMA/SPI_RAM/stm32f10x_it.h      Interrupt handlers header file
-  - DMA/SPI_RAM/main.c              Main program
-  - DMA/SPI_RAM/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line)
-    STM32100B-EVAL (Medium-Density Value line), STM32100E-EVAL (High-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-	
-  - STM32100E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)  
-    
-  - STM32100B-EVAL Set-up  
-    - Connect SPI1 SCK pin  (PA.05) to SPI2 SCK  pin (PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-      
-  - STM3210C-EVAL Set-up 
-    - Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin	(PB.13)
-    - Connect SPI3 MISO pin (PC.11) to SPI2 MISO pin (PB.14)
-    - Connect SPI3 MOSI pin (PC.12) to SPI2 MOSI pin (PB.15)
-    @note In this case SPI3 pins are remapped by software.
-
-  - STM3210E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfer with SPI2 MISO pin PB14.
-      
-  - STM3210B-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)    
- 
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h
deleted file mode 100644
index d9edf7c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file DMA/SPI_RAM/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
deleted file mode 100644
index 33a0bc0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DMA/SPI_RAM/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
deleted file mode 100644
index 46f52f1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    EXTI/EXTI_Config/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup EXTI_Config
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-EXTI_InitTypeDef   EXTI_InitStructure;
-GPIO_InitTypeDef   GPIO_InitStructure;
-NVIC_InitTypeDef   NVIC_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void EXTI0_Config(void);
-void EXTI9_5_Config(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-         
-  /* Initialize LED1 and Key Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  
-  /* Configure PA.00 in interrupt mode */
-  EXTI0_Config();
-
-  /* Configure PB.09 or PG.08 in interrupt mode */
-  EXTI9_5_Config();
-
-  /* Generate software interrupt: simulate a falling edge applied on EXTI0 line */
-  EXTI_GenerateSWInterrupt(EXTI_Line0);
-          
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configure PA.00 in interrupt mode
-  * @param  None
-  * @retval None
-  */
-void EXTI0_Config(void)
-{
-  /* Enable GPIOA clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-  
-  /* Configure PA.00 pin as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* Enable AFIO clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Connect EXTI0 Line to PA.00 pin */
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource0);
-
-  /* Configure EXTI0 line */
-  EXTI_InitStructure.EXTI_Line = EXTI_Line0;
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  /* Enable and set EXTI0 Interrupt to the lowest priority */
-  NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Configure PB.09 or PG.08 in interrupt mode
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_Config(void)
-{
-#if defined (STM32F10X_HD_VL) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
-  /* Enable GPIOG clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE);
-
-  /* Configure PG.08 pin as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-  /* Enable AFIO clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-  /* Connect EXTI8 Line to PG.08 pin */
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOG, GPIO_PinSource8);
-
-  /* Configure EXTI8 line */
-  EXTI_InitStructure.EXTI_Line = EXTI_Line8;
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  /* Enable and set EXTI9_5 Interrupt to the lowest priority */
-  NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-  NVIC_Init(&NVIC_InitStructure);
-#else
-  /* Enable GPIOB clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-
-  /* Configure PB.09 pin as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* Enable AFIO clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-  /* Connect EXTI9 Line to PB.09 pin */
-  GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource9);
-
-  /* Configure EXTI9 line */
-  EXTI_InitStructure.EXTI_Line = EXTI_Line9;
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  /* Enable and set EXTI9_5 Interrupt to the lowest priority */
-  NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-  NVIC_Init(&NVIC_InitStructure);
-#endif
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c
deleted file mode 100644
index 0a507d7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    EXTI/EXTI_Config/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup EXTI_Config
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles External line 0 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI0_IRQHandler(void)
-{
-  if(EXTI_GetITStatus(EXTI_Line0) != RESET)
-  {
-    /* Toggle LED1 */
-     STM_EVAL_LEDToggle(LED1);
-
-    /* Clear the  EXTI line 0 pending bit */
-    EXTI_ClearITPendingBit(EXTI_Line0);
-  }
-}
-
-/**
-  * @brief  This function handles External lines 9 to 5 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_IRQHandler(void)
-{
-#if defined (STM32F10X_HD_VL) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
-  if(EXTI_GetITStatus(EXTI_Line8) != RESET)
-  {
-    /* Toggle LED2 */
-     STM_EVAL_LEDToggle(LED2);
-
-    /* Clear the  EXTI line 8 pending bit */
-    EXTI_ClearITPendingBit(EXTI_Line8);
-  }
-#else
-  if(EXTI_GetITStatus(EXTI_Line9) != RESET)
-  {
-    /* Toggle LED2 */
-     STM_EVAL_LEDToggle(LED2);
-
-    /* Clear the  EXTI line 9 pending bit */
-    EXTI_ClearITPendingBit(EXTI_Line9);
-  }
-#endif
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h
deleted file mode 100644
index 893a2c9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    EXTI/EXTI_Config/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI0_IRQHandler(void);
-void EXTI9_5_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c
deleted file mode 100644
index 1c27fac..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    EXTI/EXTI_Config/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd
deleted file mode 100644
index 505bd47..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd
+++ /dev/null
@@ -1,1403 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>STM32F10X_XL_BANK1</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>21</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f10xxe.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>5.30.0.51236</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>JLINK_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>5.41.2.51798</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
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-        <option>
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-          <name>CRDIDriverDll</name>
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-          <name>CCSTLinkInterfaceCmdLine</name>
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-    <settings>
-      <name>THIRDPARTY_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
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-          <name>CThirdPartyLogFileCheck</name>
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-          <name>CThirdPartyLogFileEditB</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
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-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
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-    <debuggerPlugins>
-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-      <plugin>
-        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
-        <loadFlag>0</loadFlag>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
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-        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp
deleted file mode 100644
index 2e02b84..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp
+++ /dev/null
@@ -1,1664 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
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-      <name>ARM</name>
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-      </data>
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-      <archiveVersion>3</archiveVersion>
-      <data>
-        <extensions></extensions>
-        <cmdline></cmdline>
-      </data>
-    </settings>
-    <settings>
-      <name>BICOMP</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
-    </settings>
-    <settings>
-      <name>BUILDACTION</name>
-      <archiveVersion>1</archiveVersion>
-      <data>
-        <prebuild></prebuild>
-        <postbuild></postbuild>
-      </data>
-    </settings>
-    <settings>
-      <name>ILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>8</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IlinkLibIOConfig</name>
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-          <state>STM32F10X_XL_BANK2.out</state>
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-          <state>1</state>
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-          <state></state>
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-          <state></state>
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-          <name>IlinkMapFile</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkLogFile</name>
-          <state>0</state>
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-          <name>IlinkLogInitialization</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkLogModule</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogSection</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkLogVeneer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIcfOverride</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkIcfFile</name>
-          <state>$PROJ_DIR$\stm32f10x_flash_xl_bank2.icf</state>
-        </option>
-        <option>
-          <name>IlinkIcfFileSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkEnableRemarks</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkSuppressDiags</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsRem</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsWarn</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkTreatAsErr</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkWarningsAreErrors</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkUseExtraOptions</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkLowLevelInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAutoLibEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkAdditionalLibs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IlinkOverrideProgramEntryLabel</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkProgramEntryLabelSelect</name>
-          <state>0</state>
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-        <option>
-          <name>IlinkProgramEntryLabel</name>
-          <state>__iar_program_start</state>
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-          <name>DoFill</name>
-          <state>0</state>
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-        <option>
-          <name>FillerByte</name>
-          <state>0xFF</state>
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-        <option>
-          <name>FillerStart</name>
-          <state>0x0</state>
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-          <state>1</state>
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-          <state>1</state>
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-          <name>CrcPoly</name>
-          <state>0x11021</state>
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-          <name>CrcCompl</name>
-          <version>0</version>
-          <state>0</state>
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-          <name>CrcBitOrder</name>
-          <version>0</version>
-          <state>0</state>
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-        <option>
-          <name>CrcInitialValue</name>
-          <state>0x0</state>
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-        <option>
-          <name>DoCrc</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkBufferedTerminalOutput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>IlinkStdoutInterfaceSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CrcFullSize</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>IlinkIElfToolPostProcess</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARCHIVE</name>
-      <archiveVersion>0</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>IarchiveInputs</name>
-          <state></state>
-        </option>
-        <option>
-          <name>IarchiveOverride</name>
-          <state>0</state>
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-        <option>
-          <name>IarchiveOutput</name>
-          <state>###Unitialized###</state>
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-      </data>
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-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data/>
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-  </configuration>
-  <group>
-    <name>CMSIS</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c</name>
-    </file>
-  </group>
-  <group>
-    <name>Doc</name>
-    <file>
-      <name>$PROJ_DIR$\..\readme.txt</name>
-    </file>
-  </group>
-  <group>
-    <name>EWARMv5</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\iar\startup_stm32f10x_xl.s</name>
-    </file>
-  </group>
-  <group>
-    <name>StdPeriph_Driver</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
-    </file>
-  </group>
-  <group>
-    <name>STM32_EVAL</name>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_lcd.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\..\..\Utilities\STM32_EVAL\stm32_eval.c</name>
-    </file>
-  </group>
-  <group>
-    <name>User</name>
-    <file>
-      <name>$PROJ_DIR$\..\main.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\stm32f10x_it.c</name>
-    </file>
-  </group>
-</project>
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww
deleted file mode 100644
index e0fd14b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww
+++ /dev/null
@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
-  <project>
-    <path>$WS_DIR$\Project.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf
deleted file mode 100644
index 2d868e1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08080000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08080000;
-define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp
deleted file mode 100644
index 9eb095c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp
+++ /dev/null
@@ -1,1103 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103ZG.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722678" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325328" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954468" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="0" y="0"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="844" cy="610"></Size>
-				<Position x="-4" y="-23"></Position>
-			</Rectangle>
-			<Tabs Count="4" Active="3">
-				<Tab Pos="0" PosX="11" PosY="20" Module="readme.txt" TopLine="9" FilePath="$(PROJECTDIR)\..\..\readme.txt" Application="STM3210X-XL_BANK1"/>
-				<Tab Pos="1" PosX="60" PosY="97" Module="STM32F10x_XL_Bank1.lsl" TopLine="85" FilePath="$(PROJECTDIR)\Settings\STM32F10x_XL_Bank1.lsl" Application=""/>
-				<Tab Pos="2" PosX="11" PosY="250" Module="main" TopLine="248" FilePath="$(PROJECTDIR)\..\..\main.c" Application="STM3210X-XL_BANK1"/>
-				<Tab Pos="3" PosX="0" PosY="46" Module="cstart_thumb2" TopLine="29" FilePath="$(PROJECTDIR)\cstart_thumb2.asm" Application="STM3210X-XL_BANK1"/>
-			</Tabs>
-		</Window>
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-							<Control Id="40398" Class="CXTPControlButton"/>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter=".\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText=".\\Settings\\reset_appl.scr"/>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter=".\\Settings\\reset_go_main.scr" TooltipText=".\\Settings\\reset_go_main.scr"/>
-							<Control Id="10053" Class="CControlScriptButton"/>
-							<Control Id="10054" Class="CControlScriptButton"/>
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-							<Control Id="10057" Class="CControlScriptButton"/>
-							<Control Id="10058" Class="CControlScriptButton"/>
-							<Control Id="10059" Class="CControlScriptButton"/>
-							<Control Id="10060" Class="CControlScriptButton"/>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."/>
-								<Control Id="40398" Class="CXTPControlButton"/>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"/>
-								<Control Id="10052" Class="CControlScriptButton"/>
-								<Control Id="10053" Class="CControlScriptButton"/>
-								<Control Id="10054" Class="CControlScriptButton"/>
-								<Control Id="10055" Class="CControlScriptButton"/>
-								<Control Id="10056" Class="CControlScriptButton"/>
-								<Control Id="10057" Class="CControlScriptButton"/>
-								<Control Id="10058" Class="CControlScriptButton"/>
-								<Control Id="10059" Class="CControlScriptButton"/>
-								<Control Id="10060" Class="CControlScriptButton"/>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
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-			</CommandBars>
-		</Layout>
-	</ScreenLayouts>
-	<HitopObjects>
-		<Watches>
-			<Watch Id="O3" Expr="RCC"/>
-			<Watch Id="O4" Expr="tmp"/>
-			<Watch Id="O5" Expr="0x1f&amp;0x20"/>
-			<Watch Id="O1" Expr="SCB"/>
-			<Watch Id="O2" Expr="TimingDelay"/>
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-		<Breakpoints/>
-		<MiniSequences/>
-		<TimerTriggers/>
-	</HitopObjects>
-	<DownloadOptions Verify="0">
-		<PreLoadScript File="" Execute="0" ProjRelative="1"/>
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-	<ExceptionAssistant>
-		<Exceptions Id="ARM low vectors" Count="7">
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-			<Exception Name="Undefined Instruction" Number="1"/>
-			<Exception Name="SWI" Number="2"/>
-			<Exception Name="Prefetch Abort" Number="3"/>
-			<Exception Name="Data abort" Number="4"/>
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-		<Interrupts Id="STR9 2x ARM - PL190" Count="64" VectorCount="32">
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-			<IRQ Name="Debug Receive Command" Number="2"/>
-			<IRQ Name="Debug Transmit Command" Number="3"/>
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-			<IRQ Name="Timer 2" Number="6"/>
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-			<IRQ Name="SCU" Number="10"/>
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-			<IRQ Name="UART 0" Number="16"/>
-			<IRQ Name="UART 1" Number="17"/>
-			<IRQ Name="UART 2" Number="18"/>
-			<IRQ Name="I2 C0" Number="19"/>
-			<IRQ Name="I2 C1" Number="20"/>
-			<IRQ Name="SSP 0" Number="21"/>
-			<IRQ Name="SSP 1" Number="22"/>
-			<IRQ Name="SCU" Number="23"/>
-			<IRQ Name="RTC" Number="24"/>
-			<IRQ Name="WIU all" Number="25"/>
-			<IRQ Name="WIU Group 0" Number="26"/>
-			<IRQ Name="WIU Group 1" Number="27"/>
-			<IRQ Name="WIU Group 2" Number="28"/>
-			<IRQ Name="WIU Group 3" Number="29"/>
-			<IRQ Name="USB" Number="30"/>
-			<IRQ Name="PFW-BC" Number="31"/>
-			<IRQ Name="IRQ 32" Number="32"/>
-			<IRQ Name="IRQ 33" Number="33"/>
-			<IRQ Name="IRQ 34" Number="34"/>
-			<IRQ Name="IRQ 35" Number="35"/>
-			<IRQ Name="IRQ 36" Number="36"/>
-			<IRQ Name="IRQ 37" Number="37"/>
-			<IRQ Name="IRQ 38" Number="38"/>
-			<IRQ Name="IRQ 39" Number="39"/>
-			<IRQ Name="IRQ 40" Number="40"/>
-			<IRQ Name="IRQ 41" Number="41"/>
-			<IRQ Name="IRQ 42" Number="42"/>
-			<IRQ Name="IRQ 43" Number="43"/>
-			<IRQ Name="IRQ 44" Number="44"/>
-			<IRQ Name="IRQ 45" Number="45"/>
-			<IRQ Name="IRQ 46" Number="46"/>
-			<IRQ Name="IRQ 47" Number="47"/>
-			<IRQ Name="IRQ 48" Number="48"/>
-			<IRQ Name="IRQ 49" Number="49"/>
-			<IRQ Name="IRQ 50" Number="50"/>
-			<IRQ Name="IRQ 51" Number="51"/>
-			<IRQ Name="IRQ 52" Number="52"/>
-			<IRQ Name="IRQ 53" Number="53"/>
-			<IRQ Name="IRQ 54" Number="54"/>
-			<IRQ Name="IRQ 55" Number="55"/>
-			<IRQ Name="IRQ 56" Number="56"/>
-			<IRQ Name="IRQ 57" Number="57"/>
-			<IRQ Name="IRQ 58" Number="58"/>
-			<IRQ Name="IRQ 59" Number="59"/>
-			<IRQ Name="IRQ 60" Number="60"/>
-			<IRQ Name="IRQ 61" Number="61"/>
-			<IRQ Name="IRQ 62" Number="62"/>
-			<IRQ Name="IRQ 63" Number="63"/>
-		</Interrupts>
-		<Exceptions Id="cortex-M3 vectors" Count="10">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="NMI" Number="1"/>
-			<Exception Name="HardFault" Number="2"/>
-			<Exception Name="MemManage" Number="3"/>
-			<Exception Name="BusFault" Number="4"/>
-			<Exception Name="UsageFault" Number="5"/>
-			<Exception Name="SVCall" Number="6"/>
-			<Exception Name="DebugMon" Number="7"/>
-			<Exception Name="PendSV" Number="8"/>
-			<Exception Name="SysTick" Number="9"/>
-		</Exceptions>
-		<Interrupts Id="STM32_NVIC" Count="43" VectorCount="43">
-			<Vector Number="0" Enabled="0"/>
-			<Vector Number="1" Enabled="0"/>
-			<Vector Number="2" Enabled="0"/>
-			<Vector Number="3" Enabled="0"/>
-			<Vector Number="4" Enabled="0"/>
-			<Vector Number="5" Enabled="0"/>
-			<Vector Number="6" Enabled="0"/>
-			<Vector Number="7" Enabled="0"/>
-			<Vector Number="8" Enabled="0"/>
-			<Vector Number="9" Enabled="0"/>
-			<Vector Number="10" Enabled="0"/>
-			<Vector Number="11" Enabled="0"/>
-			<Vector Number="12" Enabled="0"/>
-			<Vector Number="13" Enabled="0"/>
-			<Vector Number="14" Enabled="0"/>
-			<Vector Number="15" Enabled="0"/>
-			<Vector Number="16" Enabled="0"/>
-			<Vector Number="17" Enabled="0"/>
-			<Vector Number="18" Enabled="0"/>
-			<Vector Number="19" Enabled="0"/>
-			<Vector Number="20" Enabled="0"/>
-			<Vector Number="21" Enabled="0"/>
-			<Vector Number="22" Enabled="0"/>
-			<Vector Number="23" Enabled="0"/>
-			<Vector Number="24" Enabled="0"/>
-			<Vector Number="25" Enabled="0"/>
-			<Vector Number="26" Enabled="0"/>
-			<Vector Number="27" Enabled="0"/>
-			<Vector Number="28" Enabled="0"/>
-			<Vector Number="29" Enabled="0"/>
-			<Vector Number="30" Enabled="0"/>
-			<Vector Number="31" Enabled="0"/>
-			<Vector Number="32" Enabled="0"/>
-			<Vector Number="33" Enabled="0"/>
-			<Vector Number="34" Enabled="0"/>
-			<Vector Number="35" Enabled="0"/>
-			<Vector Number="36" Enabled="0"/>
-			<Vector Number="37" Enabled="0"/>
-			<Vector Number="38" Enabled="0"/>
-			<Vector Number="39" Enabled="0"/>
-			<Vector Number="40" Enabled="0"/>
-			<Vector Number="41" Enabled="0"/>
-			<Vector Number="42" Enabled="0"/>
-			<IRQ Name="WWDG" Number="0"/>
-			<IRQ Name="PVD" Number="1"/>
-			<IRQ Name="TAMPER" Number="2"/>
-			<IRQ Name="RTC" Number="3"/>
-			<IRQ Name="FLASH" Number="4"/>
-			<IRQ Name="RCC" Number="5"/>
-			<IRQ Name="EXTI 0" Number="6"/>
-			<IRQ Name="EXTI 1" Number="7"/>
-			<IRQ Name="EXTI 2" Number="8"/>
-			<IRQ Name="EXTI 3" Number="9"/>
-			<IRQ Name="EXTI 4" Number="10"/>
-			<IRQ Name="DMA Channel 1" Number="11"/>
-			<IRQ Name="DMA Channel 2" Number="12"/>
-			<IRQ Name="DMA Channel 3" Number="13"/>
-			<IRQ Name="DMA Channel 4" Number="14"/>
-			<IRQ Name="DMA Channel 5" Number="15"/>
-			<IRQ Name="DMA Channel 6" Number="16"/>
-			<IRQ Name="DMA Channel 7" Number="17"/>
-			<IRQ Name="ADC" Number="18"/>
-			<IRQ Name="USB_HP_CAN_TX" Number="19"/>
-			<IRQ Name="USB_LP_CAN_RX 0" Number="20"/>
-			<IRQ Name="CAN_RX 1" Number="21"/>
-			<IRQ Name="CAN_SCE" Number="22"/>
-			<IRQ Name="EXTI 5-9" Number="23"/>
-			<IRQ Name="TIM 1 BRK" Number="24"/>
-			<IRQ Name="TIM 1 UP" Number="25"/>
-			<IRQ Name="TIM 1 TRG COM" Number="26"/>
-			<IRQ Name="TIM 1 CC" Number="27"/>
-			<IRQ Name="TIM 2" Number="28"/>
-			<IRQ Name="TIM 3" Number="29"/>
-			<IRQ Name="TIM 4" Number="30"/>
-			<IRQ Name="I2C 1 EV" Number="31"/>
-			<IRQ Name="I2C 1 ER" Number="32"/>
-			<IRQ Name="I2C 2 EV" Number="33"/>
-			<IRQ Name="I2C 2 ER" Number="34"/>
-			<IRQ Name="SPI 1" Number="35"/>
-			<IRQ Name="SPI 2" Number="36"/>
-			<IRQ Name="USART 1" Number="37"/>
-			<IRQ Name="USART 2" Number="38"/>
-			<IRQ Name="USART 3" Number="39"/>
-			<IRQ Name="EXTI 10-15" Number="40"/>
-			<IRQ Name="RTC ALARM" Number="41"/>
-			<IRQ Name="USB Wakeup" Number="42"/>
-		</Interrupts>
-		<Exceptions Id="STM32xxx_C_D_E" Count="76">
-			<Exception Name="" Number="0"/>
-			<Exception Name="Reset" Number="1"/>
-			<Exception Name="NMI" Number="2"/>
-			<Exception Name="HardFault" Number="3"/>
-			<Exception Name="MemManage" Number="4"/>
-			<Exception Name="BusFault" Number="5"/>
-			<Exception Name="UsageFault" Number="6"/>
-			<Exception Name="Reserved" Number="7"/>
-			<Exception Name="Reserved" Number="8"/>
-			<Exception Name="Reserved" Number="9"/>
-			<Exception Name="Reserved" Number="10"/>
-			<Exception Name="SVCall" Number="11"/>
-			<Exception Name="DebugMon" Number="12"/>
-			<Exception Name="Reserved" Number="13"/>
-			<Exception Name="PendSV" Number="14"/>
-			<Exception Name="SysTick" Number="15"/>
-			<Exception Name="WWDG" Number="16"/>
-			<Exception Name="PVD" Number="17"/>
-			<Exception Name="TAMPER" Number="18"/>
-			<Exception Name="RTC" Number="19"/>
-			<Exception Name="FLASH" Number="20"/>
-			<Exception Name="RCC" Number="21"/>
-			<Exception Name="EXTI_0" Number="22"/>
-			<Exception Name="EXTI_1" Number="23"/>
-			<Exception Name="EXTI_2" Number="24"/>
-			<Exception Name="EXTI_3" Number="25"/>
-			<Exception Name="EXTI_4" Number="26"/>
-			<Exception Name="DMA Channel 1" Number="27"/>
-			<Exception Name="DMA Channel 2" Number="28"/>
-			<Exception Name="DMA Channel 3" Number="29"/>
-			<Exception Name="DMA Channel 4" Number="30"/>
-			<Exception Name="DMA Channel 5" Number="31"/>
-			<Exception Name="DMA Channel 6" Number="32"/>
-			<Exception Name="DMA Channel 7" Number="33"/>
-			<Exception Name="ADC1_2" Number="34"/>
-			<Exception Name="USB_HP_CAN_TX" Number="35"/>
-			<Exception Name="USB_LP_CAN_RX 0" Number="36"/>
-			<Exception Name="CAN_RX 1" Number="37"/>
-			<Exception Name="CAN_SCE" Number="38"/>
-			<Exception Name="EXTI9_5" Number="39"/>
-			<Exception Name="TIM 1 BRK" Number="40"/>
-			<Exception Name="TIM 1 UP" Number="41"/>
-			<Exception Name="TIM 1 TRG COM" Number="42"/>
-			<Exception Name="TIM 1 CC" Number="43"/>
-			<Exception Name="TIM 2" Number="44"/>
-			<Exception Name="TIM 3" Number="45"/>
-			<Exception Name="TIM 4" Number="46"/>
-			<Exception Name="I2C 1 EV" Number="47"/>
-			<Exception Name="I2C 1 ER" Number="48"/>
-			<Exception Name="I2C 2 EV" Number="49"/>
-			<Exception Name="I2C 2 ER" Number="50"/>
-			<Exception Name="SPI 1" Number="51"/>
-			<Exception Name="SPI 2" Number="52"/>
-			<Exception Name="USART 1" Number="53"/>
-			<Exception Name="USART 2" Number="54"/>
-			<Exception Name="USART 3" Number="55"/>
-			<Exception Name="EXTI 10-15" Number="56"/>
-			<Exception Name="RTC ALARM" Number="57"/>
-			<Exception Name="USB Wakeup" Number="58"/>
-			<Exception Name="TIM 8 BRK" Number="59"/>
-			<Exception Name="TIM 8 UP" Number="60"/>
-			<Exception Name="TIM 8 TRG_COM" Number="61"/>
-			<Exception Name="TIM 8 CC" Number="62"/>
-			<Exception Name="ADC 3" Number="63"/>
-			<Exception Name="FSMC" Number="64"/>
-			<Exception Name="SDIO" Number="65"/>
-			<Exception Name="TIM 5" Number="66"/>
-			<Exception Name="SPI 3" Number="67"/>
-			<Exception Name="UART 4" Number="68"/>
-			<Exception Name="UART 5" Number="69"/>
-			<Exception Name="TIM 6" Number="70"/>
-			<Exception Name="TIM 7" Number="71"/>
-			<Exception Name="DMA2 Channel 1" Number="72"/>
-			<Exception Name="DMA2 Channel 2" Number="73"/>
-			<Exception Name="DMA2 Channel 3" Number="74"/>
-			<Exception Name="DMA2 Channel 4_5" Number="75"/>
-		</Exceptions>
-	</ExceptionAssistant>
-	<HiTOPOpen ComponentId="Semihosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<Directories>
-		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\IntroPack\Project\STM32F10x_StdPeriph_Examples\FLASH\Dual_Boot\HiTOP\STM3210X-XL_BANK1\objects\STM3210X-XL_BANK1.abs"/>
-	</Directories>
-	<Applications>
-		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="STM3210X-XL_BANK1">C:\PWA_2007\IntroPack\Project\STM32F10x_StdPeriph_Examples\FLASH\Dual_Boot\HiTOP\STM3210X-XL_BANK1\objects\</AppPath>
-	</Applications>
-	<Component Id="DataTrace"/>
-	<HiTOPOpen ComponentId="SemiHosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<RecentScreenLayouts Active="DebugMode">
-		<Layout Description="IdeMode">
-			<Dockinglayout>
-				<IdeMode>
-					<Summary Panes="9" Client="8" TopContainer="4"/>
-					<Pane-1 ID="40364" Tag="60270280" Type="0" Title="Workspace - ModuleView\nModuleView" DockingCX="200" DockingCY="120" LastHolder="6" DockingHolder="6"/>
-					<Pane-2 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="9" DockingHolder="9"/>
-					<Pane-3 ID="40365" Tag="73295040" Type="0" Title="Workspace - FileView\nFileView" DockingCX="200" DockingCY="120" LastHolder="6" DockingHolder="6"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="9" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="2" Pane-1="6" Pane-2="7" DockingCY="724"/>
-					<Pane-6 Type="1" Panes="2" Pane-1="1" Pane-2="3" Selected="3" DockingCX="200" DockingCY="120"/>
-					<Pane-7 Type="2" Panes="1" Pane-1="8" DockingCX="1076"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="1" Panes="1" Pane-1="2" Selected="2" DockingCX="200" DockingCY="145"/>
-				</IdeMode>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
-						<Position x="0" y="352"/>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="830" cy="485"/>
-						<Position x="0" y="0"/>
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-					<Rectangle State="Maximized">
-						<Size cx="1084" cy="758"/>
-						<Position x="-4" y="-23"/>
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-				<Position x="10" y="6"/>
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-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."/>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."/>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK1\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK1\\Settings\\reset_appl.scr"/>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK1\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK1\\Settings\\reset_go_main.scr"/>
-							<Control Id="10053" Class="CControlScriptButton"/>
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-							<Control Id="10060" Class="CControlScriptButton"/>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."/>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."/>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"/>
-								<Control Id="10052" Class="CControlScriptButton"/>
-								<Control Id="10053" Class="CControlScriptButton"/>
-								<Control Id="10054" Class="CControlScriptButton"/>
-								<Control Id="10055" Class="CControlScriptButton"/>
-								<Control Id="10056" Class="CControlScriptButton"/>
-								<Control Id="10057" Class="CControlScriptButton"/>
-								<Control Id="10058" Class="CControlScriptButton"/>
-								<Control Id="10059" Class="CControlScriptButton"/>
-								<Control Id="10060" Class="CControlScriptButton"/>
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-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."/>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."/>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="32" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767"/>
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-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."></Control>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
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-		<Layout Description="FlashTool">
-			<Dockinglayout>
-				<FlashTool>
-					<Summary Panes="14" Client="8" TopContainer="4"/>
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-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="0" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
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-					<WindowState State="Maximized"/>
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-			</Windows>
-			<CommandBars>
-				<Layout>
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-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<FlashProgramming RAMBase="0x20000000" RAMLength="0x3000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F103xG" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x08000000" Manufacturer="ST">
-			<Sectors Count="0"/>
-		</FlashDevice>
-	</FlashProgramming>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="STM3210X-XL_BANK1" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="STM3210X-XL_BANK1" CodeFile=".\objects\STM3210X-XL_BANK1.htx" LinkerFile=".\objects\STM3210X-XL_BANK1.abs" CurrentBuild="STM3210X-XL_BANK1">
-			<SymbolLoader ProjRel="1" MessageFile="" LoaderVersion="sparmed52.dll : 5.20.736.0" NeedsSymprepRun="0" SymbolFileFormat="V2.4.0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text="..\..\..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text=".\"/>
-						<Path Text="..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\"/>
-						<Path Text="..\..\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM3210X-XL_BANK1" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="STM3210X-XL_BANK1.abs">
-					<IncludePath Path="..\..\" Position="0"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\" Position="4"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\" Position="6"/>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "/>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_XL;USE_STM3210E_EVAL;  BOOT_FROM_BANK1" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -v -Wa-L1 -Wc-w560 -Wc-w523  -Wc-t4  "/>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""/>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl
deleted file mode 100644
index 0271fb5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl
+++ /dev/null
@@ -1,173 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       2k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 96k;
-    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr
deleted file mode 100644
index e3dbe23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk
deleted file mode 100644
index 423d253..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_XL_Bank1.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp
deleted file mode 100644
index 96444cb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp
+++ /dev/null
@@ -1,1110 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103ZG.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722648" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325298" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954438" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="0" y="0"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="844" cy="610"></Size>
-				<Position x="-4" y="-23"></Position>
-			</Rectangle>
-			<Tabs Count="3" Active="2">
-				<Tab Pos="0" PosX="52" PosY="91" Module="STM32F10x_XL_Bank2.lsl" TopLine="69" FilePath="$(PROJECTDIR)\Settings\STM32F10x_XL_Bank2.lsl" Application=""/>
-				<Tab Pos="1" PosX="16" PosY="260" Module="main" TopLine="248" FilePath="$(PROJECTDIR)\..\..\main.c" Application="STM3210X-XL_BANK2"/>
-				<Tab Pos="2" PosX="47" PosY="51" Module="cstart_thumb2" TopLine="29" FilePath="$(PROJECTDIR)\cstart_thumb2.asm" Application="STM3210X-XL_BANK2"/>
-			</Tabs>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941628" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000448" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059268" Alignment="LEFT"/>
-						<Watches/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="_lc_ub_stack"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08080030" Symbol="0x08080030"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x00000000" Symbol="_lc_t2_longveneertarget"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Emulator State">
-			<Tabs>
-				<Tab Pos="0">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
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-			<Watch Id="O5" Expr="0x1f&amp;0x20"/>
-			<Watch Id="O1" Expr="SCB"/>
-			<Watch Id="O2" Expr="TimingDelay"/>
-		</Watches>
-		<Breakpoints/>
-		<MiniSequences/>
-		<TimerTriggers/>
-	</HitopObjects>
-	<DownloadOptions Verify="0">
-		<PreLoadScript File="" Execute="0" ProjRelative="1"/>
-	</DownloadOptions>
-	<ExceptionAssistant>
-		<Exceptions Id="ARM low vectors" Count="7">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="Undefined Instruction" Number="1"/>
-			<Exception Name="SWI" Number="2"/>
-			<Exception Name="Prefetch Abort" Number="3"/>
-			<Exception Name="Data abort" Number="4"/>
-			<Exception Name="IRQ" Number="5"/>
-			<Exception Name="FIQ" Number="6"/>
-		</Exceptions>
-		<Interrupts Id="STR9 2x ARM - PL190" Count="64" VectorCount="32">
-			<IRQ Name="Watchdog" Number="0"/>
-			<IRQ Name="Software interrupt" Number="1"/>
-			<IRQ Name="Debug Receive Command" Number="2"/>
-			<IRQ Name="Debug Transmit Command" Number="3"/>
-			<IRQ Name="Timer 0" Number="4"/>
-			<IRQ Name="Timer 1" Number="5"/>
-			<IRQ Name="Timer 2" Number="6"/>
-			<IRQ Name="Timer 3" Number="7"/>
-			<IRQ Name="USB" Number="8"/>
-			<IRQ Name="USB" Number="9"/>
-			<IRQ Name="SCU" Number="10"/>
-			<IRQ Name="Ethernet MAC" Number="11"/>
-			<IRQ Name="DMA" Number="12"/>
-			<IRQ Name="CAN" Number="13"/>
-			<IRQ Name="IMC" Number="14"/>
-			<IRQ Name="ADC" Number="15"/>
-			<IRQ Name="UART 0" Number="16"/>
-			<IRQ Name="UART 1" Number="17"/>
-			<IRQ Name="UART 2" Number="18"/>
-			<IRQ Name="I2 C0" Number="19"/>
-			<IRQ Name="I2 C1" Number="20"/>
-			<IRQ Name="SSP 0" Number="21"/>
-			<IRQ Name="SSP 1" Number="22"/>
-			<IRQ Name="SCU" Number="23"/>
-			<IRQ Name="RTC" Number="24"/>
-			<IRQ Name="WIU all" Number="25"/>
-			<IRQ Name="WIU Group 0" Number="26"/>
-			<IRQ Name="WIU Group 1" Number="27"/>
-			<IRQ Name="WIU Group 2" Number="28"/>
-			<IRQ Name="WIU Group 3" Number="29"/>
-			<IRQ Name="USB" Number="30"/>
-			<IRQ Name="PFW-BC" Number="31"/>
-			<IRQ Name="IRQ 32" Number="32"/>
-			<IRQ Name="IRQ 33" Number="33"/>
-			<IRQ Name="IRQ 34" Number="34"/>
-			<IRQ Name="IRQ 35" Number="35"/>
-			<IRQ Name="IRQ 36" Number="36"/>
-			<IRQ Name="IRQ 37" Number="37"/>
-			<IRQ Name="IRQ 38" Number="38"/>
-			<IRQ Name="IRQ 39" Number="39"/>
-			<IRQ Name="IRQ 40" Number="40"/>
-			<IRQ Name="IRQ 41" Number="41"/>
-			<IRQ Name="IRQ 42" Number="42"/>
-			<IRQ Name="IRQ 43" Number="43"/>
-			<IRQ Name="IRQ 44" Number="44"/>
-			<IRQ Name="IRQ 45" Number="45"/>
-			<IRQ Name="IRQ 46" Number="46"/>
-			<IRQ Name="IRQ 47" Number="47"/>
-			<IRQ Name="IRQ 48" Number="48"/>
-			<IRQ Name="IRQ 49" Number="49"/>
-			<IRQ Name="IRQ 50" Number="50"/>
-			<IRQ Name="IRQ 51" Number="51"/>
-			<IRQ Name="IRQ 52" Number="52"/>
-			<IRQ Name="IRQ 53" Number="53"/>
-			<IRQ Name="IRQ 54" Number="54"/>
-			<IRQ Name="IRQ 55" Number="55"/>
-			<IRQ Name="IRQ 56" Number="56"/>
-			<IRQ Name="IRQ 57" Number="57"/>
-			<IRQ Name="IRQ 58" Number="58"/>
-			<IRQ Name="IRQ 59" Number="59"/>
-			<IRQ Name="IRQ 60" Number="60"/>
-			<IRQ Name="IRQ 61" Number="61"/>
-			<IRQ Name="IRQ 62" Number="62"/>
-			<IRQ Name="IRQ 63" Number="63"/>
-		</Interrupts>
-		<Exceptions Id="cortex-M3 vectors" Count="10">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="NMI" Number="1"/>
-			<Exception Name="HardFault" Number="2"/>
-			<Exception Name="MemManage" Number="3"/>
-			<Exception Name="BusFault" Number="4"/>
-			<Exception Name="UsageFault" Number="5"/>
-			<Exception Name="SVCall" Number="6"/>
-			<Exception Name="DebugMon" Number="7"/>
-			<Exception Name="PendSV" Number="8"/>
-			<Exception Name="SysTick" Number="9"/>
-		</Exceptions>
-		<Interrupts Id="STM32_NVIC" Count="43" VectorCount="43">
-			<Vector Number="0" Enabled="0"/>
-			<Vector Number="1" Enabled="0"/>
-			<Vector Number="2" Enabled="0"/>
-			<Vector Number="3" Enabled="0"/>
-			<Vector Number="4" Enabled="0"/>
-			<Vector Number="5" Enabled="0"/>
-			<Vector Number="6" Enabled="0"/>
-			<Vector Number="7" Enabled="0"/>
-			<Vector Number="8" Enabled="0"/>
-			<Vector Number="9" Enabled="0"/>
-			<Vector Number="10" Enabled="0"/>
-			<Vector Number="11" Enabled="0"/>
-			<Vector Number="12" Enabled="0"/>
-			<Vector Number="13" Enabled="0"/>
-			<Vector Number="14" Enabled="0"/>
-			<Vector Number="15" Enabled="0"/>
-			<Vector Number="16" Enabled="0"/>
-			<Vector Number="17" Enabled="0"/>
-			<Vector Number="18" Enabled="0"/>
-			<Vector Number="19" Enabled="0"/>
-			<Vector Number="20" Enabled="0"/>
-			<Vector Number="21" Enabled="0"/>
-			<Vector Number="22" Enabled="0"/>
-			<Vector Number="23" Enabled="0"/>
-			<Vector Number="24" Enabled="0"/>
-			<Vector Number="25" Enabled="0"/>
-			<Vector Number="26" Enabled="0"/>
-			<Vector Number="27" Enabled="0"/>
-			<Vector Number="28" Enabled="0"/>
-			<Vector Number="29" Enabled="0"/>
-			<Vector Number="30" Enabled="0"/>
-			<Vector Number="31" Enabled="0"/>
-			<Vector Number="32" Enabled="0"/>
-			<Vector Number="33" Enabled="0"/>
-			<Vector Number="34" Enabled="0"/>
-			<Vector Number="35" Enabled="0"/>
-			<Vector Number="36" Enabled="0"/>
-			<Vector Number="37" Enabled="0"/>
-			<Vector Number="38" Enabled="0"/>
-			<Vector Number="39" Enabled="0"/>
-			<Vector Number="40" Enabled="0"/>
-			<Vector Number="41" Enabled="0"/>
-			<Vector Number="42" Enabled="0"/>
-			<IRQ Name="WWDG" Number="0"/>
-			<IRQ Name="PVD" Number="1"/>
-			<IRQ Name="TAMPER" Number="2"/>
-			<IRQ Name="RTC" Number="3"/>
-			<IRQ Name="FLASH" Number="4"/>
-			<IRQ Name="RCC" Number="5"/>
-			<IRQ Name="EXTI 0" Number="6"/>
-			<IRQ Name="EXTI 1" Number="7"/>
-			<IRQ Name="EXTI 2" Number="8"/>
-			<IRQ Name="EXTI 3" Number="9"/>
-			<IRQ Name="EXTI 4" Number="10"/>
-			<IRQ Name="DMA Channel 1" Number="11"/>
-			<IRQ Name="DMA Channel 2" Number="12"/>
-			<IRQ Name="DMA Channel 3" Number="13"/>
-			<IRQ Name="DMA Channel 4" Number="14"/>
-			<IRQ Name="DMA Channel 5" Number="15"/>
-			<IRQ Name="DMA Channel 6" Number="16"/>
-			<IRQ Name="DMA Channel 7" Number="17"/>
-			<IRQ Name="ADC" Number="18"/>
-			<IRQ Name="USB_HP_CAN_TX" Number="19"/>
-			<IRQ Name="USB_LP_CAN_RX 0" Number="20"/>
-			<IRQ Name="CAN_RX 1" Number="21"/>
-			<IRQ Name="CAN_SCE" Number="22"/>
-			<IRQ Name="EXTI 5-9" Number="23"/>
-			<IRQ Name="TIM 1 BRK" Number="24"/>
-			<IRQ Name="TIM 1 UP" Number="25"/>
-			<IRQ Name="TIM 1 TRG COM" Number="26"/>
-			<IRQ Name="TIM 1 CC" Number="27"/>
-			<IRQ Name="TIM 2" Number="28"/>
-			<IRQ Name="TIM 3" Number="29"/>
-			<IRQ Name="TIM 4" Number="30"/>
-			<IRQ Name="I2C 1 EV" Number="31"/>
-			<IRQ Name="I2C 1 ER" Number="32"/>
-			<IRQ Name="I2C 2 EV" Number="33"/>
-			<IRQ Name="I2C 2 ER" Number="34"/>
-			<IRQ Name="SPI 1" Number="35"/>
-			<IRQ Name="SPI 2" Number="36"/>
-			<IRQ Name="USART 1" Number="37"/>
-			<IRQ Name="USART 2" Number="38"/>
-			<IRQ Name="USART 3" Number="39"/>
-			<IRQ Name="EXTI 10-15" Number="40"/>
-			<IRQ Name="RTC ALARM" Number="41"/>
-			<IRQ Name="USB Wakeup" Number="42"/>
-		</Interrupts>
-		<Exceptions Id="STM32xxx_C_D_E" Count="76">
-			<Exception Name="" Number="0"/>
-			<Exception Name="Reset" Number="1"/>
-			<Exception Name="NMI" Number="2"/>
-			<Exception Name="HardFault" Number="3"/>
-			<Exception Name="MemManage" Number="4"/>
-			<Exception Name="BusFault" Number="5"/>
-			<Exception Name="UsageFault" Number="6"/>
-			<Exception Name="Reserved" Number="7"/>
-			<Exception Name="Reserved" Number="8"/>
-			<Exception Name="Reserved" Number="9"/>
-			<Exception Name="Reserved" Number="10"/>
-			<Exception Name="SVCall" Number="11"/>
-			<Exception Name="DebugMon" Number="12"/>
-			<Exception Name="Reserved" Number="13"/>
-			<Exception Name="PendSV" Number="14"/>
-			<Exception Name="SysTick" Number="15"/>
-			<Exception Name="WWDG" Number="16"/>
-			<Exception Name="PVD" Number="17"/>
-			<Exception Name="TAMPER" Number="18"/>
-			<Exception Name="RTC" Number="19"/>
-			<Exception Name="FLASH" Number="20"/>
-			<Exception Name="RCC" Number="21"/>
-			<Exception Name="EXTI_0" Number="22"/>
-			<Exception Name="EXTI_1" Number="23"/>
-			<Exception Name="EXTI_2" Number="24"/>
-			<Exception Name="EXTI_3" Number="25"/>
-			<Exception Name="EXTI_4" Number="26"/>
-			<Exception Name="DMA Channel 1" Number="27"/>
-			<Exception Name="DMA Channel 2" Number="28"/>
-			<Exception Name="DMA Channel 3" Number="29"/>
-			<Exception Name="DMA Channel 4" Number="30"/>
-			<Exception Name="DMA Channel 5" Number="31"/>
-			<Exception Name="DMA Channel 6" Number="32"/>
-			<Exception Name="DMA Channel 7" Number="33"/>
-			<Exception Name="ADC1_2" Number="34"/>
-			<Exception Name="USB_HP_CAN_TX" Number="35"/>
-			<Exception Name="USB_LP_CAN_RX 0" Number="36"/>
-			<Exception Name="CAN_RX 1" Number="37"/>
-			<Exception Name="CAN_SCE" Number="38"/>
-			<Exception Name="EXTI9_5" Number="39"/>
-			<Exception Name="TIM 1 BRK" Number="40"/>
-			<Exception Name="TIM 1 UP" Number="41"/>
-			<Exception Name="TIM 1 TRG COM" Number="42"/>
-			<Exception Name="TIM 1 CC" Number="43"/>
-			<Exception Name="TIM 2" Number="44"/>
-			<Exception Name="TIM 3" Number="45"/>
-			<Exception Name="TIM 4" Number="46"/>
-			<Exception Name="I2C 1 EV" Number="47"/>
-			<Exception Name="I2C 1 ER" Number="48"/>
-			<Exception Name="I2C 2 EV" Number="49"/>
-			<Exception Name="I2C 2 ER" Number="50"/>
-			<Exception Name="SPI 1" Number="51"/>
-			<Exception Name="SPI 2" Number="52"/>
-			<Exception Name="USART 1" Number="53"/>
-			<Exception Name="USART 2" Number="54"/>
-			<Exception Name="USART 3" Number="55"/>
-			<Exception Name="EXTI 10-15" Number="56"/>
-			<Exception Name="RTC ALARM" Number="57"/>
-			<Exception Name="USB Wakeup" Number="58"/>
-			<Exception Name="TIM 8 BRK" Number="59"/>
-			<Exception Name="TIM 8 UP" Number="60"/>
-			<Exception Name="TIM 8 TRG_COM" Number="61"/>
-			<Exception Name="TIM 8 CC" Number="62"/>
-			<Exception Name="ADC 3" Number="63"/>
-			<Exception Name="FSMC" Number="64"/>
-			<Exception Name="SDIO" Number="65"/>
-			<Exception Name="TIM 5" Number="66"/>
-			<Exception Name="SPI 3" Number="67"/>
-			<Exception Name="UART 4" Number="68"/>
-			<Exception Name="UART 5" Number="69"/>
-			<Exception Name="TIM 6" Number="70"/>
-			<Exception Name="TIM 7" Number="71"/>
-			<Exception Name="DMA2 Channel 1" Number="72"/>
-			<Exception Name="DMA2 Channel 2" Number="73"/>
-			<Exception Name="DMA2 Channel 3" Number="74"/>
-			<Exception Name="DMA2 Channel 4_5" Number="75"/>
-		</Exceptions>
-	</ExceptionAssistant>
-	<HiTOPOpen ComponentId="Semihosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<Directories>
-		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\IntroPack\Project\STM32F10x_StdPeriph_Examples\FLASH\Dual_Boot\HiTOP\STM3210X-XL_BANK2\objects\STM3210X-XL_BANK2.abs"/>
-	</Directories>
-	<Applications>
-		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="STM3210X-XL_BANK2">C:\PWA_2007\IntroPack\Project\STM32F10x_StdPeriph_Examples\FLASH\Dual_Boot\HiTOP\STM3210X-XL_BANK2\objects\</AppPath>
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-	<FlashProgramming RAMBase="0x20000000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F103xG" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x8000000" Manufacturer="ST">
-			<Sectors/>
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-	</FlashProgramming>
-	<Component Id="DataTrace"/>
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-			<General Showed="0"/>
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-					<WindowState State="Maximized"></WindowState>
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-			</Windows>
-			<CommandBars>
-				<CommandBars>
-					<CommandBar BarID="10066" Class="CScriptToolBar" Flags="63" Style="4194304" Title="Execute Script" MRUWidth="32767" CustomizeDialogPresent="0">
-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."></Control>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK2\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK2\\Settings\\reset_appl.scr"></Control>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK2\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Examples\\FLASH\\Dual_Boot\\HiTOP\\STM3210X-XL_BANK2\\Settings\\reset_go_main.scr"></Control>
-							<Control Id="10053" Class="CControlScriptButton"></Control>
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-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."></Control>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"></Control>
-								<Control Id="10052" Class="CControlScriptButton"></Control>
-								<Control Id="10053" Class="CControlScriptButton"></Control>
-								<Control Id="10054" Class="CControlScriptButton"></Control>
-								<Control Id="10055" Class="CControlScriptButton"></Control>
-								<Control Id="10056" Class="CControlScriptButton"></Control>
-								<Control Id="10057" Class="CControlScriptButton"></Control>
-								<Control Id="10058" Class="CControlScriptButton"></Control>
-								<Control Id="10059" Class="CControlScriptButton"></Control>
-								<Control Id="10060" Class="CControlScriptButton"></Control>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="32" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"></BarInfo0>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="333, 49" MRUDockPos="318, 54, 634, 81"></BarInfo1>
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-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"></BarInfo5>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="10066" Id8="4004" Count="10"></DockBar0>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-		<Layout Description="FlashTool">
-			<Dockinglayout>
-				<FlashTool>
-					<Summary Panes="14" Client="8" TopContainer="4"/>
-					<Pane-1 Type="5" Panes="0" Direction="0"/>
-					<Pane-2 Type="5" Panes="0" Direction="1"/>
-					<Pane-3 Type="5" Panes="0" Direction="3"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="12" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="1" Pane-1="6" DockingCY="510"/>
-					<Pane-6 Type="2" Panes="2" Pane-1="7" Pane-2="9" DockingCX="791" DockingCY="510"/>
-					<Pane-7 Type="2" Horiz="1" Panes="1" Pane-1="8" DockingCY="401"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="2" Horiz="1" Panes="1" Pane-1="10" DockingCX="200" DockingCY="105"/>
-					<Pane-10 Type="1" Panes="1" Pane-1="11" Selected="11" DockingCX="200" DockingCY="120"/>
-					<Pane-11 ID="40050" Type="0" Title="Memory - Mem0\nMem0" DockingCX="200" DockingCY="120" LastHolder="10" DockingHolder="10"/>
-					<Pane-12 Type="2" Horiz="1" Panes="1" Pane-1="13" DockingCX="995" DockingCY="101"/>
-					<Pane-13 Type="1" Panes="1" Pane-1="14" Selected="14" DockingCX="728" DockingCY="101"/>
-					<Pane-14 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="13" DockingHolder="13"/>
-				</FlashTool>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="0" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
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-				</Window>
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-				</Window>
-			</Windows>
-			<CommandBars>
-				<Layout>
-					<DockState Count="5" Version="8" ScreenSize="1024, 768">
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-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="9025" Id4="128" Id6="10066" Id7="4004" Count="9"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="STM3210X-XL_BANK2" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="STM3210X-XL_BANK2" CodeFile=".\objects\STM3210X-XL_BANK2.htx" LinkerFile=".\objects\STM3210X-XL_BANK2.abs" CurrentBuild="STM3210X-XL_BANK2">
-			<SymbolLoader ProjRel="1" MessageFile="" LoaderVersion="sparmed52.dll : 5.20.736.0" NeedsSymprepRun="0" SymbolFileFormat="V2.4.0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text="..\..\..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text=".\"/>
-						<Path Text="..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\"/>
-						<Path Text="..\..\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM3210X-XL_BANK2" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="STM3210X-XL_BANK2.abs">
-					<IncludePath Path="..\..\" Position="0"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"/>
-					<IncludePath Path="..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\" Position="4"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"/>
-					<IncludePath Path="..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\" Position="6"/>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "/>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_XL;USE_STM3210E_EVAL;  BOOT_FROM_BANK2" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -v -Wa-L1 -Wc-w560 -Wc-w523  -Wc-t4  "/>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""/>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/STM32F10x_XL_Bank2.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/STM32F10x_XL_Bank2.lsl
deleted file mode 100644
index 72adf78..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/STM32F10x_XL_Bank2.lsl
+++ /dev/null
@@ -1,173 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08080000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08080000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 96k;
-    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/StartupScript.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/StartupScript.scr
deleted file mode 100644
index e3dbe23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/StartupScript.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl
deleted file mode 100644
index 3e6d303..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl
+++ /dev/null
@@ -1,287 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  arm_arch.lsl
-//
-//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
-//
-//  Description :  Generic LSL file for ARM architectures
-//
-//  Copyright 2008-2009 Altium BV
-//
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __STACK
-#  define __STACK                       32k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        32k
-#endif
-#ifndef __STACK_FIQ
-#  define __STACK_FIQ                   8
-#endif
-#ifndef __STACK_IRQ
-#  define __STACK_IRQ                   8
-#endif
-#ifndef __STACK_SVC
-#  define __STACK_SVC                   8
-#endif
-#ifndef __STACK_ABT
-#  define __STACK_ABT                   8
-#endif
-#ifndef __STACK_UND
-#  define __STACK_UND                   8
-#endif
-#ifndef __PROCESSOR_MODE
-#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
-#endif
-#ifndef __IRQ_BIT
-#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
-#endif
-#ifndef __FIQ_BIT
-#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
-#endif
-
-#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
-
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_ADDR
-#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
-#endif
-
-#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-#  ifndef __NR_OF_VECTORS
-#    define __NR_OF_VECTORS             16
-#  endif
-#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
-#else
-#  ifdef __PIC_VECTORS
-#    define __VECTOR_TABLE_SIZE         64
-#  else
-#    ifdef __FIQ_HANDLER_INLINE
-#      define __VECTOR_TABLE_SIZE       28
-#      define __NR_OF_VECTORS           7
-#    else
-#      define __VECTOR_TABLE_SIZE       32
-#      define __NR_OF_VECTORS           8
-#    endif
-#  endif
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_SPACE
-#  undef __VECTOR_TABLE_RAM_COPY
-#endif
-
-#ifndef __XVWBUF
-#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
-#endif
-
-#define BOUNDS_GROUP_NAME       grp_bounds
-#define BOUNDS_GROUP_SELECT     "bounds"
-
-architecture ARM
-{
-        endianness
-        {
-                little;
-                big;
-        }
-
-        space linear
-        {
-                id = 1;
-                mau = 8;
-                map (size = 4G, dest = bus:local_bus);
-
-                copytable
-                (
-                        align = 4,
-                        copy_unit = 1,
-                        dest = linear
-                );
-
-                start_address
-                (
-                        // It is not strictly necessary to define a run_addr for _START
-                        // because hardware starts execution at address 0x0 which should
-                        // be the vector table with a jump to the relocatable _START, but
-                        // an absolute address can prevent the branch to be out-of-range.
-                        // Or _START may be the entry point at reset and the reset handler
-                        // copies the vector table to address 0x0 after some ROM/RAM memory
-                        // re-mapping. In that case _START should be at a fixed address
-                        // in ROM, specifically the alias of address 0x0 before memory
-                        // re-mapping.
-#ifdef __START
-                        run_addr = __START,
-#endif
-                        symbol = "_START"
-                );
-
-                stack "stack"
-                (
-#ifdef __STACK_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size = __STACK,
-                        grows = high_to_low
-                );
-
-                heap "heap"
-                (
-#ifdef __HEAP_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size=__HEAP
-                );
-
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                stack "stack_fiq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_FIQ,
-                        grows = high_to_low
-                );
-                stack "stack_irq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_IRQ,
-                        grows = high_to_low
-                );
-                stack "stack_svc"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_SVC,
-                        grows = high_to_low
-                );
-                stack "stack_abt"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_ABT,
-                        grows = high_to_low
-                );
-                stack "stack_und"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_UND,
-                        grows = high_to_low
-                );
-#endif
-
-#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
-# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                }
-#  else
-#    ifdef __PIC_VECTORS
-                // vector table with ldrpc instructions from handler table
-                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_ldrpc",
-                                              template_symbol = "_lc_vector_ldrpc",
-                                              vector_prefix = "_vector_ldrpc_",
-                                              fill = loop
-                                            )
-                {
-                }
-                // subsequent vector table (data pool) with addresses of handlers
-                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
-                                               template = ".text.handler_address",
-                                               template_symbol = "_lc_vector_handler",
-                                               vector_prefix = "_vector_",
-                                               fill = loop[-32],
-                                               no_inline
-                                             )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    else
-                // vector table with branch instructions to handlers
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_branch",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    endif
-#  endif
-#endif
-                section_layout
-                {
-#if defined(__NO_AUTO_VECTORS)
-                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
-                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
-#endif
-#ifdef __VECTOR_TABLE_RAM_SPACE
-                        // reserve space to copy vector table from ROM to RAM
-                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
-                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
-#endif
-#ifdef __VECTOR_TABLE_RAM_COPY
-                        // provide copy address symbols for copy routine
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
-#else
-                        // prevent copy: copy address equals orig address
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
-#endif
-                        // define buffer for string input via Crossview Pro debugger
-                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
-
-                        // define labels for bounds begin and end as used in C library
-#ifndef BOUNDS_GROUP_REDEFINED
-                        group BOUNDS_GROUP_NAME (ordered, contiguous)
-                        {
-                                select BOUNDS_GROUP_SELECT;
-                        }
-#endif
-                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
-                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
-
-#ifdef __HEAPADDR
-                        group ( ordered, run_addr=__HEAPADDR )
-                        {
-                                select "heap";
-                        }
-#endif
-#ifdef __STACKADDR
-                        group ( ordered, run_addr=__STACKADDR )
-                        {
-                                select "stack";
-                        }
-#endif
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                        // symbol to set mode bits and interrupt disable bits
-                        // in cstart module before calling the application (main)
-                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
-#endif
-                }
-        }
-
-        bus local_bus
-        {
-                mau = 8;
-                width = 32;
-        }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk
deleted file mode 100644
index a3b94a1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_XL_Bank2.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr
deleted file mode 100644
index 3e9c066..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr
+++ /dev/null
@@ -1,12 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application & Go main 
-
-// Reset    
-RESET TARGET
-
-
-// execute program till main
-Go UNTIL main
-wait
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt
deleted file mode 100644
index eca625f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt
+++ /dev/null
@@ -1,2262 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>STM32F10X_XL_BANK1</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>8000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>1</RunSim>
-        <RunTarget>0</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\STM32F10X_XL\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>255</CpuCode>
-      <Books>
-        <Book>
-          <Number>0</Number>
-          <Title>Reference Manual</Title>
-          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
-        </Book>
-      </Books>
-      <DllOpt>
-        <SimDllName>SARMCM3.DLL</SimDllName>
-        <SimDllArguments></SimDllArguments>
-        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
-        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
-        <TargetDllName>SARMCM3.DLL</TargetDllName>
-        <TargetDllArguments></TargetDllArguments>
-        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
-        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
-      </DllOpt>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>1</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>BIN\UL2CM3.DLL</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
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-        <FloatingRect_bottom>250</FloatingRect_bottom>
-        <FloatingRect_right>600</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35885</WinId>
-        <ItemNo>43</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>0</AnchorWinID>
-        <AnchorWinName></AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>2</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35886</WinId>
-        <ItemNo>44</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35885</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35887</WinId>
-        <ItemNo>45</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35886</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35888</WinId>
-        <ItemNo>46</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35887</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35889</WinId>
-        <ItemNo>47</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35888</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35890</WinId>
-        <ItemNo>48</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35889</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35891</WinId>
-        <ItemNo>49</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35890</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35892</WinId>
-        <ItemNo>50</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35891</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35893</WinId>
-        <ItemNo>51</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35892</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35894</WinId>
-        <ItemNo>52</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35893</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35895</WinId>
-        <ItemNo>53</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35894</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35896</WinId>
-        <ItemNo>54</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35895</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35897</WinId>
-        <ItemNo>55</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35896</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35898</WinId>
-        <ItemNo>56</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35897</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35899</WinId>
-        <ItemNo>57</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35898</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35900</WinId>
-        <ItemNo>58</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35899</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35901</WinId>
-        <ItemNo>59</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35900</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35902</WinId>
-        <ItemNo>60</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35901</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35903</WinId>
-        <ItemNo>61</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35902</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35904</WinId>
-        <ItemNo>62</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35903</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
-        <ActiveTab>0</ActiveTab>
-        <Visible>0</Visible>
-        <Dynamic>0</Dynamic>
-      </Window>
-      <Window>
-        <WinId>35905</WinId>
-        <ItemNo>63</ItemNo>
-        <Name>not set</Name>
-        <AnchorWinID>35904</AnchorWinID>
-        <AnchorWinName>???</AnchorWinName>
-        <OtherWinID>0</OtherWinID>
-        <OtherWinName></OtherWinName>
-        <WinType>1</WinType>
-        <DockType>4</DockType>
-        <DockLocation>2</DockLocation>
-        <Pinned>0</Pinned>
-        <DockedRect_top>0</DockedRect_top>
-        <DockedRect_left>0</DockedRect_left>
-        <DockedRect_bottom>600</DockedRect_bottom>
-        <DockedRect_right>210</DockedRect_right>
-        <FloatingRect_top>0</FloatingRect_top>
-        <FloatingRect_left>0</FloatingRect_left>
-        <FloatingRect_bottom>600</FloatingRect_bottom>
-        <FloatingRect_right>250</FloatingRect_right>
-        <ContainerPercent>100</ContainerPercent>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj
deleted file mode 100644
index d63a62b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj
+++ /dev/null
@@ -1,1007 +0,0 @@
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-  <Header>### uVision Project, (C) Keil Software</Header>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project
deleted file mode 100644
index cb11100..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project
+++ /dev/null
@@ -1,196 +0,0 @@
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-		</link>
-		<link>
-			<name>Doc</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld
deleted file mode 100644
index f9c3fbf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32f10x_flash_xl_bank1.ld
-**
-**  Abstract    : Linker script for loading program in BANK1 of STM32F103ZG flash 
-**                memory.
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of 96K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.cproject b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.cproject
deleted file mode 100644
index 8134951..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.cproject
+++ /dev/null
@@ -1,263 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-<storageModule moduleId="org.eclipse.cdt.core.settings">
-<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
-<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
-<externalSettings/>
-<extensions>
-<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-</extensions>
-</storageModule>
-<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-<configuration artifactExtension="elf" artifactName="STM32F10X_XL_BANK2" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
-<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
-<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
-<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
-<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
-<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
-<option id="com.atollic.truestudio.common_options.target.endianess.1578134158" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-<option id="com.atollic.truestudio.common_options.target.mcpu.1314431980" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
-<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
-</tool>
-<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
-<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
-<listOptionValue builtIn="false" value="&quot;../..\..\&quot;"/>
-<listOptionValue builtIn="false" value="../../../../../../../Libraries/CMSIS/CM3/CoreSupport"/>
-<listOptionValue builtIn="false" value="../../../../../../../Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x"/>
-<listOptionValue builtIn="false" value="../../../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
-<listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL"/>
-<listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL/Common"/>
-<listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
-</option>
-<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
-<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
-<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
-<listOptionValue builtIn="false" value="STM32F10X_XL"/>
-<listOptionValue builtIn="false" value="BOOT_FROM_BANK2"/>
-</option>
-<option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-<option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
-<option id="com.atollic.truestudio.common_options.target.instr_set.1997653104" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.586288316" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
-<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
-<option id="com.atollic.truestudio.gcc.misc.otherflags.1820971968" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os -w" valueType="string"/>
-<inputType id="com.atollic.truestudio.gcc.input.377284588" superClass="com.atollic.truestudio.gcc.input"/>
-</tool>
-<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
-<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-<option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
-<option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32F10X_XL_BANK2\stm32f10x_flash_xl_bank2.ld}" valueType="string"/>
-<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
-<inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
-<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-</inputType>
-</tool>
-<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
-<option id="com.atollic.truestudio.gpp.symbols.defined.26443420" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
-<listOptionValue builtIn="false" value="STM32F10X_HD"/>
-<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
-</option>
-<option id="com.atollic.truestudio.common_options.target.endianess.1289217812" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-<option id="com.atollic.truestudio.common_options.target.mcpu.144019967" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
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-<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
-<parser enabled="true"/>
-</scannerInfoProvider>
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-<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
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-<openAction enabled="true" filePath=""/>
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-<scannerInfoProvider id="specsFile">
-<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
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-</storageModule>
-<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
-</cconfiguration>
-</storageModule>
-<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
-</storageModule>
-</cproject>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project
deleted file mode 100644
index d32fbd6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project
+++ /dev/null
@@ -1,196 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>STM32F10X_XL_BANK2</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-				<dictionary>
-					<key>?name?</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.append_environment</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildArguments</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildCommand</key>
-					<value>make</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildLocation</key>
-					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.contents</key>
-					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
-					<value>false</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.stopOnError</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
-					<value>true</value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>CMSIS</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>Doc</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
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-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
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-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index a3b6606..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM3210E-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F103ZG
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld
deleted file mode 100644
index 2b96afe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32f10x_flash_xl_bank2.ld
-**
-**  Abstract    : Linker script for loading program in BANK2 of STM32F103ZG flash 
-**                memory.
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of 96K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08080000, LENGTH = 512K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
deleted file mode 100644
index 9a1b53e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Dual_Boot/main.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup Dual_Boot
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-/* Uncomment one of the lines below to select which bank to boot from  */
-#if !defined(BOOT_FROM_BANK1) && !defined(BOOT_FROM_BANK2)
-//#define BOOT_FROM_BANK1           /* The program will be loaded on Flash Bank1 */
-//#define BOOT_FROM_BANK2           /* The program will be loaded on Flash Bank2 */
-#endif
-
-#if defined(BOOT_FROM_BANK1)
- #define MESSAGE4   " Running from Bank 1"
-#elif defined(BOOT_FROM_BANK2)
- #define MESSAGE4   " Running from Bank 2"
-#else
- #error "Select Boot from Bank1 or Bank2 using defines:BOOT_FROM_BANK1 or BOOT_FROM_BANK2!"
-#endif
-
-#define MESSAGE1   "  STM32 XL Density  "
-#define MESSAGE2   " Device running on  "
-#define MESSAGE3   "   STM3210E-EVAL    "
-
-#define MESSAGE5   " Joystick-DOWN: reset BFB2"
-#define MESSAGE6   "  bit to Boot from Bank2  "
-#define MESSAGE7   " Joystick-UP: set BFB2    "
-#define MESSAGE8   "  bit to Boot from Bank1  "
-
-#define MESSAGE9   " Joystick-SEL: program to "
-#define MESSAGE10  " 0x0 the base @ of Bank1/2"
-
-#define MESSAGE11   "  Operation Failed !"
-#define MESSAGE12   "Bank 1/2 base @ -> 0"
-
-#define BANK1_START_ADDRESS       0x08000000
-#define BANK2_START_ADDRESS       0x08080000
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-
-static __IO uint32_t TimingDelay;
-RCC_ClocksTypeDef RCC_Clocks;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured,
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-
-  /* Set the vector table address */
-#if defined(BOOT_FROM_BANK1)
-  /* Set the vector table to the Bank1 start address */
-  NVIC_SetVectorTable(NVIC_VectTab_FLASH, BANK1_START_ADDRESS);
-#elif defined(BOOT_FROM_BANK2)
-  /* Set the vector table to the Bank1 start address */
-  NVIC_SetVectorTable(NVIC_VectTab_FLASH, BANK2_START_ADDRESS);
-#endif /* BOOT_FROM_BANK1 */
-
-  /* Initialize LEDs, Buttons and LCD on STM3210E-EVAL board *****************/
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* SysTick end of count event each 10ms */
-  RCC_GetClocksFreq(&RCC_Clocks);
-  SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
-
-  /* Configure the Joystick buttons */
-  STM_EVAL_PBInit(BUTTON_UP, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_SEL, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_DOWN, BUTTON_MODE_GPIO);
-  /* Initialize the LCD */
-  STM3210E_LCD_Init();
-
-  /* Display message on STM3210E-EVAL LCD *************************************/
-  /* Clear the LCD */
-  LCD_Clear(LCD_COLOR_WHITE);
-
-  /* Set the LCD Back Color */
-#if defined(BOOT_FROM_BANK1)
-  LCD_SetBackColor(LCD_COLOR_BLUE);
-#elif defined(BOOT_FROM_BANK2)
-  LCD_SetBackColor(LCD_COLOR_RED);
-#endif /* BOOT_FROM_BANK1 */
-
-  /* Set the LCD Text Color */
-  LCD_SetTextColor(LCD_COLOR_WHITE);
-  LCD_DisplayStringLine(LCD_LINE_0, MESSAGE1);
-  LCD_DisplayStringLine(LCD_LINE_1, MESSAGE2);
-  LCD_DisplayStringLine(LCD_LINE_2, MESSAGE3);
-  LCD_DisplayStringLine(LCD_LINE_4, MESSAGE4);
-
-  LCD_SetFont(&Font12x12);
-  LCD_DisplayStringLine(LCD_LINE_12, MESSAGE5);
-  LCD_DisplayStringLine(LCD_LINE_13, MESSAGE6);
-  LCD_DisplayStringLine(LCD_LINE_15, MESSAGE7);
-  LCD_DisplayStringLine(LCD_LINE_16, MESSAGE8);
-  LCD_DisplayStringLine(LCD_LINE_18, MESSAGE9);
-  LCD_DisplayStringLine(LCD_LINE_19, MESSAGE10);
-  LCD_SetFont(&Font16x24);
-
-  /* Turn on leds available on STM3210E-EVAL **********************************/
-  STM_EVAL_LEDOn(LED1);
-  STM_EVAL_LEDOn(LED2);
-  STM_EVAL_LEDOn(LED3);
-  STM_EVAL_LEDOn(LED4);
-
-  /* Infinite loop */
-  while (1)
-  {
-    /*--- If Joystick DOWN button is pushed, reset BFB2 bit to enable boot from Bank2
-          (active after next reset, w/ Boot pins set in Boot from Flash memory position ---*/
-    if (STM_EVAL_PBGetState(BUTTON_DOWN) == 0)
-    {
-      /* Reset BFB2 bit to enable boot from Flash Bank2 */
-      FLASH_Unlock();
-      FLASH_EraseOptionBytes();
-
-      if (FLASH_BootConfig(FLASH_BOOT_Bank2) == FLASH_COMPLETE)
-      {
-        /* Generate System Reset to load the new option byte values */
-        NVIC_SystemReset();
-      }
-      else
-      {
-        /* Display information */
-        LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
-      }
-    }
-
-    /*--- If Joystick UP button is pushed, set BFB2 bit to enable boot from Bank1
-          (active after next reset, w/ Boot pins set in Boot from Flash memory position ---*/
-    if (STM_EVAL_PBGetState(BUTTON_UP) == 0)
-    {
-      /* Set BFB2 bit to enable boot from Flash Bank2 */
-      FLASH_Unlock();
-      FLASH_EraseOptionBytes();
-      if (FLASH_BootConfig(FLASH_BOOT_Bank1) == FLASH_COMPLETE)
-      {
-        /* Generate System Reset to load the new option byte values */
-        NVIC_SystemReset();
-      }
-      else
-      {
-        /* Display information */
-        LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
-      }
-    }
-
-    /*--- If Joystick UP button is pushed, program the content of address 0x08080000
-          (base address of Bank2) and 0x08000000(base address of Bank1) to 0x00 --*/
-    if (STM_EVAL_PBGetState(BUTTON_SEL) == 0)
-    {
-      FLASH_Unlock();
-      /* Erase stack pointer value at Bank 2 start address */
-      FLASH_ProgramWord(BANK2_START_ADDRESS, 0x00);
-      /* Erase stack pointer value at Bank 1 start address */
-      FLASH_ProgramWord(BANK1_START_ADDRESS, 0x00);
-      FLASH_Lock();
-
-      LCD_ClearLine(LCD_LINE_7);
-      LCD_ClearLine(LCD_LINE_8);
-      LCD_ClearLine(LCD_LINE_9);
-
-      /* Check if erase operation is OK */
-      if ((uint32_t)(*(uint32_t *)BANK2_START_ADDRESS) ==  0x00)
-      {
-        if ((uint32_t)(*(uint32_t *)BANK1_START_ADDRESS) !=  0x00)
-        {
-          /* Display information */
-          LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
-        }
-        else
-        {
-          /* Display information */
-          LCD_DisplayStringLine(LCD_LINE_6, MESSAGE12);
-        }
-      }
-      else
-      {
-        /* Display information */
-        LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
-      }
-    }
-
-    /* Toggle LD3 */
-    STM_EVAL_LEDToggle(LED3);
-
-    /* Insert 50 ms delay */
-    Delay(5);
-
-    /* Toggle LD2 */
-    STM_EVAL_LEDToggle(LED2);
-
-    /* Insert 100 ms delay */
-    Delay(10);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in 10 ms.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{
-  TimingDelay = nTime;
-
-  while (TimingDelay != 0);
-}
-
-/**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
-  */
-void TimingDelay_Decrement(void)
-{
-  if (TimingDelay != 0x00)
-  {
-    TimingDelay--;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h
deleted file mode 100644
index dd55adf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Dual_Boot/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-#include "stm3210e_eval_lcd.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void TimingDelay_Decrement(void);
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt
deleted file mode 100644
index b27b7b4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
-  @page Dual_Boot XL-Density devices FLASH Dual Boot capability example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FLASH/Dual_Boot/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the XL-Density devices FLASH Dual Boot capability example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demonstrates the dual Flash boot capability of XL-Density devices:
-boot from Flash memory Bank1 or Bank2.
-
-At startup, if BFB2 option bit is reset and the boot pins are in the boot from main
-Flash memory configuration, the device boots from Flash memory Bank1 or Bank2,
-depending on the activation of the bank. The active banks are checked in the following
-order: Bank2, followed by Bank1.
-The active bank is identified by the value programmed at the base address of the 
-bank (corresponding to the initial stack pointer value in the interrupt vector table). 
-For further details, please refer to AN2606 "STM32 microcontroller system memory boot mode."
-
-To demonstrate this feature, this example provides two programs:
-  - 1st program will be loaded in Flash Bank1 (starting from @ 0x08000000), for this
-     you have to enable BOOT_FROM_BANK1 define in main.c 
-  - 2nd program will be loaded in Flash Bank2 (starting from @ 0x08080000), for this
-     you have to enable BOOT_FROM_BANK2 define in main.c 
-
-Once these two programs are loaded and boot pins set in boot from Flash memory,
-after reset the device will boot from Bank1 (default). Then you have to follow
-the instructions provided on the LCD:
-  - "Joystick-DOWN: reset BFB2 bit to Boot from Bank2" => when pushing the Joystick
-     DOWN button, BFB2 option bit will be reset then a system (SW) reset will be
-     generated. After startup from reset, the device will boot from Bank2. 
-      - Note: when booting from Bank2 the same menu will be displayed
- 
-  - "Joystick-UP: set BFB2 bit to Boot from Bank1" => when pushing the Joystick
-     UP button, BFB2 option bit will be set then a system (SW) reset will be
-     generated. After startup from reset, the device will boot from Bank1.       
- 
-  - "Joystick-SEL: program to 0x0 the base @ of Bank1/2" => when pushing the Joystick
-     SEL button, the content of address 0x08080000 and 0x08000000 will be programmed to 0x0.
-       - If the program was previously booting from Bank2 (i.e. BFB2 bit is reset), 
-         in this case after reset no program is executed and the Bootloader code
-         is executed instead. 
-       - If the program was previously booting from Bank1 (i.e. BFB2 bit is set), 
-         in this case after reset no program is executed.
-       - You have to load again the two programs to Bank1 and Bank2.
- 
-@b Important Note
-=================
-When BFB2 bit is cleared and Bank2 or/and Bank1 contain valid user application code,
-the Bootloader will always jump to this code and never continue normal code execution 
-(i.e. it’s no more possible to use the Bootloader for code upgrade and option bytes
-programming). As consequence, if the user has cleared BFB2 bit (to boot from Bank2),
-in order to be able to execute the embedded Bootloader code he has to: 
-   - either, set BFB2 bit to 1
-   - or, program the content of address 0x08080000 and 0x08000000 to 0x0
-=> This example allows performing the two actions described above.
-
-
-@par Directory contents 
-
-  - FLASH/Dual_Boot/stm32f10x_conf.h    Library Configuration file
-  - FLASH/Dual_Boot/stm32f10x_it.h      Interrupt handlers header file
-  - FLASH/Dual_Boot/stm32f10x_it.c      Interrupt handlers
-  - FLASH/Dual_Boot/main.c              Main program
-  - FLASH/Dual_Boot/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) 
-    evaluation board and can be easily tailored to any development board. 
-
- 
-@par How to use it ? 
-    
-In order to load the IAP code, you have to do the following:
- - EWARM:
-    - Open the Project.eww workspace
-    - In the workspace toolbar select the project config:
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor)
-    - Rebuild all files: Project->Rebuild all
-    - Load project image: Project->Debug
-    - Run program: Debug->Go(F5)
-
- - HiTOP
-    - Open the HiTOP toolchain.
-    - Browse to open:
-        -STM32F10X_XL_BANK1.htp: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                             already defined in the project preprocessor)
-        -STM32F10X_XL_BANK2.htp: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                             already defined in the project preprocessor)  
-     - A "Download application" window is displayed, click "cancel".
-     - Rebuild all files: Project->Rebuild all
-     - Load project image : Click "ok" in the "Download application" window.
-     - Run the "RESET_GO_MAIN" script to set the PC at the "main"
-     - Run program: Debug->Go(F5).
-     
- - MDK-ARM 
-    - Open Project.uvproj project
-    - In the build toolbar select the project config:
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor)  
-    - Rebuild all files: Project->Rebuild all target files
-    - Load project image: Debug->Start/Stop Debug Session
-    - Run program: Debug->Run (F5)
-
- - TrueSTUDIO 
-    - Open the TrueSTUDIO toolchain.
-    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
-      directory.
-    - Click on File->Import, select General->'Existing Projects into Workspace' 
-      and then click "Next". 
-    - Browse to the TrueSTUDIO workspace directory and select the project: 
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor) 
-    - Under Windows->Preferences->General->Workspace->Linked Resources, add 
-      a variable path named "CurPath" which points to the folder containing
-      "Libraries", "Project" and "Utilities" folders.
-    - Rebuild all project files: Select the project in the "Project explorer" 
-      window then click on Project->build project menu.
-    - Run program: Select the project in the "Project explorer" window then click 
-      Run->Debug (F11)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.  
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h
deleted file mode 100644
index c4654a7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Dual_Boot/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/readme.txt
deleted file mode 100644
index 095d3d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/readme.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
-  @page FLASH_Program FLASH Program example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FLASH/Program/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FLASH Program example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to program the STM32F10x FLASH.
-
-After Reset, the Flash memory Program/Erase Controller is locked. To unlock it,
-the FLASH_Unlock function is used.
-Before programming the desired addresses, an erase operation is performed using 
-the flash erase page feature. The erase procedure starts with the calculation of
-the number of pages to be used. Then all these pages will be erased one by one by
-calling FLASH_ErasePage function. 
-
-Once this operation is finished, the programming operation will be performed by 
-using the FLASH_ProgramWord function. The written data is then checked and the
-result of the programming operation is stored into the MemoryProgramStatus variable.
-
-@par Directory contents 
-
-  - FLASH/Program/stm32f10x_conf.h    Library Configuration file
-  - FLASH/Program/stm32f10x_it.h      Interrupt handlers header file
-  - FLASH/Program/stm32f10x_it.c      Interrupt handlers
-  - FLASH/Program/main.c              Main program
-  - FLASH/Program/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and 
-    STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored 
-    to any other supported device and development board. 
- 
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.  
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c
deleted file mode 100644
index 65e24ee..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Program/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FLASH_Program
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h
deleted file mode 100644
index 2596f20..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Program/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt
deleted file mode 100644
index 0d0d2a5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
-  @page FLASH_Write_Protection FLASH Write Protection example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FLASH/Write_Protection/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FLASH Write Protection example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to enable and disable the write protection
-for the STM32F10x FLASH:
-
-- Enable Write protection: 
-   To enable the Write Protection, uncomment the line "#define WRITE_PROTECTION_ENABLE"
-   in main.c file.  
-   To protect a set of pages, the user has to call the function FLASH_EraseOptionBytes
-   to erase all the option bytes then to call the function  FLASH_EnableWriteProtection.
-   The parameter of the later function will define the number of pages to be protected
-   (The desired pages and already protected pages).
-   To load the new option byte values, a system Reset is necessary, for this, the
-   function NVIC_SystemReset() is used.
- 
-- Disable Write protection:
-   To disable the Write Protection, uncomment the line "#define WRITE_PROTECTION_DISABLE"
-   in main.c file.
-   To disable the write protection of the STM32F10x Flash, an erase of the Option 
-   Bytes is necessary by the function FLASH_EraseOptionBytes, then call the function 
-   FLASH_EnableWriteProtection to protect the pags that are already protected.
-   To load the new option byte values, a system Reset is necessary, for this, the
-   function NVIC_SystemReset() is used.
-   
-- Program the selected pages:
-  To program the desired pages (if the flash is not write protected) uncomment the line
-  "#define FLASH_PAGE_PROGRAM" in main.c file. 
-
-If the desired pages are not write protected, an erase and a write operation are
-performed.
-
-
-@par Directory contents 
-
-  - FLASH/Write_Protection/stm32f10x_conf.h     Library Configuration file
-  - FLASH/Write_Protection/stm32f10x_it.h       Interrupt handlers header file
-  - FLASH/Write_Protection/stm32f10x_it.c       Interrupt handlers
-  - FLASH/Write_Protection/main.c               Main program
-  - FLASH/Write_Protection/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    High-Density Value line, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.  
-
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h
deleted file mode 100644
index 7277913..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Write_Protection/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c
deleted file mode 100644
index c8862d6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Write_Protection/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FLASH_Write_Protection
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h
deleted file mode 100644
index 3ee053b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Write_Protection/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c
deleted file mode 100644
index 584f560..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FLASH/Write_Protection/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt
deleted file mode 100644
index 46fb146..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  @page FSMC_NAND FSMC NAND example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NAND/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC NAND example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the FSMC firmware library and
-an associate driver to perform erase/read/write operations on the NAND512W3A2 memory
-mounted on STM3210E-EVAL board.
-
-@par Directory contents 
-
-  - FSMC/NAND/stm32f10x_conf.h    Library Configuration file
-  - FSMC/NAND/stm32f10x_it.c      Interrupt handlers
-  - FSMC/NAND/stm32f10x_it.h      Header for stm32f10x_it.c
-  - FSMC/NAND/main.c              Main program
-  - FSMC/NAND/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-    
-  - STM3210E-EVAL Set-up 
-    - This example runs on STMicroelectronics STM3210E-EVAL evaluation board RevD.
-
-@note make sure that the Jumper 7 (JP7) is in position 1<-->2. 
-    
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h
deleted file mode 100644
index be40441..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NAND/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c
deleted file mode 100644
index 24834be..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NAND/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_NAND
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h
deleted file mode 100644
index f5bb61c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NAND/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
deleted file mode 100644
index 8a3e123..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210e_eval_fsmc_nor.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_NOR
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BUFFER_SIZE        0x400
-#define WRITE_READ_ADDR    0x8000
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t TxBuffer[BUFFER_SIZE];
-uint16_t RxBuffer[BUFFER_SIZE];
-uint32_t WriteReadStatus = 0, Index = 0;
-NOR_IDTypeDef NOR_ID;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize Leds mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  
-  /* Write/read to/from FSMC SRAM memory  *************************************/
-  /* Enable the FSMC Clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-
-  /* Configure FSMC Bank1 NOR/SRAM2 */
-  NOR_Init();
- 
-  /* Read NOR memory ID */
-  NOR_ReadID(&NOR_ID);
-
-  NOR_ReturnToReadMode();
-
-  /* Erase the NOR memory block to write on */
-  NOR_EraseBlock(WRITE_READ_ADDR);
-
-  /* Write data to FSMC NOR memory */
-  /* Fill the buffer to send */
-  Fill_Buffer(TxBuffer, BUFFER_SIZE, 0x3210);
-  NOR_WriteBuffer(TxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);
-
-  /* Read data from FSMC NOR memory */
-  NOR_ReadBuffer(RxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);  
-
-  /* Read back NOR memory and check content correctness */   
-  for (Index = 0x00; (Index < BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
-  {
-    if (RxBuffer[Index] != TxBuffer[Index])
-    {
-      WriteReadStatus = Index + 1;
-    }
-  }
-
-  if (WriteReadStatus == 0)
-  {
-    /* OK */
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  { 
-    /* KO */
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Fill the global buffer
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  BufferSize: size of the buffer to fill
-  * @param  Offset: first value to fill on the Buffer
-  */
-void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
-{
-  uint16_t IndexTmp = 0;
-
-  /* Put in global buffer same values */
-  for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
-  {
-    pBuffer[IndexTmp] = IndexTmp + Offset;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/readme.txt
deleted file mode 100644
index fdf3f25..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/readme.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
-  @page FSMC_NOR FSMC NOR example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NOR/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC NOR example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the FSMC firmware library and
-an associate driver to perform erase/read/write operations on the M29W128FL,
-M29W128GL or S29GL128P NOR memories mounted on the STM3210E-EVAL board.
-
-@par Directory contents 
-
-  - FSMC/NOR/stm32f10x_conf.h    Library Configuration file
-  - FSMC/NOR/stm32f10x_it.c      Interrupt handlers
-  - FSMC/NOR/stm32f10x_it.h      Header for stm32f10x_it.c
-  - FSMC/NOR/main.c              Main program
-  - FSMC/NOR/system_stm32f10x.c  STM32F10x system source file  
-
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h
deleted file mode 100644
index 534ca2f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c
deleted file mode 100644
index 1fd54a1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_NOR
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h
deleted file mode 100644
index 13906bc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini
deleted file mode 100644
index 109757e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini
+++ /dev/null
@@ -1,38 +0,0 @@
-/******************************************************************************/
-/* FLASH_NOR.ini: NOR Initialization File                                     */
-/******************************************************************************/
-// <<< Use Configuration Wizard in Context Menu >>>                           // 
-/******************************************************************************/
-/* This file is part of the uVision/ARM development tools.                    */
-/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
-/* This software may only be used under the terms of a valid, current,        */
-/* end user licence from KEIL for a compatible version of KEIL software       */
-/* development tools. Nothing else gives you the right to use this software.  */
-/******************************************************************************/
-
-FUNC void Setup(void) {
-
-  _WDWORD(0x40021014, 0x00000114);   // FSMC clock enable
-  _WDWORD(0x40021018, 0x000001FD);   // GPIOD~G clock enable
-
-  _WDWORD(0x40011400, 0x44BB44BB);   // GPIOD config
-  _WDWORD(0x40011404, 0xBBBBBBBB);   // GPIOD config
-  
-  _WDWORD(0x40011800, 0xBBBBB444);   // GPIOE config
-  _WDWORD(0x40011804, 0xBBBBBBBB);   // GPIOE config
-
-  _WDWORD(0x40011C00, 0x44BBBBBB);   // GPIOF config
-  _WDWORD(0x40011C04, 0xBBBB4444);   // GPIOF config
-
-  _WDWORD(0x40012000, 0x44BBBBBB);   // GPIOG config
-  _WDWORD(0x40012004, 0x444444B4);   // GPIOG config
-
-  _WDWORD(0xA0000000, 0x000030DB);   // FSMC config
-  _WDWORD(0xA0000008, 0x00001059);   // FSMC config
-  _WDWORD(0xA000000C, 0x10000705);   // FSMC config
-  _WDWORD(0xA0000104, 0x0FFFFFFF);   // FSMC config
-}
-
-Setup();
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt
deleted file mode 100644
index a06bbdc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
-  @page FSMC_NOR_CodeExecute_binary FSMC NOR CodeExecute example binary directory
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NOR_CodeExecute/binary/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC NOR CodeExecute example binary directory.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description
-
-This directory contains a set of sources files that build the application to be
-loaded into the NOR memory mounted on STM3210E-EVAL board.
-
-The GPIO IOToggle example provided within the STM32F10x Firmware library is used
-as illustration. In this example four LEDs: LED1, LED2, LED3 and LED4 are 
-toggled in an infinite loop.
-
-@par Directory contents 
-
-  - FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h        Library Configuration file
-  - FSMC/NOR_CodeExecute/binary/stm32f10x_it.c          Interrupt handlers
-  - FSMC/NOR_CodeExecute/binary/stm32f10x_it.h          Header for stm32f10x_it.c  
-  - FSMC/NOR_CodeExecute/binary/main.c                  Main program
-  - FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini           NOR Initialization File for MDK-ARM toolchain. 
-  - FSMC/NOR_CodeExecute/binary/STM3210E-EVAL_NOR.FLM   STM3210E-EVAL board NOR flasher for MDK-ARM toolchain.
-  - FSMC/NOR_CodeExecute/binary/system_stm32f10x.c      STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following:
-- Create a project and setup all project configuration:
-<ul>
-    <li> MDK-ARM 
-         - copy "STM3210E-EVAL_NOR.FLM" file under "C:\Keil\ARM\Flash" directory
-         - in Project->Options->Target window, select 'ROM1', enter 0x64000000 as
-           start address with size of 0x1000000 and check "Startup" option 
-          (IROM1 must be un-checked)
-         - in Project->Options->Linker window, uncheck "Use memory Layout from 
-           Target Dialog" then enter 0x64000000 as R/O base address and chek 
-           again "Use memory Layout from Target Dialog"                  
-         - in Project->Options->Utilities window, select "Use Target Driver for 
-           Flash Programming"
-         - Click on 'Settings' button then select "STM3210E_EVAL NOR Flash" as
-           Programming Algorithms (start:0x64000000, size:0x1000000)
-         - in Project->Options->Debug select "FLASH_NOR.ini" provided within this 
-           example directory as initialization file.       
-
-    <li> EWARM
-         - use "stm32f10x_nor.icf" as linker file
-         - in project->options ->debugger-> setup , the "run to main" option 
-           should be un-checked
-         - in project->options ->J-Link/J-Trace-> setup , set the "Reset" to 
-           "Normal"
-         - in project->options ->debugger->download, click on "edit" button
-           ("Use flash loader(s)" option should be checked)
-         - select the default flash loader then click on "edit" button
-         - check "override default flash loader path" option and select
-           "FlashSTM32F10x_NOR.xml" as flash loader 
-           ($TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10x_NOR.xml)
-</ul>
-
-- Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
-- Open your preferred toolchain 
-- Rebuild all files and load your image into target memory
-- Run the example       
-- Link all compiled files and load your image into NOR memory
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
deleted file mode 100644
index f63a140..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
deleted file mode 100644
index 9a0d596..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_NOR_CodeExecute_binary
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h
deleted file mode 100644
index 39e43ea..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
deleted file mode 100644
index c508705..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt
deleted file mode 100644
index ee90ac8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  @page FSMC_NOR_CodeExecute FSMC NOR CodeExecute example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NOR_CodeExecute/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC NOR CodeExecute example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This directory contains a set of sources files that describes how to build an
-application to be loaded into the NOR memory mounted on STM3210E-EVAL board then
-execute it from internal Flash.
-
-@par Directory contents 
-
- - FSMC/NOR_CodeExecute/binary: Contains a set of sources files that build the 
-                                application to be loaded into the NOR memory 
-                                mounted on STM3210E-EVAL board.
- - FSMC/NOR_CodeExecute/stm32f10x_conf.h    Library Configuration file 
- - FSMC/NOR_CodeExecute/stm32f10x_it.c      Interrupt handlers 
- - FSMC/NOR_CodeExecute/stm32f10x_it.h      Header for stm32f10x_it.c 
- - FSMC/NOR_CodeExecute/main.c              Main program 
- - FSMC/NOR_CodeExecute/system_stm32f10x.c  STM32F10x system source file
-    
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board and can be easily tailored to any other 
-    supported device and development board.
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following:
-
-1. Program the NOR memory with the example provided in the "binary" directory
-
-2. Program the internal Flash with the code that will jump to the NOR memory to execute 
-   the loaded example, for this you have to:      
-   - Copy all source files from this example folder to the template folder under
-     Project\STM32F10x_StdPeriph_Template
-   - Open your preferred toolchain 
-   - Rebuild all files and load your image into target memory
-   - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h
deleted file mode 100644
index b9ae62b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c
deleted file mode 100644
index 9a5bfab..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_NOR_CodeExecute
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h
deleted file mode 100644
index 1cb267f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c
deleted file mode 100644
index 80c04af..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
deleted file mode 100644
index 9ef7497..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/OneNAND/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-#include "stm32100e_eval_fsmc_onenand.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_OneNAND
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define OneNAND_SAMSUNG_MANUFACTURER_ID     0x00EC
-#define OneNAND_SAMSUNG_DEVICE_ID           0x0025
-
-#define OneNAND_BUFFER_SIZE                 0x0400 /* Page size: 1024 x 16 bits = 2048 Bytes */
-#define OneNAND_WRITE_BLOCK_NUMBER          0x0000 /* should be between 0 and 511, the block size is 128 KBytes */
-#define OneNAND_WRITE_PAGE_NUMBER           0x0000 /* The page size inside a Block is 2 KBytes */
-#define OneNAND_NUMBER_OF_PAGE_PER_BLOCK    0x0040 /* 64 pages per block */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-OneNAND_IDTypeDef OneNAND_ID;
-OneNAND_ADDRESS Address;
-uint16_t TxBuffer[OneNAND_BUFFER_SIZE], RxBuffer_A[OneNAND_BUFFER_SIZE], RxBuffer_S[OneNAND_BUFFER_SIZE];
-uint32_t j = 0, PageIndex = 0, Status = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-  
-  /* Initialize LEDs on STM3220F-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);  
-  STM_EVAL_LEDInit(LED4); 
-  
-  /* FSMC Initialization */
-  OneNAND_Init();
-
-  /* Read OneNAND memory ID */
-  OneNAND_ReadID(&OneNAND_ID);
-
-  /* Verify the OneNAND ID */ 
-  if((OneNAND_ID.Manufacturer_ID == OneNAND_SAMSUNG_MANUFACTURER_ID) && 
-     (OneNAND_ID.Device_ID == OneNAND_SAMSUNG_DEVICE_ID)) 
-  {
-    /* Fill the buffer to send */
-    Fill_hBuffer(TxBuffer, OneNAND_BUFFER_SIZE , 0x320F);
-    Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-    Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-    
-
-    /***** Erase then write to the OneNAND memory ******************************/  
-    /* Unlock the selected OneNAND block */
-    Status = OneNAND_UnlockBlock(OneNAND_WRITE_BLOCK_NUMBER);
-
-    if (Status == 0)
-    { 
-      /* Erase the selected OneNAND block */
-      Status = OneNAND_EraseBlock(Address.Block);
-
-      if (Status == 0)
-      { 
-        /* Write data to the OneNAND memory (128Kbytes by page 2KBytes each) */
-        for(PageIndex = 0; (PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK) && (Status ==0); PageIndex++)
-        {
-          Status = OneNAND_WriteBuffer(TxBuffer, Address, OneNAND_BUFFER_SIZE);
-          Address.Page++;
-        }
-
-        if (Status == 0)
-        { 
-          /***** Verify of the written data using asynchronous read ***********/
-          Fill_hBuffer(RxBuffer_A, OneNAND_BUFFER_SIZE , 0xFF);
-          Status = 0;
-          Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-          Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-
-          for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
-          {
-            /* Read back the written data (By page) */
-            OneNAND_AsynchronousRead(RxBuffer_A, Address, OneNAND_BUFFER_SIZE);
-   
-            /* Verify the written data */
-            for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
-            {
-              if(TxBuffer[j] != RxBuffer_A[j])
-              {
-                Status++;
-              }
-            }
-            Address.Page++;
-          }
-          
-          if (Status != 0)
-          { 
-            /* Turn ON LED2 */
-            STM_EVAL_LEDOn(LED2); 
-          }
-
-          /***** Verify of the written data using synchronous read ************/   
-          Fill_hBuffer(RxBuffer_S, OneNAND_BUFFER_SIZE , 0xFF);
-          Status = 0;
-          Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-          Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-
-          for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
-          {
-            /* Read back the written data (By page) */
-            OneNAND_SynchronousRead(RxBuffer_S, Address, OneNAND_BUFFER_SIZE);
-   
-            /* Verify the written data */
-            for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
-            {
-              if(TxBuffer[j] != RxBuffer_S[j])
-              {
-                Status++;
-              }
-            }
-            Address.Page++;
-          }
-
-          if (Status != 0)
-          { 
-            /* Turn ON LED3 */
-            STM_EVAL_LEDOn(LED3);
-          }
-        }        
-        else
-        { 
-          /* Turn ON LED4 */
-          STM_EVAL_LEDOn(LED4); 
-        }
-      } 
-      else
-      { 
-        /* Turn ON LED2 and LED4*/
-        STM_EVAL_LEDOn(LED2); 
-        STM_EVAL_LEDOn(LED4); 
-      }     
-    } 
-    else
-    { 
-      /* Turn ON LED3 and LED4 */
-      STM_EVAL_LEDOn(LED3);
-      STM_EVAL_LEDOn(LED4); 
-    }  
-  }
-  else
-  {
-    /* Turn ON LED2, LED3 and LED4 */
-    STM_EVAL_LEDOn(LED2);    
-    STM_EVAL_LEDOn(LED3);
-    STM_EVAL_LEDOn(LED4);
-  }
-
-  if (Status == 0)
-  { 
-   /* Turn ON LED1 */
-   STM_EVAL_LEDOn(LED1);
-  }
-  		  
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Fills a global 16-bit buffer
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  BufferSize: size of the buffer to fill
-  * @param  Offset: first value to fill on the Buffer
-  * @retval None
-  */
-void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
-{
-  uint16_t IndexTmp = 0;
-
-  /* Put in global buffer different values */
-  for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
-  {
-    pBuffer[IndexTmp] = IndexTmp + Offset;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt
deleted file mode 100644
index ae132d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
-  @page FSMC_OneNAND FSMC OneNAND example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/OneNAND/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC OneNAND example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the FSMC to drive the OneNAND memory mounted 
-on STM32100E-EVAL board. 
-
-In this example a basic example of how to use the FSMC firmware library and
-an associate driver to perform read/write operations on the KFG1216U2A/B-DIB6 
-OneNAND memory.
-
-The different OneNAND memory operations (Unlock, Erase, Write, Read) results are 
-signalled using four LEDs as follows:
-     - LED2, LED3 and LED4 are ON: OneNAND ID read failed
-     - LED3 and LED4 ON: Unlock Block failed
-     - LED2 and LED4 ON: Erase Block failed
-     - LED4 ON: Write Buffer failed
-     - LED2 ON: Asynchronous Read failed
-     - LED3 ON: Synchronous Read 
-     - LED1 ON: All OneNAND memory operations are OK
-
-
-@par Directory contents
-
-  - FSMC/OneNAND/stm32f10x_conf.h     Library Configuration file
-  - FSMC/OneNAND/stm32f10x_it.c       Interrupt handlers
-  - FSMC/OneNAND/stm32f10x_it.h       Header for stm32f10x_it.c
-  - FSMC/OneNAND/main.c               Main program
-  - FSMC/OneNAND/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x High-density value line Devices.
-  
-  - This example has been tested with STM32100E-EVAL and can be easily tailored
-    to any other development board.
-    Make sure that the jumper JP6 is in position 2<->3
-
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.  
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c
deleted file mode 100644
index 0bf6afe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/OneNAND/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_OneNAND
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c
deleted file mode 100644
index ffd831d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/OneNAND/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h
deleted file mode 100644
index 32e2cf2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h
deleted file mode 100644
index bccefcf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c
deleted file mode 100644
index 3777114..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s
deleted file mode 100644
index 48be84c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s
+++ /dev/null
@@ -1,464 +0,0 @@
-;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_hd_vl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 08-April-2011
-;* Description        : STM32F10x High Density Value Line Devices vector table 
-;*                      for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system and the external SRAM 
-;*                        mounted on STM32100E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-__initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     __initial_spTop           ; Use internal RAM for stack for calling SystemInit.
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler               ; Window Watchdog
-        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler             ; Tamper
-        DCD     RTC_IRQHandler                ; RTC
-        DCD     FLASH_IRQHandler              ; Flash
-        DCD     RCC_IRQHandler                ; RCC
-        DCD     EXTI0_IRQHandler              ; EXTI Line 0
-        DCD     EXTI1_IRQHandler              ; EXTI Line 1
-        DCD     EXTI2_IRQHandler              ; EXTI Line 2
-        DCD     EXTI3_IRQHandler              ; EXTI Line 3
-        DCD     EXTI4_IRQHandler              ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler               ; ADC1
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-        DCD     TIM1_BRK_TIM15_IRQHandler     ; TIM1 Break and TIM15
-        DCD     TIM1_UP_TIM16_IRQHandler      ; TIM1 Update and TIM16
-        DCD     TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
-        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler               ; TIM2
-        DCD     TIM3_IRQHandler               ; TIM3
-        DCD     TIM4_IRQHandler               ; TIM4
-        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-        DCD     SPI1_IRQHandler               ; SPI1
-        DCD     SPI2_IRQHandler               ; SPI2
-        DCD     USART1_IRQHandler             ; USART1
-        DCD     USART2_IRQHandler             ; USART2
-        DCD     USART3_IRQHandler             ; USART3
-        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-        DCD     CEC_IRQHandler                ; HDMI-CEC
-        DCD     TIM12_IRQHandler              ; TIM12
-        DCD     TIM13_IRQHandler              ; TIM13
-        DCD     TIM14_IRQHandler              ; TIM14
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     0                             ; Reserved
-        DCD     TIM5_IRQHandler               ; TIM5
-        DCD     SPI3_IRQHandler               ; SPI3
-        DCD     UART4_IRQHandler              ; UART4
-        DCD     UART5_IRQHandler              ; UART5                       
-        DCD     TIM6_DAC_IRQHandler           ; TIM6 and DAC underrun
-        DCD     TIM7_IRQHandler               ; TIM7     
-        DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-        DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5                   
-        DCD     DMA2_Channel5_IRQHandler      ; DMA2 Channel5
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0   
-        LDR     R0, =sfe(CSTACK)          ; restore original stack pointer
-        MSR     MSP, R0             
-        LDR     R0, =__iar_program_start
-        BX      R0                 
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM15_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_TIM15_IRQHandler
-        B TIM1_BRK_TIM15_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM16_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_TIM16_IRQHandler
-        B TIM1_UP_TIM16_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_TIM17_IRQHandler
-        B TIM1_TRG_COM_TIM17_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK CEC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CEC_IRQHandler
-        B CEC_IRQHandler
-
-        PUBWEAK TIM12_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM12_IRQHandler
-        B TIM12_IRQHandler
-
-        PUBWEAK TIM13_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM13_IRQHandler
-        B TIM13_IRQHandler
-
-        PUBWEAK TIM14_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM14_IRQHandler
-        B TIM14_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-        
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel4_5_IRQHandler
-        B DMA2_Channel4_5_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-                
-        END
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s
deleted file mode 100644
index 580307f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,500 +0,0 @@
-;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_xl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 08-April-2011
-;* Description        : STM32F10x XL-Density Devices vector table for EWARM 
-;*                      toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Configure the clock system and the external SRAM 
-;*                        mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR address,
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;     
- __initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
- 
-    MODULE  ?cstartup
-        
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-       
-__vector_table
-        DCD     __initial_spTop           ; Use internal RAM for stack for calling SystemInit.
-        DCD     Reset_Handler             ; Reset Handler
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler               ; Window Watchdog
-        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-        DCD     TAMPER_IRQHandler             ; Tamper
-        DCD     RTC_IRQHandler                ; RTC
-        DCD     FLASH_IRQHandler              ; Flash
-        DCD     RCC_IRQHandler                ; RCC
-        DCD     EXTI0_IRQHandler              ; EXTI Line 0
-        DCD     EXTI1_IRQHandler              ; EXTI Line 1
-        DCD     EXTI2_IRQHandler              ; EXTI Line 2
-        DCD     EXTI3_IRQHandler              ; EXTI Line 3
-        DCD     EXTI4_IRQHandler              ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-        DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-        DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-        DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler               ; TIM2
-        DCD     TIM3_IRQHandler               ; TIM3
-        DCD     TIM4_IRQHandler               ; TIM4
-        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-        DCD     SPI1_IRQHandler               ; SPI1
-        DCD     SPI2_IRQHandler               ; SPI2
-        DCD     USART1_IRQHandler             ; USART1
-        DCD     USART2_IRQHandler             ; USART2
-        DCD     USART3_IRQHandler             ; USART3
-        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-        DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-        DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-        DCD     ADC3_IRQHandler               ; ADC3
-        DCD     FSMC_IRQHandler               ; FSMC
-        DCD     SDIO_IRQHandler               ; SDIO
-        DCD     TIM5_IRQHandler               ; TIM5
-        DCD     SPI3_IRQHandler               ; SPI3
-        DCD     UART4_IRQHandler              ; UART4
-        DCD     UART5_IRQHandler              ; UART5
-        DCD     TIM6_IRQHandler               ; TIM6
-        DCD     TIM7_IRQHandler               ; TIM7
-        DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-        DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0   
-        LDR     R0, =sfe(CSTACK)          ; restore original stack pointer
-        MSR     MSP, R0             
-        LDR     R0, =__iar_program_start
-        BX      R0                 
-               
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-
-        PUBWEAK USB_HP_CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_HP_CAN1_TX_IRQHandler
-        B USB_HP_CAN1_TX_IRQHandler
-
-        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_LP_CAN1_RX0_IRQHandler
-        B USB_LP_CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN1_SCE_IRQHandler
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_BRK_TIM9_IRQHandler
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_UP_TIM10_IRQHandler
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_TRG_COM_TIM11_IRQHandler
-        B TIM1_TRG_COM_TIM11_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK USBWakeUp_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBWakeUp_IRQHandler
-        B USBWakeUp_IRQHandler
-
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_BRK_TIM12_IRQHandler
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_UP_TIM13_IRQHandler
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_TRG_COM_TIM14_IRQHandler
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM8_CC_IRQHandler
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK ADC3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC3_IRQHandler
-        B ADC3_IRQHandler
-
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-FSMC_IRQHandler
-        B FSMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_5_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA2_Channel4_5_IRQHandler
-        B DMA2_Channel4_5_IRQHandler
-        
-        
-        END
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm
deleted file mode 100644
index 21e11b0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm
+++ /dev/null
@@ -1,157 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-
-__initial_spTop .equ   0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
-
-      
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        
-		
-		
-		LDR     R0, =__initial_spTop       ; use internal RAM for stack for calling SystemInit
-        MSR     MSP, R0  
-		
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		
-		bl  SystemInit
-
-		;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s
deleted file mode 100644
index c028799..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s
+++ /dev/null
@@ -1,352 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_hd.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 08-April-2011
-;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-__initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_spTop            ; use internal RAM for stack for calling SystemInit
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI-CEC
-                DCD     TIM12_IRQHandler                ; TIM12
-                DCD     TIM13_IRQHandler                ; TIM13 
-                DCD     TIM14_IRQHandler                ; TIM14
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM5_IRQHandler                 ; TIM5
-                DCD     SPI3_IRQHandler                 ; SPI3
-                DCD     UART4_IRQHandler                ; UART4
-                DCD     UART5_IRQHandler                ; UART5
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
-                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5 
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit       
-
-                LDR     R0, =SystemInit
-                BLX     R0               
-
-                LDR     R0, =__initial_sp          ; restore original stack pointer
-                MSR     MSP, R0                   
-
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTCAlarm_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM12_IRQHandler                 [WEAK]
-                EXPORT  TIM13_IRQHandler                 [WEAK]
-                EXPORT  TIM14_IRQHandler                 [WEAK]
-                EXPORT  TIM5_IRQHandler                  [WEAK]
-                EXPORT  SPI3_IRQHandler                  [WEAK]
-                EXPORT  UART4_IRQHandler                 [WEAK]
-                EXPORT  UART5_IRQHandler                 [WEAK]                
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler         [WEAK] 
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-CEC_IRQHandler
-TIM12_IRQHandler
-TIM13_IRQHandler
-TIM14_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-DMA2_Channel5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s
deleted file mode 100644
index b9227a6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,363 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_xl.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 08-April-2011
-;* Description        : STM32F10x XL-Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-__initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_spTop            ; use internal RAM for stack for calling SystemInit
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-                DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-                DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-                DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-                DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-                DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-                DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-                DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler               ; ADC3
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     SDIO_IRQHandler               ; SDIO
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                
-                LDR     R0, =SystemInit
-                BLX     R0   
-                LDR     R0, =__initial_sp          ; restore original stack pointer
-                MSR     MSP, R0 
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_2_IRQHandler             [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler     [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler    [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler           [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler           [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM1_BRK_TIM9_IRQHandler      [WEAK]
-                EXPORT  TIM1_UP_TIM10_IRQHandler      [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTCAlarm_IRQHandler           [WEAK]
-                EXPORT  USBWakeUp_IRQHandler          [WEAK]
-                EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]
-                EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]
-                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
-                EXPORT  TIM8_CC_IRQHandler            [WEAK]
-                EXPORT  ADC3_IRQHandler               [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  SDIO_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s
deleted file mode 100644
index ace5557..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd_vl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      08-April-2011
-  * @brief     STM32F10x High Density Value Line Devices vector table for RIDE7
-  *            toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM32100E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)               
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-/* Stack used for SystemInit & SystemInit_ExtMemCtl*/
-.equ __initial_spTop,    0x20000400 
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval None
-*/
-
-  .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b     LoopCopyDataInit
-
-CopyDataInit:
-  ldr   r3, =_sidata
-  ldr   r3, [r3, r1]
-  str   r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr   r0, =_sdata
-  ldr   r3, =_edata
-  adds  r2, r0, r1
-  cmp   r2, r3
-  bcc   CopyDataInit
-  ldr   r2, =_sbss
-  b     LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str   r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr   r3, = _ebss
-  cmp   r2, r3
-  bcc   FillZerobss
-          
-/* Call the clock system intitialization function.*/
-  bl  SystemInit 
-/* Restore original stack pointer. */
-  ldr     r0, =_estack          
-  msr     MSP, r0 
-/* Call the application's entry point.*/
-  bl    main
-  bx    lr    
-.size   Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt. This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-  .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-******************************************************************************/    
-  .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word  __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM15_IRQHandler
-  .word  TIM1_UP_TIM16_IRQHandler
-  .word  TIM1_TRG_COM_TIM17_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  CEC_IRQHandler  
-  .word  TIM12_IRQHandler
-  .word  TIM13_IRQHandler
-  .word  TIM14_COM_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_DAC_IRQHandler
-  .word  TIM7_IRQHandler  
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  DMA2_Channel5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density Value line devices. */
-   
-/*******************************************************************************
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_COM_IRQHandler
-  .thumb_set TIM14_COM_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler 
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler      
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s
deleted file mode 100644
index 63f88fe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,470 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_xl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      08-April-2011
-  * @brief     STM32F10x XL-Density Devices vector table for RIDE7 toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM3210E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-/* Stack used for SystemInit & SystemInit_ExtMemCtl*/
-.equ __initial_spTop,    0x20000400
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-             
-/* Call the clock system intitialization function.*/
-  bl  SystemInit 
-/* Restore original stack pointer. */
-  ldr     r0, =_estack          
-  msr     MSP, r0 
-/* Call the application's entry point.*/
-  bl    main
-  bx    lr    
-.size   Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s
deleted file mode 100644
index 720297a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s
+++ /dev/null
@@ -1,474 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_hd.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      08-April-2011
-  * @brief     STM32F10x High Density Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Configure the clock system  
-  *                - Configure external SRAM mounted on STM3210E-EVAL board
-  *                  to be used as data memory (optional, to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-    .syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-.global	g_pfnVectors
-.global	Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word	_sidata
-/* start address for the .data section. defined in linker script */
-.word	_sdata
-/* end address for the .data section. defined in linker script */
-.word	_edata
-/* start address for the .bss section. defined in linker script */
-.word	_sbss
-/* end address for the .bss section. defined in linker script */
-.word	_ebss
-
-/* ; stack used for SystemInit & SystemInit_ExtMemCtl*/
-.equ __initial_spTop, 0x20000400 
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section	.text.Reset_Handler
-	.weak	Reset_Handler
-	.type	Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs	r1, #0
-  b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	adds	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	adds	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-             
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Restore original stack pointer. */
-    ldr     r0, =_estack          
-    msr     MSP, r0
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-.size	Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section	.text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-	b	Infinite_Loop
-	.size	Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- 	.section	.isr_vector,"a",%progbits
-	.type	g_pfnVectors, %object
-	.size	g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word   __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
-	.word	Reset_Handler
-	.word	NMI_Handler
-	.word	HardFault_Handler
-	.word	MemManage_Handler
-	.word	BusFault_Handler
-	.word	UsageFault_Handler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	SVC_Handler
-	.word	DebugMon_Handler
-	.word	0
-	.word	PendSV_Handler
-	.word	SysTick_Handler
-	.word	WWDG_IRQHandler
-	.word	PVD_IRQHandler
-	.word	TAMPER_IRQHandler
-	.word	RTC_IRQHandler
-	.word	FLASH_IRQHandler
-	.word	RCC_IRQHandler
-	.word	EXTI0_IRQHandler
-	.word	EXTI1_IRQHandler
-	.word	EXTI2_IRQHandler
-	.word	EXTI3_IRQHandler
-	.word	EXTI4_IRQHandler
-	.word	DMA1_Channel1_IRQHandler
-	.word	DMA1_Channel2_IRQHandler
-	.word	DMA1_Channel3_IRQHandler
-	.word	DMA1_Channel4_IRQHandler
-	.word	DMA1_Channel5_IRQHandler
-	.word	DMA1_Channel6_IRQHandler
-	.word	DMA1_Channel7_IRQHandler
-	.word	ADC1_2_IRQHandler
-	.word	USB_HP_CAN1_TX_IRQHandler
-	.word	USB_LP_CAN1_RX0_IRQHandler
-	.word	CAN1_RX1_IRQHandler
-	.word	CAN1_SCE_IRQHandler
-	.word	EXTI9_5_IRQHandler
-	.word	TIM1_BRK_IRQHandler
-	.word	TIM1_UP_IRQHandler
-	.word	TIM1_TRG_COM_IRQHandler
-	.word	TIM1_CC_IRQHandler
-	.word	TIM2_IRQHandler
-	.word	TIM3_IRQHandler
-	.word	TIM4_IRQHandler
-	.word	I2C1_EV_IRQHandler
-	.word	I2C1_ER_IRQHandler
-	.word	I2C2_EV_IRQHandler
-	.word	I2C2_ER_IRQHandler
-	.word	SPI1_IRQHandler
-	.word	SPI2_IRQHandler
-	.word	USART1_IRQHandler
-	.word	USART2_IRQHandler
-	.word	USART3_IRQHandler
-	.word	EXTI15_10_IRQHandler
-	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler
-	.word	TIM8_BRK_IRQHandler
-	.word	TIM8_UP_IRQHandler
-	.word	TIM8_TRG_COM_IRQHandler
-	.word	TIM8_CC_IRQHandler
-	.word	ADC3_IRQHandler
-	.word	FSMC_IRQHandler
-	.word	SDIO_IRQHandler
-	.word	TIM5_IRQHandler
-	.word	SPI3_IRQHandler
-	.word	UART4_IRQHandler
-	.word	UART5_IRQHandler
-	.word	TIM6_IRQHandler
-	.word	TIM7_IRQHandler
-	.word	DMA2_Channel1_IRQHandler
-	.word	DMA2_Channel2_IRQHandler
-	.word	DMA2_Channel3_IRQHandler
-	.word	DMA2_Channel4_5_IRQHandler
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	0
-	.word	BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-  .weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-  .weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-  .weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_IRQHandler
-	.thumb_set PVD_IRQHandler,Default_Handler
-
-	.weak	TAMPER_IRQHandler
-	.thumb_set TAMPER_IRQHandler,Default_Handler
-
-	.weak	RTC_IRQHandler
-	.thumb_set RTC_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC1_2_IRQHandler
-	.thumb_set ADC1_2_IRQHandler,Default_Handler
-
-	.weak	USB_HP_CAN1_TX_IRQHandler
-	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-	.weak	USB_LP_CAN1_RX0_IRQHandler
-	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-	.weak	CAN1_RX1_IRQHandler
-	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-	.weak	CAN1_SCE_IRQHandler
-	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM3_IRQHandler
-	.thumb_set TIM3_IRQHandler,Default_Handler
-
-	.weak	TIM4_IRQHandler
-	.thumb_set TIM4_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	USART3_IRQHandler
-	.thumb_set USART3_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTCAlarm_IRQHandler
-	.thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-	.weak	USBWakeUp_IRQHandler
-	.thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-	.weak	TIM8_BRK_IRQHandler
-	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM8_UP_IRQHandler
-	.thumb_set TIM8_UP_IRQHandler,Default_Handler
-
-	.weak	TIM8_TRG_COM_IRQHandler
-	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM8_CC_IRQHandler
-	.thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-	.weak	ADC3_IRQHandler
-	.thumb_set ADC3_IRQHandler,Default_Handler
-
-	.weak	FSMC_IRQHandler
-	.thumb_set FSMC_IRQHandler,Default_Handler
-
-	.weak	SDIO_IRQHandler
-	.thumb_set SDIO_IRQHandler,Default_Handler
-
-	.weak	TIM5_IRQHandler
-	.thumb_set TIM5_IRQHandler,Default_Handler
-
-	.weak	SPI3_IRQHandler
-	.thumb_set SPI3_IRQHandler,Default_Handler
-
-	.weak	UART4_IRQHandler
-	.thumb_set UART4_IRQHandler,Default_Handler
-
-	.weak	UART5_IRQHandler
-	.thumb_set UART5_IRQHandler,Default_Handler
-
-	.weak	TIM6_IRQHandler
-	.thumb_set TIM6_IRQHandler,Default_Handler
-
-	.weak	TIM7_IRQHandler
-	.thumb_set TIM7_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_5_IRQHandler
-	.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s
deleted file mode 100644
index 7526cf3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f10x_xl.s
-  * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      08-April-2011
-  * @brief     STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. 
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system and the external SRAM mounted on 
-  *                  STM3210E-EVAL board to be used as data memory (optional, 
-  *                  to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */  
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/* ; stack used for SystemInit & SystemInit_ExtMemCtl*/
-.equ __initial_spTop, 0x20000400 
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Restore original stack pointer. */
-  ldr     r0, =_estack          
-  msr     MSP, r0 
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  main
-  bx  lr    
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-* 
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-    
-    
-g_pfnVectors:
-  .word  __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTCAlarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTCAlarm_IRQHandler
-  .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
deleted file mode 100644
index eaff5dd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM_DataMemory/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_SRAM_DataMemory
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint32_t Tab[1024], Index;
-__IO uint32_t TabAddr, MSPValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  for (Index = 0; Index <1024 ; Index++)
-  {
-     Tab[Index] =Index;
-  }
-
-  TabAddr = (uint32_t)Tab; /* should be 0x680xxxxx */
-
-  /* Get main stack pointer value */
-  MSPValue = __get_MSP(); /* should be 0x680xxxxx */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h
deleted file mode 100644
index f83d30d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM_DataMemory/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h
deleted file mode 100644
index 457981c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM_DataMemory/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c
deleted file mode 100644
index 5e8a158..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM_DataMemory/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
- #define DATA_IN_ExtSRAM
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c
deleted file mode 100644
index 449bd2f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/IOToggle/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup GPIO_IOToggle
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-GPIO_InitTypeDef GPIO_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* GPIOD Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
-
-  /* Configure PD0 and PD2 in output pushpull mode */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  /* To achieve GPIO toggling maximum frequency, the following  sequence is mandatory. 
-     You can monitor PD0 or PD2 on the scope to measure the output signal. 
-     If you need to fine tune this frequency, you can add more GPIO set/reset 
-     cycles to minimize more the infinite loop timing.
-     This code needs to be compiled with high speed optimization option.  */
-  while (1)
-  {
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-
-    /* Set PD0 and PD2 */
-    GPIOD->BSRR = 0x00000005;
-    /* Reset PD0 and PD2 */
-    GPIOD->BRR  = 0x00000005;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h
deleted file mode 100644
index 900c7c1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/IOToggle/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c
deleted file mode 100644
index 4242895..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/IOToggle/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c
deleted file mode 100644
index 3f2d562..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/JTAG_Remap/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup GPIO_JTAG_Remap
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-GPIO_InitTypeDef GPIO_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Configure the system clocks */
-  RCC_Configuration();
-    
-  /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-       
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
-
-  /* Test if Key Button GPIO Pin level is low (Key push-button on Eval Board pressed) */
-  if (STM_EVAL_PBGetState(BUTTON_KEY) == 0x00)
-  { /* Key is pressed */
-
-     /* Turn on LED1 */
-     STM_EVAL_LEDOn(LED1);
-
-    /* Disable the Serial Wire Jtag Debug Port SWJ-DP */
-    GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
-
-    /* Configure PA.13 (JTMS/SWDAT), PA.14 (JTCK/SWCLK) and PA.15 (JTDI) as 
-       output push-pull */
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-    GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-    /* Configure PB.03 (JTDO) and PB.04 (JTRST) as output push-pull */
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4;
-    GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-    while (1)
-    {
-      /* Toggle JTMS/SWDAT pin */
-      GPIO_WriteBit(GPIOA, GPIO_Pin_13, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_13)));
-      /* Insert delay */
-      Delay(0x5FFFF);
-
-      /* Toggle JTCK/SWCLK pin */
-      GPIO_WriteBit(GPIOA, GPIO_Pin_14, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_14)));
-      /* Insert delay */
-      Delay(0x5FFFF);
-
-      /* Toggle JTDI pin */
-      GPIO_WriteBit(GPIOA, GPIO_Pin_15, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_15)));
-      /* Insert delay */
-      Delay(0x5FFFF);
-
-      /* Toggle JTDO pin */
-      GPIO_WriteBit(GPIOB, GPIO_Pin_3, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_3)));
-      /* Insert delay */
-      Delay(0x5FFFF);
-
-      /* Toggle JTRST pin */
-      GPIO_WriteBit(GPIOB, GPIO_Pin_4, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_4)));
-      /* Insert delay */
-      Delay(0x5FFFF);
-    }
-  }
-  else
-  {
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-
-    while (1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* Enable GPIOA, GPIOB, RCC_APB2Periph_GPIO_KEY_BUTTON and AFIO clocks */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt
deleted file mode 100644
index 4e9c8f7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
-  @page GPIO_JTAG_Remap GPIO JTAG Remap example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    GPIO/JTAG_Remap/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the GPIO JTAG Remap example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a short description of how to use the JTAG IOs as standard 
-GPIOs and gives a configuration sequence. 
-
-First, the SWJ-DP is disabled. The SWJ-DP pins are configured as output push-pull.
-Five LEDs connected to the PA.13(JTMS/SWDAT), PA.14(JTCK/SWCLK), PA.15(JTDI), 
-PB.03(JTDO) and PB.04(JTRST) pins are toggled in an infinite loop.
-
-Note that once the JTAG IOs are disabled, the connection with the host debugger is
-lost and cannot be re-established as long as the JTAG IOs remain disabled. 
-
-To avoid this situation, a specified pin is connected to a push-button that is used
-to disable or not the JTAG IOs:
- 1. push-button pressed at reset: JTAG IOs disabled	and LED1 turned on
- 2. push-button not pressed at reset: JTAG IOs unchanged and LED2 turned on
-
-Before starting this example, you should disconnect your tool chain debugging probe
-and run the example in standalone mode.
-
-@par Directory contents 
-
-  - GPIO/JTAG_Remap/stm32f10x_conf.h     Library Configuration file
-  - GPIO/JTAG_Remap/stm32f10x_it.c       Interrupt handlers
-  - GPIO/JTAG_Remap/stm32f10x_it.h       Header for stm32f10x_it.c
-  - GPIO/JTAG_Remap/main.c               Main program
-  - GPIO/JTAG_Remap/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use LD1 and LD2 connected respectively to PF.06 and PF.07
-    
-  - STM32100B-EVAL Set-up  
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
-    
-  - STM3210C-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
-
-  - STM3210E-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use LD1 and LD2 connected respectively to PF.06 and PF.07
-    
-  - STM3210B-EVAL Set-up  
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
- 
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h
deleted file mode 100644
index 210aea2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/JTAG_Remap/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c
deleted file mode 100644
index bfd9fac..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/JTAG_Remap/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
deleted file mode 100644
index ce8cb69..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_i2c_ee.h"
-
-
-#ifdef USE_STM3210E_EVAL
- #include "stm3210e_eval_lcd.h"
-#elif defined(USE_STM3210B_EVAL)
- #include "stm3210b_eval_lcd.h"
-#elif defined(USE_STM3210C_EVAL)
- #include "stm3210c_eval_lcd.h"
-#elif defined(USE_STM32100B_EVAL)
- #include "stm32100b_eval_lcd.h"
-#elif defined(USE_STM32100E_EVAL)
- #include "stm32100e_eval_lcd.h"
-#endif /* USE_STM3210E_EVAL */  
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_EEPROM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-/* Uncomment the following line to enable using LCD screen for messages display */
-#define ENABLE_LCD_MSG_DISPLAY
-
-#define sEE_WRITE_ADDRESS1        0x50
-#define sEE_READ_ADDRESS1         0x50
-#define BUFFER_SIZE1             (countof(Tx1_Buffer)-1)
-#define BUFFER_SIZE2             (countof(Tx2_Buffer)-1)
-#define sEE_WRITE_ADDRESS2       (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)
-#define sEE_READ_ADDRESS2        (sEE_READ_ADDRESS1 + BUFFER_SIZE1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a) (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-uint8_t Tx1_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
-                        buffer 1 transfer into address sEE_WRITE_ADDRESS1 */ \
-                        Example Description \
-                        This firmware provides a basic example of how to use the I2C firmware library and\
-                        an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the\
-                        example is interfacing with M24C64 EEPROM)\
-                          \
-                        I2C peripheral is configured in Master transmitter during write operation and in\
-                        Master receiver during read operation from I2C EEPROM. \
-                          \
-                        The peripheral used is I2C1 but can be configured by modifying the defines values\
-                        in stm32xxxx_eval.h file. The speed is set to 200kHz and can be configured by \
-                        modifying the relative define in stm32_eval_i2c_ee.h file.\
-                         \
-                        For M24C64 devices all the memory is accessible through the two-bytes \
-                        addressing mode and need to define block addresses. In this case, only the physical \
-                        address has to be defined (according to the address pins (E0,E1 and E2) connection).\
-                        This address is defined in i2c_ee.h (default is 0xA0: E0, E1 and E2 tied to ground).\
-                        The EEPROM addresses where the program start the write and the read operations \
-                        is defined in the main.c file. \
-                         \
-                        First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the\
-                        written data are read. The written and the read buffers data are then compared.\
-                        Following the read operation, the program waits that the EEPROM reverts to its \
-                        Standby state. A second write operation is, then, performed and this time, Tx2_Buffer\
-                        is written to EEPROM_WriteAddress2, which represents the address just after the last \
-                        written one in the first write. After completion of the second write operation, the \
-                        written data are read. The contents of the written and the read buffers are compared.\
-                         \
-                        All transfers are managed in DMA mode (except when 1-byte read/write operation is\
-                        required). Once sEE_ReadBuffer() or sEE_WriteBuffer() function is called, the \
-                        use application may perform other tasks in parallel while Read/Write operation is\
-                        managed by DMA.\
-                          \
-                        This example provides the possibility to use the STM32XXXX-EVAL LCD screen for\
-                        messages display (transfer status: Ongoing, PASSED, FAILED).\
-                        To enable this option uncomment the define ENABLE_LCD_MSG_DISPLAY in the main.c\
-                        file.                                                                              ";
-uint8_t Tx2_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
-                        buffer 2 transfer into address sEE_WRITE_ADDRESS2 */";
-uint8_t Rx1_Buffer[BUFFER_SIZE1], Rx2_Buffer[BUFFER_SIZE2];
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-volatile uint16_t NumDataRead = 0;
-
-/* Private functions ---------------------------------------------------------*/
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-#ifdef ENABLE_LCD_MSG_DISPLAY
-  /* Initialize the LCD screen for information display */
- #ifdef USE_STM3210E_EVAL
-  STM3210E_LCD_Init();
- #elif defined(USE_STM3210B_EVAL)
-  STM3210B_LCD_Init();
- #elif defined(USE_STM3210C_EVAL)
-  STM3210C_LCD_Init();
- #elif defined(USE_STM32100B_EVAL)
-  STM32100B_LCD_Init();
- #elif defined(USE_STM32100E_EVAL)
-  STM32100E_LCD_Init();
- #endif /* USE_STM3210E_EVAL */  
-  
-  /* Display application information */
-  LCD_Clear(LCD_COLOR_BLUE);  
-  LCD_SetBackColor(LCD_COLOR_BLUE);
-  LCD_SetTextColor(LCD_COLOR_WHITE);
-  LCD_DisplayStringLine(LCD_LINE_0, "SMT32F1xx FW Library");
-  LCD_DisplayStringLine(LCD_LINE_1, "   EEPROM Example   ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */    
-  
-  /* Initialize the I2C EEPROM driver ----------------------------------------*/
-  sEE_Init();  
-
-  /* First write in the memory followed by a read of the written data --------*/
-  /* Write on I2C EEPROM from sEE_WRITE_ADDRESS1 */
-  sEE_WriteBuffer(Tx1_Buffer, sEE_WRITE_ADDRESS1, BUFFER_SIZE1);
-
-  /* Set the Number of data to be read */
-  NumDataRead = BUFFER_SIZE1;
-  
-  /* Read from I2C EEPROM from sEE_READ_ADDRESS1 */
-  sEE_ReadBuffer(Rx1_Buffer, sEE_READ_ADDRESS1, (uint16_t *)(&NumDataRead)); 
-
-#ifdef ENABLE_LCD_MSG_DISPLAY  
-  LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 Ongoing ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */   
-
-  /* Wait till DMA transfer is complete (Transfer complete interrupt handler 
-    resets the variable holding the number of data to be read) */
-  while (NumDataRead > 0)
-  {    
-    /* Starting from this point, if the requested number of data is higher than 1, 
-       then only the DMA is managing the data transfer. Meanwhile, CPU is free to 
-       perform other tasks:
-       
-      // Add your code here: 
-      //...
-      //...
-  
-       For simplicity reasons, this example is just waiting till the end of the 
-       transfer. */    
-  }
-  
-  /* Check if the data written to the memory is read correctly */
-  TransferStatus1 = Buffercmp(Tx1_Buffer, Rx1_Buffer, BUFFER_SIZE1);
-  /* TransferStatus1 = PASSED, if the transmitted and received data 
-     to/from the EEPROM are the same */
-  /* TransferStatus1 = FAILED, if the transmitted and received data 
-     to/from the EEPROM are different */
-#ifdef ENABLE_LCD_MSG_DISPLAY  
-  if (TransferStatus1 == PASSED)
-  {
-    LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 PASSED  ");
-  }
-  else
-  {
-    LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 FAILED  ");
-  }  
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-
-/*----------------------------------
-  
-                                    ------------------------------------------*/
-  
-  /* Second write in the memory followed by a read of the written data -------*/
-  /* Write on I2C EEPROM from sEE_WRITE_ADDRESS2 */
-  sEE_WriteBuffer(Tx2_Buffer, sEE_WRITE_ADDRESS2, BUFFER_SIZE2);
-
-  /* Set the Number of data to be read */
-  NumDataRead = BUFFER_SIZE2;  
-  
-  /* Read from I2C EEPROM from sEE_READ_ADDRESS2 */
-  sEE_ReadBuffer(Rx2_Buffer, sEE_READ_ADDRESS2, (uint16_t *)(&NumDataRead));
-
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 Ongoing ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */  
-  
-  /* Wait till DMA transfer is complete (Transfer complete interrupt handler 
-    resets the variable holding the number of data to be read) */
-  while (NumDataRead > 0)
-  {
-    /* Starting from this point, if the requested number of data is higher than 1, 
-       then only the DMA is managing the data transfer. Meanwhile, CPU is free to 
-       perform other tasks:
-       
-      // Add your code here: 
-      //...
-      //...
-  
-       For simplicity reasons, this example is just waiting till the end of the 
-       transfer. */    
-  }
-  
-  /* Check if the data written to the memory is read correctly */
-  TransferStatus2 = Buffercmp(Tx2_Buffer, Rx2_Buffer, BUFFER_SIZE2);
-  /* TransferStatus2 = PASSED, if the transmitted and received data 
-     to/from the EEPROM are the same */
-  /* TransferStatus2 = FAILED, if the transmitted and received data 
-     to/from the EEPROM are different */
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  if (TransferStatus1 == PASSED)
-  {
-    LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 PASSED  ");
-  }
-  else
-  {
-    LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 FAILED  ");
-  }  
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-  
-  /* Free all used resources */
-  sEE_DeInit();
-
-#ifdef ENABLE_LCD_MSG_DISPLAY
-  /* Display end of example information */
-  LCD_DisplayStringLine(LCD_LINE_7, "---End Of Example---");
-#endif /* ENABLE_LCD_MSG_DISPLAY */  
-
-  while (1)
-  {
-  }
-}
-
-#ifndef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
-  * @brief  Example of timeout situation management.
-  * @param  None.
-  * @retval None.
-  */
-uint32_t sEE_TIMEOUT_UserCallback(void)
-{
-  /* Use application may try to recover the communication by resetting I2C
-    peripheral (calling the function I2C_SoftwareResetCmd()) then re-start
-    the transmission/reception from a previously stored recover point.
-    For simplicity reasons, this example only shows a basic way for errors 
-    managements which consists of stopping all the process and requiring system
-    reset. */
-  
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  /* Display error message on screen */
-  LCD_Clear(LCD_COLOR_RED);  
-  LCD_DisplayStringLine(LCD_LINE_4, "Communication ERROR!");
-  LCD_DisplayStringLine(LCD_LINE_5, "Try again after res-");
-  LCD_DisplayStringLine(LCD_LINE_6, "  etting the Board  ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-  
-  /* Block communication and all processes */
-  while (1)
-  {   
-  }  
-}
-
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt
deleted file mode 100644
index e928351..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
-  @page I2C_EEPROM I2C and M24CXX EEPROM communication example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    I2C/EEPROM/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the I2C and M24CXX EEPROM communication example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the I2C firmware library and
-an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the
-example is interfacing with M24CXX EEPROMs where XX={01, 02, 04, 08, 16, 32, 64}.
-
-I2C peripheral is configured in Master transmitter during write operation and in
-Master receiver during read operation from I2C EEPROM. 
-
-The peripheral used is I2C1 but can be configured by modifying the defines values
-in stm32_eval_i2c_ee.c file. The speed is set to 200kHz and can be configured to
-other values by setting the define I2C_SPEED in stm32_eval_i2c_ee.h file.
-All transfers are performed through DMA access (except for One Byte Receiving case)
-which allows user application to perform parallel tasks while transfer to/from 
-EEPROM is ongoing.
-
-For M24C02 to M24C16 devices, one I2C EEPROM Block address where the program will 
-write the buffer have to be selected from the four address available and defined 
-in the stm32_eval_i2c_ee.h file.
-
-For M24C32 and M24C64 devices all the memory is accessible through the two-bytes 
-addressing mode and need to define block addresses. In this case, only the physical 
-address has to be defined (according to the address pins (E0,E1 and E2) connection).
-This address is defined in stm32_eval_i2c_ee.c.h (default is 0xA0: E0, E1 and E2 
-tied to ground). 
-The EEPROM addresses where the program start the write and the read operations 
-is defined in the main.c file. 
-
-First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the
-written data are read. The written and the read buffers data are then compared.
-Following the read operation, the program waits that the EEPROM reverts to its 
-Standby state. A second write operation is, then, performed and this time, Tx2_Buffer
-is written to EEPROM_WriteAddress2, which represents the address just after the last 
-written one in the first write. After completion of the second write operation, the 
-written data are read. The contents of the written and the read buffers are compared.
-
-
-@par Directory contents 
-
-  - I2C/EEPROM/stm32f10x_conf.h    Library Configuration file
-  - I2C/EEPROM/stm32f10x_it.c      Interrupt handlers
-  - I2C/EEPROM/stm32f10x_it.h      Interrupt handlers header file
-  - I2C/EEPROM/main.c              Main program
-  - I2C/EEPROM/system_stm32f10x.c  STM32F10x system source file  
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STM32100E-EVAL (STM32F10x High-Density Value 
-    line) evaluation board (implemented EEPROM is M24C64) and STM3210C-EVAL 
-    (STM32F10x Connectivity-Line) evaluation board (implemented EEPROM is M24C64) 
-    with no additional hardware, and can be easily tailored to any other supported 
-    device and development board.
-
-  - STM32100E-EVAL Set-up 
-    - Make sure the jumper JP14 "ROM_WP" is fitted on the board.
-    - No additional Hardware connections are needed.
-
-
-  - STM3210C-EVAL Set-up 
-    - Make sure the Jumper JP17 "I2C_SCK" is fitted on the board.
-    - Make sure the jumper JP9 "ROM_WP" is fitted on the board.
-    - No additional Hardware connections are needed.
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
deleted file mode 100644
index e25eef8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-#define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c
deleted file mode 100644
index 4e76f63..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_EEPROM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h
deleted file mode 100644
index 5b97d9d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c
deleted file mode 100644
index 748cac7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
deleted file mode 100644
index f417dea..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/I2C_TSENSOR/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include <stdlib.h>
-#include "stm32_eval_i2c_tsensor.h"
-#include "stm32_eval.h"
-
-#ifdef USE_STM32100E_EVAL
-  #include "stm32100e_eval_lcd.h"
-#elif defined USE_STM3210E_EVAL
-  #include "stm3210e_eval_lcd.h"
-#elif defined USE_STM32100B_EVAL
-  #include "stm32100b_eval_lcd.h"
-#elif defined USE_STM3210B_EVAL
-  #include "stm3210b_eval_lcd.h"
-#endif
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_TSENSOR
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TEMPERATURE_THYS    31
-#define TEMPERATURE_TOS     32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static uint8_t TempCelsiusDisplay[]     = "       +abc.d C     ";
-static uint8_t TempFahrenheitDisplay[]  = "       +abc.d F     ";
-static int32_t TempValue = 0, TempValueCelsius = 0, TempValueFahrenheit = 0;
-__IO uint8_t SMbusAlertOccurred = 0; 
-uint32_t index = 0;
-      
-/* Private functions ---------------------------------------------------------*/
-void NVIC_Configuration(void);
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
- 
-  /* NVIC Configuration */
-  NVIC_Configuration();
-
-  /* Initialize the LCD */
-#ifdef USE_STM32100E_EVAL
-  STM32100E_LCD_Init();
-#elif defined USE_STM3210E_EVAL
-  STM3210E_LCD_Init();
-#elif defined USE_STM32100B_EVAL
-  STM32100B_LCD_Init();
-#elif defined USE_STM3210B_EVAL
-  STM3210B_LCD_Init();
-#endif
-
-  
-#ifdef USE_STM3210E_EVAL
-  /* Disable FSMC only for STM32 High-density and XL-density devices */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
-#endif /* USE_STM3210E_EVAL */
-  
-  /* Initialize the Temperature Sensor */
-  LM75_Init();
-
-  if (LM75_GetStatus() == SUCCESS)
-  {    
-#ifdef USE_STM3210E_EVAL
-    /* Enable FSMC */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-#endif /* USE_STM3210E_EVAL */
-    
-    /* Clear the LCD */
-    LCD_Clear(LCD_COLOR_WHITE);
-    
-    /* Set the Back Color */
-    LCD_SetBackColor(LCD_COLOR_BLUE);
-    
-    /* Set the Text Color */
-    LCD_SetTextColor(LCD_COLOR_GREEN);
-    
-    LCD_DisplayStringLine(LCD_LINE_0, "     Temperature    ");
-
-#ifdef USE_STM3210E_EVAL        
-    /* Disable FSMC */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
-
-    /* Initialize the Temperature Sensor */
-    LM75_Init();
-    
-#endif /* USE_STM3210E_EVAL */
-    
-    /* Configure the Temperature sensor device STLM75:
-    - Thermostat mode Interrupt
-    - Fault tolerance: 00
-    */
-    LM75_WriteConfReg(0x02);
-    
-    /* Configure the THYS and TOS in order to use the SMbus alert interrupt */
-    LM75_WriteReg(LM75_REG_THYS, TEMPERATURE_THYS << 8);  /*31ÝC*/
-    LM75_WriteReg(LM75_REG_TOS, TEMPERATURE_TOS << 8);   /*32ÝC*/
-    
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_SMBALERT);
-    
-    SMbusAlertOccurred = 0;
-    
-    /* Infinite Loop */
-    while (1)
-    {
-#ifdef USE_STM3210E_EVAL        
-    /* Disable FSMC */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
-
-    /* Initialize the Temperature Sensor */
-    LM75_Init();
-#endif /* USE_STM3210E_EVAL */
-      
-      /* Get double of Temperature value */
-      TempValue = LM75_ReadTemp();
-
-#ifdef USE_STM3210E_EVAL          
-      /* Enable FSMC */
-      RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-#endif /* USE_STM3210E_EVAL */
-      
-      if (TempValue <= 256)
-      {
-        /* Positive temperature measured */
-        TempCelsiusDisplay[7] = '+';
-        
-        /* Initialize the temperature sensor value*/
-        TempValueCelsius = TempValue;
-      }
-      else
-      {
-        /* Negative temperature measured */
-        TempCelsiusDisplay[7] = '-';
-        /* Remove temperature value sign */
-        TempValueCelsius = 0x200 - TempValue;
-      }
-      
-      /* Calculate temperature digits in ÝC */
-      if ((TempValueCelsius & 0x01) == 0x01)
-      {
-        TempCelsiusDisplay[12] = 0x05 + 0x30;
-        TempFahrenheitDisplay[12] = 0x05 + 0x30;
-      }
-      else
-      {
-        TempCelsiusDisplay[12] = 0x00 + 0x30;
-        TempFahrenheitDisplay[12] = 0x00 + 0x30;
-      }
-      
-      TempValueCelsius >>= 1;
-      
-      TempCelsiusDisplay[8] = (TempValueCelsius / 100) + 0x30;
-      TempCelsiusDisplay[9] = ((TempValueCelsius % 100) / 10) + 0x30;
-      TempCelsiusDisplay[10] = ((TempValueCelsius % 100) % 10) + 0x30;
-      
-      if (TempValue > 256)
-      {
-        if (((9 * TempValueCelsius) / 5) <= 32)
-        {
-          /* Convert temperature ÝC to Fahrenheit */
-          TempValueFahrenheit = abs (32 - ((9 * TempValueCelsius) / 5));
-          
-          /* Calculate temperature digits in ÝF */
-          TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
-          TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
-          TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
-          /* Positive temperature measured */
-          TempFahrenheitDisplay[7] = '+';
-        }
-        else
-        {
-          /* Convert temperature ÝC to Fahrenheit */
-          TempValueFahrenheit = abs(((9 * TempValueCelsius) / 5) - 32);
-          /* Calculate temperature digits in ÝF */
-          TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
-          TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
-          TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
-          
-          /* Negative temperature measured */
-          TempFahrenheitDisplay[7] = '-';
-        }
-      }
-      else
-      {
-        /* Convert temperature ÝC to Fahrenheit */
-        TempValueFahrenheit = ((9 * TempValueCelsius) / 5) + 32;
-        
-        /* Calculate temperature digits in ÝF */
-        TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
-        TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
-        TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
-        
-        /* Positive temperature measured */
-        TempFahrenheitDisplay[7] = '+';
-      }
-      
-      /* Display Fahrenheit value on LCD */
-      for (index = 0; index < 20; index++)
-      {
-        LCD_DisplayChar(LCD_LINE_6, (319 - (16 * index)), TempCelsiusDisplay[index]);
-        
-        LCD_DisplayChar(LCD_LINE_7, (319 - (16 * index)), TempFahrenheitDisplay[index]);
-      }
-      
-      if (SMbusAlertOccurred == 1)
-      {
-        /* Set the Back Color */
-        LCD_SetBackColor(LCD_COLOR_BLUE);
-        /* Set the Text Color */
-        LCD_SetTextColor(LCD_COLOR_RED);
-        LCD_DisplayStringLine(LCD_LINE_2, "Warning: Temp exceed");
-        LCD_DisplayStringLine(LCD_LINE_3, "        32 C        ");
-      }
-      if (SMbusAlertOccurred == 2)
-      {
-        /* Set the Back Color */
-        LCD_SetBackColor(LCD_COLOR_WHITE);
-        /* Set the Text Color */
-        LCD_SetTextColor(LCD_COLOR_WHITE);
-        LCD_ClearLine(LCD_LINE_2);
-        LCD_ClearLine(LCD_LINE_3);
-        SMbusAlertOccurred = 0;
-        /* Set the Back Color */
-        LCD_SetBackColor(LCD_COLOR_BLUE);
-        /* Set the Text Color */
-        LCD_SetTextColor(LCD_COLOR_GREEN);
-      }
-    }
-  }
-  else
-  {
-    LCD_Clear(LCD_COLOR_WHITE);
-    LCD_DisplayStringLine(LCD_LINE_2, " LM75 not correctly ");
-    LCD_DisplayStringLine(LCD_LINE_3, " initialized...     ");
-    LCD_DisplayStringLine(LCD_LINE_4, " Please restart the ");
-    LCD_DisplayStringLine(LCD_LINE_5, " example.           ");   
-    /* Infinite Loop */
-    while(1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Configures the different interrupt.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-  
-  /* Re-configure and enable I2C2 error interrupt to have the higher priority */
-#ifdef USE_STM32100E_EVAL
-  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
-#else
-  NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
-#endif
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h
deleted file mode 100644
index ce6e6ae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/I2C_TSENSOR/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
deleted file mode 100644
index 1ab4f75..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/I2C_TSENSOR/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval_i2c_tsensor.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_TSENSOR
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint8_t SMbusAlertOccurred;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-/**
-  * @brief  This function handles I2C2 Error interrupt request.
-  * @param  None
-  * @retval None
-  */
-#ifdef USE_STM32100E_EVAL
-void I2C2_ER_IRQHandler(void)
-#else
-void I2C1_ER_IRQHandler(void)
-#endif /* STM32100E-EVAL */
-{
-  /* Check on I2C2 SMBALERT flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_SMBALERT))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_SMBALERT);
-    SMbusAlertOccurred++;
-  }
-  /* Check on I2C2 Time out flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_TIMEOUT))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_TIMEOUT);
-  }
-  /* Check on I2C2 Arbitration Lost flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_ARLO))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_ARLO);
-  } 
-
-  /* Check on I2C2 PEC error flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_PECERR))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_PECERR);
-  } 
-  /* Check on I2C2 Overrun/Underrun error flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_OVR))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_OVR);
-  } 
-  /* Check on I2C2 Acknowledge failure error flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_AF))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_AF);
-  }
-  /* Check on I2C2 Bus error flag and clear it */
-  if (I2C_GetITStatus(LM75_I2C, I2C_IT_BERR))
-  {
-    I2C_ClearITPendingBit(LM75_I2C, I2C_IT_BERR);
-  }   
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
deleted file mode 100644
index 86b6e1b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/I2C_TSENSOR/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c
deleted file mode 100644
index cf56f60..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/I2C_TSENSOR/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
deleted file mode 100644
index 67d0244..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_IOExpander
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#ifdef USE_STM3210C_EVAL 
-  #define MESSAGE1   "   STM3210C-EVAL    " 
-#elif defined (USE_STM32100E_EVAL)
-  #define MESSAGE1   "   STM32100E-EVAL   " 
-#endif
-
-#define MESSAGE2   "  Example on how to " 
-#define MESSAGE3   " use the IO Expander"   
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /* Initialize LEDs and push-buttons mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  
-   /* Initialize the LCD */
-#ifdef USE_STM3210C_EVAL
-  STM3210C_LCD_Init();
-#elif defined (USE_STM32100E_EVAL)
-  STM32100E_LCD_Init();  
-#endif /* USE_STM3210C_EVAL */
- 
-  /* Clear the LCD */ 
-  LCD_Clear(White);
-  
-  /* Set the LCD Back Color */
-  LCD_SetBackColor(Blue);
-  
-  /* Set the LCD Text Color */
-  LCD_SetTextColor(White);    
- 
-  /* Display messages on the LCD */
-  LCD_DisplayStringLine(Line0, MESSAGE1);
-  LCD_DisplayStringLine(Line1, MESSAGE2);
-  LCD_DisplayStringLine(Line2, MESSAGE3);
-  
-  /* Configure the IO Expander */
-  if (IOE_Config() == IOE_OK)
-  {
-    /* Display "IO Expander OK" on the LCD */
-    LCD_DisplayStringLine(Line4, "   IO Expander OK   ");
-  }
-  else
-  { 
-    LCD_DisplayStringLine(Line4, "IO Expander FAILED ");
-    LCD_DisplayStringLine(Line5, " Please Reset the  ");
-    LCD_DisplayStringLine(Line6, "   board and start ");
-    LCD_DisplayStringLine(Line7, "    again          ");
-    while(1);
-  }
-
-  /* Draw a rectangle with the specifies parameters and Blue Color */
-  LCD_SetTextColor(Blue);
-  LCD_DrawRect(180, 310, 40, 60);
-  
-  /* Draw a rectangle with the specifies parameters and Red Color */
-  LCD_SetTextColor(Red);
-  LCD_DrawRect(180, 230, 40, 60);
-  
-  /* Draw a rectangle with the specifies parameters and Yellow Color */
-  LCD_SetTextColor(Yellow);
-  LCD_DrawRect(180, 150, 40, 60);
-  
-  /* Draw a rectangle with the specifies parameters and Black Color */
-  LCD_SetTextColor(Black);
-  LCD_DrawRect(180, 70, 40, 60);
-  
-
-#ifdef IOE_INTERRUPT_MODE
-
- #ifdef  USE_STM32100E_EVAL
-  /* Enable the Touch Screen interrupts */
-  IOE_ITConfig(IOE_ITSRC_TSC);
-  
- #else
-  /* Enable the Touch Screen and Joystick interrupts */
-  IOE_ITConfig(IOE_ITSRC_JOYSTICK | IOE_ITSRC_TSC);
- #endif /* USE_STM32100E_EVAL */
- 
-#endif /* IOE_INTERRUPT_MODE */
-  
-  /* Loop infinitely */
-  while(1)
-  {
-#ifdef IOE_POLLING_MODE
- static TS_STATE* TS_State;
-    
- #ifdef  USE_STM3210C_EVAL
- 
-    static JOY_State_TypeDef JoyState = JOY_NONE;
-    
-    /* Get the Joytick State */
-    JoyState = IOE_JoyStickGetState();
-    
-    switch (JoyState)
-    {
-	/* None Joystick has been selected */
-    case JOY_NONE:
-      LCD_DisplayStringLine(Line5, "JOY:     ----       ");
-      break; 
-    case JOY_UP:
-      LCD_DisplayStringLine(Line5, "JOY:     UP         ");
-      break;     
-    case JOY_DOWN:
-      LCD_DisplayStringLine(Line5, "JOY:    DOWN        ");
-      break;          
-    case JOY_LEFT:
-      LCD_DisplayStringLine(Line5, "JOY:    LEFT        ");
-      break;         
-    case JOY_RIGHT:
-      LCD_DisplayStringLine(Line5, "JOY:    RIGHT       ");
-      break;                 
-    case JOY_CENTER:
-      LCD_DisplayStringLine(Line5, "JOY:    CENTER      ");
-      break; 
-    default:
-      LCD_DisplayStringLine(Line5, "JOY:    ERROR       ");
-      break;         
-    }
- #endif /* USE_STM3210C_EVAL */
-    
-   
-    /* Update the structure with the current position of the Touch screen */
-    TS_State = IOE_TS_GetState();  
-    
-    if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180))
-    {
-      if ((TS_State->X > 10) && (TS_State->X < 70))
-      { 
-      /* Display LD4 on the LCD and turn on LED4 */
-        LCD_DisplayStringLine(Line6, " LD4                ");
-        STM_EVAL_LEDOn(LED4);
-      }
-      else if ((TS_State->X > 90) && (TS_State->X < 150))
-      {
-      /* Display LD3 on the LCD and turn on LED3 */
-        LCD_DisplayStringLine(Line6, "      LD3           ");
-        STM_EVAL_LEDOn(LED3);
-      }
-      else if ((TS_State->X > 170) && (TS_State->X < 230))
-      {
-      /* Display LD2 on the LCD and turn on LED2 */
-        LCD_DisplayStringLine(Line6, "           LD2      ");
-        STM_EVAL_LEDOn(LED2);
-      } 
-      else if ((TS_State->X > 250) && (TS_State->X < 310))
-      {
-      /* Display LD1 on the LCD and turn on LED1 */
-        LCD_DisplayStringLine(Line6, "                LD1 ");
-        STM_EVAL_LEDOn(LED1);
-      }
-      
-    }
-    else
-    {
-    /* Turn off LED1..4 */
-      STM_EVAL_LEDOff(LED1);
-      STM_EVAL_LEDOff(LED2);
-      STM_EVAL_LEDOff(LED3);
-      STM_EVAL_LEDOff(LED4);
-    }
-
-#endif /* IOE_POLLING_MODE */  
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-   LCD_DisplayStringLine(Line0, "assert_param error!!");
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h
deleted file mode 100644
index b14ffb0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-
-#if !(defined USE_STM32100E_EVAL) && !(defined USE_STM3210C_EVAL)
- #error "Please select STM3210C_EVAL or STM32100E_EVAL board For this example"
-#endif
-
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-#include <stdio.h>
- 
-#ifdef USE_STM3210C_EVAL
- #include "stm3210c_eval_lcd.h"
- #include "stm3210c_eval_ioe.h"
- 
-#elif defined USE_STM32100E_EVAL
- #include "stm32100e_eval_lcd.h"
- #include "stm32100e_eval_ioe.h"
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-// #define IOE_POLLING_MODE
-#define IOE_INTERRUPT_MODE
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt
deleted file mode 100644
index 9a187de..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
-  @page  IOExpander_Example I2C and STMPE811 IO Expander communication example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    I2C/IOExpander/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the I2C and STMPE811 IO Expander communication 
-  *          example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This firmware provides an example of configuring and using the IO Expander STMPE811 
-in order to control input Joystick IOs, output IOs and the Touch Screen feature.
-This example provides the elementary steps to control the following modules and
-use them in an application:
-The IO pins are used for:
-  - Getting Joystick pins status (Polling and interrupt) only for STM3210C-EVAL.
-  - The Touch Screen controller is used to get the Touched area detection information
-    in a single point mode (Polling and interrupt).
-    
-The input information can be used either in Polling mode (uncomment the define
-#define IOE_POLLING_MODE) or in Interrupt mode (uncomment the define #define
-IOE_INTERRUPT_MODE). These defines are in main.h file.
-
-After configuring the IO Expander modules and Interrupts (if needed), the output
-IOs are set to their default state. These operations are done by the functions: 
-IOE_Config() and IOE_ITConfig(). If the IO Expander is not operational (or the 
-I2C pins are not in the correct level) the IOE_Config() function returns a value
-different from 0 and a message is displayed on the LCD screen.
-
-To get the status of an input:
- - IOE_JoyStickGetState() function is used for Joystick and returns a JOY_State_TypeDef
-    value indicating the currently pressed key. This information is used to update 
-    the LCD display (the Joystick pressed key name is displayed) (only for STM3210C-EVAL).
- - IOE_TS_GetState() function is used for Touch Screen and returns a pointer to 
-    a structure holding the Touch Screen status (did a Touch Detection happened, 
-    X, Y, and Z positions). Only detection into the drawn rectangles areas is 
-    considered and used to update the LEDs status and LCD display (corresponding  
-    LED turned ON when its rectangle is touched, and the LED name is displayed on
-    the LCD screen).
-
-Besides, the examples checks the status of the other Push-Buttons implemented on
-the board (Key, Tamper and WakeUp push-buttons). They are checked in parallel 
-with the IO Expander IOs and the LCD display and LEDs are updated according to 
-the push buttons state. 
-
- 
-@par Directory contents 
-
-  - I2C/IOExpander/stm32f10x_conf.h     Library Configuration file
-  - I2C/IOExpander/stm32f10x_it.c       Interrupt handlers
-  - I2C/IOExpander/stm32f10x_it.h       Header for stm32f10x_it.c
-  - I2C/IOExpander/main.c               Main program
-  - I2C/IOExpander/main.h               Header for main.c
-  - I2C/IOExpander/system_stm32f10x.c   STM32F10x system source file
-
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density 
-    Value line, Low-Density and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line) and STM3210C-EVAL (Connectivity line) evaluation boards 
-    and can be easily tailored to any other supported device and development 
-    board.
-    
-  - STM32100E-EVAL Set-up 
-    - Use two IO Expanders connected to I2C2 SCL and SDA pins PB10 and PB11 and 
-      interrupt output pin connected to PA12 (EXTI mode). IO Expander 1 address 
-      pins is connected to Gnd (address is 0x82).
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF.07, PF.08
-      and PF.09 pins
-    - Use LCD connected to SPI3 remapped pins SCK, MISO and MOSI: PC10, PC11, 
-      PC12 and the CS pin PB2.
-    - Use LCD Touch Screen module connected to IO Expander 1 pins IO_Pin_1, 
-      IO_Pin_2, IO_Pin_3 and IO_Pin_4 (respectively Y-, X-, Y+, X+ lines).
-    
-  - STM3210C-EVAL Set-up 
-    - Use two IO Expanders connected to I2C1 SCL and SDA pins PB6 and PB7 and 
-      interrupt output pin connected to PB14 (EXTI mode). IO Expander 1 address 
-      pins is connected to Gnd (address is 0x82) and IO Expander 2 address pins 
-      is connected to Vcc (address is 0x88).  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - Use LCD connected to SPI3 remapped pins SCK, MISO and MOSI: PC10, PC11, 
-      PC12 and the CS pin PB2.
-    - Use LCD Touch Screen module connected to IO Expander 1 pins IO_Pin_1, 
-      IO_Pin_2, IO_Pin_3 and IO_Pin_4 (respectively Y-, X-, Y+, X+ lines).
-    - Use Joystick module connected to IO Expander 2 pins IO_Pin_3, IO_Pin_4, 
-      IO_Pin_5, IO_Pin_6 and IO_Pin_7 (respectively UP, Right, Left, Down and Center)
-
-          
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h
deleted file mode 100644
index 4a42998..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c
deleted file mode 100644
index a4c77be..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-  
-/** @addtogroup I2C_IOExpander
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles External lines 15 to 10 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI15_10_IRQHandler(void)
-{   
-  /* Checks whether the IOE EXTI line is asserted or not */
-  if(EXTI_GetITStatus(IOE_IT_EXTI_LINE) != RESET)
-  {
-    
-#ifdef IOE_INTERRUPT_MODE       
-    /* Check if the interrupt source is the Touch Screen */
-    if (IOE_GetGITStatus(IOE_1_ADDR, IOE_TS_IT) & IOE_TS_IT)
-    {
-      static TS_STATE* TS_State;
-      
-      /* Update the structure with the current position */
-      TS_State = IOE_TS_GetState();  
-      
-      if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180))
-      {
-        if ((TS_State->X > 10) && (TS_State->X < 70))
-        {
-          LCD_DisplayStringLine(Line6, " LD4                ");
-          STM_EVAL_LEDOn(LED4);
-        }
-        else if ((TS_State->X > 90) && (TS_State->X < 150))
-        {
-          LCD_DisplayStringLine(Line6, "      LD3           ");
-          STM_EVAL_LEDOn(LED3);
-        }
-        else if ((TS_State->X > 170) && (TS_State->X < 230))
-        {
-          LCD_DisplayStringLine(Line6, "           LD2      ");
-          STM_EVAL_LEDOn(LED2);
-        }     
-        else if ((TS_State->X > 250) && (TS_State->X < 310))
-        {
-          LCD_DisplayStringLine(Line6, "                LD1 ");
-          STM_EVAL_LEDOn(LED1);
-        }
-      }
-      else
-      {
-        STM_EVAL_LEDOff(LED1);
-        STM_EVAL_LEDOff(LED2);
-        STM_EVAL_LEDOff(LED3);
-        STM_EVAL_LEDOff(LED4);
-      }    
-      
-      /* Clear the interrupt pending bits */    
-      IOE_ClearGITPending(IOE_1_ADDR, IOE_TS_IT);      
-    }
- #ifdef USE_STM3210C_EVAL 
-    else if (IOE_GetGITStatus(IOE_2_ADDR, IOE_GIT_GPIO))
-    {
-      static JOY_State_TypeDef JoyState = JOY_NONE;
-      
-      /* Get the Joystick State */
-      JoyState = IOE_JoyStickGetState();
-      
-      switch (JoyState)
-      {
-      case JOY_NONE:
-        LCD_DisplayStringLine(Line5, "JOY: IT  ----       ");
-        break;
-      case JOY_UP:
-        LCD_DisplayStringLine(Line5, "JOY: IT  UP         ");
-        break;     
-      case JOY_DOWN:
-        LCD_DisplayStringLine(Line5, "JOY: IT DOWN        ");
-        break;          
-      case JOY_LEFT:
-        LCD_DisplayStringLine(Line5, "JOY: IT LEFT        ");
-        break;         
-      case JOY_RIGHT:
-        LCD_DisplayStringLine(Line5, "JOY: IT  RIGHT      ");
-        break;                 
-      case JOY_CENTER:
-        LCD_DisplayStringLine(Line5, "JOY: IT CENTER      ");
-        break; 
-      default:
-        LCD_DisplayStringLine(Line5, "JOY: IT ERROR       ");
-        break;         
-      }   
-      
-      /* Clear the interrupt pending bits */    
-      IOE_ClearGITPending(IOE_2_ADDR, IOE_GIT_GPIO);
-      IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT);     
-    }
-    /* CLear all pending interrupt */
-    IOE_ClearGITPending(IOE_2_ADDR, ALL_IT);
-    IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT);    
- #endif /* USE_STM3210C_EVAL */
-    
-    /* CLear all pending interrupt */
-    IOE_ClearGITPending(IOE_1_ADDR, ALL_IT);
-    
-#endif /* IOE_INTERRUPT_MODE */
-    
-    EXTI_ClearITPendingBit(IOE_IT_EXTI_LINE);
-  }  
-}
-
-/**
-  * @}
-  */ 
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h
deleted file mode 100644
index 91e8742..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI15_10_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c
deleted file mode 100644
index a892d06..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
deleted file mode 100644
index c79a83e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2S_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-I2S_InitTypeDef I2S_InitStructure;
-const uint16_t I2S3_Buffer_Tx[32] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
-                                     0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
-                                     0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
-                                     0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
-                                     0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
-                                     0x3D3E, 0x3F40};
-
-uint16_t I2S2_Buffer_Rx[32];
-__IO uint32_t TxIdx = 0, RxIdx = 0;
-TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-ErrorStatus HSEStartUpStatus;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  SPI_I2S_DeInit(SPI3);
-  SPI_I2S_DeInit(SPI2);
-  
-  /* I2S peripheral configuration */
-  I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
-  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16bextended;
-  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-  I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_48k;
-  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
-
-  /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
-  /* I2S3 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
-  I2S_Init(SPI3, &I2S_InitStructure);
-
-  /* I2S2 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
-  I2S_Init(SPI2, &I2S_InitStructure);
-
-  /* Enable the I2S3 TxE interrupt */
-  SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
-
-  /* Enable the I2S2 RxNE interrupt */
-  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
-
-  /* Enable the I2S2 */
-  I2S_Cmd(SPI2, ENABLE);
-
-  /* Enable the I2S3 */
-  I2S_Cmd(SPI3, ENABLE);
-
-  /* Wait the end of communication */
-  while (RxIdx < 32)
-  {}
-
-  TransferStatus1 = Buffercmp(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
-  /* TransferStatus1 = PASSED, if the data transmitted from I2S3 and received by
-                               I2S2 are the same
-     TransferStatus1 = FAILED, if the data transmitted from I2S3 and received by
-                               I2S2 are different */
-  
-  /* Reinitialize the buffers */
-  for (RxIdx = 0; RxIdx < 32; RxIdx++)
-  {
-    I2S2_Buffer_Rx[RxIdx] = 0;
-  }
-  TxIdx = 0;
-  RxIdx = 0;
-
-  SPI_I2S_DeInit(SPI3);
-  SPI_I2S_DeInit(SPI2);  
-  
-  /* I2S peripheral configuration */
-  I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
-  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_24b;
-  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-  I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_16k;
-  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
-
-  /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
-  /* I2S3 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
-  I2S_Init(SPI3, &I2S_InitStructure);
-
-  /* I2S2 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
-  I2S_Init(SPI2, &I2S_InitStructure);
-
-  /* Enable the I2S3 TxE interrupt */
-  SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
-
-  /* Enable the I2S2 RxNE interrupt */
-  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
-
-  /* Enable the I2S2 */
-  I2S_Cmd(SPI2, ENABLE);
-
-  /* Enable the I2S3 */
-  I2S_Cmd(SPI3, ENABLE);
-
-  /* Wait the end of communication */
-  while (RxIdx < 32)
-  {
-  }
-
-  TransferStatus2 = Buffercmp24bits(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
-  /* TransferStatus2 = PASSED, if the data transmitted from I2S3 and received by
-                               I2S2 are the same
-     TransferStatus2 = FAILED, if the data transmitted from I2S3 and received by
-                               I2S2 are different */     
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if(HSEStartUpStatus == SUCCESS)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 2 wait state */
-    FLASH_SetLatency(FLASH_Latency_2);
-	
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK/2 */
-    RCC_PCLK1Config(RCC_HCLK_Div2);
-
-    /* ADCCLK = PCLK2/4 */
-    RCC_ADCCLKConfig(RCC_PCLK2_Div4); 
-  
-#ifndef STM32F10X_CL  
-    /* PLLCLK = 8MHz * 9 = 72 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
-
-#else
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
-
-    /* PLL3 configuration: PLL3CLK = (HSE / 5) * 11 => PLL3_VCO = 110 MHz */
-    RCC_PLL3Config(RCC_PLL3Mul_11);
-    /* Enable PLL3 */
-    RCC_PLL3Cmd(ENABLE);    
-    /* Wait till PLL3 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
-    {}
-
-    /* Configure I2S clock source: On Connectivity Line Devices, the I2S can be 
-        clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher 
-        precision */
-    RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO);
-    RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO);  
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while(RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }  
-  
-  /* Enable peripheral clocks ------------------------------------------------*/
-  /* GPIOA, GPIOB and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_AFIO, ENABLE);
-
-#ifdef USE_STM3210C_EVAL 
-  /* GPIOC Clock enable (for the SPI3 remapped pins)  */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);  
-#endif /* USE_STM3210C_EVAL */
-  
-  /* SPI3 and SPI2 clocks enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3 | RCC_APB1Periph_SPI2, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210E_EVAL
-  /* Disable the JTAG interface and enable the SWJ interface
-      This operation is not necessary for Connectivity Line devices since
-      SPI3 I/Os can be remapped on other GPIO pins */
-  GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
-#endif /* USE_STM3210E_EVAL */ 
-
-  /* Configure SPI2 pins: CK, WS and SD ---------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-#ifdef USE_STM3210C_EVAL
-  
-  /* Remap SPI3 on PC10-PC11-PC12-PA4 GPIO pins ------------------------*/
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
-  
-  /* Configure SPI3 pins: CK and SD ------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);  
-
-  /* Configure SPI3 pins: WS -------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  
-#elif defined (USE_STM3210E_EVAL)
-  
-  /* Configure SPI3 pins: CK and SD ------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* Configure SPI3 pins: WS -------------------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  
-#endif /* USE_STM3210C_EVAL */  
-}
-
-/**
-  * @brief  Configure the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-
-  /* SPI3 IRQ Channel configuration */
-  NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* SPI2 IRQ channel configuration */
-  NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-/**
-  * @brief  Compares two buffers in 24 bits data format.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      if (*pBuffer1 != (*pBuffer2 & 0xFF00))
-      {
-        return FAILED;
-      }
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h
deleted file mode 100644
index f7f98b6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c
deleted file mode 100644
index eb3764d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2S_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern const uint16_t I2S3_Buffer_Tx[32];
-extern uint16_t I2S2_Buffer_Rx[32];
-extern  __IO uint32_t TxIdx, RxIdx;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles SPI3 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void SPI3_IRQHandler(void)
-{
-  /* Check the interrupt source */
-  if (SPI_I2S_GetITStatus(SPI3, SPI_I2S_IT_TXE) == SET)
-  {
-    /* Send a data from I2S3 */
-    SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
-  }
-
-  /* Check the end of buffer transfer */
-  if (RxIdx == 32)
-  {
-    /* Disable the I2S3 TXE interrupt to end the communication */
-    SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, DISABLE);
-  }
-}
-
-/**
-  * @brief  This function handles SPI2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void SPI2_IRQHandler(void)
-{
-  /* Check the interrupt source */
-  if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_RXNE) == SET)
-  {
-    /* Store the I2S2 received data in the relative data table */
-    I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h
deleted file mode 100644
index d78b0da..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void SPI2_IRQHandler(void);
-void SPI3_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c
deleted file mode 100644
index e8b2dd4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c
deleted file mode 100644
index 3a0c3d5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/SPI_I2S_Switch/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2S_SPI_I2S_Switch
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_Switch_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h
deleted file mode 100644
index 9a9d957..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/SPI_I2S_Switch/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c
deleted file mode 100644
index e34f002..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/SPI_I2S_Switch/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt
deleted file mode 100644
index 667f562..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
-  @page IWDG_Reset IWDG Reset example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    IWDG/IWDG_Reset/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the IWDG Reset example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to update at regular period the IWDG reload counter and 
-how to simulate a software fault generating an MCU IWDG reset on expiry of a 
-programmed time period.
-
-The IWDG timeout is set to 250 ms (the timeout may varies due to LSI frequency 
-dispersion).
-
-First, the TIM5 timer is configured to measure the LSI frequency as the 
-LSI is internally connected to TIM5 CH4, in order to adjust the IWDG clock.
-
-The LSI measurement using the TIM5 is described below:
- - Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to 
-   the LSI clock output.
- - Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the
-   period value is stored in a variable and compared to the HCLK clock to get
-   its real value. 
-
-@note The LSI is internally connected to TIM5 IC4 only on STM32F10x Connectivity 
-      line, High-Density Value line, High-Density and XL-Density Devices.
-      When using other devices, you should comment the "#define LSI_TIM_MEASURE"
-      in main.c file and in this case the LSI frequency is set by default to 40KHz.
-   
-Then, the IWDG reload counter is configured to obtain 240ms according to the 
-measured LSI frequency.
-
-The IWDG reload counter is refreshed each 240ms in the main program infinite loop 
-to prevent a IWDG reset.
-LED2 is also toggled each 240ms indicating that the program is running.
-
-An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
-on the rising edge of the signal.
-
-The EXTI Line is used to simulate a software failure: once the EXTI Line event 
-occurs, by pressing the Key push-button, the corresponding interrupt is served.
-In the ISR, a write to invalid address generates a Hardfault exception containing
-an infinite loop and preventing to return to main program (the IWDG reload counter 
-is not refreshed).
-As a result, when the IWDG counter reaches 00h, the IWDG reset occurs.
-If the IWDG reset is generated, after the system resumes from reset, LED1 turns on.
-
-If the EXTI Line event does not occur, the IWDG counter is indefinitely refreshed
-in the main program infinite loop, and there is no IWDG reset.
-
-
-In this example the system clock is set to 24 MHz on Value line devices and to
-72MHz on other devices.
-
-@note The IWDG Counter can be only written when the RVU flag is reset. 
-      In this example, as the SysTick period is too higher than the IWDG Counter
-      Update timing (5 Cycles 40KHz RC), the Reload Value Update "RVU" flag is 
-      not checked before reloading the counter.
-
-@par Directory contents 
-
-  - IWDG/IWDG_Reset/stm32f10x_conf.h     Library Configuration file
-  - IWDG/IWDG_Reset/stm32f10x_it.c       Interrupt handlers
-  - IWDG/IWDG_Reset/stm32f10x_it.h       Header for stm32f10x_it.c
-  - IWDG/IWDG_Reset/main.c               Main program
-  - IWDG/IWDG_Reset/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density 
-    Value line, Low-Density and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density), STM32100E-EVAL 
-    (High-Density Value line) and STM3210B-EVAL (Medium-Density) evaluation 
-    boards and can be easily tailored to any other supported device and development 
-    board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
-    
-  - STM32100B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1 and LD2 connected respectively to PD.07 and PD.13 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    
-  - STM3210E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory 
- - Link all compiled files and load your image into target memory
- - Run the example in standalone mode (without debugger connection)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h
deleted file mode 100644
index 0424491..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    IWDG/IWDG_Reset/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c
deleted file mode 100644
index 1b359b2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    IWDG/IWDG_Reset/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c
deleted file mode 100644
index aa882ef..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Lib_DEBUG/RunTime_Check/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32f10x_ip_dbg.h"
-#include "stm32_eval.h"
-#include <stdio.h>
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup Lib_DEBUG_RunTime_Check
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
- USART_InitTypeDef USART_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-#ifdef __GNUC__
-  /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
-     set to 'Yes') calls __io_putchar() */
-  #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
-#else
-  #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
-#endif /* __GNUC__ */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  GPIO_InitTypeDef GPIOA_InitStructure;
-
-  /* USARTx configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-
-  /* Initialize all peripherals pointers */
-  debug();
-  
-  printf("\r\n STM32F10x Firmware Library compiled with FULL ASSERT function... \n\r");
-  printf("...Run-time checking enabled  \n\r");
-
-  /* Simulate wrong parameter passed to library function ---------------------*/
-  /* To enable SPI1 clock, RCC_APB2PeriphClockCmd function must be used and
-     not RCC_APB1PeriphClockCmd */
-  RCC_APB1PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
-  
-  /* Some member of GPIOA_InitStructure structure are not initialized */
-  GPIOA_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIOA_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  /* GPIOA_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; */
-  GPIO_Init(GPIOA, &GPIOA_InitStructure);
-  
-  while (1)
-  {
-  }
-
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number */
-
-  printf("\n\r Wrong parameter value detected on\r\n");
-  printf("       file  %s\r\n", file);
-  printf("       line  %d\r\n", line);
-    
-  /* Infinite loop */
-  /* while (1)
-  {
-  } */
-}
-
-#endif
-
-/**
-  * @brief  Retargets the C library printf function to the USART.
-  * @param  None
-  * @retval None
-  */
-PUTCHAR_PROTOTYPE
-{
-  /* Place your implementation of fputc here */
-  /* e.g. write a character to the USART */
-  USART_SendData(EVAL_COM1, (uint8_t) ch);
-
-  /* Loop until the end of transmission */
-  while(USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
-  {
-  }
-
-  return ch;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
deleted file mode 100644
index 2d6baa3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-#define USE_FULL_ASSERT    1
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
deleted file mode 100644
index 84bc179..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the library peripherals Debug.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10X_IP_DBG_H
-#define __STM32F10X_IP_DBG_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void debug(void);
-					 
-#endif /* __STM32F10X_IP_DBG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html
deleted file mode 100644
index 643c366..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html
+++ /dev/null
@@ -1,2010 +0,0 @@
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-  
-  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
-
-  
-  <link rel="File-List" href="Library_Examples_files/filelist.xml">
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-  <link rel="Edit-Time-Data" href="Library_Examples_files/editdata.mso"><!--[if !mso]>
-
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-
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-  <o:LastAuthor>Youssef GHANNOUCHI</o:LastAuthor>
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-  <o:TotalTime>17</o:TotalTime>
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-  <o:Created>2010-04-21T19:58:00Z</o:Created>
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-  <link rel="themeData" href="Library_Examples_files/themedata.thmx">
-
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-
- </o:shapelayout></xml><![endif]-->
-  <meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
-<div class="WordSection1">
-<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
-<div align="center">
-<table class="MsoNormalTable" style="width: 796.5pt;" border="0" cellpadding="0" cellspacing="0" width="1062">
-  <tbody>
-    <tr style="">
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-      
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-            <p class="MsoNormal" style="text-align: center;" align="center"><strong><span style="font-size: 18pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">STM32F10x
-Standard Peripherals&nbsp;Library: <i>Peripheral&#8217;s examples</i></span></strong><strong><span style="font-size: 18pt; color: rgb(51, 102, 255);"><o:p></o:p></span></strong></p>
-            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
-            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">Copyright
-2011 STMicroelectronics<o:p></o:p></span></p>
-            <p style="text-align: center;" class="MsoNormal" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1033" src="../../_htmresc/logo.bmp"></span><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></p>
-            </td>
-          </tr>
-        </tbody>
-      </table>
-      <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
-      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-        <tbody>
-          <tr>
-            <td style="padding: 0in;" valign="top">
-            <table class="MsoNormalTable" style="width: 790.5pt;" border="0" cellpadding="0" cellspacing="5" width="1054">
-              <tbody>
-                <tr style="height: 31.5pt;">
-                  <td style="padding: 0in; width: 842pt; height: 31.5pt;" valign="top" width="1123">
-                  <table style="width: 620.25pt;" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="0" width="827">
-                    <tbody>
-                      <tr style="">
-                        <td style="padding: 1.5pt; width: 827.7pt;" width="1104">
-                        <p style="text-align: justify;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">The
-STM32F10x Standard Peripherals&nbsp;library provides a rich set of
-examples covering the main features of each peripheral. All the
-examples are independent from the software toolchain. </span><span style="font-size: 10pt; font-family: Arial;">These
-examples run on STMicroelectronics </span>
-                                          <span style="font-size: 10pt; font-family: Arial;">STM32100E-EVAL (High-density Value line), 
-                                          </span>
-                                          <span style="font-size: 10pt; font-family: Arial;">STM32100B-EVAL
-(Medium-density Value line),&nbsp;STM3210C-EVAL
-(Connectivity&nbsp;line), STM3210E-EVAL (High-density and XL-density)
-and STM3210B-EVAL (Medium-density)&nbsp;evaluation boards</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"> and can be easily tailored to any
-other supported device and development board. Only source files are
-provided for each example and user can tailor the provided&nbsp;project
-template to run the selected example with his preferred toolchain.<br>
-<br>
-                        </span></p>
-                        <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">How to
-proceed?</span><span style=""><o:p></o:p></span></h2>
-
-                        
-                        
-                        <ul>
-</ul>
-                        
-                        <ul>
-
-                          
-                          </ul>
-                        <ul>
-                          <li>
-                            <p><small><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">Copy the files <span style="font-weight: bold;">main.c</span>, <span style="font-weight: bold;">main.h</span> (if exists), <span style="font-weight: bold;">stm32f10x_it.c</span>, <span style="font-weight: bold;">system_stm32f10x.c</span>, <span style="font-weight: bold;">stm32f10x_it.h</span>, <span style="font-weight: bold;">stm32f10x_conf.h</span> and any other source files from the specified example to your toolchain folder under <span style="font-weight: bold;">Project\STM32F10x_StdPeriph_Template</span>. This project folder contains already all toolchain files needed for creating projects for STM32F10x microcontrollers.</span></small></p>
-                          </li>
-                        </ul>
-                        <ul>
-                          <li>
-                            <p><small><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">Open your preferred toolchain<br>
-                            </span></small></p>
-                          </li>
-                        </ul>
-                        <ul>
-                          <li>
-                            <p><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><small>If needed, add in the project list the additional files required to run the example (refer to your example readme file)<br>
-                            </small></span></p>
-                          </li>
-                          <li>
-                            <p><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><small>Rebuild all files and load your image into target memory</small></span></p>
-                          </li>
-                          <li>
-                            <p><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><small>Run the example</small></span></p>
-                          </li>
-                        </ul>
-<ul>
-
-                        
-                        </ul>
-
-                        <span style="font-family: &quot;Times New Roman&quot;,&quot;serif&quot;;"></span>
-
-                        <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span class="GramE"><span style="font-size: 12pt; color: white;">STM32F10x &nbsp;StdPeriph</span></span><span style="font-size: 12pt; color: white;">_Lib Examples</span><span style=""><o:p></o:p></span></h2>
-                        <p><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">The
-package contains the following examples:</span></p>
-                        <p class="MsoNormal" style="text-align: center;" align="center"><font size="+2"><font size="+3"><a href="#ADC"><span style="font-size: 7.5pt;">A</span><span style="font-size: 7.5pt;">DC</span></a></font><span style="font-size: 7.5pt;"> - <a href="#BKP">BKP</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"><a href="#CAN">CAN</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"><a href="#CEC">CEC</a> -</span></font><font size="+2"><span style="font-size: 7.5pt;"></span></font><font size="+2"><span style="font-size: 7.5pt;"> <a href="#CortexM3">CortexM3</a> - <a href="#CRC">CRC</a> - <a href="#DAC">DAC</a> - <a href="#DMA">DMA</a> - <a href="#EXTI">EXTI</a>
-- <a href="#FLASH">FLASH</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"><a href="#FSMC">FSMC</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"> <a href="#GPIO">GPIO</a> - <a href="#I2C">I2C</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"><a href="#I2S">I2S</a> -</span></font><font size="+2"><span style="font-size: 7.5pt;"> <a href="#IWDG">IWDG</a> - <a href="#Lib_DEBUG"><span class="SpellE">Lib_DEBUG</span></a> - <a href="#NVIC">NVIC</a> - <a href="#PWR">PWR</a> - <a href="#RCC">RCC</a>
-- <a href="#RTC">RTC</a> - </span></font><font size="+2"><span style="font-size: 7.5pt;"><a href="#SDIO">SDIO</a> -</span></font><font size="+2"><span style="font-size: 7.5pt;"> <a href="#SPI">SPI</a> - <a href="#SysTick">SysTick</a> - <a href="#TIM">TIM</a> - <a href="#USART">USART</a> - <a href="#WWDG">WWDG</a></span><span style="font-size: 10pt;"><o:p></o:p></span></font></p><big><big><big><br></big></big></big>
-                        <table class="MsoNormalTable" style="width: 660pt; margin-left: 4.65pt; border-collapse: collapse;" border="0" cellpadding="0" cellspacing="0" width="880">
-
- <tbody><tr style="height: 16.5pt;">
-  <td rowspan="2" style="border-style: solid; border-color: blue windowtext black blue; border-width: 1.5pt 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(102, 102, 153) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 16.5pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: center; line-height: normal;" align="center"><b><span style="font-size: 14pt; color: white;">IP/Module</span></b></p>
-  </td>
-  <td colspan="2" style="border-style: solid solid solid none; border-color: blue blue windowtext -moz-use-text-color; border-width: 1.5pt 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(102, 102, 153) none repeat scroll 0% 50%; width: 583pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 16.5pt;" nowrap="nowrap" width="777">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: center; line-height: normal;" align="center"><b><span style="font-size: 14pt; color: white;">Example</span></b></p>
-  </td>
- </tr>
- <tr style="height: 16.5pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(102, 102, 153) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 16.5pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: center; line-height: normal;" align="center"><b><span style="font-size: 12pt; color: white;">Name</span></b></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(102, 102, 153) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 16.5pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: center; line-height: normal;" align="center"><b><span style="font-size: 12pt; color: white;">Brief Description</span></b></p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="6" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11.05pt; line-height: normal;"><b>&nbsp;<a href="ADC">ADC</a></b></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">3 ADCs DMA</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="ADC"></a>This example describes how to use the 3 ADCs in
-  independent conversions. <br>
-  Two of them; ADC1 and ADC3 are transferring continuously converted data using
-  DMA while ADC2 converted data are stored using End of conversion interrupt.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC1 DMA</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use the ADC1 and
-  DMA to transfer continuously <br>
-  converted data from ADC1 to memory.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC analog watchdog</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use the ADC analog
-  watchdog to guard continuously an ADC channel.</p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC external lines trigger</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to trigger ADC regular
-  and injected groups channels <br>
-  conversion using two external line events. Discontinuous mode is enabled for
-  regular group channel conversion and configured to convert one regular
-  channel on each external trigger.</p>
-  </td>
- </tr>
- <tr style="height: 75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC regular simultaneous dual mode</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use ADC1 and ADC2
-  in regular simultaneous dual mode. ADC1 is configured to convert channel14
-  and channel17 regular channels continuously. ADC2 is configured to convert
-  channel11 and channel12 regular channels continuously. The connection between
-  internal Vref and channel17 is enabled for ADC1.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC TIM trigger and auto-injection</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to convert ADC regular
-  group channels continuously using TIM1 external trigger and injected group
-  channels using the auto-injected feature.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="2" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="BKP"><b>BKP</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Backup Data</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="BKP"></a>This example shows how to store user data in the
-  Backup data registers.<br>
-  As the Backup (BKP) domain still powered by VBAT when VDD is switched off,
-  its<br>
-  contents are not lost if a battery is connected to VBAT pin.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">BKP Tamper</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to write/read data to/from
-  Backup data registers and <br>
-  demonstrates the Tamper detection feature.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="3" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="CAN"><b>CAN</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">LoopBack</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="CAN"></a>This example provides a description of how to set
-  a communication with the CAN<br>
-  in loopback mode.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Networking (Ex: Normal)</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to configure the CAN
-  peripheral to send and receive CAN frames in normal mode. The sent frames are
-  used to control Leds by pressing key push button.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Dual CAN</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to configure the CAN1 and
-  CAN2 peripherals to send and <br>
-  receive CAN frames in normal mode. The sent frames are used to control Leds
-  by <br>
-  pressing KEY or Tamper push buttons.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11.05pt; line-height: normal;"><a href="CEC"><b>CEC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">CEC Data Exchange using Interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="CEC"></a>This example shows how to configure the HDMI-CEC
-  peripheral and how to create CEC network providing a high level communication
-  between three different devices using CEC protocol messages.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="3" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="CortexM3"><b>CortexM3</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Bit Banding</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="CortexM3"></a>This example shows how to use CortexM3 Bit-Band
-  access to perform atomic read-modify-write and read operations on a variable
-  in SRAM.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">MPU</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example presents the MPU features on
-  STM32F10x XL-density devices and it <br>
-  can be easily ported to any other STM32 device supporting MPU.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Mode Privilege</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to modify CortexM3 Thread
-  mode privilege access and stack. CortexM3 Thread mode is entered on Reset,
-  and can be entered as a result of an exception return.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="CRC"><b>CRC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">CRC Calculation</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="CRC"></a>This example shows how to use CRC (cyclic
-  redundancy check) calculation unit to get a CRC code of a given buffer of
-  data word (32-bit), based on a fixed generator polynomial (0x4C11DB7).</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="4" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="DAC"><b>DAC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DAC dual mode sine wave</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="DAC"></a>This example describes how to use DAC dual
-  channel mode with DMA to generate sine waves on both DAC channels outputs.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DAC one channel noise wave</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use one DAC channel
-  to generate a signal with noise waves on DAC Channel1 output.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DAC one channel DMA escalator</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use one DAC channel
-  mode with DMA to generate an escalator signal on DAC channel1 output.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DAC two channels triangle wave</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example describes how to use two DAC
-  channels to generate two different<br>
-  signals with triangle waves on each DAC Channel output.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="5" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11.05pt; line-height: normal;"><b>&nbsp;<a href="DMA">DMA</a></b></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">ADC1 TIM1</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="DMA"></a>This example provides a description of how to use
-  a DMA channel to transfer<br>
-  continuously a data from a peripheral (ADC1) to another peripheral (TIM1)
-  supporting DMA transfer.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">FLASH to RAM</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a description of how to use
-  a DMA channel to transfer <br>
-  a word data buffer from FLASH memory to embedded SRAM memory.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">FSMC</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a description of how to use
-  two DMA channels to transfer<br>
-  a word data buffer from Flash memory to external SRAM memory and to
-  recuperate<br>
-  the written data from external SRAM to be stored in internal SRAM.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">I2C to RAM</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a description of how to use
-  two DMA channels to transfer a <br>
-  data buffer from memory to I2C2 through I2C1.</p>
-  </td>
- </tr>
- <tr style="height: 75.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">SPI to RAM</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a description of how to use
-  four DMA channels to transfer<br>
-  a data buffer from memory to SPI_SLAVE through SPI_MASTER and a second data
-  buffer from memory to SPI_MASTER through SPI_SLAVE in full-duplex mode.<br>
-  SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on
-  the<br>
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 60.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="EXTI"><b>EXTI</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">EXTI configuration</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="EXTI"></a>This example shows how to configure external
-  interrupt lines.<br>
-  In this example, 2 EXTI lines (EXTI0 and EXTI8 or EXTI9) are configured <br>
-  to generate an interrupt on each rising or falling edge. In the interrupt
-  routine <br>
-  a led connected to a specific GPIO pin is toggled.</p>
-  </td>
- </tr>
- <tr style="height: 15.75pt;">
-  <td rowspan="3" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="FLASH"><b>FLASH</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Program</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="FLASH"></a>This example provides a description of how to
-  program the STM32F10x FLASH.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color windowtext -moz-use-text-color -moz-use-text-color; border-width: medium 1pt medium medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">XL-Density devices FLASH Dual Boot capability</p>
-  </td>
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color blue -moz-use-text-color -moz-use-text-color; border-width: medium 1.5pt medium medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example demonstrates the dual Flash boot
-  capability of XL-Density devices: <br>
-  boot from Flash memory Bank1 or Bank2.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: solid solid solid none; border-color: windowtext windowtext windowtext -moz-use-text-color; border-width: 1pt 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Write Protection</p>
-  </td>
-  <td style="border-style: solid solid solid none; border-color: windowtext blue windowtext -moz-use-text-color; border-width: 1pt 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a description of how to
-  enable and disable the write protection for the STM32F10x FLASH.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="6" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="FSMC"><b>FSMC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">NAND</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="FSMC"></a>This example provides a basic example of how to
-  use the FSMC firmware library and an associate driver to perform
-  erase/read/write operations on the NAND512W3A2 memory mounted on
-  STM3210E-EVAL board.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">NOR</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a basic example of how to
-  use the FSMC firmware library and an associate driver to perform
-  erase/read/write operations on the M29W128FL, M29W128GL or S29GL128P NOR
-  memories mounted on the STM3210E-EVAL board.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">NOR_CodeExecute</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This directory contains a set of sources files
-  that describes how to build an<br>
-  application to be loaded into the NOR memory mounted on STM3210E-EVAL board
-  then execute it from internal Flash.</p>
-  </td>
- </tr>
- <tr style="height: 75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">One-NAND</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to configure the FSMC to
-  drive the OneNAND memory mounted on STM32100E-EVAL board. In this example a
-  basic example of how to use the FSMC firmware library and an associate driver
-  to perform read/write operations on the KFG1216U2A/B-DIB6 OneNAND memory.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">SRAM</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a basic example of how to
-  use the FSMC firmware library and an associate driver to perform read/write
-  operations on the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">SRAM DataMemory</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example shows how to use the external SRAM
-  mounted on STM3210E-EVAL or <br>
-  STM32100E-EVAL board as program data memory and internal SRAM for Stack.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="2" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="GPIO"><b>GPIO</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IO Toggle</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;"><a name="GPIO"></a>GPIO ports are connected on APB2 bus, using BSRRH
-  and BSRRL registers 2 cycles <br>
-  are required to set a pin and another cycle to reset it. So GPIO pins can
-  toggle <br>
-  at AHB clock divided by 4.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">JTAG Remap</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify; line-height: normal;">This example provides a short description of how
-  to use the JTAG IOs as standard <br>
-  GPIOs and gives a configuration sequence.</p>
-  </td>
- </tr>
- <tr style="height: 75pt;">
-  <td rowspan="3" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11.05pt; line-height: normal;"><a href="I2C"><b>I2C</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">I2C and M24CXX EEPROM communication</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="I2C"></a>This example provides a basic example of
-  how to use the I2C firmware library and<br>
-  an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here
-  the example is interfacing with M24CXX EEPROMs where XX={01, 02, 04, 08, 16,
-  32, 64}. I2C peripheral is configured in Master transmitter during write
-  operation and in Master receiver during read operation from I2C EEPROM. </p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color windowtext -moz-use-text-color -moz-use-text-color; border-width: medium 1pt medium medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">I2C and LM75 Temperature Sensor communication</p>
-  </td>
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color blue -moz-use-text-color -moz-use-text-color; border-width: medium 1.5pt medium medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use the I2C to communicate with <br>
-  an STLM75 (or a compatible device) I2C temperature sensor is mounted on the <br>
-  evaluation board and used to get instantaneous external temperature<br>
-  (-55°C to +125°C).</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: solid solid solid none; border-color: windowtext windowtext windowtext -moz-use-text-color; border-width: 1pt 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">I2C and STMPE811 IO Expander communication</p>
-  </td>
-  <td style="border-style: solid solid solid none; border-color: windowtext blue windowtext -moz-use-text-color; border-width: 1pt 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This firmware provides an example of
-  configuring and using the IO Expander STMPE811 in order to control input
-  Joystick IOs, output IOs and the Touch Screen feature.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="2" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="I2S"><b>I2S</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="I2S"></a>This example provides a description of
-  how to set a communication between two<br>
-  SPIs in I2S mode using interrupts and performing a transfer from Master to
-  Slave.</p>
-  </td>
- </tr>
- <tr style="height: 60.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">SPI_I2S_Switch</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to set a communication between two<br>
-  SPIs in I2S mode, and how to switch between SPI and I2S modes, performing a <br>
-  transfer from Master to Slave in I2S modes then a transfer from master to
-  slave <br>
-  in SPI mode and finally a transfer from Slave to Master in I2S mode.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="IWDG"><b>IWDG</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IWDG Reset</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="IWDG"></a>This example shows how to update at
-  regular period the IWDG reload counter and <br>
-  how to simulate a software fault generating an MCU IWDG reset on expiry of a <br>
-  programmed time period.</p>
-  </td>
- </tr>
- <tr style="height: 75.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;"><a href="Lib_DEBUG">&nbsp;<b>LIB_DEBUG</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Run Time Checking </p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="Lib_DEBUG"></a>This example demonstrates how to
-  declare dynamic peripherals pointers used for Debug mode.&nbsp; To use Debug mode
-  you have to add the stm32f10x_ip_dbg.c file to your application. This creates
-  a pointer to the peripheral structure in SRAM. Debugging consequently becomes
-  easier and all register settings can be obtained by dumping a peripheral
-  variable.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="4" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;"><a href="NVIC">&nbsp;<b>NVIC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA in WFI mode</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="NVIC"></a>This example shows how to enter the
-  system to WFI mode with DMA transfer enabled and wake-up from this mode by
-  the DMA End of Transfer interrupt.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IRQ Mask</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example demonstrates the use of
-  the Nested Vectored Interrupt Controller (NVIC) IRQ Channels configuration
-  and how to mask/activate different IRQs.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IRQ Priority </p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example demonstrates the use of
-  the Nested Vectored Interrupt Controller (NVIC).</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">VectorTable Relocation</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example describes how to set the CortexM3
-  vector table in a specific <br>
-  address other than default using the NVIC_SetVectorTable function from the <br>
-  misc.h/.c driver.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td rowspan="3" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="PWR"><b>PWR</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">STANDBY</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="PWR"></a>This example shows how to enter the system
-  to STANDBY mode and wake-up from this mode using: external RESET, RTC Alarm
-  or WKUP pin.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">STOP</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to enter the
-  system to STOP mode and wake-up using EXTI Line interrupts. The EXTI Line
-  sources are PB.09/PG.08 and RTC Alarm.</p>
-  </td>
- </tr>
- <tr style="height: 60.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">PVD</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the programmable voltage detector using<br>
-  an external interrupt line. In this example, EXTI line 16 is configured to
-  generate <br>
-  an interrupt on each rising or falling edge of the PVD output signal (which <br>
-  indicates that the Vdd voltage is below the PVD threshold).</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="RCC"><b>RCC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Clock configuration</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="RCC"></a>This example shows how to configure
-  the System clock (SYSCLK) to have different frequencies: 24MHz, 36MHz, 48MHz,
-  56MHz and 72MHz (common frequencies that covers the major of the
-  applications). </p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="2" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="RTC"><b>RTC</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Calendar</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="RTC"></a>This example demonstrates and explains
-  how to use the RTC peripheral. As an application example, it demonstrates how
-  to setup the RTC peripheral, in terms of prescaler and interrupts, to be used
-  to keep time and to generate Second interrupt.</p>
-  </td>
- </tr>
- <tr style="height: 30.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">LSI_Calib</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example demonstrates and explains
-  how to use the LSI clock source auto calibration to get a precise RTC clock. </p>
-  </td>
- </tr>
- <tr style="height: 60.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="SDIO"><b>SDIO</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Micro SD Card</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="SDIO"></a>This example provides a basic example
-  of how to use the SDIO firmware library and an associate driver to perform
-  read/write operations on the SD Card memory (SD Card V1.0, V1.1, V2.0 and SDHC
-  (High Capacity) protocol) that could be mounted on the STM3210E-EVAL board.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td rowspan="5" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="SPI"><b>SPI</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">CRC</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="SPI"></a>This example provides a description of
-  how to set a communication between two<br>
-  SPIs in full-duplex mode and performs a transfer from Master to Slave and&nbsp; <br>
-  Slave to Master followed by CRC transmission.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to set a communication between the two SPIs in simplex mode and performs
-  a transfer from SPI_MASTER in polling mode to the SPI_SLAVE in DMA receive
-  mode. </p>
-  </td>
- </tr>
- <tr style="height: 75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Full Duplex Software NSS</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to set a communication between SPIy and SPIz in full-duplex mode and
-  performs a transfer from Master to Slave and then Slave to Master in the same
-  application with software NSS management.<br>
-  SPIy and SPIz can be SPI1 and SPI2 or SPI3 and SPI2, depending on the
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">SPI_FLASH</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic example
-  of how to use the SPI firmware library<br>
-  and an associate SPI FLASH driver to communicate with an M25P64 or M25P128
-  FLASH.</p>
-  </td>
- </tr>
- <tr style="height: 75.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Simplex Interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to set a communication between two<br>
-  SPIs in simplex mode and performs a data buffer transfer from SPI_MASTER to<br>
-  SPI_SLAVE using TxE interrupt for master and RxNE interrupt for slave.<br>
-  SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on
-  the<br>
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="SysTick"><b>SysTick</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Time Base</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="SysTick"></a>This example shows how to configure
-  the SysTick to generate a time base equal to<br>
-  1 ms. The system clock is set to 24 MHz on Value line devices and to 72 MHz
-  on <br>
-  other devices, the SysTick is clocked by the AHB clock (HCLK).</p>
-  </td>
- </tr>
- <tr style="height: 75pt;">
-  <td rowspan="20" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext black blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="TIM"><b>TIM</b></a></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">6 Steps</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="TIM"></a>This example shows how to configure the
-  TIM1 peripheral to generate 6 Steps.<br>
-  The STM32F10x TIM1 peripheral offers the possibility to program in advance
-  the <br>
-  configuration for the next TIM1 outputs behavior (step) and change the
-  configuration of all the channels at the same time. This operation is
-  possible when the COM (commutation) event is used.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">7 PWM Output</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM1 peripheral to generate 7 PWM signals with 4 different duty cycles
-  (50%, 37.5%, 25% and 12.5%).</p>
-  </td>
- </tr>
- <tr style="height: 15.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Cascade Synchro</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to synchronize
-  TIM peripherals in cascade mode.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Complementary Signals</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM1 peripheral to generate three <br>
-  complementary TIM1 signals, to insert a defined dead time value, to use the
-  break <br>
-  feature and to lock the desired parameters.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use DMA with TIM1 Update request<br>
-  to transfer Data from memory to TIM1 Capture Compare Register3.</p>
-  </td>
- </tr>
- <tr style="height: 15.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA Burst</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">&nbsp;This example shows how to update the TIM1 channel1 period and the duty cycle <br>
-using the TIM1 DMA burst feature.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">External Trigger Synchro</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to synchronize
-  TIM peripherals in cascade mode with an<br>
-  external trigger.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Input Capture</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to use the TIM
-  peripheral to measure the frequency of an <br>
-  external signal.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">OC Active</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM peripheral to generate four different <br>
-  signals with four different delays.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">OC Inactive</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM peripheral in Output Compare Inactive mode with the corresponding Interrupt
-  requests for each channel.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">OC Toggle</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM3 peripheral to generate four different signals with four different
-  frequencies.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">One Pulse </p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to use the TIM
-  peripheral to generate a One pulse Mode <br>
-  after a Rising edge of an external signal is received in Timer Input pin.</p>
-  </td>
- </tr>
- <tr style="height: 15.75pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Parallel Synchro</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 15.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to synchronize
-  TIM peripherals in parallel mode.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">PWM Input </p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to use the TIM peripheral
-  to measure the frequency and <br>
-  duty cycle of an external signal.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">PWM Output</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM peripheral in PWM (Pulse Width Modulation) mode.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">TIM1 Synchro</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to synchronize TIM1
-  and Timers (TIM3 and TIM4) in parallel mode.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">TIM10 PWM Output</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM10 peripheral in PWM (Pulse Width Modulation) mode.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">TIM15 Complementary Signals </p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM15 peripheral to generate one <br>
-  complementary TIM15 signal, to insert a defined dead time value, to use the
-  break <br>
-  feature and to lock the desired parameters.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color windowtext -moz-use-text-color -moz-use-text-color; border-width: medium 1pt medium medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">&nbsp;TIM9 OC Toggle</p>
-  </td>
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color blue -moz-use-text-color -moz-use-text-color; border-width: medium 1.5pt medium medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM9 peripheral to generate two different signals with two different
-  frequencies.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: solid solid solid none; border-color: windowtext windowtext windowtext -moz-use-text-color; border-width: 1pt 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Time Base</p>
-  </td>
-  <td style="border-style: solid solid solid none; border-color: windowtext blue windowtext -moz-use-text-color; border-width: 1pt 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to configure
-  the TIM peripheral in Output Compare Timing mode with the corresponding
-  Interrupt requests for each channel in order to generate 4 different time
-  bases.</p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td rowspan="13" style="border-style: none solid solid; border-color: -moz-use-text-color windowtext windowtext blue; border-width: medium 1pt 1pt 1.5pt; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<b>&nbsp;<a href="USART">USART</a></b></p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA Interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="USART"></a>This example provides a basic
-  communication between USARTy and USARTz using DMA capability, flags and
-  interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3,
-  depending on the STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">DMA Polling</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication between USARTy and USARTz using DMA capability. USARTy and
-  USARTz can be USART1 and USART2 or USART2 and USART3, depending on the
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Half Duplex</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication between USARTy and USARTz in <br>
-  Half-Duplex mode using flags. USARTy and USARTz can be USART1 and USART2 or<br>
-  USART2 and USART3, depending on the STMicroelectronics EVAL board you are
-  using.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Hyperterminal Hardware Flow Control</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use the USART with hardware flow<br>
-  control and communicate with the HyperTerminal.</p>
-  </td>
- </tr>
- <tr style="height: 30pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">&nbsp;Hyperterminal interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 30pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use the EVAL_COM1 Transmit and Receive interrupts to communicate with
-  the HyperTerminal.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Interrupt</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication between USARTy and USARTz using <br>
-  interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, <br>
-  depending on the STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IrDA Receive</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication USARTy IrDA receive mode. Four leds<br>
-  are used to show which byte is received. USARTy can be USART3 or USART2
-  depending on the STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">IrDA Transmit</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication USARTy IrDA transmit mode. Five pins, configured in input
-  floating mode, are used to select the byte to be send at <br>
-  each pin state change. USARTy can be USART3 or USART2 depending on the<br>
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 60pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Multi Processor</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 60pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use the USART in multi-processor mode.<br>
-  USARTy and USARTz can be USART1 and USART2 or USART2 and USART3 respectively,
-  <br>
-  depending on the STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Polling</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication between USARTy and USARTz using flags. USARTy and USARTz can be
-  USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics
-  EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Printf</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example shows how to retarget the
-  C library printf function to the USART. <br>
-  This implementation output the printf message on the HyperTerminal using
-  USARTx. USARTx can be USART1 or USART2 depending on the EVAL board you are
-  using.</p>
-  </td>
- </tr>
- <tr style="height: 45pt;">
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color windowtext windowtext -moz-use-text-color; border-width: medium 1pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Smartcard</p>
-  </td>
-  <td style="border-style: none solid solid none; border-color: -moz-use-text-color blue windowtext -moz-use-text-color; border-width: medium 1.5pt 1pt medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a description of
-  how to use the USART in Smartcard mode. <br>
-  The example gives only the possibility to read the ATR and decode it into <br>
-  predefined buffer.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color windowtext -moz-use-text-color -moz-use-text-color; border-width: medium 1pt medium medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">Synchronous</p>
-  </td>
-  <td style="border-style: none solid none none; border-color: -moz-use-text-color blue -moz-use-text-color -moz-use-text-color; border-width: medium 1.5pt medium medium; padding: 0in 5.4pt; background: rgb(149, 179, 215) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;">This example provides a basic
-  communication between USARTy (Synchronous mode) and SPIy using flags. USARTy
-  and SPIy can be USART1 and SPI1 or USART2 and SPI3, depending on the
-  STMicroelectronics EVAL board you are using.</p>
-  </td>
- </tr>
- <tr style="height: 45.75pt;">
-  <td style="border-style: none solid solid; border-color: -moz-use-text-color windowtext blue blue; border-width: medium 1pt 1.5pt 1.5pt; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 77pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="103">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 11pt; line-height: normal;">&nbsp;<a href="WWDG"><b>WWDG</b></a></p>
-  </td>
-  <td style="border-style: solid solid solid none; border-color: windowtext windowtext blue -moz-use-text-color; border-width: 1pt 1pt 1.5pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 170pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="227">
-  <p class="MsoNormal" style="margin-bottom: 0.0001pt; text-indent: 2.1pt; line-height: normal;">&nbsp;WWDG Reset</p>
-  </td>
-  <td style="border-style: solid solid solid none; border-color: windowtext blue blue -moz-use-text-color; border-width: 1pt 1.5pt 1.5pt medium; padding: 0in 5.4pt; background: rgb(0, 176, 240) none repeat scroll 0% 50%; width: 413pt; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; height: 45.75pt;" width="551">
-  <p class="MsoNormal" style="margin: 0in 0in 0.0001pt; text-align: justify; text-indent: -1.2pt; line-height: normal;"><a name="WWDG"></a>This example shows how to update at
-  regular period the WWDG counter and how to simulate a software fault generating
-  an MCU WWDG reset on expiry of a programmed time period.</p>
-  </td>
- </tr>
-</tbody>
-                        </table>
-<p class="MsoNormal" style="text-align: right;" align="right"><span style="font-size: 7.5pt;"><a href="Library_Examples.html">Back to Top</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-
-
-                        
-                        
-                        
-                        
-                        
-                        
-                        
-                        
-                        </td>
-                      </tr>
-                    </tbody>
-                  </table>
-                  <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
-                  <table class="MsoNormalTable" style="width: 96.22%; top: 1547px;" border="0" cellpadding="0" cellspacing="5" width="96%">
-                    <tbody>
-                      <tr style="">
-                        <td style="border-style: solid none none; border-color: -moz-use-text-color; border-width: 1pt medium medium; padding: 0in; width: 98.84%;" width="98%">
-                        <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
-                        <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;">For
-complete documentation on STM32 (CORTEX M3) 32-bit Microcontrollers
-platform visit&nbsp;<span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span><o:p></o:p></span></p>
-                        </td>
-                      </tr>
-                    </tbody>
-                  </table>
-                  <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></p>
-                  </td>
-                </tr>
-              </tbody>
-            </table>
-            </td>
-          </tr>
-        </tbody>
-      </table>
-      <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></p>
-      </td>
-    </tr>
-  </tbody>
-</table>
-</div>
-<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
-</div>
-
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
deleted file mode 100644
index f056195..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/DMA_WFIMode/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup NVIC_DMA_WFIMode
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#ifdef USE_STM3210C_EVAL
-#define USARTy_DR_Address    0x40004404
-#define USARTy_DMA1_Channel  DMA1_Channel6
-#define USARTy_DMA1_IRQn     DMA1_Channel6_IRQn
-#else
-#define USARTy_DR_Address    0x40013804
-#define USARTy_DMA1_Channel  DMA1_Channel5
-#define USARTy_DMA1_IRQn     DMA1_Channel5_IRQn
-#endif
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-NVIC_InitTypeDef  NVIC_InitStructure;
-USART_InitTypeDef  USART_InitStructure;
-DMA_InitTypeDef  DMA_InitStructure;
-__IO uint32_t LowPowerMode = 0;
-uint16_t DST_Buffer[10]= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void DMA_Configuration(void);
-uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Configure the system clocks */
-  RCC_Configuration();
-
-  /* Initialize Leds and Key Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); 
- 
-  /* Configures the DMA Channel */
-  DMA_Configuration();
-  
-/* EVAL_COM1 configuration ---------------------------------------------------*/
-  /* EVAL_COM1 configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-  USART_DMACmd(EVAL_COM1, USART_DMAReq_Rx, ENABLE);
-  
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-  
-  /* Enable the USARTy_DMA1_IRQn Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = USARTy_DMA1_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Enable the EXTI9_5  Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_Init(&NVIC_InitStructure);
-    
-  while (1)
-  {
-    if(LowPowerMode == 1)
-    {
-
-      STM_EVAL_LEDOff(LED2);
-      STM_EVAL_LEDOff(LED3);
-
-      /* Request to enter WFI mode */
-      __WFI();
-      LowPowerMode = 0;
-    }
-
-    Delay(0xFFFFF);
-    STM_EVAL_LEDToggle(LED1);
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{ 
-  /* DMA1 clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-}
-
-/**
-  * @brief  Configures the used DMA Channel.
-  * @param  None
-  * @retval None
-  */
-void DMA_Configuration(void)
-{
-  DMA_InitTypeDef  DMA_InitStructure;
-
-  /* USARTy_DMA1_Channel Config */
-  DMA_DeInit(USARTy_DMA1_Channel);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Address;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = 10;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(USARTy_DMA1_Channel, &DMA_InitStructure);
-
-  /* Enable USARTy_DMA1_Channel Transfer complete interrupt */
-  DMA_ITConfig(USARTy_DMA1_Channel, DMA_IT_TC, ENABLE);
-  
-  /* USARTy_DMA1_Channel enable */
-  DMA_Cmd(USARTy_DMA1_Channel, ENABLE);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval 0: pBuffer1 identical to pBuffer2
-  *         1: pBuffer1 differs from pBuffer2
-  */
-uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return 1;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-  return 0;
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt
deleted file mode 100644
index 3a1b997..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  @page NVIC_DMA_WFIMode DMA in WFI mode example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    NVIC/DMA_WFIMode/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the NVIC DMA in WFI mode example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to enters the system to WFI mode with DMA transfer enabled
-and wake-up from this mode by the DMA End of Transfer interrupt.
-
-In the associated software, the system clock is set to 72 MHz (24MHz on Value line), 
-the DMA1 Channely is configured to transfer 10 data from the EVAL COM1 USART data 
-register to a predefined buffer, DST_Buffer, and to generate an interrupt at the 
-end of the transfer.
-The EVAL COM1 USART receives data from HyperTerminal.
-A LED1 is toggled with a frequency depending on the system clock, this is used 
-to indicate whether the MCU is in WFI or RUN mode. 
-
-A falling edge on the selected EXTI Line will put the core in the WFI mode, 
-causing the led pin to stop toggling.
-To wake-up from WFI mode you have to send the sequence (0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
-from the Hyperterminal to the EVAL COM1 USART. These bytes will be transferred 
-by the DMA from the EVAL COM1 receive data register to the predefined buffer, 
-then generates an interrupt which exits the system from WFI mode. 
-The LED1 restarts toggling and a LED2 will toggle if the buffer is correctly 
-received else a LED3 is toggled.
-
-
-@par Directory contents 
-
-  - NVIC/DMA_WFIMode/stm32f10x_conf.h     Library Configuration file
-  - NVIC/DMA_WFIMode/stm32f10x_it.c       Interrupt handlers
-  - NVIC/DMA_WFIMode/stm32f10x_it.h       Interrupt handlers header file
-  - NVIC/DMA_WFIMode/main.c               Main program
-  - NVIC/DMA_WFIMode/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-    - The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232
-      transceiver.
-    - Connect a null-modem female/female RS232 cable between the DB9 connector,
-      CN12 on STM3210E-EVAL board, and PC serial port.   
-    - Hyperterminal configuration:
-       - Word Length = 8 Bits
-       - One Stop Bit
-       - No parity
-       - BaudRate = 115200 baud
-       - flow control: None 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8). 
-        
-  - STM32100B-EVAL Set-up   
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-    - The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232
-      transceiver.
-    - Connect a null-modem female/female RS232 cable between the DB9 connector, 
-      CN10 on STM32100B-EVAL board, and PC serial port.   
-    - Hyperterminal configuration:
-       - Word Length = 8 Bits
-       - One Stop Bit
-       - No parity
-       - BaudRate = 115200 baud
-       - flow control: None   
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - The USART2 signals (Rx, Tx) must be connected to a DB9 connector using a RS232
-      transceiver.
-    - Connect a null-modem female/female RS232 cable between the DB9 connector,
-      CN6 on STM3210C-EVAL board, and PC serial port.   
-    - Hyperterminal configuration:
-       - Word Length = 8 Bits
-       - One Stop Bit
-       - No parity
-       - BaudRate = 115200 baud
-       - flow control: None 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9). 
-    
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-    - The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232
-      transceiver.
-    - Connect a null-modem female/female RS232 cable between the DB9 connector,
-      CN12 on STM3210E-EVAL board, and PC serial port.   
-    - Hyperterminal configuration:
-       - Word Length = 8 Bits
-       - One Stop Bit
-       - No parity
-       - BaudRate = 115200 baud
-       - flow control: None 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).   
-
-  - STM3210B-EVAL Set-up   
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-    - The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232
-      transceiver.
-    - Connect a null-modem female/female RS232 cable between the DB9 connector, 
-      CN6 on STM3210B-EVAL board, and PC serial port.   
-    - Hyperterminal configuration:
-       - Word Length = 8 Bits
-       - One Stop Bit
-       - No parity
-       - BaudRate = 115200 baud
-       - flow control: None   
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-
-	
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h
deleted file mode 100644
index f21d3d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/DMA_WFIMode/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c
deleted file mode 100644
index 4b0bf3e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/DMA_WFIMode/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt
deleted file mode 100644
index 082a709..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  @page NVIC_IRQ_Mask NVIC IRQ Mask example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    NVIC/IRQ_Mask/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the NVIC IRQ Mask example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demontrates the use of the Nested Vectored Interrupt Controller (NVIC)
-IRQ Channels configuration and how to mask/activate different IRQs: 
-
-- Configuration of 3 TIM (TIM2..TIM4)timers to generate an interrupt on each 
-  counter update event.
-
-- The three timers are linked to their correspondant Update IRQ channel.
-
-- Assignment of a ascendant IRQ priority for each IRQ channel :
-     - TIM2 has a preemption priority of 0
-     - TIM3 has a preemption priority of 1
-     - TIM4 has a preemption priority of 2
-- In each interrupt routine: 
-   - TIM2 toggles a LED1 each 1s 
-   - TIM3 toggles a LED2 each 2s 
-   - TIM4 toggles a LED3 each 3s 
-
-- The KEY and WAKEUP buttons are used to boost the execution priority as follows:
-
-  - The KEY button is used in GPIO mode and at each KEY button press, the execution 
-    priority is raised to 0 and turn LED4 ON. This prevents all exceptions with 
-    configurable priority from activating, other than through the HardFault fault 
-    escalation mechanism. As consequence, all LEDs stop toggling as TIM2, TIM3 
-    and TIM4 IRQs are prevented from activation. 
-    
-    Pressing again the KEY button will release the priority boosting, turn LED4 
-    OFF and will allow all exceptions with configurable priority to be activated 
-    and TIM2, TIM3 and TIM4 can be generated again and the LEDs restart toggling.
-    
-    This execution priority is made using the CMSIS functions "__disable_irq()" 
-    and "__enable_irq()". 
-    These two functions are managing the Cortex-M3 PRIMASK special register.
-
-  - The WAKEUP button is used in EXTI mode and at each WAKEUP button press, the execution 
-    priority is masked to 0x40 using the BASEPRI register. 
-    A non-zero value will act as a priority mask, affecting the execution priority 
-    when the priority defined by BASEPRI is the same or higher than the current 
-    executing priority. 
-    As consequence, LED2 and LED3 stop toggling as TIM3 and TIM4 IRQs are 
-    prevented from activation. 
-    Pressing again the WAKEUP button will configure the BASEPRI register to 0, 
-    thus it has no effect on the current priority and TIM3 and TIM4 can be 
-    generated again and LED2 and LED3 restart toggling.
-    
-    This execution priority is made using the CMSIS functions "__set_BASEPRI()". 
-    This function is managing the Cortex-M3 BASEPRI special register.
-    Setting the BASEPRI register has no effect when the execution priority is
-    raised to 0 using the "__disable_irq()" function.
-
-@note These mechanisms only affect the group priority. They have no effect on 
-      the sub-priority. The sub-priority is only used to sort pending exception 
-      priorities, and does not affect active exceptions.
-
-@par Directory contents 
-
-  - NVIC/IRQ_Mask/stm32f10x_conf.h    Library Configuration file
-  - NVIC/IRQ_Mask/stm32f10x_it.c      Interrupt handlers
-  - NVIC/IRQ_Mask/stm32f10x_it.h      Interrupt handlers header file
-  - NVIC/IRQ_Mask/main.c              Main program
-  - NVIC/IRQ_Mask/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07
-      PF.08 and PF.09
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8). 
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0). 
-    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button    
-            
-  - STM32100B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07,
-      PC.08 and PC.09
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).    
-        
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).         
-    @note  Make sure that the Jumper 14 is in position 2<->3.
-              
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07
-      PF.08 and PF.09
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).   
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
-    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button          
-
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07,
-      PC.08 and PC.09
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).   
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).       
-	
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h
deleted file mode 100644
index fc54fb1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/IRQ_Mask/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c
deleted file mode 100644
index 67293b9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/IRQ_Mask/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
deleted file mode 100644
index 33b3007..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/IRQ_Priority/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup IRQ_Priority
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint8_t PreemptionOccured = 0; 
-__IO uint8_t PreemptionPriorityValue = 0; 
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Config(void);
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Config();     
-  
-  /* Initialize LED1..LED4, Key and Sel Joystick Buttons mounted on STM3210X-EVAL 
-     board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
-  STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI); 
-
-  /* Configure the SysTick Handler Priority: Preemption priority and subpriority */
-  NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0));
-
-  while (1)
-  {
-    if(PreemptionOccured != 0)
-    {
-      /* Toggel The lED1 */
-      STM_EVAL_LEDToggle(LED1);
-      
-      /* Insert delay Time */
-      Delay(0x5FFFF);
-      
-      STM_EVAL_LEDToggle(LED2);
-      
-      Delay(0x5FFFF);
-      
-      STM_EVAL_LEDToggle(LED3);
-      
-      Delay(0x5FFFF);
-      
-      STM_EVAL_LEDToggle(LED4);
-      
-      Delay(0x5FFFF); 
-    }
-  }
-}
-
-/**
-  * @brief  Configures the NVIC interrupts.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Config(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure the preemption priority and subpriority:
-     - 1 bits for pre-emption priority: possible value are 0 or 1 
-     - 3 bits for subpriority: possible value are 0..7
-     - Lower values gives higher priority  
-   */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-  
-  /* Enable the WAKEUP_BUTTON_EXTI_IRQn Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-  
-  /* Enable the KEY_BUTTON_EXTI_IRQn Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = KEY_BUTTON_EXTI_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt
deleted file mode 100644
index cd86c9b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
-  @page NVIC_IRQ_Priority NVIC IRQ Priority example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    NVIC/IRQ_Priority/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the NVIC IRQ Priority example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC): 
-
-- Configuration of 2 EXTI Lines (Wakeup button EXTI Line & Key button EXTI Line)
-  to generate an interrupt on each falling edge and use the SysTick interrupt.
-- These interrupts are configured with the following parameters:
-    - Wakeup button EXTI Line:  
-        - PreemptionPriority = PreemptionPriorityValue
-        - SubPriority = 0
-    - Key button EXTI Line:    
-        - PreemptionPriority = 0
-        - SubPriority = 1           
-    - SysTick Handler:  
-        - PreemptionPriority = !PreemptionPriorityValue
-        - SubPriority = 0             
-First, the PreemptionPriorityValue is equal to 0, the Wakeup button EXTI Line 
-has higher preemption priority than the SysTick handler. 
-
-In the key button EXTI Line interrupt routine the Wakeup button EXTI Line and 
-SysTick preemption priorities are inverted. 
-In the Wakeup button EXTI Line interrupt routine the pending bit of the SysTick 
-interrupt is set this will cause SysTick ISR to preempt the Wakeup button EXTI 
-Line ISR only if it has higher preemption priority.
-
-The system behaves as following:
- 
-1) The first time Key button EXTI Line interrupt occurs the SysTick preemption 
-become higher than Wakeup button EXTI Line one. So when the Wakeup button EXTI 
-Line interrupt occurs, the SysTick ISR is executed and the PreemptionOccured 
-variable become TRUE and the four leds (LED1, LED2, LED3, LED4) start toggling.
-
-2) When the next Key button EXTI Line interrupt occurs the SysTick preemption
-become lower than Wakeup button EXTI Line one. So when the Wakeup button EXTI Line
-interrupt occurs, the PreemptionOccured variable became FALSE and the four leds
-(LED1, LED2, LED3, LED4) stop toggling.
-
-Then this behavior is repeated from point 1) in an infinite loop.
-
-
-@par Directory contents 
-
-  - NVIC/IRQ_Priority/stm32f10x_conf.h     Library Configuration file
-  - NVIC/IRQ_Priority/stm32f10x_it.c       Interrupt handlers
-  - NVIC/IRQ_Priority/stm32f10x_it.h       Interrupt handlers header file
-  - NVIC/IRQ_Priority/main.c               Main program
-  - NVIC/IRQ_Priority/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 
-      and PF.09 pins
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
-    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button
-        
-  - STM32100B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).  
-    
- - STM3210C-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0). Make sure 
-      that the Jumper 14 is in position 2<->3.
-      
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 
-      and PF.09 pins
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
-    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button
-    
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
-
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h
deleted file mode 100644
index 0566ac2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/IRQ_Priority/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h
deleted file mode 100644
index a3a3aff..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/IRQ_Priority/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI0_IRQHandler(void);
-void EXTI9_5_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf
deleted file mode 100644
index 1efdb2b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08003000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08003000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl
deleted file mode 100644
index a3adbc0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl
+++ /dev/null
@@ -1,155 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 120k;
-    map ( size = 120k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 8k;
-    map ( size = 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1                        
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break and TIM15
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );       // TIM1 Update and TIM16
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation and TIM17
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // HDMI-CEC                   
-                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 and DAC underrun
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk
deleted file mode 100644
index 2d9c35c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl
deleted file mode 100644
index c0c6865..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl
+++ /dev/null
@@ -1,168 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 504k;
-    map ( size = 504k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 32k;
-    map ( size = 32k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                   // ADC1 
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );        // TIM1_BRK_TIM15_IRQHandler
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );              // TIM1_UP_TIM16_IRQHandler
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );         // TIM1_TRG_COM_TIM17_IRQHandler
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                 // CEC_IRQHandler
-                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );             // TIM12_IRQHandler
-                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );              // TIM13_IRQHandler
-                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );             // TIM14_IRQHandler
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );                 // TIM6_DAC_IRQHandler
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );      // DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk
deleted file mode 100644
index 2d9c35c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl
deleted file mode 100644
index 7d95809..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl
+++ /dev/null
@@ -1,157 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 120k;
-    map ( size = 120k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 20k;
-    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk
deleted file mode 100644
index 3f877d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk
+++ /dev/null
@@ -1,5 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
---output=.\Objects\$(Target)
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl
deleted file mode 100644
index 65789ce..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl
+++ /dev/null
@@ -1,174 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 504k;
-    map ( size = 504k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 64k;
-    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk
deleted file mode 100644
index 2d9c35c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl
deleted file mode 100644
index 3046e73..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl
+++ /dev/null
@@ -1,173 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size =0xFE000;
-    map ( size = 0xFE000, dest_offset=0x08003000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 96k;
-    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk
deleted file mode 100644
index 2d9c35c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld
deleted file mode 100644
index 9349b62..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32f10x_flash_offset.ld
-**
-**  Abstract    : Linker script for STM32F10x XL-density devices with
-**                1MByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of 96K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 1024K - 0x3000
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
deleted file mode 100644
index 849726c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/VectorTable_Relocation/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup NVIC_VectorTable_Relocation
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __IO uint32_t TimingDelay;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Initialize Leds mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Turn on LED1 and LED3 */
-  STM_EVAL_LEDOn(LED1);
-  STM_EVAL_LEDOn(LED3);
-
-  /* Setup SysTick Timer for 1 msec interrupts  */
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-  
-  while (1)
-  {
-    /* Toggle LED1, LED2, LED3 and LED4 */
-    STM_EVAL_LEDToggle(LED1);
-    STM_EVAL_LEDToggle(LED2);
-    STM_EVAL_LEDToggle(LED3);    
-    STM_EVAL_LEDToggle(LED4);
-
-    /* Insert 500 ms delay */
-    Delay(500);
-
-    /* Toggle LED1, LED2, LED3 and LED4 */
-    STM_EVAL_LEDToggle(LED1);
-    STM_EVAL_LEDToggle(LED2);
-    STM_EVAL_LEDToggle(LED3);    
-    STM_EVAL_LEDToggle(LED4);
-
-    /* Insert 300 ms delay */
-    Delay(300);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{
-  TimingDelay = nTime;
-
-  while(TimingDelay != 0)
-  {
-  }
-}
-
-/**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
-  */
-void TimingDelay_Decrement(void)
-{
-  if (TimingDelay != 0x00)
-  { 
-    TimingDelay--;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h
deleted file mode 100644
index 6ad4c41..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/VectorTable_Relocation/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void TimingDelay_Decrement(void);
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h
deleted file mode 100644
index e823189..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/VectorTable_Relocation/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c
deleted file mode 100644
index 6b81deb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/VectorTable_Relocation/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup NVIC_VectorTable_Relocation
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  TimingDelay_Decrement();
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h
deleted file mode 100644
index f649072..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/VectorTable_Relocation/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c
deleted file mode 100644
index 0672dd3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/PVD/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup PWR_PVD
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-void EXTI_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-
-  /* Enable PWR and BKP clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Configure EXTI Line to generate an interrupt on falling edge */
-  EXTI_Configuration();
-
-  /* NVIC configuration */
-  NVIC_Configuration();
- 
-  /* Configure the PVD Level to 2.9V */
-  PWR_PVDLevelConfig(PWR_PVDLevel_2V9);
-
-  /* Enable the PVD Output */
-  PWR_PVDCmd(ENABLE);
-  
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures EXTI Lines.
-  * @param  None
-  * @retval None
-  */
-void EXTI_Configuration(void)
-{
-  EXTI_InitTypeDef EXTI_InitStructure;
-
-  /* Configure EXTI Line16(PVD Output) to generate an interrupt on rising and
-     falling edges */
-  EXTI_ClearITPendingBit(EXTI_Line17);
-  EXTI_InitStructure.EXTI_Line = EXTI_Line17;
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-}
-
-/**
-  * @brief  Configures NVIC and Vector Table base location.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-  
-  /* Configure one bit for preemption priority */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-  
-  /* Enable the PVD Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = PVD_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt
deleted file mode 100644
index 3668412..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
-  @page PWR_PVD PWR PVD example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    PWR/PVD/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the PWR PVD example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the programmable voltage detector using
-an external interrupt line. In this example, EXTI line 16 is configured to generate 
-an interrupt on each rising or falling edge of the PVD output signal (which 
-indicates that the Vdd voltage is below the PVD threshold).
-In the interrupt routine a led connected to a specific GPIO pin is toggled every 
-time the voltage drops below or  the target threshold.
-
-
-@par Directory contents 
-
-  - PWR/PVD/stm32f10x_conf.h     Library Configuration file
-  - PWR/PVD/stm32f10x_it.c       Interrupt handlers
-  - PWR/PVD/stm32f10x_it.h       Header for stm32f10x_it.c
-  - PWR/PVD/main.c               Main program
-  - PWR/PVD/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up  
-    - Use LED1 led connected to PC.06 pin
-    
-  - STM32100B-EVAL Set-up  
-    - Use LED1 led connected to PC.06 pin
-    
-  - STM3210C-EVAL Set-up 
-    - Use LED1 led connected to PD.07 pin
-
-  - STM3210E-EVAL Set-up 
-    - Use LED1 led connected to PF.06 pin
-
-  - STM3210B-EVAL Set-up  
-    - Use LED1 led connected to PC.06 pin
-
-@note
-- Use a variable DC power supply connected to the 3V3 input to the evaluation 
-  board and dropping the voltage below 2.7V. 
-         
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example in standalone mode (without debugger connection)
-  
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h
deleted file mode 100644
index 945ae07..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/PVD/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c
deleted file mode 100644
index 9cd98b1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/PVD/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c
deleted file mode 100644
index bb32524..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STANDBY/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup PWR_STANDBY
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-void RTC_Configuration(void);
-void SysTick_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
-
-  /* Turn on LED1 */
-  STM_EVAL_LEDOn(LED1);
-
-  /* Enable PWR and BKP clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Enable WKUP pin */
-  PWR_WakeUpPinCmd(ENABLE);
-
-  /* Allow access to BKP Domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Configure RTC clock source and prescaler */
-  RTC_Configuration();
-
-  /* Configure the SysTick to generate an interrupt each 250 ms */
-  SysTick_Configuration();
- 
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures RTC clock source and prescaler.
-  * @param  None
-  * @retval None
-  */
-void RTC_Configuration(void)
-{
-  /* Check if the StandBy flag is set */
-  if(PWR_GetFlagStatus(PWR_FLAG_SB) != RESET)
-  {/* System resumed from STANDBY mode */
-
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-
-    /* Clear StandBy flag */
-    PWR_ClearFlag(PWR_FLAG_SB);
-
-    /* Wait for RTC APB registers synchronisation */
-    RTC_WaitForSynchro();
-    /* No need to configure the RTC as the RTC configuration(clock source, enable,
-       prescaler,...) is kept after wake-up from STANDBY */
-  }
-  else
-  {/* StandBy flag is not set */
-
-    /* RTC clock source configuration ----------------------------------------*/
-    /* Reset Backup Domain */
-    BKP_DeInit();
-  
-    /* Enable LSE OSC */
-    RCC_LSEConfig(RCC_LSE_ON);
-    /* Wait till LSE is ready */
-    while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
-    {
-    }
-
-    /* Select the RTC Clock Source */
-    RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
-    /* Enable the RTC Clock */
-    RCC_RTCCLKCmd(ENABLE);
-
-    /* RTC configuration -----------------------------------------------------*/
-    /* Wait for RTC APB registers synchronisation */
-    RTC_WaitForSynchro();
-
-    /* Set the RTC time base to 1s */
-    RTC_SetPrescaler(32767);  
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-  }
-}
-
-/**
-  * @brief  Configures the SysTick to generate an interrupt each 250 ms.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Configuration(void)
-{
-  /* SysTick interrupt each 250 ms with SysTick Clock equal to (HCLK/8) */
-  if (SysTick_Config((SystemCoreClock/8) / 4))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  /* Select AHB clock(HCLK) divided by 8 as SysTick clock source */
-  SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-
-  /* Set SysTick Preemption Priority to 1 */
-  NVIC_SetPriority(SysTick_IRQn, 0x04);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c
deleted file mode 100644
index 6358763..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STANDBY/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup PWR_STANDBY
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  /* Toggle LED1 */
-  STM_EVAL_LEDToggle(LED1);
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles External lines 9 to 5 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_IRQHandler(void)
-{
-  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
-  { 
-    /* Clear the Key Button EXTI line pending bit */  
-    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
-
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-
-    /* Wait till RTC Second event occurs */
-    RTC_ClearFlag(RTC_FLAG_SEC);
-    while(RTC_GetFlagStatus(RTC_FLAG_SEC) == RESET);
-
-    /* Set the RTC Alarm after 3s */
-    RTC_SetAlarm(RTC_GetCounter()+ 3);
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-
-    /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */
-    PWR_EnterSTANDBYMode();
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h
deleted file mode 100644
index d961b1d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STANDBY/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI9_5_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/readme.txt
deleted file mode 100644
index 962c3a0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/readme.txt
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
-  @page PWR_STOP PWR STOP example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    PWR/STOP/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the PWR STOP example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to enter the system to STOP mode and wake-up using EXTI
-Line interrupts. The EXTI Line sources are PB.09/PG.08 and RTC Alarm.
-
-The EXTI line9/8 is configured to generate interrupt on falling edge.
-The EXTI line17(RTC Alarm) is configured to generate interrupt on rising edge and
-the RTC time base is set to 1 second using the external low speed oscillator(LSE).
-
-The system clock is set to 24 MHz on Value line devices and to 72 MHz on other 
-devices using the external high speed oscillator(HSE).
-
-The system enters and exits STOP mode as following:
-After 2 second from system start-up, the RTC is configured to generate an Alarm
-event in 3 second then the system enters STOP mode. To wake-up from STOP mode you
-have to apply a rising edge on EXTI line9/8, otherwise the  RTC Alarm will wake-up
-the system within 3 second. After exit from STOP the system clock is reconfigured
-to its previous state (as HSE and PLL are disabled in STOP mode).
-Then after a delay the system will enter again in STOP mode and exit in the way
-described above. This behavior is repeated in an infinite loop.
-
-Three leds LED1, LED2 and LED3 are used to monitor the system state as following:
- - LED1 on: system in RUN mode
- - LED1 off: system in STOP mode
- - LED2 is toggled if EXTI Line9/8 is used to exit from STOP 
- - LED3 is toggled if EXTI line17(RTC Alarm) is used to exit from STOP 
-
-
-@par Directory contents 
-
-  - PWR/STOP/stm32f10x_conf.h     Library Configuration file
-  - PWR/STOP/stm32f10x_it.c       Interrupt handlers
-  - PWR/STOP/stm32f10x_it.h       Header for stm32f10x_it.c
-  - PWR/STOP/main.c               Main program
-  - PWR/STOP/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line),STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    
-  - STM32100B-EVAL Set-up  
-    - Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PD.07, PD.13 and PF.03 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-	
-@note For power consumption measurement in STOP mode you have to: 
-- Modify the example to configure all unused GPIO port pins in Analog Input mode
-  (floating input trigger OFF). Refer to GPIO\IOToggle example for more details. 
-- Replace jumper JP9 in the STM3210B-EVAL board, JP12 in the STM3210E-EVAL, 
-  JP23 (position 1-2) in the STM3210C-EVAL board or JP8 (position 1-2) in the 
-  STM32100B-EVAL board by an amperemeter.
-
-         
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example in standalone mode (without debugger connection)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h
deleted file mode 100644
index 2dc3aa3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STOP/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
deleted file mode 100644
index 5682ad3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STOP/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup PWR_STOP
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t TimingDelay = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  TimingDelay--;
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles External lines 9 to 5 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_IRQHandler(void)
-{
-  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
-  { 
-    /* Clear the Key Button EXTI line pending bit */  
-    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
-
-    /* Toggle LED2 */
-    STM_EVAL_LEDToggle(LED2);
-  }
-}
-
-/**
-  * @brief  This function handles RTC Alarm interrupt request.
-  * @param  None
-  * @retval None
-  */
-void RTCAlarm_IRQHandler(void)
-{
-  if(RTC_GetITStatus(RTC_IT_ALR) != RESET)
-  {
-    /* Toggle LED3 */
-    STM_EVAL_LEDToggle(LED3);
-
-    /* Clear EXTI line17 pending bit */
-    EXTI_ClearITPendingBit(EXTI_Line17);
-
-    /* Check if the Wake-Up flag is set */
-    if(PWR_GetFlagStatus(PWR_FLAG_WU) != RESET)
-    {
-      /* Clear Wake Up flag */
-      PWR_ClearFlag(PWR_FLAG_WU);
-    }
-
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();   
-    /* Clear RTC Alarm interrupt pending bit */
-    RTC_ClearITPendingBit(RTC_IT_ALR);
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h
deleted file mode 100644
index 7ca57f1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STOP/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI9_5_IRQHandler(void);
-void RTCAlarm_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c
deleted file mode 100644
index 0db2022..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    PWR/STOP/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
deleted file mode 100644
index 8dba3b1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-
-/** @addtogroup RCC_ClockConfig
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define DELAY_COUNT    0x3FFFF
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-GPIO_InitTypeDef GPIO_InitStructure;
-RCC_ClocksTypeDef RCC_ClockFreq;
-ErrorStatus HSEStartUpStatus;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-void Delay(__IO uint32_t nCount);
-
-void SetSysClock(void);
-#ifdef SYSCLK_HSE
-  void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  void SetSysClockTo72(void);
-#endif
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  SetSysClock();
-
-  /* This function fills the RCC_ClockFreq structure with the current
-     frequencies of different on chip clocks (for debug purpose) */
-  RCC_GetClocksFreq(&RCC_ClockFreq);
-
-  /* Enable Clock Security System(CSS): this will generate an NMI exception
-     when HSE clock fails */
-  RCC_ClockSecuritySystemCmd(ENABLE);
-     
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Configuration();
- 
-  /* Initialize Leds mounted on STM3210X-EVAL board --------------------------*/
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Output HSE clock on MCO pin ---------------------------------------------*/
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  RCC_MCOConfig(RCC_MCO_HSE);
-  
-  while (1)
-  {
-    /* Toggle LED1 */
-    STM_EVAL_LEDToggle(LED1);
-    /* Insert delay */
-    Delay(DELAY_COUNT);
-
-    /* Toggle LED2 */
-    STM_EVAL_LEDToggle(LED2);
-	/* Insert delay */
-    Delay(DELAY_COUNT);
-
-    /* Toggle LED3 */
-    STM_EVAL_LEDToggle(LED3);
-    /* Insert delay */
-    Delay(DELAY_COUNT);
-
-    /* Toggle LED4 */
-    STM_EVAL_LEDToggle(LED4);
-    /* Insert a delay */
-    Delay(DELAY_COUNT);
-  }
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1
-  *         prescalers.
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{    
-/* The System clock configuration functions defined below assume that:
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.*/
-
-#if defined SYSCLK_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();  
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56(); 
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockToHSE(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-#ifndef STM32F10X_CL
-    /* Flash 0 wait state */
-    FLASH_SetLatency(FLASH_Latency_0);
-#else
-    if (HSE_Value <= 24000000)
-	{
-      /* Flash 0 wait state */
-      FLASH_SetLatency(FLASH_Latency_0);
-	}
-	else
-	{
-      /* Flash 1 wait state */
-      FLASH_SetLatency(FLASH_Latency_1);
-	}
-
-#endif /* STM32F10X_CL */
-#endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK */
-    RCC_PCLK1Config(RCC_HCLK_Div1);
-
-    /* Select HSE as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
-
-    /* Wait till PLL is used as system clock source */
-    while (RCC_GetSYSCLKSource() != 0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockTo24(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 0 wait state */
-    FLASH_SetLatency(FLASH_Latency_0);
-#endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK */
-    RCC_PCLK1Config(RCC_HCLK_Div1);
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
-#elif defined STM32F10X_LD_VL || defined STM32F10X_MD_VL || defined STM32F10X_HD_VL 
-    /* PLLCLK = (8MHz/2) * 6 = 24 MHz */
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_HSE, RCC_PREDIV1_Div2);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
-#else
-    /* PLLCLK = 8MHz * 3 = 24 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3);
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while (RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockTo36(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 1 wait state */
-    FLASH_SetLatency(FLASH_Latency_1);
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK */
-    RCC_PCLK1Config(RCC_HCLK_Div1);
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
-#else
-    /* PLLCLK = (8MHz / 2) * 9 = 36 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while (RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockTo48(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 1 wait state */
-    FLASH_SetLatency(FLASH_Latency_1);
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK/2 */
-    RCC_PCLK1Config(RCC_HCLK_Div2);
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
-#else
-    /* PLLCLK = 8MHz * 6 = 48 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6);
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while (RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockTo56(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 2 wait state */
-    FLASH_SetLatency(FLASH_Latency_2);
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK/2 */
-    RCC_PCLK1Config(RCC_HCLK_Div2);
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7);
-#else
-    /* PLLCLK = 8MHz * 7 = 56 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while (RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @param  None
-  * @retval None
-  */
-void SetSysClockTo72(void)
-{
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
-  /* RCC system reset(for debug purpose) */
-  RCC_DeInit();
-
-  /* Enable HSE */
-  RCC_HSEConfig(RCC_HSE_ON);
-
-  /* Wait till HSE is ready */
-  HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-  if (HSEStartUpStatus == SUCCESS)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-    /* Flash 2 wait state */
-    FLASH_SetLatency(FLASH_Latency_2);
- 
-    /* HCLK = SYSCLK */
-    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
-  
-    /* PCLK2 = HCLK */
-    RCC_PCLK2Config(RCC_HCLK_Div1); 
-
-    /* PCLK1 = HCLK/2 */
-    RCC_PCLK1Config(RCC_HCLK_Div2);
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs *********************************************************/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    RCC_PREDIV2Config(RCC_PREDIV2_Div5);
-    RCC_PLL2Config(RCC_PLL2Mul_8);
-
-    /* Enable PLL2 */
-    RCC_PLL2Cmd(ENABLE);
-
-    /* Wait till PLL2 is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
-    {}
-
-    /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ 
-    RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
-    RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
-#else
-    /* PLLCLK = 8MHz * 9 = 72 MHz */
-    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
-#endif
-
-    /* Enable PLL */ 
-    RCC_PLLCmd(ENABLE);
-
-    /* Wait till PLL is ready */
-    while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-    /* Wait till PLL is used as system clock source */
-    while(RCC_GetSYSCLKSource() != 0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock configuration.
-       User can add here some code to deal with this error */    
-
-    /* Go to infinite loop */
-    while (1)
-    {
-    }
-  }
-}
-
-#endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
-
-/**
-  * @brief  Configures Vector Table base location.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable and configure RCC global IRQ channel */
-  NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;  
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount!= 0;nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h
deleted file mode 100644
index b3a67d8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source) */
-//#define SYSCLK_HSE
-#define SYSCLK_FREQ_24MHz
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-  //#define SYSCLK_FREQ_36MHz
-  //#define SYSCLK_FREQ_48MHz
-  //#define SYSCLK_FREQ_56MHz
-  #define SYSCLK_FREQ_72MHz
-#endif
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt
deleted file mode 100644
index 8bfbccd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
-  @page RCC_ClockConfig RCC Clock configuration example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    RCC/RCC_ClockConfig/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the RCC Clock configuration example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the System clock(SYSCLK) to have different
-frequencies: 24MHz, 36MHz, 48MHz, 56MHz and 72MHz (common frequencies that covers
-the major of the applications). 
-The SYSCLK frequency is selected by user in main.h file.
-
-It shows how to use, for debug purpose, the RCC_GetClocksFreq function to retrieve
-the current status and frequencies of different on chip clocks. You can see the
-RCC_ClockFreq structure content, which hold the frequencies of different on chip
-clocks, using your toolchain debugger.
-
-This example handles also the High Speed External clock (HSE) failure detection:
-when the HSE clock disappears (broken or disconnected external Quartz); HSE, PLL
-are disabled (but no change on PLL config), HSI selected as system clock source
-and an interrupt (NMI) is generated. In the NMI ISR, the HSE, HSE ready interrupt
-are enabled and once HSE clock recover, the HSERDY interrupt is generated and in
-the RCC ISR routine the system clock is reconfigured to its previous state (before
-HSE clock failure). You can monitor the HSE clock on the MCO pin (PA.08).
-
-Four LEDs are toggled with a timing defined by the Delay function.
-
-@note To adjust the External High Speed oscillator (HSE) Startup Timeout value,
-use HSEStartUp_TimeOut variable defined in the stm32f10x.h file.
-
-
-@par Directory contents 
-
-  - RCC/RCC_ClockConfig/stm32f10x_conf.h     Library Configuration file
-  - RCC/RCC_ClockConfig/stm32f10x_it.c       Interrupt handlers
-  - RCC/RCC_ClockConfig/stm32f10x_it.h       Header for stm32f10x_it.c
-  - RCC/RCC_ClockConfig/main.h               Main header file
-  - RCC/RCC_ClockConfig/main.c               Main program
-  - RCC/RCC_ClockConfig/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line),STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-      
-  - STM32100B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-      
-  - STM3210C-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    
-  - STM3210E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-	  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-   
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h
deleted file mode 100644
index f5534f0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c
deleted file mode 100644
index b0e6201..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
deleted file mode 100644
index e2e18ec..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-#include <stdio.h>
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup RTC_Calendar
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define RTCClockOutput_Enable  /* RTC Clock/64 is output on tamper pin(PC.13) */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t TimeDisplay = 0;
-USART_InitTypeDef USART_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RTC_Configuration(void);
-void NVIC_Configuration(void);
-uint32_t Time_Regulate(void);
-void Time_Adjust(void);
-void Time_Show(void);
-void Time_Display(uint32_t TimeVar);
-uint8_t USART_Scanf(uint32_t value);
-
-#ifdef __GNUC__
-/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
-   set to 'Yes') calls __io_putchar() */
-#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
-#else
-#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
-#endif /* __GNUC__ */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize LED1 mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-
-  /* USARTx configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-
-
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
-  {
-    /* Backup data register value is not correct or not yet programmed (when
-       the first time the program is executed) */
-
-    printf("\r\n\n RTC not yet configured....");
-
-    /* RTC Configuration */
-    RTC_Configuration();
-
-    printf("\r\n RTC configured....");
-
-    /* Adjust time by values entered by the user on the hyperterminal */
-    Time_Adjust();
-
-    BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
-  }
-  else
-  {
-    /* Check if the Power On Reset flag is set */
-    if (RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET)
-    {
-      printf("\r\n\n Power On Reset occurred....");
-    }
-    /* Check if the Pin Reset flag is set */
-    else if (RCC_GetFlagStatus(RCC_FLAG_PINRST) != RESET)
-    {
-      printf("\r\n\n External Reset occurred....");
-    }
-
-    printf("\r\n No need to configure RTC....");
-    /* Wait for RTC registers synchronization */
-    RTC_WaitForSynchro();
-
-    /* Enable the RTC Second */
-    RTC_ITConfig(RTC_IT_SEC, ENABLE);
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-  }
-
-#ifdef RTCClockOutput_Enable
-  /* Enable PWR and BKP clocks */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Allow access to BKP Domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Disable the Tamper Pin */
-  BKP_TamperPinCmd(DISABLE); /* To output RTCCLK/64 on Tamper pin, the tamper
-                                 functionality must be disabled */
-
-  /* Enable RTC Clock Output on Tamper Pin */
-  BKP_RTCOutputConfig(BKP_RTCOutputSource_CalibClock);
-#endif
-
-  /* Clear reset flags */
-  RCC_ClearFlag();
-
-  /* Display time in infinite loop */
-  Time_Show();
-}
-
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure one bit for preemption priority */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-
-  /* Enable the RTC Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Configures the RTC.
-  * @param  None
-  * @retval None
-  */
-void RTC_Configuration(void)
-{
-  /* Enable PWR and BKP clocks */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Allow access to BKP Domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Reset Backup Domain */
-  BKP_DeInit();
-
-  /* Enable LSE */
-  RCC_LSEConfig(RCC_LSE_ON);
-  /* Wait till LSE is ready */
-  while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
-  {}
-
-  /* Select LSE as RTC Clock Source */
-  RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
-  /* Enable RTC Clock */
-  RCC_RTCCLKCmd(ENABLE);
-
-  /* Wait for RTC registers synchronization */
-  RTC_WaitForSynchro();
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-
-  /* Enable the RTC Second */
-  RTC_ITConfig(RTC_IT_SEC, ENABLE);
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-
-  /* Set RTC prescaler: set RTC period to 1sec */
-  RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-}
-
-/**
-  * @brief  Returns the time entered by user, using Hyperterminal.
-  * @param  None
-  * @retval Current time RTC counter value
-  */
-uint32_t Time_Regulate(void)
-{
-  uint32_t Tmp_HH = 0xFF, Tmp_MM = 0xFF, Tmp_SS = 0xFF;
-
-  printf("\r\n==============Time Settings=====================================");
-  printf("\r\n  Please Set Hours");
-
-  while (Tmp_HH == 0xFF)
-  {
-    Tmp_HH = USART_Scanf(23);
-  }
-  printf(":  %d", Tmp_HH);
-  printf("\r\n  Please Set Minutes");
-  while (Tmp_MM == 0xFF)
-  {
-    Tmp_MM = USART_Scanf(59);
-  }
-  printf(":  %d", Tmp_MM);
-  printf("\r\n  Please Set Seconds");
-  while (Tmp_SS == 0xFF)
-  {
-    Tmp_SS = USART_Scanf(59);
-  }
-  printf(":  %d", Tmp_SS);
-
-  /* Return the value to store in RTC counter register */
-  return((Tmp_HH*3600 + Tmp_MM*60 + Tmp_SS));
-}
-
-/**
-  * @brief  Adjusts time.
-  * @param  None
-  * @retval None
-  */
-void Time_Adjust(void)
-{
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-  /* Change the current time */
-  RTC_SetCounter(Time_Regulate());
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-}
-
-/**
-  * @brief  Displays the current time.
-  * @param  TimeVar: RTC counter value.
-  * @retval None
-  */
-void Time_Display(uint32_t TimeVar)
-{
-  uint32_t THH = 0, TMM = 0, TSS = 0;
-  
-  /* Reset RTC Counter when Time is 23:59:59 */
-  if (RTC_GetCounter() == 0x0001517F)
-  {
-     RTC_SetCounter(0x0);
-     /* Wait until last write operation on RTC registers has finished */
-     RTC_WaitForLastTask();
-  }
-  
-  /* Compute  hours */
-  THH = TimeVar / 3600;
-  /* Compute minutes */
-  TMM = (TimeVar % 3600) / 60;
-  /* Compute seconds */
-  TSS = (TimeVar % 3600) % 60;
-
-  printf("Time: %0.2d:%0.2d:%0.2d\r", THH, TMM, TSS);
-}
-
-/**
-  * @brief  Shows the current time (HH:MM:SS) on the Hyperterminal.
-  * @param  None
-  * @retval None
-  */   
-void Time_Show(void)
-{
-  printf("\n\r");
-
-  /* Infinite loop */
-  while (1)
-  {
-    /* If 1s has been elapsed */
-    if (TimeDisplay == 1)
-    {
-      /* Display current time */
-      Time_Display(RTC_GetCounter());
-      TimeDisplay = 0;
-    }
-  }
-}
-
-
-/**
-  * @brief  Retargets the C library printf function to the USART.
-  * @param  None
-  * @retval None
-  */
-PUTCHAR_PROTOTYPE
-{
-  /* Place your implementation of fputc here */
-  /* e.g. write a character to the USART */
-  USART_SendData(EVAL_COM1, (uint8_t) ch);
-
-  /* Loop until the end of transmission */
-  while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
-  {}
-
-  return ch;
-}
-
-/**
-  * @brief  Gets numeric values from the hyperterminal.
-  * @param  None
-  * @retval None
-  */
-uint8_t USART_Scanf(uint32_t value)
-{
-  uint32_t index = 0;
-  uint32_t tmp[2] = {0, 0};
-
-  while (index < 2)
-  {
-    /* Loop until RXNE = 1 */
-    while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET)
-    {}
-    tmp[index++] = (USART_ReceiveData(EVAL_COM1));
-    if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39))
-    {
-      printf("\n\rPlease enter valid number between 0 and 9");
-      index--;
-    }
-  }
-  /* Calculate the Corresponding value */
-  index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10);
-  /* Checks */
-  if (index > value)
-  {
-    printf("\n\rPlease enter valid number between 0 and %d", value);
-    return 0xFF;
-  }
-  return index;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h
deleted file mode 100644
index 01155f6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c
deleted file mode 100644
index f22491d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup RTC_Calendar
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint32_t TimeDisplay;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles RTC global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void RTC_IRQHandler(void)
-{
-  if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
-  {
-    /* Clear the RTC Second interrupt */
-    RTC_ClearITPendingBit(RTC_IT_SEC);
-
-    /* Toggle LED1 */
-    STM_EVAL_LEDToggle(LED1);
-
-    /* Enable time update */
-    TimeDisplay = 1;
-
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-    
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h
deleted file mode 100644
index 861a5e1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void RTC_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt
deleted file mode 100644
index f465c39..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt
+++ /dev/null
@@ -1,111 +0,0 @@
-
-/**
-  @page RTC_LSI_Calib RTC LSI_Calib example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    RTC/LSI_Calib/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the RTC LSI_Calib example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demonstrates and explains how to use the LSI clock source auto
-calibration to get a precise RTC clock. 
-As an application example, it demonstrates how to configure the TIM5 timer
-internally connected to LSI clock output, in order to adjust the RTC prescaler. 
-
-The Low Speed External (LSI) clock is used as RTC clock source.
-After reset, the RTC prescaler is set with the default value (40000). 
-The inaccuracy of the LSI clock causes the RTC Second signal to be inaccurate. This
-signal is output on the Tamper pin (PC.13) and can be measured by on oscilloscope
-or a frequencymeter.
-
-The program waits until Key Push button is pressed to begin the auto calibration procedure:
- - Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to the
-   LSI clock output.
- - Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the
-   period value is stored in a variable and compared to the HCLK clock to get
-   its real value.
- - The RTC prescaler is adjusted with this LSI frequency value so that the RTC
-   Second value become more accurate.
- - When calibration is done a led connected to PF.07 is turned ON to indicate the
-    end of this operation. At this moment, you can  monitor the Second signal on
-    an oscilloscope to measure its accuracy again.
-
-The RTC Second signal can be monitored either on Tamper pin or on LED1 which is 
-toggled into the RTC Second interrupt service routine.
-    
- 
-@par Directory contents 
-
-  - RTC/LSI_Calib/stm32f10x_conf.h     Library Configuration file
-  - RTC/LSI_Calib/stm32f10x_it.c       Interrupt handlers
-  - RTC/LSI_Calib/stm32f10x_it.h       Header for stm32f10x_it.c
-  - RTC/LSI_Calib/main.h               Main header file
-  - RTC/LSI_Calib/main.c               Main program
-  - RTC/LSI_Calib/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density Value line,
-    High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210C-EVAL 
-    (Connectivity Line) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the Key push button connected to PG.08 pin
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PD.07 and PD.13 pins
-    - Use the Key push-button connected to PB.09 pin
-
-  - STM3210E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the Key push button connected to PG.08 pin
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h
deleted file mode 100644
index b6cd4ef..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file RTC/LSI_Calib/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
deleted file mode 100644
index d9218cb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/LSI_Calib/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "main.h" 
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup RTC_LSI_Calib
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t tmpCC4[2] = {0, 0};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles RTC global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void RTC_IRQHandler(void)
-{
-  if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
-  {
-    /* Toggle LED1 */
-    STM_EVAL_LEDToggle(LED1);
-
-    /* Clear Interrupt pending bit */
-    RTC_ClearITPendingBit(RTC_FLAG_SEC);
-  }
-}
-
-/**
-  * @brief  This function handles TIM5 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM5_IRQHandler(void)
-{
-  uint32_t tmp = 0; 
-  
-  if (TIM_GetITStatus(TIM5, TIM_IT_CC4) == SET)
-  {
-    tmpCC4[IncrementVar_OperationComplete()] = (uint16_t)(TIM5->CCR4);
-
-    TIM_ClearITPendingBit(TIM5, TIM_IT_CC4);
-
-    if (GetVar_OperationComplete() >= 2)
-    {
-      /* Compute the period length */
-      tmp = (uint16_t)(tmpCC4[1] - tmpCC4[0] + 1);
-      SetVar_PeriodValue(tmp);
-
-      /* Disable the interrupt */
-      TIM_ITConfig(TIM5, TIM_IT_CC4, DISABLE);
-      TIM_Cmd(TIM5, DISABLE);
-    }
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
deleted file mode 100644
index 9131767..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/LSI_Calib/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void RTC_IRQHandler(void);
-void TIM5_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html
deleted file mode 100644
index 8b0640c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html
+++ /dev/null
@@ -1,441 +0,0 @@
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-            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>
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-<td style="padding: 1.5pt;">
-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x Standard Peripherals Library Examples
-(StdPeriph_Examples)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr>
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
-Examples update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;">
-</span>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
-Peripherals Library Examples update History</span></h2><br>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 08-April-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add two new examples: <br>
-</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">MPU</span>:
-This example presents the MPU features on STM32F10x XL-density devices
-and it can be easily ported to any other STM32 device supporting MPU.<br style="text-decoration: underline;">
-                  </span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">TIM DMA Burst</span>:This example shows how to update the TIM1 channel1 period and the duty cycle using the TIM1 DMA burst feature.</span></li>
-              </ul>
-
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">FSMC OneNAND, GPIO IO Toggle, EXTI, Lib_DEBUG, IWDG, WWDG, NVIC, SDIO and SysTick examples updated.</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">FSMC OneNAND</span> example updated according to the last stm32100e_eval_fsmc_onenand.h/.c driver modification</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">SDIO</span> example </span><span style="font-size: 10pt; font-family: Verdana;">enhanced</span><span style="font-size: 10pt; font-family: Verdana;"> according to the last stm32_eval_sdio_sd.h/.c driver enhancement: SD Card driver is running up to 24MHz. Refer to </span><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL release notes.</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">GPIO IO Toggle</span> is updated to achieve maximum IO toggling frequency (HLCK/4).</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">EXTI</span> example updated to give more details on how to configure an external interrupt.</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">IWDG</span> </span><span style="font-size: 10pt; font-family: Verdana;">enhanced</span><span style="font-size: 10pt; font-family: Verdana;"> is updated to use accurate timeout thanks to LSI frequency measure with Timers.</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">NVIC and SysTick</span> examples enhanced to provide more details on how to use them with CMSIS layer.</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">WWDG</span> enhanced to provide more details on how to use the peripheral and how to use its interrupt.<br>
-                  </span></li>
-              </ul>
-
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
-            <ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density Value line</span> devices.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">"<span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span>" placed in each example folder.<br>
-</span></li>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new examples: <br>
-                </span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FSMC OneNAND. </span><br>
-                  <span style="font-size: 10pt; font-family: Verdana;"></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C EEPROM, </span><span style="font-size: 10pt; font-family: Verdana;">I2C TSENSOR and I2C IOExpander. </span><br>
-<span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Remove </span><span style="font-size: 10pt; font-family: Verdana;">old </span><span style="font-size: 10pt; font-family: Verdana;">I2C examples: DualAddress, 10bitAddress, Interrupt, </span><span style="font-size: 10pt; font-family: Verdana;">M24C08_EEPROM</span><span style="font-size: 10pt; font-family: Verdana;"> and SMBus. <br>
-</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update SPI GPIO Configurations in all SPI examples: MISO is configured as Input floating.<br>
-</span></li>
-
-            </ul>
-
-            <ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">&nbsp;FLASH</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-
-            
-            <ul style="margin-top: 0in;" type="disc">
-<ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Write_Protection modified to keep user configuration (already protected pages) and when Options bytes are not erased.</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul>
-            </ul>
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">FSMC</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u>
-
-            
-            
-                <ul style="margin-top: 0in;" type="circle">
-                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New
-example OneNAND: this example shows how to configure the FSMC to drive
-the OneNAND memory mounted&nbsp; on STM32100E-EVAL board. </span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
-                </ul>
-                <br>
-<i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></i></li>
-              <li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">I2C</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></li>
-
-            </ul>
-
-
-            
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Old Examples removed.</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example EEPROM (based on old </span><span style="font-size: 10pt; font-family: Verdana;">M24C08_EEPROM example</span><span style="font-size: 10pt; font-family: Verdana;">):
-Using the latest version of I2C EEPROM driver (use of DMA to manage
-transfer from/to I2C memory). For more details refer to STM32_EVAL
-release note "Release_Notes_for_STM32_EVAL.html".</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New
-example "I2C TSENSOR": this example shows how to use the I2C to
-communicate with&nbsp; an STLM75 (or a compatible device) I2C
-temperature sensor mounted on the&nbsp; evaluation board and used to
-get instantaneous external temperature<br>
-(-55°C to +125°C). This example uses the latest I2C TSensor driver </span><span style="font-size: 10pt; font-family: Verdana;">(use of DMA to
-manage transfer from/to I2C device). For more details refer to
-STM32_EVAL release note "Release_Notes_for_STM32_EVAL.html".</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New
-example "I2C IOExpander": this example shows how to configure and to
-use the IO Expander STMPE811&nbsp; in order to control input Joystick
-IOs, output IOs and the Touch Screen feature. </span><span style="font-size: 10pt; font-family: Verdana;">This example uses the latest I2C IO Expander driver </span><span style="font-size: 10pt; font-family: Verdana;">(use of DMA to
-manage transfer from/to I2C device). For more details refer to
-STM32_EVAL release note "Release_Notes_for_STM32_EVAL.html".</span></li>
-</ul>
-            </ul>
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">SPI</span></u></i><br>
-</li>
-            </ul>
-
-
-
-
-            
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update SPI GPIO Configurations in all SPI examples: MISO is configured as Input floating.</span></li></ul>
-            </ul>
-            <br>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
-- 04/16/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density</span> devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new examples: Flash Dual_Boot, TIM9_OCToggle and TIM10_PWMOutput.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul>
-<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">&nbsp;FLASH</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-            <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example "</span><span style="font-size: 10pt; font-family: Verdana;">Dual_Boot": this example demonstrates the dual Flash boot capability of XL-Density devices;<br>boot from Flash memory Bank1 or Bank2.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update "Program" and "Write_Protection" to support </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">XL-density</span> devices (up to 1Mbyte of Flash memory)</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul></ul><ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">I2C</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></li></ul>
-
-            <ul style="margin-top: 0in;" type="circle"><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">M24C08_EEPROM: updated to use the latest version of I2C EEPROM driver (use of DMA to manage transfer from/to I2C memory).</span></li></ul></ul><ul><li><i><u><span style="font-size: 10pt; font-family: Verdana;">TIM</span></u></i><br>
-  </li></ul>
-
-
-
-            <ul style="margin-top: 0in;" type="circle"><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example "TIM9_OCToggle"</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">: this example shows how to configure the TIM9 peripheral to generate two different signals with two different frequencies.<br>
-                  </span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">New example "TIM10_PWMOutput"</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">: this example shows how to configure the TIM10 peripheral in PWM (Pulse Width Modulation) mode.</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b> for almost examples.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new examples: HDMI-CEC, Dual CAN, PVD and TIM15 Complementary Signals.</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-</ul>
-<ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">CAN</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-</ul>
-            <ul style="margin-top: 0in;" type="disc">
-
-              <ul style="margin-top: 0in;" type="circle">
-
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new example Dual CAN: This example shows how to configure the CAN1 and CAN2 peripherals to send and <br>
-receive CAN frames in normal mode. The sent frames are used to control Leds by pressing KEY or Tamper push buttons.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">CAN Normal example renamed to CAN Networking example.<br>
-</span></li>
-
-              </ul>
-
-            </ul>
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u><i><u><span style="font-size: 10pt; font-family: Verdana;">CEC</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></li>
-            </ul>
-
-            <ul style="margin-top: 0in;" type="circle">
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example: This example provides a basic communication between two HDMI-CEC devices using interrupts.</span></li>
-              </ul>
-            </ul>
-            <ul>
-              <li><i><u><span style="font-size: 10pt; font-family: Verdana;">PWR</span></u></i><br>
-              </li>
-            </ul>
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example PVD: This example shows how to configure the programmable voltage detector using an external interrupt line. <br>
-</span></li></ul>
-            </ul>
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">TIM</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New example </span><span style="font-size: 10pt; font-family: Verdana;">TIM15 Complementary Signals</span><span style="font-size: 10pt; font-family: Verdana;">: This example shows how to configure the TIM15 peripheral to generate one <br>
-complementary TIM15 signal, to insert a defined dead time value, to use the break feature and to lock the desired parameters. <br>
-                  </span></li>
-                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Cascade_Synchro,Parallel_Synchro,
-ExtTrigger_Synchro, TIM1_Synchro examples main files: Add
-TIM_SelectMasterSlaveMode() function call for all slaves and masters.</span></li>
-</ul>
-            </ul>
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">I2C</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">EEPROM
-example: the i2c_ee.h/.c files are removed. The example is using the
-new Serial EEPROM driver stm32_eval_i2c_ee.h/.c driver available under
-Utilities\STM32_EVAL\Common.</span><span style="font-size: 10pt; font-family: Verdana;"><br>
-      </span></li></ul>
-            </ul>
-
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">SPI</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">M25P64_FLASH example renamed to SPI_FLASH:
-the spi_flash.h/.c files are removed. The example is using the new Serial SPI FLASH
-driver stm32_eval_spi_flash.h/.c driver available under
-Utilities\STM32_EVAL\Common.</span><span style="font-size: 10pt; font-family: Verdana;">
-      </span></li></ul>
-            </ul>
-
-            <span style="font-size: 10pt; font-family: Verdana;"></span>
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">SDIO</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">The sdcard.h/.c files are removed. The example is using the new SD Card
-driver stm32_eval_sdio_sd.h/.c driver available under
-Utilities\STM32_EVAL\Common.</span><span style="font-size: 10pt; font-family: Verdana;">
-      </span></li></ul>
-            </ul>
-
-            <span style="font-size: 10pt; font-family: Verdana;">
-            </span>
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">FSMC</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All FSMC example:
-the fsmc_sram.h/.c, </span><span style="font-size: 10pt; font-family: Verdana;">fsmc_nor.h/.c and </span><span style="font-size: 10pt; font-family: Verdana;">fsmc_nand.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"> files are removed. The examples are using the new FSMC memories
-drivers stm3210e_eval_fsmc_sram.h/.c, </span><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nor.h/.c and </span><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nand.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"> drivers available under
-Utilities\STM32_EVAL\STM3210E_EVAL.</span><span style="font-size: 10pt; font-family: Verdana;">
-      </span></li></ul>
-            </ul>
-
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">DMA</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FSMC example:
-the fsmc_sram.h/.c files are removed. The example is using the new FSMC SRAM
-driver stm3210e_eval_fsmc_sram.h/.c driver available under
-Utilities\STM32_EVAL\</span><span style="font-size: 10pt; font-family: Verdana;">STM3210E_EVAL</span><span style="font-size: 10pt; font-family: Verdana;">.</span><span style="font-size: 10pt; font-family: Verdana;">
-      </span></li></ul>
-            </ul>
-
-            <ul>
-<li><i><u><span style="font-size: 10pt; font-family: Verdana;">ADC</span></u></i><br>
-  </li>
-            </ul>
-
-
-
-
-            <ul style="margin-top: 0in;" type="circle">
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All ADC examples are using a dedicated system_stm32f10x.c file to configure the system core clock to 56MHz.</span><span style="font-size: 10pt; font-family: Verdana;"> <br>
-      </span></li></ul>
-            </ul>
-
-            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<ul style="margin-top: 0in;" type="disc">
-
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
deleted file mode 100644
index 3a28739..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval_sdio_sd.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SDIO_uSDCard
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BLOCK_SIZE            512 /* Block Size in Bytes */
-
-#define NUMBER_OF_BLOCKS      32  /* For Multi Blocks operation (Read/Write) */
-#define MULTI_BUFFER_SIZE    (BLOCK_SIZE * NUMBER_OF_BLOCKS)
-
-#define SD_OPERATION_ERASE          0
-#define SD_OPERATION_BLOCK          1
-#define SD_OPERATION_MULTI_BLOCK    2 
-#define SD_OPERATION_END            3
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint8_t Buffer_Block_Tx[BLOCK_SIZE], Buffer_Block_Rx[BLOCK_SIZE];
-uint8_t Buffer_MultiBlock_Tx[MULTI_BUFFER_SIZE], Buffer_MultiBlock_Rx[MULTI_BUFFER_SIZE];
-volatile TestStatus EraseStatus = FAILED, TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-SD_Error Status = SD_OK;
-__IO uint32_t SDCardOperation = SD_OPERATION_ERASE;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-void SD_EraseTest(void);
-void SD_SingleBlockTest(void);
-void SD_MultiBlockTest(void);
-void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength);
-TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-
-  /* Initialize LEDs available on STM3210X-EVAL board *************************/
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);  
-
-  /* Interrupt Config */
-  NVIC_Configuration();
-
-  /*------------------------------ SD Init ---------------------------------- */
-  if((Status = SD_Init()) != SD_OK)
-  {
-    STM_EVAL_LEDOn(LED4); 
-  }
-        
-  while((Status == SD_OK) && (SDCardOperation != SD_OPERATION_END) && (SD_Detect()== SD_PRESENT))
-  {
-    switch(SDCardOperation)
-    {
-      /*-------------------------- SD Erase Test ---------------------------- */
-      case (SD_OPERATION_ERASE):
-      {
-        SD_EraseTest();
-        SDCardOperation = SD_OPERATION_BLOCK;
-        break;
-      }
-      /*-------------------------- SD Single Block Test --------------------- */
-      case (SD_OPERATION_BLOCK):
-      {
-        SD_SingleBlockTest();
-        SDCardOperation = SD_OPERATION_MULTI_BLOCK;
-        break;
-      }       
-      /*-------------------------- SD Multi Blocks Test --------------------- */
-      case (SD_OPERATION_MULTI_BLOCK):
-      {
-        SD_MultiBlockTest();
-        SDCardOperation = SD_OPERATION_END;
-        break;
-      }              
-    }
-  }
-  
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures SDIO IRQ channel.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure the NVIC Preemption Priority Bits */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-
-  NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Tests the SD card erase operation.
-  * @param  None
-  * @retval None
-  */
-void SD_EraseTest(void)
-{
-  /*------------------- Block Erase ------------------------------------------*/
-  if (Status == SD_OK)
-  {
-    /* Erase NumberOfBlocks Blocks of WRITE_BL_LEN(512 Bytes) */
-    Status = SD_Erase(0x00, (BLOCK_SIZE * NUMBER_OF_BLOCKS));
-  }
-
-  if (Status == SD_OK)
-  {
-    Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-
-    /* Wait until end of DMA transfer */
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of erased blocks */
-  if (Status == SD_OK)
-  {
-    EraseStatus = eBuffercmp(Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
-  }
-  
-  if(EraseStatus == PASSED)
-  {
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED1);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Tests the SD card Single Blocks operations.
-  * @param  None
-  * @retval None
-  */
-void SD_SingleBlockTest(void)
-{
-  /*------------------- Block Read/Write --------------------------*/
-  /* Fill the buffer to send */
-  Fill_Buffer(Buffer_Block_Tx, BLOCK_SIZE, 0x320F);
-
-  if (Status == SD_OK)
-  {
-    /* Write block of 512 bytes on address 0 */
-    Status = SD_WriteBlock(Buffer_Block_Tx, 0x00, BLOCK_SIZE);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitWriteOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  if (Status == SD_OK)
-  {
-    /* Read block of 512 bytes from address 0 */
-    Status = SD_ReadBlock(Buffer_Block_Rx, 0x00, BLOCK_SIZE);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of written data */
-  if (Status == SD_OK)
-  {
-    TransferStatus1 = Buffercmp(Buffer_Block_Tx, Buffer_Block_Rx, BLOCK_SIZE);
-  }
-  
-  if(TransferStatus1 == PASSED)
-  {
-    STM_EVAL_LEDOn(LED2);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED2);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Tests the SD card Multiple Blocks operations.
-  * @param  None
-  * @retval None
-  */
-void SD_MultiBlockTest(void)
-{
-  /*--------------- Multiple Block Read/Write ---------------------*/
-  /* Fill the buffer to send */
-  Fill_Buffer(Buffer_MultiBlock_Tx, MULTI_BUFFER_SIZE, 0x0);
-
-  if (Status == SD_OK)
-  {
-    /* Write multiple block of many bytes on address 0 */
-    Status = SD_WriteMultiBlocks(Buffer_MultiBlock_Tx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitWriteOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  if (Status == SD_OK)
-  {
-    /* Read block of many bytes from address 0 */
-    Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of written data */
-  if (Status == SD_OK)
-  {
-    TransferStatus2 = Buffercmp(Buffer_MultiBlock_Tx, Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
-  }
-  
-  if(TransferStatus2 == PASSED)
-  {
-    STM_EVAL_LEDOn(LED3);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED3);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-/**
-  * @brief  Fills buffer with user predefined data.
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  BufferLength: size of the buffer to fill
-  * @param  Offset: first value to fill on the Buffer
-  * @retval None
-  */
-void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset)
-{
-  uint16_t index = 0;
-
-  /* Put in global buffer same values */
-  for (index = 0; index < BufferLength; index++)
-  {
-    pBuffer[index] = index + Offset;
-  }
-}
-
-/**
-  * @brief  Checks if a buffer has all its values are equal to zero.
-  * @param  pBuffer: buffer to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer values are zero
-  *         FAILED: At least one value from pBuffer buffer is different from zero.
-  */
-TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    /* In some SD Cards the erased state is 0xFF, in others it's 0x00 */
-    if ((*pBuffer != 0xFF) && (*pBuffer != 0x00))
-    {
-      return FAILED;
-    }
-
-    pBuffer++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt
deleted file mode 100644
index 9659113..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-/**
-  @page SDIO_uSDCard SDIO Micro SD Card example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SDIO/uSDCard/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SDIO Micro SD Card example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the SDIO firmware library and
-an associate driver to perform read/write operations on the SD Card memory (SD Card 
-V1.0, V1.1, V2.0 and SDHC (High Capacity) protocol)that could be mounted on the 
-STM3210E-EVAL board.
-
-The example provides different SD Card transfer states and operations and here
-below a description of each step:
-  - First the SDIO peripheral and SD Card are initialized using the SD_Init()
-    function: 
-            - Configure the SDIO according to the desired SDIO_CK clock frequency.
-            - Reset the SD Card
-            - Identify the SD Card
-            - Initializes the SD Card
-            - Get the SD Card Info
-            - Select the SD Card
-            - Enable the Wide Bus mode (4-bit data)
-
-  - SD Card Erase Operation
-            - Starts an Erase operation: Erase the corresponding blocks using 
-              the SD_Erase() function 
-            - Read the Erased blocks using the SD_ReadMultiBlocks() function
-            - Test if the corresponding Blocks are well erased: check if the 
-              EraseStatus variable is equal to PASSED. If the erase operation is
-              passed LED1 is turned ON.
-            
-  - SD Card Single Block Operation
-            - Starts a Write operation: Write a single Block using the SD_WriteBlock()
-              function 
-            - Read a single Block using the SD_ReadBlock() function
-            - Compare the written Block and the read one: check if the TransferStatus1 
-              variable is equal to PASSED. If the Single Block Read/write operation
-              is passed LED2 is turned ON.
-
-  - SD Card Multiple Block Operation
-            - Starts a Multiple Write operation: Write a multi Blocks using the 
-              SD_WriteMultiBlocks() function. 
-            - Read a multiple Blocks using the SD_ReadMultiBlocks() function
-            - Compare the written Blocks and the read one: check if the TransferStatus2 
-              variable is equal to PASSED. If the Multiple Blocks Read/Write operation
-              is passed LED3 is turned ON.
-
-All data transfers are made by DMA.
-At each operation, the SD Card presence and status is checked using the SD_GetStatus()
-function and a global variable "Status" storing the results of the last operation.
-
-SD Card Operations and Written/Read data correctness is signaled  by LED 
-lightening and though as follow:
-   - If the Erase operation is PASSED then LED1 ON else the LED4 is ON and LED1 is OFF 
-   - If the Single Block Write/Read operation is PASSED then LED2 ON else the LED4 is ON and LED2 is OFF
-   - If the Multi Blocks Write/Read operation is PASSED then LED3 ON else the LED4 is ON and LED3 is OFF
-   - Any SD Card operation including the SD Initialization error is signaled by
-     LED4 ON.
- 
-
-@par Directory contents 
-
-  - SDIO/uSDCard/stm32f10x_conf.h    Library Configuration file
-  - SDIO/uSDCard/stm32f10x_it.c      Interrupt handlers
-  - SDIO/uSDCard/stm32f10x_it.h      Header for stm32f10x_it.c
-  - SDIO/uSDCard/main.c              Main program
-  - SDIO/uSDCard/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board and can be easily tailored to any other 
-    supported device and development board.
-
-@note Make sure that the Jumper 17 (JP17) is closed and Jumper 20 (JP20) is open
-      in STM3210E-EVAL 
-
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h
deleted file mode 100644
index 385772d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c
deleted file mode 100644
index 66ded33..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval_sdio_sd.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SDIO_uSDCard
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles SDIO global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void SDIO_IRQHandler(void)
-{
-  /* Process All SDIO Interrupt Sources */
-  SD_ProcessIRQSrc();
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h
deleted file mode 100644
index 8ff798e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void SDIO_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c
deleted file mode 100644
index 769c6d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
deleted file mode 100644
index ef642cd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/CRC/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_CRC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize  32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SPI_InitTypeDef  SPI_InitStructure;
-uint16_t SPI1_Buffer_Tx[BufferSize] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
-                                  0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
-                                  0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
-                                  0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
-                                  0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
-                                  0x3D3E, 0x3F40};
-uint16_t SPI2_Buffer_Tx[BufferSize] = {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
-                                  0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
-                                  0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
-                                  0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
-                                  0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
-                                  0x8D8E, 0x8F90};
-uint16_t SPI1_Buffer_Rx[BufferSize], SPI2_Buffer_Rx[BufferSize];
-uint32_t TxIdx = 0, RxIdx = 0;
-__IO uint16_t CRC1Value = 0, CRC2Value = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-
-/* Private functions ---------------------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* SPI1 configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SPI1, &SPI_InitStructure);
-
-  /* SPI2 configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPI2, &SPI_InitStructure);
-
-  /* Enable SPI1 CRC calculation */
-  SPI_CalculateCRC(SPI1, ENABLE);
-  /* Enable SPI2 CRC calculation */
-  SPI_CalculateCRC(SPI2, ENABLE);
-
-  /* Enable SPI1 */
-  SPI_Cmd(SPI1, ENABLE);
-  /* Enable SPI2 */
-  SPI_Cmd(SPI2, ENABLE);
-
-  /* Transfer procedure */
-  while (TxIdx < BufferSize - 1)
-  {
-    /* Wait for SPI1 Tx buffer empty */
-    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
-    /* Send SPI2 data */
-    SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
-    /* Send SPI1 data */
-    SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx++]);
-    /* Wait for SPI2 data reception */
-    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPI2 received data */
-    SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
-    /* Wait for SPI1 data reception */
-    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPI1 received data */
-    SPI1_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI1);
-  }
-
-  /* Wait for SPI1 Tx buffer empty */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
-  /* Wait for SPI2 Tx buffer empty */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
-
-  /* Send last SPI2_Buffer_Tx data */
-  SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
-  /* Enable SPI2 CRC transmission */
-  SPI_TransmitCRC(SPI2);
-  /* Send last SPI1_Buffer_Tx data */
-  SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx]);
-  /* Enable SPI1 CRC transmission */
-  SPI_TransmitCRC(SPI1);
-
-  /* Wait for SPI1 last data reception */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Read SPI1 last received data */
-  SPI1_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI1);
-
-  /* Wait for SPI2 last data reception */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Read SPI2 last received data */
-  SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
-
-  /* Wait for SPI1 data reception: CRC transmitted by SPI2 */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Wait for SPI2 data reception: CRC transmitted by SPI1 */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(SPI2_Buffer_Rx, SPI1_Buffer_Tx, BufferSize);
-  TransferStatus2 = Buffercmp(SPI1_Buffer_Rx, SPI2_Buffer_Tx, BufferSize);
-  /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
-     are correct */
-  /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
-     are different */
-
-  /* Test on the SPI1 CRC Error flag */
-  if ((SPI_I2S_GetFlagStatus(SPI1, SPI_FLAG_CRCERR)) == SET)
-  {
-    TransferStatus2 = FAILED;
-  }
-
-  /* Test on the SPI2 CRC Error flag */
-  if ((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_CRCERR)) == SET)
-  {
-    TransferStatus1 = FAILED;
-  }
-
-  /* Read SPI1 received CRC value */
-  CRC1Value = SPI_I2S_ReceiveData(SPI1);
-  /* Read SPI2 received CRC value */
-  CRC2Value = SPI_I2S_ReceiveData(SPI2);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK2 = HCLK/2 */
-  RCC_PCLK2Config(RCC_HCLK_Div2);
-
-  /* Enable peripheral clocks --------------------------------------------------*/
-  /* GPIOA, GPIOB and SPI1 clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_SPI1, ENABLE);
-
-  /* SPI2 Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure SPI1 pins: SCK, MISO and MOSI ---------------------------------*/
-  /* Confugure SCK and MOSI pins as Alternate Function Push Pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  /* Confugure MISO pin as Input Floating  */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  
-  /* Configure SPI2 pins: SCK, MISO and MOSI ---------------------------------*/
-  /* Confugure SCK and MOSI pins as Input Floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-  /* Confugure MISO pin as Alternate Function Push Pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
- 
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt
deleted file mode 100644
index e3311a5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
-  @page SPI_CRC SPI CRC example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/CRC/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI CRC example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to set a communication between two
-SPIs in full-duplex mode and performs a transfer from Master to Slave and  
-Slave to Master followed by CRC transmission.
-
-SPI1 is configured as master and SPI2 as slave and both are in full-duplex
-configuration mode with 16bit data size and a 4.5 Mbit/s communication speed 
-(for Value line devices the speed is set at 1.5 Mbit/s).
-CRC calculation is enabled for both SPIs.
-
-After enabling both SPIs, the first data from SPI2_Buffer_Tx is transmitted from
-slave followed by the first data from SPI1_Buffer_Tx send by the master. A test 
-on RxNE flag is done for both master and slave to check the reception of data on
-their respective data register. The same procedure is done for the remaining data
-to transfer except the last ones. 
-
-Last data from SPI1_Buffer_Tx is transmitted followed by enabling CRC transmission
-for SPI1 and the last data from SPI2_Buffer_Tx is transmitted followed by enabling
-CRC transmission for SPI2: user must take care to reduce code on this phase for
-high speed communication. 
-
-Last transmitted buffer data and CRC value are then received successively on
-master and slave data registers. The received CRC value are stored on CRC1Value
-and CRC2Value respectively for SPI1 and SPI2.
-
-Once the transfer is completed a comparison is done and TransferStatus1 and 
-TransferStatus2 gives the data transfer status for each data transfer direction 
-where it is PASSED if transmitted and received data are the same otherwise it 
-is FAILED.
-A check of CRC error flag, for the master and the salve, is done after receiving
-CRC data.
-
-@par Directory contents 
-
-  - SPI/CRC/stm32f10x_conf.h     Library Configuration file
-  - SPI/CRC/stm32f10x_it.c       Interrupt handlers
-  - SPI/CRC/stm32f10x_it.h       Header for stm32f10x_it.c
-  - SPI/CRC/main.c               Main program
-  - SPI/CRC/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL(STM32F10x Medium-Density Value line), STM3210E-EVAL 
-    (STM32F10x High-Density) and STM3210B-EVAL (STM32F10x Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported 
-    device and development board.
-    This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x 
-    Connectivity Line) evaluation board.
-
-  - STM32100E-EVAL Set-up 
-     - Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
-     - Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
-     - Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
-         
-  - STM32100B-EVAL Set-up 
-     - Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
-     - Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
-     - Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
-
-  - STM3210E-EVAL Set-up 
-     - Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
-     - Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
-     - Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfer with SPI2 MISO pin PB14.
-
-  - STM3210B-EVAL Set-up 
-     - Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
-     - Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
-     - Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
-	 
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h
deleted file mode 100644
index 8331a3f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/CRC/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c
deleted file mode 100644
index 74631fd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/CRC/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_CRC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h
deleted file mode 100644
index 9c67ba1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/CRC/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c
deleted file mode 100644
index dc6cd30..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/CRC/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
deleted file mode 100644
index 985e800..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/DMA/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize       32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SPI_InitTypeDef  SPI_InitStructure;
-DMA_InitTypeDef  DMA_InitStructure;
-GPIO_InitTypeDef GPIO_InitStructure;
-
-uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
-                                            0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C,
-                                            0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12,
-                                            0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
-                                            0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E,
-                                            0x1F, 0x20};
-uint8_t SPI_SLAVE_Buffer_Rx[BufferSize];
-__IO uint8_t TxIdx = 0;
-volatile TestStatus TransferStatus = FAILED;
-
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* SPI_SLAVE_Rx_DMA_Channel configuration ---------------------------------------------*/
-  DMA_DeInit(SPI_SLAVE_Rx_DMA_Channel);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Rx;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = BufferSize;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(SPI_SLAVE_Rx_DMA_Channel, &DMA_InitStructure);
-
-  /* SPI_MASTER configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SPI_MASTER, &SPI_InitStructure);
-
-  /* SPI_SLAVE configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Rx;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPI_SLAVE, &SPI_InitStructure);
-
-  /* Enable SPI_MASTER NSS output for master mode */
-  SPI_SSOutputCmd(SPI_MASTER, ENABLE);
-
-  /* Enable SPI_SLAVE Rx request */
-  SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Rx, ENABLE);
-
-  /* Enable SPI_SLAVE */
-  SPI_Cmd(SPI_SLAVE, ENABLE);
-  /* Enable SPI_MASTER */
-  SPI_Cmd(SPI_MASTER, ENABLE);
-
-  /* Enable DMA1 Channel4 */
-  DMA_Cmd(SPI_SLAVE_Rx_DMA_Channel, ENABLE);
-
-  /* Transfer procedure */
-  while (TxIdx < BufferSize)
-  {
-    /* Wait for SPI_MASTER Tx buffer empty */
-    while (SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_I2S_FLAG_TXE) == RESET);
-    /* Send SPI_MASTER data */
-    SPI_I2S_SendData(SPI_MASTER, SPI_MASTER_Buffer_Tx[TxIdx++]);
-  }
-
-  /* Wait for DMA1 channel4 transfer complete */
-  while (!DMA_GetFlagStatus(SPI_SLAVE_Rx_DMA_FLAG));
-
-  /* Check the correctness of written data */
-  TransferStatus = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
-  /* TransferStatus = PASSED, if the transmitted and received data
-     are equal */
-  /* TransferStatus = FAILED, if the transmitted and received data
-     are different */
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK2 = HCLK/2 */
-  RCC_PCLK2Config(RCC_HCLK_Div2); 
-
-  /* Enable peripheral clocks --------------------------------------------------*/
-  /* Enable SPI_SLAVE DMA clock */
-  RCC_AHBPeriphClockCmd(SPI_SLAVE_DMA_CLK, ENABLE);
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
-  RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
-                         RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable SPI_MASTER Periph clock */
-  RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
-                           
-#else
-  /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
-  RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
-                         SPI_MASTER_CLK, ENABLE);
-#endif
-  /* Enable SPI_SLAVE Periph clock */
-  RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable SPI3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
-
-  /* Configure SPI_MASTER pins: SCK and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
-
-  /* Configure SPI_MASTER NSS pin */
-  GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_NSS;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_MASTER_GPIO_NSS, &GPIO_InitStructure);
-
-#else
-  /* Configure SPI_MASTER pins: NSS, SCK and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_NSS | SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
-#endif
-
-  /* Configure SPI_SLAVE pins: NSS, SCK and MISO*/
-  GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_NSS | SPI_SLAVE_PIN_SCK;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin =  SPI_SLAVE_PIN_MISO;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
-  
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h
deleted file mode 100644
index a628e14..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/DMA/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)&&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
-  #define SPI_MASTER                   SPI1
-  #define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
-  #define SPI_MASTER_GPIO              GPIOA
-  #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA  
-  #define SPI_MASTER_PIN_NSS           GPIO_Pin_4
-  #define SPI_MASTER_PIN_SCK           GPIO_Pin_5
-  #define SPI_MASTER_PIN_MISO          GPIO_Pin_6
-  #define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
-  
-  #define SPI_SLAVE                    SPI2
-  #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
-  #define SPI_SLAVE_GPIO               GPIOB
-  #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB 
-  #define SPI_SLAVE_PIN_NSS            GPIO_Pin_12
-  #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
-  #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
-  #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15 
-  #define SPI_SLAVE_DMA                DMA1
-  #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1  
-  #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
-  #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
-  #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
-  #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5  
-  #define SPI_SLAVE_DR_Base            0x4000380C
-          
-#elif defined (USE_STM3210C_EVAL)
-  #define SPI_MASTER                   SPI3   /* SPI pins are remapped by software */
-  #define SPI_MASTER_CLK               RCC_APB1Periph_SPI3
-  #define SPI_MASTER_GPIO              GPIOC
-  #define SPI_MASTER_GPIO_NSS          GPIOA
-  #define SPI_MASTER_GPIO_CLK          (RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA)  
-  #define SPI_MASTER_PIN_NSS           GPIO_Pin_4
-  #define SPI_MASTER_PIN_SCK           GPIO_Pin_10
-  #define SPI_MASTER_PIN_MISO          GPIO_Pin_11
-  #define SPI_MASTER_PIN_MOSI          GPIO_Pin_12
-  
-  #define SPI_SLAVE                    SPI2
-  #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
-  #define SPI_SLAVE_GPIO               GPIOB
-  #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
-  #define SPI_SLAVE_PIN_NSS            GPIO_Pin_12
-  #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
-  #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
-  #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
-  #define SPI_SLAVE_DMA                DMA1
-  #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
-  #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
-  #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
-  #define SPI_SLAVE_DR_Base            0x4000380C 
-
-#endif
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt
deleted file mode 100644
index 726061f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
-  @page SPI_DMA SPI DMA example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/DMA/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI DMA example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to set a communication between the two
-SPIs in simplex mode and performs a transfer from SPI_MASTER in polling mode to the
-SPI_SLAVE in DMA receive mode. 
-
-SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the
-STMicroelectronics EVAL board you are using.
-
-Both SPIs are configured with 8bit data frame and a 18Mbit/s communication speed.
-SPI_MASTER is configured in bidirectional mode as transmitter only, while SPI_SLAVE
-is configured in bidirectional mode but as receiver only. Both master and slave NSS
-pins are managed by hardware.
-A dedicated DMA channel is configured for SPI_SLAVE Rx request to store received
-data in SPI_SLAVE_Buffer_Rx. 
-
-SPI_MASTER starts by transferring the first data, once this data is received by the
-SPI_SLAVE the RxNE request will trigger the DMA to transfer this data and store it
-into SPI_SLAVE_Buffer_Rx. The same action is done for the rest of the buffer.
-
-Once the transfer is completed a comparison is done and TransferStatus gives the
-data transfer status where it is PASSED if transmitted and received data are the
-same otherwise it is FAILED.
-
-
-@par Directory contents 
-
-  - SPI/DMA/platform_config.h   Evaluation board specific configuration file
-  - SPI/DMA/stm32f10x_conf.h    Library Configuration file
-  - SPI/DMA/stm32f10x_it.c      Interrupt handlers
-  - SPI/DMA/stm32f10x_it.h      Interrupt handlers header file
-  - SPI/DMA/main.c              Main program
-  - SPI/DMA/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity
-    line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    This example can't be tested with STMicroelectronics STM32100E-EVAL (STM32F10x 
-    High-Density Value line) and STM32100B-EVAL (STM32F10x Medium-Density Value line) 
-    evaluation boards. To select the STMicroelectronics evaluation board used to 
-    run the example,uncomment the corresponding line in SPI/DMA/platform_config.h file.  
-
-  
-  - STM3210C-EVAL Set-up 
-    - Connect SPI2 NSS pin (PB.12) to SPI3 NSS pin	(PA.04)
-    - Connect SPI2 SCK pin (PB.13) to SPI3 SCK pin (PC.10)
-    - Connect SPI2 MISO pin (PB.14) to SPI3 MOSI pin (PC.12)
-    @note In this case SPI3 pins are remapped by software.
-
-  - STM3210E-EVAL Set-up 
-    - Connect SPI2 NSS pin (PB.12) to SPI1 NSS pin (PA.04)
-    - Connect SPI2 SCK pin (PB.13) to SPI1 SCK pin (PA.05)
-    - Connect SPI2 MISO pin (PB.14) to SPI1 MOSI pin (PA.07)
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfer with SPI2 MISO pin PB14.
-
-  - STM3210B-EVAL Set-up 
-    - Connect SPI2 NSS pin (PB.12) to SPI1 NSS pin (PA.04)
-    - Connect SPI2 SCK pin (PB.13) to SPI1 SCK pin (PA.05)
-    - Connect SPI2 MISO pin (PB.14) to SPI1 MOSI pin (PA.07)
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h
deleted file mode 100644
index 352148a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/DMA/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c
deleted file mode 100644
index d8e98db..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/DMA/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h
deleted file mode 100644
index 54b35d9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/DMA/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c
deleted file mode 100644
index 34c34c7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/DMA/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
deleted file mode 100644
index 8e34cbd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/FullDuplex_SoftNSS/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_FullDuplex_SoftNSS
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize 32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SPI_InitTypeDef   SPI_InitStructure;
-uint8_t SPIy_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-                                      0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E,
-                                      0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
-                                      0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C,
-                                      0x1D, 0x1E, 0x1F, 0x20};
-uint8_t SPIz_Buffer_Tx[BufferSize] = {0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-                                      0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E,
-                                      0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 
-                                      0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C,
-                                      0x6D, 0x6E, 0x6F, 0x70};
-uint8_t SPIy_Buffer_Rx[BufferSize], SPIz_Buffer_Rx[BufferSize];
-__IO uint8_t TxIdx = 0, RxIdx = 0, k = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-volatile TestStatus TransferStatus3 = FAILED, TransferStatus4 = FAILED;
-
-/* Private functions ---------------------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(uint16_t SPIy_Mode, uint16_t SPIz_Mode);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* 1st phase: SPIy Master and SPIz Slave */
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration(SPI_Mode_Master, SPI_Mode_Slave);
-  
-  /* SPIy Config -------------------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SPIy, &SPI_InitStructure);
-
-  /* SPIz Config -------------------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPIz, &SPI_InitStructure);
-
-  /* Enable SPIy */
-  SPI_Cmd(SPIy, ENABLE);
-  /* Enable SPIz */
-  SPI_Cmd(SPIz, ENABLE);
-
-  /* Transfer procedure */
-  while (TxIdx < BufferSize)
-  {
-    /* Wait for SPIy Tx buffer empty */
-    while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_TXE) == RESET);
-    /* Send SPIz data */
-    SPI_I2S_SendData(SPIz, SPIz_Buffer_Tx[TxIdx]);
-    /* Send SPIy data */
-    SPI_I2S_SendData(SPIy, SPIy_Buffer_Tx[TxIdx++]);
-    /* Wait for SPIz data reception */
-    while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPIz received data */
-    SPIz_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPIz);
-    /* Wait for SPIy data reception */
-    while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPIy received data */
-    SPIy_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPIy);
-  }
-
-  /* Check the correctness of written dada */
-  TransferStatus1 = Buffercmp(SPIz_Buffer_Rx, SPIy_Buffer_Tx, BufferSize);
-  TransferStatus2 = Buffercmp(SPIy_Buffer_Rx, SPIz_Buffer_Tx, BufferSize);
-  /* TransferStatus1, TransferStatus2 = PASSED, if the transmitted and received data
-     are equal */
-  /* TransferStatus1, TransferStatus2 = FAILED, if the transmitted and received data
-     are different */
-
-  /* 2nd phase: SPIy Slave and SPIz Master */
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration(SPI_Mode_Slave , SPI_Mode_Master);
-  
-  /* SPIy Re-configuration ---------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPIy, &SPI_InitStructure);
-
-  /* SPIz Re-configuration ---------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_Init(SPIz, &SPI_InitStructure);
-
-  /* Reset TxIdx, RxIdx indexes and receive tables values */
-  TxIdx = 0;
-  RxIdx = 0;
-  for (k = 0; k < BufferSize; k++)  SPIz_Buffer_Rx[k] = 0;
-  for (k = 0; k < BufferSize; k++)  SPIy_Buffer_Rx[k] = 0;
-
-  /* Transfer procedure */
-  while (TxIdx < BufferSize)
-  {
-    /* Wait for SPIz Tx buffer empty */
-    while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_TXE) == RESET);
-    /* Send SPIy data */
-    SPI_I2S_SendData(SPIy, SPIy_Buffer_Tx[TxIdx]);
-    /* Send SPIz data */
-    SPI_I2S_SendData(SPIz, SPIz_Buffer_Tx[TxIdx++]);
-    /* Wait for SPIy data reception */
-    while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPIy received data */
-    SPIy_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPIy);
-    /* Wait for SPIz data reception */
-    while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPIz received data */
-    SPIz_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPIz);
-  }
-
-  /* Check the correctness of written dada */
-  TransferStatus3 = Buffercmp(SPIz_Buffer_Rx, SPIy_Buffer_Tx, BufferSize);
-  TransferStatus4 = Buffercmp(SPIy_Buffer_Rx, SPIz_Buffer_Tx, BufferSize);
-  /* TransferStatus3, TransferStatus4 = PASSED, if the transmitted and received data
-     are equal */
-  /* TransferStatus3, TransferStatus4 = FAILED, if the transmitted and received data
-     are different */
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK2 = HCLK/2 */
-  RCC_PCLK2Config(RCC_HCLK_Div2); 
-
-/* Enable peripheral clocks --------------------------------------------------*/
-#ifdef USE_STM3210C_EVAL
-  /* Enable GPIO clock for SPIy and SPIz */
-  RCC_APB2PeriphClockCmd(SPIy_GPIO_CLK | SPIz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable SPIy Periph clock */
-  RCC_APB1PeriphClockCmd(SPIy_CLK, ENABLE);
-                           
-#else
-  /* Enable SPIy clock and GPIO clock for SPIy and SPIz */
-  RCC_APB2PeriphClockCmd(SPIy_GPIO_CLK | SPIz_GPIO_CLK | SPIy_CLK, ENABLE);
-#endif
-  /* Enable SPIz Periph clock */
-  RCC_APB1PeriphClockCmd(SPIz_CLK, ENABLE);
-}
-
-/**
-  * @brief  Configures the different SPIy and SPIz GPIO ports.
-  * @param  SPIy_Mode: Specifies the SPIy operating mode. 
-  *            This parameter can be:
-  *              -  SPIy_Mode_Master
-  *              -  SPIy_Mode_Slave                 
-  * @param  SPIz_Mode: Specifies the SPIz operating mode. 
-  *            This parameter can be:
-  *              -  SPIz_Mode_Master
-  *              -  SPIz_Mode_Slave 
-  * @retval None
-  */
-void GPIO_Configuration(uint16_t SPIy_Mode, uint16_t SPIz_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable SPI3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
-#endif
-
-  /* Configure SPIy pins: SCK, MISO and MOSI ---------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = SPIy_PIN_SCK | SPIy_PIN_MOSI;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  if(SPIy_Mode == SPI_Mode_Master)
-  {
-    /* Configure SCK and MOSI pins as Alternate Function Push Pull */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  }
-  else
-  {
-    /* Configure SCK and MOSI pins as Input Floating */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  }
-  GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = SPIy_PIN_MISO;
-
-  if(SPIy_Mode == SPI_Mode_Master)
-  {
-    /* Configure MISO pin as Input Floating  */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  }
-  else
-  {
-    /* Configure MISO pin as Alternate Function Push Pull */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  }
-  GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure SPIz pins: SCK, MISO and MOSI ---------------------------------*/
-  GPIO_InitStructure.GPIO_Pin = SPIz_PIN_SCK | SPIz_PIN_MOSI;
-
-  if(SPIz_Mode == SPI_Mode_Slave)
-  {
-    /* Configure SCK and MOSI pins as Input Floating */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  }
-  else
-  { 
-    /* Configure SCK and MOSI pins as Alternate Function Push Pull */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  }
-  GPIO_Init(SPIz_GPIO, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = SPIz_PIN_MISO;
-  if(SPIz_Mode == SPI_Mode_Slave)
-  {
-    /* Configure MISO pin as Alternate Function Push Pull */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  }
-  else
-  { /* Configure MISO pin as Input Floating  */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  }
-  GPIO_Init(SPIz_GPIO, &GPIO_InitStructure);
-}
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt
deleted file mode 100644
index 5468227..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-/**
-  @page SPI_FullDuplex_SoftNSS SPI Full Duplex Software NSS example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/FullDuplex_SoftNSS/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI Full Duplex Software NSS example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to set a communication between SPIy and
-SPIz in full-duplex mode and performs a transfer from Master to Slave and then 
-Slave to Master in the same application with software NSS management.
-SPIy and SPIz can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics
-EVAL board you are using.
-
-Both SPIs are configured with 8bit data frame and a 9Mbit/s communication speed.
-(for Value line devices the speed is set at 6Mbit/s).
-In the first phase, the master SPIy starts the SPIy_Buffer_Tx transfer while the 
-slave SPIz transmit SPIz_Buffer_Tx. Once the transfer is completed a comparison 
-is done and TransferStatus1 and TransferStatus2 gives the data transfer status for
-each data transfer direction where it is PASSED if transmitted and received data 
-are the same otherwise it is FAILED.
-
-As the NSS pin is managed by software, this permit to SPIy to become slave and SPIz
-to become master without hardware modification.
-In the second step, the slave SPIy starts the SPIy_Buffer_Tx transfer while the 
-master SPIz transmit SPIz_Buffer_Tx. Once the transfer is completed a comparison 
-is done and TransferStatus3 and TransferStatus4 gives the data transfer status for
-each data transfer direction where it is PASSED if transmitted and received data 
-are the same otherwise it is FAILED.
-
-
-@par Directory contents 
-
-  - SPI/FullDuplex_SoftNSS/platform_config.h   Evaluation board specific configuration file
-  - SPI/FullDuplex_SoftNSS/stm32f10x_conf.h    Library Configuration file
-  - SPI/FullDuplex_SoftNSS/stm32f10x_it.c      Interrupt handlers
-  - SPI/FullDuplex_SoftNSS/stm32f10x_it.h      Interrupt handlers header file
-  - SPI/FullDuplex_SoftNSS/main.c              Main program
-  - SPI/FullDuplex_SoftNSS/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in SPI/FullDuplex_SoftNSS/platform_config.h file.  
-
-  - STM32100E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-    
-  - STM32100B-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-    
-  - STM3210C-EVAL Set-up 
-    - Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin	(PB.13)
-    - Connect SPI3 MISO pin (PC.11) to SPI2 MISO pin (PB.14)
-    - Connect SPI3 MOSI pin (PC.12) to SPI2 MOSI pin (PB.15)
-    @note In this case SPI3 pins are remapped by software.
-
-  - STM3210E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfer with SPI2 MISO pin PB14.
-
-  - STM3210B-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin	(PB.13)
-    - Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
deleted file mode 100644
index 45a1e9c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/FullDuplex_SoftNSS/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c
deleted file mode 100644
index 4649493..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/FullDuplex_SoftNSS/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_FullDuplex_SoftNSS
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h
deleted file mode 100644
index 50d395b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/FullDuplex_SoftNSS/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c
deleted file mode 100644
index e70492d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/FullDuplex_SoftNSS/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
deleted file mode 100644
index f2a0a05..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/SPI_FLASH/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-#include "stm32_eval_spi_flash.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_FLASH
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define  FLASH_WriteAddress     0x700000
-#define  FLASH_ReadAddress      FLASH_WriteAddress
-#define  FLASH_SectorToErase    FLASH_WriteAddress
-
-#if defined(USE_STM32100B_EVAL) || defined(USE_STM32100E_EVAL)
-  #define  sFLASH_ID       sFLASH_M25P128_ID
-#else
-  #define  sFLASH_ID       sFLASH_M25P64_ID
-#endif
-
-#define  BufferSize (countof(Tx_Buffer)-1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a) (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-uint8_t Tx_Buffer[] = "STM32F10x SPI Firmware Library Example: communication with an M25P SPI FLASH";
-uint8_t  Rx_Buffer[BufferSize];
-__IO uint8_t Index = 0x0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = PASSED;
-__IO uint32_t FlashID = 0;
-
-/* Private functions ---------------------------------------------------------*/
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Initialize Leds mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-
-  /* Initialize the SPI FLASH driver */
-  sFLASH_Init();
-
-  /* Get SPI Flash ID */
-  FlashID = sFLASH_ReadID();
-  
-  /* Check the SPI Flash ID */
-  if (FlashID == sFLASH_ID)
-  {
-    /* OK: Turn on LD1 */
-    STM_EVAL_LEDOn(LED1);
-
-    /* Perform a write in the Flash followed by a read of the written data */
-    /* Erase SPI FLASH Sector to write on */
-    sFLASH_EraseSector(FLASH_SectorToErase);
-
-    /* Write Tx_Buffer data to SPI FLASH memory */
-    sFLASH_WriteBuffer(Tx_Buffer, FLASH_WriteAddress, BufferSize);
-
-    /* Read data from SPI FLASH memory */
-    sFLASH_ReadBuffer(Rx_Buffer, FLASH_ReadAddress, BufferSize);
-
-    /* Check the correctness of written dada */
-    TransferStatus1 = Buffercmp(Tx_Buffer, Rx_Buffer, BufferSize);
-    /* TransferStatus1 = PASSED, if the transmitted and received data by SPI1
-       are the same */
-    /* TransferStatus1 = FAILED, if the transmitted and received data by SPI1
-       are different */
-
-    /* Perform an erase in the Flash followed by a read of the written data */
-    /* Erase SPI FLASH Sector to write on */
-    sFLASH_EraseSector(FLASH_SectorToErase);
-
-    /* Read data from SPI FLASH memory */
-    sFLASH_ReadBuffer(Rx_Buffer, FLASH_ReadAddress, BufferSize);
-
-    /* Check the correctness of erasing operation dada */
-    for (Index = 0; Index < BufferSize; Index++)
-    {
-      if (Rx_Buffer[Index] != 0xFF)
-      {
-        TransferStatus2 = FAILED;
-      }
-    }
-    /* TransferStatus2 = PASSED, if the specified sector part is erased */
-    /* TransferStatus2 = FAILED, if the specified sector part is not well erased */
-  }
-  else
-  {
-    /* Error: Turn on LD2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-  
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt
deleted file mode 100644
index 4c6c1da..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
-  @page SPI_FLASH SPI SPI_FLASH example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/SPI_FLASH/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI SPI_FLASH example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the SPI firmware library
-and an associate SPI FLASH driver to communicate with an M25P64 or M25P128 FLASH.
-
-The first step consist in reading the SPI Flash ID. A comparison between the ID 
-read from SPI flash and the expected one is done and LED1 is turned on in case
-of success otherwise LED2 is turned on.  
-
-Using this driver the program performs an erase of the sector to be accessed, a 
-write of a Tx_Buffer, defined in the main.c file, to the memory followed by a read
-of the written data. Then data read from the memory stored in the Rx_Buffer are
-compared with the expected values of the Tx_Buffer. The result of this comparison
-is stored in the "TransferStatus1" variable.
-
-A second erase of the same sector is done at the end, and a test is done to be
-sure that all the data written there are erased further to the sector erase. All
-the data location are read and checked with 0xFF value. The result of this test
-is stored in "TransferStatus2" variable which is FAILED in case of error.
-
-The SPI1 is configured as Master with an 8-bit data size. The SPI1 baudrate 
-is set to 18 Mbit/s (for Value line devices the baudrate is set to 12 Mbit/s).
-The FLASH_WriteAddress and the FLASH_ReadAddress where the program start the write 
-and the read operations are defined in the main.c file. 
-
-
-@par Directory contents 
-
-  - SPI/SPI_FLASH/stm32f10x_conf.h     Library Configuration file
-  - SPI/SPI_FLASH/stm32f10x_it.c       Interrupt handlers
-  - SPI/SPI_FLASH/stm32f10x_it.h       Header for stm32f10x_it.c
-  - SPI/SPI_FLASH/main.c               Main program
-  - SPI/SPI_FLASH/system_stm32f10x.c   STM32F10x system source file   
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL 
-    (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation
-    boards and can be easily tailored to any other supported device 
-    and development board.
-    This example can't be tested with STM3210C-EVAL (Connectivity Line)
-    evaluation board (no SPI FLASH available).
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file.
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
-    - M25P128 FLASH is already available on this board.
-@note
-  - The SPI FLASH example is only working on STM32100E-EVAL Rev B.
-        
-  - STM32100B-EVAL Set-up  
-    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
-    - M25P128 FLASH is already available on this board.
-    
-  - STM3210E-EVAL Set-up 
-    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
-    - M25P64 FLASH is already available on this board.
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfere with SPI2 MISO pin PB14.
-      
-  - STM3210B-EVAL Set-up  
-    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
-    - M25P64 FLASH is already available on this board.
-
-		  
-  - Other platform Set-up
-    - Use STM3210B-EVAL hardware configuration defines. 
-    - Connect LED1 and LED2 respectively to PD.07 and PD.13 pins
-    - Connect both SPI1 and SPI FLASH pins as following:
-      - Connect SPI1_NSS (PA.04) pin to SPI Flash chip select (pin1)
-      - Connect SPI1_SCLK (PA.05) pin to SPI Flash serial clock (pin6)
-      - Connect SPI1_MISO (PA.06) pin to SPI Flash serial data output (pin2)
-      - Connect SPI1_MOSI (PA.07) pin to SPI Flash serial data input (pin5)
-      - Connect SPI Flash Write Protect (pin3) to Vdd
-      - Connect SPI Flash Hold (pin7) to Vdd
-      - Connect SPI Flash Vcc (pin8) to Vdd
-      - Connect SPI Flash Vss (pin4) to Vss
-
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c
deleted file mode 100644
index 9914252..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/SPI_FLASH/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_FLASH
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h
deleted file mode 100644
index 7b857ba..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/SPI_FLASH/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c
deleted file mode 100644
index b8b6cd7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/SPI_FLASH/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt
deleted file mode 100644
index 09e717c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
-  @page SPI_Simplex_Interrupt SPI Simplex Interrupt example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/Simplex_Interrupt/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI Simplex Interrupt example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to set a communication between two
-SPIs in simplex mode and performs a data buffer transfer from SPI_MASTER to
-SPI_SLAVE using TxE interrupt for master and RxNE interrupt for slave.
-SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the
-STMicroelectronics EVAL board you are using.
-
-Both SPIs are configured with 8bit data frame and a 9Mbit/s communication speed
-(for Value line devices the communication speed is set to 3Mbit/s).
-The TxE interrupt is enabled for the master and the RxNE interrupt is enabled for
-the slave.
-
-Once both SPIs are enabled, first TxE interrupt is generated for the master
-and in its interrupt service routine the first data is sent from SPI_MASTER_Buffer_Tx. 
-Once this data is received by the slave the RxNE interrupt is generated and in
-the routine this data is stored in the SPI_SLAVE_Buffer_Rx.
-
-The same procedure is followed for the remaining SPI_MASTER_Buffer_Tx data.
-Once all data buffer are received by the slave the TxE interrupt is disabled.
-A comparison is done and TransferStatus variable gives the data transfer status
-where it is PASSED if transmitted and received data are the same otherwise it is FAILED.
-
-
-@par Directory contents 
-
-  - SPI/Simplex_Interrupt/platform_config.h    Evaluation board specific configuration file
-  - SPI/Simplex_Interrupt/stm32f10x_conf.h     Library Configuration file
-  - SPI/Simplex_Interrupt/stm32f10x_it.c       Interrupt handlers
-  - SPI/Simplex_Interrupt/stm32f10x_it.h       Header for stm32f10x_it.c
-  - SPI/Simplex_Interrupt/main.c               Main program
-  - SPI/Simplex_Interrupt/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in SPI/Simplex_Interrupt/platform_config.h file.  
-
-  - STM32100E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
-    
-  - STM32100B-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
-
-  - STM3210C-EVAL Set-up 
-    - Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin (PB.13)
-    - Connect SPI3 MOSI pin (PC.12) to SPI2 MISO pin (PB.14)
-    @note In this case SPI3 pins are remapped by software.
-
-  - STM3210E-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfer with SPI2 MISO pin PB14.
-
-  - STM3210B-EVAL Set-up 
-    - Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
-    - Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 75867c9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/Simplex_Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
deleted file mode 100644
index 8960329..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/Simplex_Interrupt/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_Simplex_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BufferSize  32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint8_t TxIdx, RxIdx;
-extern uint8_t SPI_MASTER_Buffer_Tx[BufferSize], SPI_SLAVE_Buffer_Rx[BufferSize];
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles SPI1 or SPI3 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-#ifndef  USE_STM3210C_EVAL
- void SPI1_IRQHandler(void)
-#else
- void SPI3_IRQHandler(void)
-#endif
-{
-  if (SPI_I2S_GetITStatus(SPI_MASTER, SPI_I2S_IT_TXE) != RESET)
-  {
-    /* Send SPI_MASTER data */
-    SPI_I2S_SendData(SPI_MASTER, SPI_MASTER_Buffer_Tx[TxIdx++]);
-
-    /* Disable SPI_MASTER TXE interrupt */
-    if (TxIdx == BufferSize)
-    {
-      SPI_I2S_ITConfig(SPI_MASTER, SPI_I2S_IT_TXE, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  This function handles SPI2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void SPI2_IRQHandler(void)
-{
-  /* Store SPI_SLAVE received data */
-  SPI_SLAVE_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI_SLAVE);
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
deleted file mode 100644
index 12f829a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/Simplex_Interrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void SPI1_IRQHandler(void);
-void SPI2_IRQHandler(void);
-void SPI3_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c
deleted file mode 100644
index 73a619d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/Simplex_Interrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c
deleted file mode 100644
index 687ed68..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SysTick_TimeBase
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __IO uint32_t TimingDelay;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize Leds mounted on STM3210X-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Turn on LED1 and LED3 */
-  STM_EVAL_LEDOn(LED1);
-  STM_EVAL_LEDOn(LED3);
-
-  /* Setup SysTick Timer for 1 msec interrupts.
-     ------------------------------------------
-    1. The SysTick_Config() function is a CMSIS function which configure:
-       - The SysTick Reload register with value passed as function parameter.
-       - Configure the SysTick IRQ priority to the lowest value (0x0F).
-       - Reset the SysTick Counter register.
-       - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
-       - Enable the SysTick Interrupt.
-       - Start the SysTick Counter.
-    
-    2. You can change the SysTick Clock source to be HCLK_Div8 by calling the
-       SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8) just after the
-       SysTick_Config() function call. The SysTick_CLKSourceConfig() is defined
-       inside the misc.c file.
-
-    3. You can change the SysTick IRQ priority by calling the
-       NVIC_SetPriority(SysTick_IRQn,...) just after the SysTick_Config() function 
-       call. The NVIC_SetPriority() is defined inside the core_cm3.h file.
-
-    4. To adjust the SysTick time base, use the following formula:
-                            
-         Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-    
-       - Reload Value is the parameter to be passed for SysTick_Config() function
-       - Reload Value should not exceed 0xFFFFFF
-   */
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  while (1)
-  {
-    /* Toggle LED2 and LED4 */
-    STM_EVAL_LEDToggle(LED2);
-    STM_EVAL_LEDToggle(LED4);
-
-    /* Insert 50 ms delay */
-    Delay(50);
-
-    /* Toggle LED1 and LED3 */
-    STM_EVAL_LEDToggle(LED1);
-    STM_EVAL_LEDToggle(LED3);
-
-    /* Insert 100 ms delay */
-    Delay(100);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{ 
-  TimingDelay = nTime;
-
-  while(TimingDelay != 0);
-}
-
-/**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
-  */
-void TimingDelay_Decrement(void)
-{
-  if (TimingDelay != 0x00)
-  { 
-    TimingDelay--;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.h
deleted file mode 100644
index d49630e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/main.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Header for main.c module
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void TimingDelay_Decrement(void);
-
-#endif /* __MAIN_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h
deleted file mode 100644
index f032f0e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c
deleted file mode 100644
index 7100fdc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SysTick_TimeBase
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  TimingDelay_Decrement();
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h
deleted file mode 100644
index 7f3aa14..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
deleted file mode 100644
index c6bc875..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
deleted file mode 100644
index c3fa83c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/6Steps/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_6Steps
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
-uint16_t CCR1_Val = 32767;
-uint16_t CCR2_Val = 24575;
-uint16_t CCR3_Val = 16383;
-uint16_t CCR4_Val = 8191;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void SysTick_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-           
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* SysTick Configuration */
-  SysTick_Configuration();
-
-  /*-----------------------------------------------------------------------------
-  The STM32F10x TIM1 peripheral offers the possibility to program in advance the 
-  configuration for the next TIM1 outputs behaviour (step) and change the configuration
-  of all the channels at the same time. This operation is possible when the COM 
-  (commutation) event is used.
-  The COM event can be generated by software by setting the COM bit in the TIM1_EGR
-  register or by hardware (on TRC rising edge).
-  In this example, a software COM event is generated each 100 ms: using the Systick 
-  interrupt.
-  The TIM1 is configured in Timing Mode, each time a COM event occurs, 
-  a new TIM1 configuration will be set in advance.
-  The following Table  describes the TIM1 Channels states:
-              -----------------------------------------------
-             | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
-   ----------------------------------------------------------
-  |Channel1  |   1   |   0   |   0   |   0   |   0   |   1   |
-   ----------------------------------------------------------
-  |Channel1N |   0   |   0   |   1   |   1   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel2  |   0   |   0   |   0   |   1   |   1   |   0   |
-   ----------------------------------------------------------
-  |Channel2N |   1   |   1   |   0   |   0   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel3  |   0   |   1   |   1   |   0   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel3N |   0   |   0   |   0   |   0   |   1   |   1   |
-   ----------------------------------------------------------
-  -----------------------------------------------------------------------------*/
-
-  /* Time Base configuration */
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseStructure.TIM_Period = 4095;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
-
-  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
-
-  /* Channel 1, 2,3 and 4 Configuration in PWM mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 2047;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
-  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
-  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set;
-
-  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = 1023;
-  TIM_OC2Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = 511;
-  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
-
-  /* Automatic Output enable, Break, dead time and lock configuration*/
-  TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
-  TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
-  TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
-  TIM_BDTRInitStructure.TIM_DeadTime = 1;
-  TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
-  TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
-  TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
-
-  TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
-
-  TIM_CCPreloadControl(TIM1, ENABLE);
-
-  TIM_ITConfig(TIM1, TIM_IT_COM, ENABLE);
-
-  /* TIM1 counter enable */
-  TIM_Cmd(TIM1, ENABLE);
-
-  /* Main Output Enable */
-  TIM_CtrlPWMOutputs(TIM1, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
-                         RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the TIM1 Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|
-                                GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* GPIOE Configuration: BKIN pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* TIM1 Full remapping pins */
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); 
-
-#else
-  /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: BKIN pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);  
-#endif
-}
-
-/**
-  * @brief  Configures the SysTick.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Configuration(void)
-{
-  /* Setup SysTick Timer for 100 msec interrupts  */
-  if (SysTick_Config((SystemCoreClock) / 10))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-   NVIC_SetPriority(SysTick_IRQn, 0x0);
-}
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the TIM1 Interrupt */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_TIM17_IRQn;
-#else
-  NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_IRQn;
-#endif
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure); 
-
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt
deleted file mode 100644
index 2fc3977..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
-  @page TIM_6Steps TIM 6 Steps example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/6Steps/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM 6 Steps example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM1 peripheral to generate 6 Steps.
-The STM32F10x TIM1 peripheral offers the possibility to program in advance the 
-configuration for the next TIM1 outputs behaviour (step) and change the configuration
-of all the channels at the same time. This operation is possible when the COM 
-(commutation) event is used.
-The COM event can be generated by software by setting the COM bit in the TIM1_EGR
-register or by hardware (on TRC rising edge).
-In this example, a software COM event is generated each 100 ms: using the SysTick 
-interrupt.
-The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1
-configuration will be set in advance.
-
-The break Polarity is used at High level.
-
-The following Table describes the TIM1 Channels states:
-@verbatim
-              -----------------------------------------------
-             | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
-   ----------------------------------------------------------
-  |Channel1  |   1   |   0   |   0   |   0   |   0   |   1   |
-   ----------------------------------------------------------
-  |Channel1N |   0   |   0   |   1   |   1   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel2  |   0   |   0   |   0   |   1   |   1   |   0   |
-   ----------------------------------------------------------
-  |Channel2N |   1   |   1   |   0   |   0   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel3  |   0   |   1   |   1   |   0   |   0   |   0   |
-   ----------------------------------------------------------
-  |Channel3N |   0   |   0   |   0   |   0   |   1   |   1   |
-   ----------------------------------------------------------
- @endverbatim
-
-@par Directory contents 
-
-  - TIM/6Steps/stm32f10x_conf.h    Library Configuration file
-  - TIM/6Steps/stm32f10x_it.c      Interrupt handlers
-  - TIM/6Steps/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/6Steps/main.c              Main program
-  - TIM/6Steps/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    
-
-  - STM3210C-EVAL Set-up 
-    - Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
-      - TIM1_CH3  pin (PE.13)
-      - TIM1_CH1N pin (PE.08)  
-      - TIM1_CH2  pin (PE.11)  
-      - TIM1_CH3N pin (PE.12)
-      - TIM1_CH1  pin (PE.09)  
-      - TIM1_CH2N pin (PE.10)  
-    - Connect the TIM1 break pin TIM1_BKIN pin (PE.15) to the GND. To generate a 
-      break event, switch this pin level from 0V to 3.3V.     
-
-  - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up 
-    - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
-      - TIM1_CH3  pin (PA.10)
-      - TIM1_CH1N pin (PB.13)  
-      - TIM1_CH2  pin (PA.09)  
-      - TIM1_CH3N pin (PB.15)
-      - TIM1_CH1  pin (PA.08)  
-      - TIM1_CH2N pin (PB.14)    
-    - Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a 
-      break event, switch this pin level from 0V to 3.3V. 
-  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
deleted file mode 100644
index f90cc9f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/6Steps/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_6Steps
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t step = 1;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  /* Generate TIM1 COM event by software */
-  TIM_GenerateEvent(TIM1, TIM_EventSource_COM);
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles TIM1 Trigger and commutation interrupts
-  *   requests.
-  * @param  None
-  * @retval None
-  */
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-void TIM1_TRG_COM_TIM17_IRQHandler(void)
-#else
-void TIM1_TRG_COM_IRQHandler(void)
-#endif	
-{
-   /* Clear TIM1 COM pending bit */
-   TIM_ClearITPendingBit(TIM1, TIM_IT_COM);
-
-  if (step == 1)
-  {
-    /* Next step: Step 2 Configuration ---------------------------- */
-    /*  Channel3 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
-
-    /*  Channel1 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
-
-    /*  Channel2 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1 );
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
-    step++;
-  }
-  else if (step == 2)
-  {
-    /* Next step: Step 3 Configuration ---------------------------- */
-    /*  Channel2 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
-    
-    /*  Channel3 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
-     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
-
-    /*  Channel1 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
-    step++;
-  }
-  else if (step == 3)
-  {
-    /* Next step: Step 4 Configuration ---------------------------- */
-    /*  Channel3 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
-
-    /*  Channel2 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
-
-    /*  Channel1 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
-    step++;
-  }
-  else if (step == 4)
-  {
-    /* Next step: Step 5 Configuration ---------------------------- */
-    /*  Channel3 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
-
-    /*  Channel1 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
-
-    /*  Channel2 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
-    step++;
-  }
-  else if (step == 5)
-  {
-    /* Next step: Step 6 Configuration ---------------------------- */
-    /*  Channel3 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
-
-    /*  Channel1 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
-
-    /*  Channel2 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
-    step++;
-  }
-  else
-  {
-    /* Next step: Step 1 Configuration ---------------------------- */
-    /*  Channel1 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
-
-    /*  Channel3 configuration */
-    TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
-    TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
-
-    /*  Channel2 configuration */
-    TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
-    TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
-    step = 1;
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
deleted file mode 100644
index 12ed6f1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/6Steps/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
-void TIM1_TRG_COM_TIM17_IRQHandler(void);
-#else
-void TIM1_TRG_COM_IRQHandler(void);
-#endif					 
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c
deleted file mode 100644
index be27213..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/6Steps/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
deleted file mode 100644
index 7f23815..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/7PWM_Output/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_7PWM_Output
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-uint16_t TimerPeriod = 0;
-uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0, Channel4Pulse = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* TIM1 Configuration ---------------------------------------------------
-   Generate 7 PWM signals with 4 different duty cycles:
-   TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
-   SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-   and Connectivity line devices and to 24 MHz for Low-Density Value line and
-   Medium-Density Value line devices
-   
-   The objective is to generate 7 PWM signal at 17.57 KHz:
-     - TIM1_Period = (SystemCoreClock / 17570) - 1
-   The channel 1 and channel 1N duty cycle is set to 50%
-   The channel 2 and channel 2N duty cycle is set to 37.5%
-   The channel 3 and channel 3N duty cycle is set to 25%
-   The channel 4 duty cycle is set to 12.5%
-   The Timer pulse is calculated as follows:
-     - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
-  ----------------------------------------------------------------------- */
-  /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */
-  TimerPeriod = (SystemCoreClock / 17570 ) - 1;
-  /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */
-  Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
-  /* Compute CCR2 value to generate a duty cycle at 37.5%  for channel 2 and 2N */
-  Channel2Pulse = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
-  /* Compute CCR3 value to generate a duty cycle at 25%  for channel 3 and 3N */
-  Channel3Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
-  /* Compute CCR4 value to generate a duty cycle at 12.5%  for channel 4 */
-  Channel4Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod- 1)) / 1000);
-
-  /* Time Base configuration */
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
-
-  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
-
-  /* Channel 1, 2,3 and 4 Configuration in PWM mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
-  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
-  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
-  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
-
-  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = Channel2Pulse;
-  TIM_OC2Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = Channel3Pulse;
-  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = Channel4Pulse;
-  TIM_OC4Init(TIM1, &TIM_OCInitStructure);
-
-  /* TIM1 counter enable */
-  TIM_Cmd(TIM1, ENABLE);
-
-  /* TIM1 Main Output Enable */
-  TIM_CtrlPWMOutputs(TIM1, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
-                         RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the TIM1 Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N and 4 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|GPIO_Pin_14|
-                                GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* TIM1 Full remapping pins */
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); 
-
-#else
-  /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-#endif
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h
deleted file mode 100644
index 9827ef8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/7PWM_Output/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
deleted file mode 100644
index bf0b15b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/7PWM_Output/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_7PWM_Output
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h
deleted file mode 100644
index 4f1bba1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/7PWM_Output/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c
deleted file mode 100644
index 19c5e51..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/7PWM_Output/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c
deleted file mode 100644
index 172f3ee..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Cascade_Synchro/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Cascade_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* Timers synchronisation in cascade mode ----------------------------
-     1/TIM2 is configured as Master Timer:
-     - PWM Mode is used
-     - The TIM2 Update event is used as Trigger Output  
-
-     2/TIM3 is slave for TIM2 and Master for TIM4,
-     - PWM Mode is used
-     - The ITR1(TIM2) is used as input trigger 
-     - Gated mode is used, so start and stop of slave counter
-      are controlled by the Master trigger output signal(TIM2 update event).
-      - The TIM3 Update event is used as Trigger Output. 
-
-      3/TIM4 is slave for TIM3,
-     - PWM Mode is used
-     - The ITR2(TIM3) is used as input trigger
-     - Gated mode is used, so start and stop of slave counter
-      are controlled by the Master trigger output signal(TIM3 update event).
-
-     * For Low-density, Medium-density, High-density and Connectivity line devices:
-       The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
-
-       The Master Timer TIM2 is running at TIM2 frequency :
-       TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz 
-       and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
-
-       The TIM3 is running:
-       - At (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle
-         equal to TIM3_CCR1/(TIM3_ARR + 1) = 25%
-
-        The TIM4 is running:
-      - At (TIM3 frequency)/ (TIM4 period + 1) = 17.578 KHz and a duty cycle
-        equal to TIM4_CCR1/(TIM4_ARR + 1) = 25%
-
-     * For Low-Density Value line,Medium-Density and High-Density Value line devices:
-       The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
-       So TIM2 frequency = 93.750 KHz,
-       TIM3 is running at 23.437 KHz,
-       and TIM4 is running at 5.85 KHz
-  -------------------------------------------------------------------- */
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 255;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 3;
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 3;
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  /* Master Configuration in PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 64;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection */
-  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
-
-  /* Slaves Configuration: PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 1;
-
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM3 */
-  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection: TIM3 */
-  TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update);
-
-  /* Slave Mode selection: TIM4 */
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2);
-  
-  /* TIM enable counter */
-  TIM_Cmd(TIM3, ENABLE);
-  TIM_Cmd(TIM2, ENABLE);
-  TIM_Cmd(TIM4, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* TIM2, TIM3 and TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
-                         RCC_APB1Periph_TIM4, ENABLE);
-
-  /* GPIOA, GPIOB, GPIOC and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIOD Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /*GPIOB Configuration:  PC6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 ;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
-#else
-/* GPIOA Configuration: PA6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-#endif
-  /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt
deleted file mode 100644
index c842531..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
-  @page TIM_Cascade_Synchro TIM Cascade Synchro example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/Cascade_Synchro/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM Cascade Synchro example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to synchronize TIM peripherals in cascade mode.
-In this example three timers are used:
-
-Timers synchronisation in cascade mode:
-
-1/TIM2 is configured as Master Timer:
- - PWM Mode is used
- - The TIM2 Update event is used as Trigger Output  
-
-2/TIM3 is slave for TIM2 and Master for TIM4,
- - PWM Mode is used
- - The ITR1(TIM2) is used as input trigger 
- - Gated mode is used, so start and stop of slave counter
-	  are controlled by the Master trigger output signal(TIM2 update event).
- - The TIM3 Update event is used as Trigger Output. 
-
-3/TIM4 is slave for TIM3,
- - PWM Mode is used
- - The ITR2(TIM3) is used as input trigger
- - Gated mode is used, so start and stop of slave counter  are controlled by the
-   Master trigger output signal(TIM3 update event).
-
-o For Low-density, Medium-density, High-density and Connectivity line devices:
-  The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
-
-  The Master Timer TIM2 is running at TIM2 frequency :
-  TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz 
-  and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
-
-  The TIM3 is running at:
-  (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle equal 
-  to TIM3_CCR1/(TIM3_ARR + 1) = 25%
-
-  The TIM4 is running at:
-  (TIM3 frequency)/ (TIM4 period + 1) = 17.578 Hz and a duty cycle equal 
-  to TIM4_CCR1/(TIM4_ARR + 1) = 25%  
-
-o For Low-Density Value line, Medium-Density and High-Density Value line devices:
-  The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
-  So TIM2 frequency = 93.750 KHz,
-  TIM3 is running at 23.437 KHz,
-  and TIM4 is running at 5.85 KHz
-
-@par Directory contents 
-
-  - TIM/Cascade_Synchro/stm32f10x_conf.h    Library Configuration file
-  - TIM/Cascade_Synchro/stm32f10x_it.c      Interrupt handlers
-  - TIM/Cascade_Synchro/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/Cascade_Synchro/main.c              Main program
-  - TIM/Cascade_Synchro/system_stm32f10x.c  STM32F10x system source file
-   
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM3210C-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:
-        - TIM2 CH1 (PA.00) 
-        - TIM3 CH1 (PC.06) Remapped pin
-        - TIM4 CH1 (PB.06) 
-
-  - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:
-        - TIM2 CH1 (PA.00) 
-        - TIM3 CH1 (PA.06)
-        - TIM4 CH1 (PB.06)    
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h
deleted file mode 100644
index e42fe40..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Cascade_Synchro/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c
deleted file mode 100644
index 0e0b5bb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Cascade_Synchro/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Cascade_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h
deleted file mode 100644
index ea41bc8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Cascade_Synchro/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c
deleted file mode 100644
index 4a408b6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Cascade_Synchro/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
deleted file mode 100644
index 8095899..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_ComplementarySignals
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
-uint16_t TimerPeriod = 0;
-uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* -----------------------------------------------------------------------
-  TIM1 Configuration to:
-
-  1/ Generate 3 complementary PWM signals with 3 different duty cycles:
-    TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the 
-    TIM1 counter clock used is SystemCoreClock.
-    * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-    and Connectivity line devices. For Low-Density Value line and Medium-Density 
-    Value line devices, SystemCoreClock is set to 24 MHz.
-
-    The objective is to generate PWM signal at 17.57 KHz:
-    - TIM1_Period = (SystemCoreClock / 17570) - 1
-
-    The Three Duty cycles are computed as the following description: 
-
-    The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
-    The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
-    The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
-    The Timer pulse is calculated as follows:
-      - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
-
-  2/ Insert a dead time equal to 11/SystemCoreClock ns
-  3/ Configure the break feature, active at High level, and using the automatic 
-     output enable feature
-  4/ Use the Locking parameters level1. 
-  ----------------------------------------------------------------------- */
-
-  /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
-  TimerPeriod = (SystemCoreClock / 17570) - 1;
-  /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 */
-  Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
-  /* Compute CCR2 value to generate a duty cycle at 25%  for channel 2 */
-  Channel2Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
-  /* Compute CCR3 value to generate a duty cycle at 12.5%  for channel 3 */
-  Channel3Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod - 1)) / 1000);
-
-  /* Time Base configuration */
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
-
-  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
-
-  /* Channel 1, 2 and 3 Configuration in PWM mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
-  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
-  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
-  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
-
-  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = Channel2Pulse;
-  TIM_OC2Init(TIM1, &TIM_OCInitStructure);
-
-  TIM_OCInitStructure.TIM_Pulse = Channel3Pulse;
-  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
-
-  /* Automatic Output enable, Break, dead time and lock configuration*/
-  TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
-  TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
-  TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
-  TIM_BDTRInitStructure.TIM_DeadTime = 11;
-  TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
-  TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
-  TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
-
-  TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
-
-  /* TIM1 counter enable */
-  TIM_Cmd(TIM1, ENABLE);
-
-  /* Main Output Enable */
-  TIM_CtrlPWMOutputs(TIM1, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
-                         RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the TIM1 Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|
-                                GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* GPIOE Configuration: BKIN pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* TIM1 Full remapping pins */
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); 
-
-#else
-  /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: BKIN pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);  
-#endif
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt
deleted file mode 100644
index 4174001..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  @page TIM_ComplementarySignals TIM Complementary Signals example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/ComplementarySignals/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM Complementary Signals example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM1 peripheral to generate three 
-complementary TIM1 signals, to insert a defined dead time value, to use the break 
-feature and to lock the desired parameters.
-
-TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the 
-TIM1 counter clock used is SystemCoreClock.
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices. For Low-Density Value line, Medium-Density and
-High-Density Value line devices, SystemCoreClock is set to 24 MHz.
-
-The objective is to generate PWM signal at 17.57 KHz:
-  - TIM1_Period = (SystemCoreClock / 17570) - 1
-
-The Three Duty cycles are computed as the following description: 
-The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
-The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
-The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
-The Timer pulse is calculated as follows:
-  - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
-
-A dead time equal to 11/SystemCoreClock is inserted between the different 
-complementary signals, and the Lock level 1 is selected.
-The break Polarity is used at High level.
-
-The TIM1 waveform can be displayed using an oscilloscope.
-
-@par Directory contents 
-
-  - TIM/ComplementarySignals/stm32f10x_conf.h    Library Configuration file
-  - TIM/ComplementarySignals/stm32f10x_it.c      Interrupt handlers
-  - TIM/ComplementarySignals/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/ComplementarySignals/main.c              Main program
-  - TIM/ComplementarySignals/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    
-
-  - STM3210C-EVAL Set-up 
-    - Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
-      - TIM1_CH1  pin (PE.09)
-      - TIM1_CH1N pin (PE.08)  
-      - TIM1_CH2  pin (PE.11)  
-      - TIM1_CH1N pin (PE.10)
-      - TIM1_CH3  pin (PE.13)  
-      - TIM1_CH3N pin (PE.12)  
-    - Connect the TIM1 break pin TIM1_BKIN pin (PE.15) to the GND. To generate a 
-      break event, switch this pin level from 0V to 3.3V. 
-
-  - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up 
-    - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
-      - TIM1_CH1  pin (PA.08)  
-      - TIM1_CH1N pin (PB.13)  
-      - TIM1_CH2  pin (PA.09)  
-      - TIM1_CH2N pin (PB.14)  
-      - TIM1_CH3  pin (PA.10)  
-      - TIM1_CH3N pin (PB.15)
-
-    - Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a 
-      break event, switch this pin level from 0V to 3.3V.  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c
deleted file mode 100644
index 3725d4d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *         This file provides template for all exceptions handler and
-  *         peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_ComplementarySignals
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h
deleted file mode 100644
index b4e5a70..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c
deleted file mode 100644
index 4ebbc9b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt
deleted file mode 100644
index 436b3fb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
-  @page TIM_DMA TIM DMA example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/DMA/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM DMA example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use DMA with TIM1 Update request
-to transfer Data from memory to TIM1 Capture Compare Register3.
-
-TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices. For Low-Density Value line, Medium-Density and
-High-Density Value line devices, SystemCoreClock is set to 24 MHz.
-
-The objective is to configure TIM1 channel 3 to generate complementary PWM
-signal with a frequency equal to 17.57 KHz:
-   - TIM1_Period = (SystemCoreClock / 17570) - 1
-and a variable duty cycle that is changed by the DMA after a specific number of
-Update DMA request.
-
-The number of this repetitive requests is defined by the TIM1 Repetion counter,
-each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new 
-value defined by the SRC_Buffer.
-
-
-@par Directory contents 
-
-  - TIM/DMA/stm32f10x_conf.h    Library Configuration file
-  - TIM/DMA/stm32f10x_it.c      Interrupt handlers
-  - TIM/DMA/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/DMA/main.c              Main program 
-  - TIM/DMA/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:  
-        - TIM1 CH3  (PA.10)
-        - TIM1 CH3N (PB.15)  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h
deleted file mode 100644
index 84b2d00..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMA/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
deleted file mode 100644
index 7fca938..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMA/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_DMA
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h
deleted file mode 100644
index e5284ca..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMA/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c
deleted file mode 100644
index ed65f3b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMA/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h
deleted file mode 100644
index a1b5c9d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMABurst/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
deleted file mode 100644
index 13e96b4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ExtTrigger_Synchro/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_ExtTrigger_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_ICInitTypeDef  TIM_ICInitStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Timers synchronisation in cascade mode with an external trigger -----
-    1/TIM1 is configured as Master Timer:
-     - Toggle Mode is used
-     - The TIM1 Enable event is used as Trigger Output 
-
-    2/TIM1 is configured as Slave Timer for an external Trigger connected
-     to TIM1 TI2 pin (TIM1 CH2 configured as input pin):
-     - The TIM1 TI2FP2 is used as Trigger Input
-     - Rising edge is used to start and stop the TIM1: Gated Mode.
-
-    3/TIM3 is slave for TIM1 and Master for TIM4,
-     - Toggle Mode is used
-     - The ITR1(TIM1) is used as input trigger 
-     - Gated mode is used, so start and stop of slave counter
-       are controlled by the Master trigger output signal(TIM1 enable event).
-     - The TIM3 enable event is used as Trigger Output. 
-
-    4/TIM4 is slave for TIM3,
-     - Toggle Mode is used
-     - The ITR2(TIM3) is used as input trigger
-     - Gated mode is used, so start and stop of slave counter
-       are controlled by the Master trigger output signal(TIM3 enable event).
-
-    * For Low-density, Medium-density, High-density and Connectivity line devices:
-      The TIMxCLK is fixed to 72 MHZ, the Prescaler is equal to 2 so the TIMx clock 
-      counter is equal to 24 MHz.
-      The Three Timers are running at: 
-      TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz.
-
-    * For Low-Density Value line and Medium-Density Value line devices:
-      The TIMxCLK is fixed to 24 MHz, the Prescaler is equal to 2 so the TIMx clock 
-      counter is equal to 8 MHz.
-      TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 54 KHz.
-
-    The starts and stops of the TIM1 counters are controlled by the 
-    external trigger.
-    The TIM3 starts and stops are controlled by the TIM1, and the TIM4 
-    starts and stops are controlled by the TIM3.  
-  -------------------------------------------------------------------- */
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 73;
-  TIM_TimeBaseStructure.TIM_Prescaler = 2;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 73;
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 73;
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  /* Master Configuration in Toggle Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 64;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
-
-  /* TIM1 Input Capture Configuration */
-  TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
-  TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
-  TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
-  TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
-  TIM_ICInitStructure.TIM_ICFilter = 0;
-
-  TIM_ICInit(TIM1, &TIM_ICInitStructure);
-
-  /* TIM1 Input trigger configuration: External Trigger connected to TI2 */
-  TIM_SelectInputTrigger(TIM1, TIM_TS_TI2FP2);
-  TIM_SelectSlaveMode(TIM1, TIM_SlaveMode_Gated);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection: TIM1 */
-  TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Enable);
-
-  /* Slaves Configuration: Toggle Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM3 */
-  TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0);
-  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection: TIM3 */
-  TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Enable);
-
-  /* Slave Mode selection: TIM4 */
-  TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2);
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
-  
-  /* TIM1 Main Output Enable */
-  TIM_CtrlPWMOutputs(TIM1, ENABLE);
-
-  /* TIM enable counter */
-  TIM_Cmd(TIM1, ENABLE);
-  TIM_Cmd(TIM3, ENABLE);
-  TIM_Cmd(TIM4, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* TIM1, TIM3 and TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 |
-                         RCC_APB1Periph_TIM4, ENABLE);
-
-  /* TIM1, GPIOA, GPIOE, GPIOC and GPIOB clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIO Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-#ifdef STM32F10X_CL
-  /* GPIOE Configuration: Channel 1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-   /* GPIOE Configuration: Channel 2 as Input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /* TIM1 Full remapping pins */
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE); 
-
- /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
-  /* GPIOB Configuration: PB.06(TIM4 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-#else
-  /* GPIOA Configuration: PA.08(TIM1 CH1) and PA.06(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: PB.06(TIM4 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* GPIOA Configuration: PA.09(TIM1 CH2) */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-#endif
-
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h
deleted file mode 100644
index 2481540..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ExtTrigger_Synchro/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c
deleted file mode 100644
index a0540f0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ExtTrigger_Synchro/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *        This file provides template for all exceptions handler and 
-  *        peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_ExtTrigger_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void TPPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/readme.txt
deleted file mode 100644
index 7e3f72b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/readme.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
-  @page TIM_Input_Capture TIM Input Capture example 
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/InputCapture/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM Input Capture example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to use the TIM peripheral to measure the frequency of an 
-external signal.
-
-The TIMxCLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the 
-TIM3 counter clock is SystemCoreClock (Hz).
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices. For Low-Density Value line and Medium-Density 
-Value line devices, SystemCoreClock is set to 24 MHz.
-
-TIM3 is configured in Input Capture Mode: the external signal is connected to 
-TIM3 Channel2 used as input pin.
-To measure the frequency we use the TIM3 CC2 interrupt request,
-so In the TIM3_IRQHandler routine, the frequency of the external signal is computed. 
-The "TIM3Freq" variable contains the external signal frequency:
-TIM3Freq = TIM3 counter clock / Capture in Hz,
-where the Capture is the difference between two consecutive TIM3 captures. 
-
-For Low-density, Medium-density, High-density and Connectivity line devices, 
-the minimum frequency value to measure is 1100 Hz. 
-For Low-Density Value line, Medium-Density and High-Density Value line devices, 
-the minimum frequency value to measure is 366 Hz.
-
-@par Directory contents 
-
-  - TIM/InputCapture/stm32f10x_conf.h    Library Configuration file
-  - TIM/InputCapture/stm32f10x_it.c      Interrupt handlers
-  - TIM/InputCapture/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/InputCapture/main.c              Main program 
-  - TIM/InputCapture/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the external signal to measure to the TIM3 CH2 pin (PA.07).   
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h
deleted file mode 100644
index a1620b0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/InputCapture/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
deleted file mode 100644
index 61a3258..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/InputCapture/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Input_Capture
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint16_t IC3ReadValue1 = 0, IC3ReadValue2 = 0;
-__IO uint16_t CaptureNumber = 0;
-__IO uint32_t Capture = 0;
-__IO uint32_t TIM3Freq = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-/**
-  * @brief  This function handles TIM3 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM3_IRQHandler(void)
-{ 
-  if(TIM_GetITStatus(TIM3, TIM_IT_CC2) == SET) 
-  {
-    /* Clear TIM3 Capture compare interrupt pending bit */
-    TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
-    if(CaptureNumber == 0)
-    {
-      /* Get the Input Capture value */
-      IC3ReadValue1 = TIM_GetCapture2(TIM3);
-      CaptureNumber = 1;
-    }
-    else if(CaptureNumber == 1)
-    {
-      /* Get the Input Capture value */
-      IC3ReadValue2 = TIM_GetCapture2(TIM3); 
-      
-      /* Capture computation */
-      if (IC3ReadValue2 > IC3ReadValue1)
-      {
-        Capture = (IC3ReadValue2 - IC3ReadValue1); 
-      }
-      else
-      {
-        Capture = ((0xFFFF - IC3ReadValue1) + IC3ReadValue2); 
-      }
-      /* Frequency computation */ 
-      TIM3Freq = (uint32_t) SystemCoreClock / Capture;
-      CaptureNumber = 0;
-    }
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h
deleted file mode 100644
index 8ad4cc3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/InputCapture/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void TIM3_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c
deleted file mode 100644
index 4b41133..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/InputCapture/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
deleted file mode 100644
index 8691aa2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCActive/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OCActive
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-uint16_t CCR1_Val = 1000;
-uint16_t CCR2_Val = 500;
-uint16_t CCR3_Val = 250;
-uint16_t CCR4_Val = 125;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
- /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* ---------------------------------------------------------------
-    TIM3 Configuration: 
-    TIM3CLK = SystemCoreClock / 2,
-    The objective is to get TIM3 counter clock at 1 KHz:
-     - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
-    And generate 4 signals with 4 different delays:
-    TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms
-    TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms
-    TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms
-    TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms
-
-  * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-    and Connectivity line devices and to 24 MHz for Low-Density Value line and
-    Medium-Density Value line devices
-  --------------------------------------------------------------- */
-  /*Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 2000) - 1;
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 65535;
-  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  /* Output Compare Active Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Active;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel2 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
-
-  TIM_OC2Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel3 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
-
-  TIM_OC3Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel4 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
-
-  TIM_OC4Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable);
-
-  TIM_ARRPreloadConfig(TIM3, ENABLE);
-
-#ifdef STM32F10X_CL
-  /* Set PD.07 pin */
-  GPIO_SetBits(GPIOD, GPIO_Pin_7);
-#else
-  /* Set PC.06 pin */
-  GPIO_SetBits(GPIOC, GPIO_Pin_6);
-#endif
-
-  /* TIM3 enable counter */
-  TIM_Cmd(TIM3, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK1 = HCLK/4 */
-  RCC_PCLK1Config(RCC_HCLK_Div4);
-
-  /* TIM3 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
-
-  /* GPIOA and GPIOC clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the TIM3 and the GPIOE Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
- /* GPIOD Configuration: Pin7 an Output push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-#else
-  /* GPIOA Configuration:TIM3 Channel1, 2, 3 and 4 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* GPIOC Configuration: Pin6 an Output push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-#endif
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/readme.txt
deleted file mode 100644
index e285817..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/readme.txt
+++ /dev/null
@@ -1,123 +0,0 @@
-/**
-  @page TIM_OCActive TIM OC Active example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/OCActive/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM OC Active example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM peripheral to generate four different 
-signals with four different delays.
-
-The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
-to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following:
-   - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices and to 24 MHz for Low-Density Value line,
-Medium-Density Value line and High-Density Value line devices.
-
-The TIM3 CCR1 register value is equal to 1000:
-TIM3_CH1 delay = CCR1_Val/TIM3 counter clock  = 1000 ms
-so the TIM3 Channel 1 generates a signal with a delay equal to 1000 ms.
-
-The TIM3 CCR2 register value is equal to 500:
-TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms
-so the TIM3 Channel 2 generates a signal with a delay equal to 500 ms.
-
-The TIM3 CCR3 register value is equal to 250:
-TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms
-so the TIM3 Channel 3 generates a signal with a delay equal to 250 ms.
-
-The TIM3 CCR4 register value is equal to 125:
-TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms
-so the TIM3 Channel 4 generates a signal with a delay equal to 125 ms.
-
-The delay correspond to the time difference between PC.06 and 
-TIM3_CHx signal rising edges in case of STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL 
-and STM3210B-EVAL 
-
-The delay correspond to the time difference between PD.07 and 
-TIM3_CHx signal rising edges in case of STM3210C-EVAL
-
-@par Directory contents 
-
-  - TIM/OCActive/stm32f10x_conf.h    Library Configuration file
-  - TIM/OCActive/stm32f10x_it.c      Interrupt handlers
-  - TIM/OCActive/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/OCActive/main.c              Main program 
-  - TIM/OCActive/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    
-
-  - STM3210C-EVAL Set-up 
-    - Connect the TIM3 pins(TIM3 full remapped pins) to an oscilloscope to
-      monitor the different waveforms:
-       - PD.07
-       - PC.06 (TIM3_CH1)
-       - PC.07 (TIM3_CH2)
-       - PC.08 (TIM3_CH3)
-       - PC.09 (TIM3_CH4)
-
-  - STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:
-       - PC.06
-       - PA.06 (TIM3_CH1)
-       - PA.07 (TIM3_CH2)
-       - PB.00 (TIM3_CH3)
-       - PB.01 (TIM3_CH4)
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h
deleted file mode 100644
index df1947d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCActive/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c
deleted file mode 100644
index 822ef7d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCActive/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *        This file provides template for all exceptions handler and 
-  *        peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OCActive
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h
deleted file mode 100644
index 8dd2f45..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCActive/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c
deleted file mode 100644
index 0f6a448..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCActive/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c
deleted file mode 100644
index 98e6bc1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCInactive/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OCInactive
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-uint16_t CCR1_Val = 1000;
-uint16_t CCR2_Val = 500;
-uint16_t CCR3_Val = 250;
-uint16_t CCR4_Val = 125;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* ---------------------------------------------------------------
-    TIM2 Configuration: 
-    TIM2CLK = SystemCoreClock / 2,
-    The objective is to get TIM2 counter clock at 1 KHz:
-     - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
-    And generate 4 signals with 4 different delays:
-    TIM2_CH1 delay = CCR1_Val/TIM2 counter clock = 1000 ms
-    TIM2_CH2 delay = CCR2_Val/TIM2 counter clock = 500 ms
-    TIM2_CH3 delay = CCR3_Val/TIM2 counter clock = 250 ms
-    TIM2_CH4 delay = CCR4_Val/TIM2 counter clock = 125 ms
-
-  * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-    and Connectivity line devices and to 24 MHz for Low-Density Value line and
-    Medium-Density Value line devices
-  --------------------------------------------------------------- */
-  /* Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 2000) - 1;
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 65535;
-  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
-  /* Output Compare Active Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel2 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
-
-  TIM_OC2Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel3 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
-
-  TIM_OC3Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Active Mode configuration: Channel4 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
-
-  TIM_OC4Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  TIM_ARRPreloadConfig(TIM2, ENABLE);
-
-  /* TIM IT enable */
-  TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
-
-  /* Set PC.06, PC.07, PC.08 and PC.09 pins */
-  GPIO_SetBits(GPIOC, GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9);
-
-  /* TIM2 enable counter */
-  TIM_Cmd(TIM2, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK1 = HCLK/4 */
-  RCC_PCLK1Config(RCC_HCLK_Div4);
-
-  /* TIM2 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
-
-  /* GPIOC clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIOD Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* GPIOC Configuration: Pin6, 7, 8 and 9 as output push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configure the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the TIM2 Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-  NVIC_Init(&NVIC_InitStructure);
-
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt
deleted file mode 100644
index c0ea6a0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
-  @page TIM_OCInactive TIM OC Inactive example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/OCInactive/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM OC Inactive example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM peripheral in Output Compare Inactive 
-mode with the corresponding Interrupt requests for each channel.
-
-The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
-to get TIM2 counter clock at 1 KHz so the Prescaler is computed as following:
-   - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices and to 24 MHz for Value line devices.
-
-The TIM2 CCR1 register value is equal to 1000:
-TIM2_CC1 delay = CCR1_Val/TIM2 counter clock  = 1000 ms
-so the PC.06  is reset after a delay equal to 1000 ms.
-
-The TIM2 CCR2 register value is equal to 500:
-TIM2_CC2 delay = CCR2_Val/TIM2 counter clock = 500 ms
-so the PC.07  is reset after a delay equal to 500 ms.
-
-The TIM2 CCR3 register value is equal to 250:
-TIM2_CC3 delay = CCR3_Val/TIM2 counter clock = 250 ms
-so the PC.08  is reset after a delay equal to 250 ms.
-
-The TIM2 CCR4 register value is equal to 125:
-TIM2_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms
-so the PC.09  is reset after a delay equal to 125 ms.
-
-While the counter is lower than the Output compare registers values, which 
-determines the Output delay, the PC.06, PC.07, PC.08 and PC.09 pin are turned on. 
-
-When the counter value reaches the Output compare registers values, the Output 
-Compare interrupts are generated and, in the handler routine, these pins are turned off.
-
-@par Directory contents 
-
-  - TIM/OCInactive/stm32f10x_conf.h    Library Configuration file
-  - TIM/OCInactive/stm32f10x_it.c      Interrupt handlers
-  - TIM/OCInactive/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/OCInactive/main.c              Main program
-  - TIM/OCInactive/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL STM3210B-EVAL and STM3210C-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:
-        - PC.06
-        - PC.07
-        - PC.08 
-        - PC.09
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h
deleted file mode 100644
index 156e993..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCInactive/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c
deleted file mode 100644
index a6d417f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCInactive/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OCInactive
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles TIM2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM2_IRQHandler(void)
-{
-  if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET)
-  {
-    /* Clear TIM2 Capture Compare1 interrupt pending bit*/
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);
-
-    /* PC.06 turnoff after 1000 ms */
-    GPIO_ResetBits(GPIOC, GPIO_Pin_6);
-  }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET)
-  {
-    /* Clear TIM2 Capture Compare2 interrupt pending bit*/
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC2);
-
-    /* PC.07 turnoff after 500 ms */
-    GPIO_ResetBits(GPIOC, GPIO_Pin_7);
-  }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET)
-  {
-    /* Clear TIM2 Capture Compare3 interrupt pending bit*/
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC3);
-
-    /* PC.08 turnoff after 250 ms */
-    GPIO_ResetBits(GPIOC, GPIO_Pin_8);
-  }
-  else
-  {
-    /* Clear TIM2 Capture Compare4 interrupt pending bit*/
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC4);
-
-    /* PC.09 turnoff after 125 ms */
-    GPIO_ResetBits(GPIOC, GPIO_Pin_9);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
deleted file mode 100644
index 02716ff..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCInactive/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void TIM2_IRQHandler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
deleted file mode 100644
index a5bac39..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCToggle/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OCToggle
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t capture = 0;
-extern __IO uint16_t CCR1_Val;
-extern __IO uint16_t CCR2_Val;
-extern __IO uint16_t CCR3_Val;
-extern __IO uint16_t CCR4_Val;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles TIM3 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM3_IRQHandler(void)
-{
-  /* TIM3_CH1 toggling with frequency = 183.1 Hz */
-  if (TIM_GetITStatus(TIM3, TIM_IT_CC1) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM3, TIM_IT_CC1 );
-    capture = TIM_GetCapture1(TIM3);
-    TIM_SetCompare1(TIM3, capture + CCR1_Val );
-  }
-
-  /* TIM3_CH2 toggling with frequency = 366.2 Hz */
-  if (TIM_GetITStatus(TIM3, TIM_IT_CC2) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
-    capture = TIM_GetCapture2(TIM3);
-    TIM_SetCompare2(TIM3, capture + CCR2_Val);
-  }
-
-  /* TIM3_CH3 toggling with frequency = 732.4 Hz */
-  if (TIM_GetITStatus(TIM3, TIM_IT_CC3) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM3, TIM_IT_CC3);
-    capture = TIM_GetCapture3(TIM3);
-    TIM_SetCompare3(TIM3, capture + CCR3_Val);
-  }
-
-  /* TIM3_CH4 toggling with frequency = 1464.8 Hz */
-  if (TIM_GetITStatus(TIM3, TIM_IT_CC4) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM3, TIM_IT_CC4);
-    capture = TIM_GetCapture4(TIM3);
-    TIM_SetCompare4(TIM3, capture + CCR4_Val);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h
deleted file mode 100644
index 93e159b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OCToggle/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void TIM3_IRQHandler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c
deleted file mode 100644
index 75ccc2f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OnePulse
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_ICInitTypeDef  TIM_ICInitStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* TIM4 configuration: One Pulse mode ------------------------
-     The external signal is connected to TIM4_CH2 pin (PB.07), 
-     The Rising edge is used as active edge,
-     The One Pulse signal is output on TIM4_CH1 pin (PB.06)
-     The TIM_Pulse defines the delay value 
-     The (TIM_Period -  TIM_Pulse) defines the One Pulse value.
-     TIM2CLK = SystemCoreClock, we want to get TIM2 counter clock at 24 MHz:
-     - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
-     The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value 
-     to trigger the TIM4 input is 24000000/65535 = 300 Hz.
-
-     The TIM_Pulse defines the delay value, the delay value is fixed 
-     to 682.6 us:
-     delay =  CCR1/TIM4 counter clock = 682.6 us. 
-     The (TIM_Period - TIM_Pulse) defines the One Pulse value, 
-     the pulse value is fixed to 2.048 ms:
-     One Pulse value = (TIM_Period - TIM_Pulse) / TIM4 counter clock = 2.048 ms.
-
-  * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-    and Connectivity line devices and to 24 MHz for Value line devices
-  ------------------------------------------------------------ */
-
-  /* Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 65535;
-  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  /* TIM4 PWM2 Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 16383;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* TIM4 configuration in Input Capture Mode */
-
-  TIM_ICStructInit(&TIM_ICInitStructure);
-
-  TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
-  TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
-  TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
-  TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
-  TIM_ICInitStructure.TIM_ICFilter = 0;
-
-  TIM_ICInit(TIM4, &TIM_ICInitStructure);
-
-  /* One Pulse Mode selection */
-  TIM_SelectOnePulseMode(TIM4, TIM_OPMode_Single);
-
-  /* Input Trigger selection */
-  TIM_SelectInputTrigger(TIM4, TIM_TS_TI2FP2);
-
-  /* Slave Mode selection: Trigger Mode */
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Trigger);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
-
-  /* GPIOB clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIOD Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* TIM4_CH1 pin (PB.06) configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-  /* TIM4_CH2 pin (PB.07) configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt
deleted file mode 100644
index 2c01dca..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
-  @page TIM_OnePulse TIM One Pulse example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/OnePulse/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM One Pulse example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to use the TIM peripheral to generate a One pulse Mode 
-after a Rising edge of an external signal is received in Timer Input pin.
-
-TIM2CLK = SystemCoreClock, we want to get TIM2 counter clock at 24 MHz:
-  - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices and to 24 MHz for Low-Density Value line,
-Medium-Density Value line and High-Density devices.
-
-The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value to 
-trigger the TIM4 input is 24000000/65535 = 300 Hz.
-
-The TIM4 is configured as follows: 
-The One Pulse mode is used, the external signal is connected to TIM4 CH2 pin (PB.07), 
-the rising edge is used as active edge, the One Pulse signal is output 
-on TIM4_CH1 (PB.06).
-
-The TIM_Pulse defines the delay value, the delay value is fixed to:
-delay =  CCR1/TIM4 counter clock = 16383 / 24000000 = 682.6 us. 
-The (TIM_Period - TIM_Pulse) defines the One Pulse value, the pulse value is fixed to:
-One Pulse value = (TIM_Period - TIM_Pulse)/TIM4 counter clock 
-                = (65535 - 16383) / 24000000 = 2.048 ms.
-
-@par Directory contents 
-
-  - TIM/OnePulse/stm32f10x_conf.h    Library Configuration file
-  - TIM/OnePulse/stm32f10x_it.c      Interrupt handlers
-  - TIM/OnePulse/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/OnePulse/main.c              Main program 
-  - TIM/OnePulse/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM3210B-EVAL, STM32100E-EVAL and STM3210C-EVAL  Set-up 
-   - Connect the external signal to the TIM4_CH2 pin (PB.07)
-   - Connect the TIM4_CH1 (PB.06) pin to an oscilloscope to monitor the waveform.   
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h
deleted file mode 100644
index e93a14c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c
deleted file mode 100644
index 623bf36..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *        This file provides template for all exceptions handler and 
-  *        peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OnePulse
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h
deleted file mode 100644
index b7643cf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c
deleted file mode 100644
index eca0ad8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt
deleted file mode 100644
index 10772aa..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
-  @page TIM_PWM_Input TIM PWM Input example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/PWM_Input/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM PWM Input example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to use the TIM peripheral to measure the frequency and 
-duty cycle of an external signal.
-
-The TIMxCLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the 
-TIM3 counter clock is SystemCoreClock (Hz).
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices. For Low-Density Value line, Medium-Density 
-Value line and High-Density devices, SystemCoreClock is set to 24 MHz.
-
-TIM3 is configured in PWM Input Mode: the external signal is connected to 
-TIM3 Channel2 used as input pin.
-To measure the frequency and the duty cycle we use the TIM3 CC2 interrupt request,
-so In the TIM3_IRQHandler routine, the frequency and the duty cycle of the external 
-signal are computed. 
-The "Frequency" variable contains the external signal frequency:
-Frequency = TIM3 counter clock / TIM3_CCR2 in Hz, 
-The "DutyCycle" variable contains the external signal duty cycle:
-DutyCycle = (TIM3_CCR1*100)/(TIM3_CCR2) in %.
-
-For Low-density, Medium-density, High-density and Connectivity line devices, 
-the minimum frequency value to measure is 1100 Hz. 
-For Low-Density Value line and Medium-Density Value line devices, the minimum
-frequency value to measure is 366 Hz.
-
-@par Directory contents 
-
-  - TIM/PWM_Input/stm32f10x_conf.h    Library Configuration file
-  - TIM/PWM_Input/stm32f10x_it.c      Interrupt handlers
-  - TIM/PWM_Input/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/PWM_Input/main.c              Main program 
-  - TIM/PWM_Input/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL, STM3210B-EVAL and STM3210C-EVAL  Set-up 
-    - Connect the external signal to measure to the TIM3 CH2 pin (PA.07).   
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h
deleted file mode 100644
index 37b05f7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/PWM_Input/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c
deleted file mode 100644
index 00a2f82..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/PWM_Input/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt
deleted file mode 100644
index 469aa30..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
-  @page TIM_PWM_Output TIM PWM Output example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/PWM_Output/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM PWM Output example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description
-
-This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) 
-mode.
-
-The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter
-clock at 24 MHz the Prescaler is computed as following:
-   - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices and to 24 MHz for Value line devices.
-
-The TIM3 is running at 36 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1)
-                                              = 24 MHz / 666 = 36 KHz
-The TIM3 CCR1 register value is equal to 500, so the TIM3 Channel 1 generates a 
-PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 50%:
-TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR + 1)* 100 = 50%
-
-The TIM3 CCR2 register value is equal to 375, so the TIM3 Channel 2 generates a 
-PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 37.5%:
-TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR + 1)* 100 = 37.5%
-
-The TIM3 CCR3 register value is equal to 250, so the TIM3 Channel 3 generates a 
-PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 25%:
-TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR + 1)* 100 = 25%
-
-The TIM3 CCR4 register value is equal to 125, so the TIM3 Channel 4 generates a 
-PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 12.5%:
-TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR + 1)* 100 = 12.5%
-
-The PWM waveform can be displayed using an oscilloscope.
-
-@par Directory contents 
-
-  - TIM/PWM_Output/stm32f10x_conf.h    Library Configuration file
-  - TIM/PWM_Output/stm32f10x_it.c      Interrupt handlers
-  - TIM/PWM_Output/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/PWM_Output/main.c              Main program 
-  - TIM/PWM_Output/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM3210C-EVAL Set-up 
-    - Connect the following pins(TIM3 full remapping pins) to an oscilloscope to monitor the different 
-      waveforms:
-        - PC.06: (TIM3_CH1)
-        - PC.07: (TIM3_CH2)
-        - PC.08: (TIM3_CH3)
-        - PC.09: (TIM3_CH4)      
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the following pins to an oscilloscope to monitor the different 
-      waveforms:
-        - PA.06: (TIM3_CH1)
-        - PA.07: (TIM3_CH2)
-        - PB.00: (TIM3_CH3)
-        - PB.01: (TIM3_CH4)  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h
deleted file mode 100644
index 605b2ad..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/PWM_Output/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c
deleted file mode 100644
index 01c4cb1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/PWM_Output/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *         This file provides template for all exceptions handler and
-  *         peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_PWM_Output
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h
deleted file mode 100644
index bfcc9ea..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/PWM_Output/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c
deleted file mode 100644
index 199efb6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Parallel_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* Timers synchronisation in parallel mode ----------------------------
-     1/TIM2 is configured as Master Timer:
-     - PWM Mode is used
-     - The TIM2 Update event is used as Trigger Output  
-     2/TIM3 and TIM4 are slaves for TIM2,
-     - PWM Mode is used
-     - The ITR1(TIM2) is used as input trigger for both slaves
-     - Gated mode is used, so starts and stops of slaves counters
-      are controlled by the Master trigger output signal(update event).
-
-  * For Low-density, Medium-density, High-density and Connectivity line devices:
-     The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
-     The Master Timer TIM2 is running at 281.250 KHz and the duty cycle
-     is equal to 25%
-     The TIM3 is running:
-     - At (TIM2 frequency)/ (TIM3 period + 1) = 28.125 KHz and a duty cycle
-     equal to TIM3_CCR1/(TIM3_ARR + 1) = 30%
-     The TIM4 is running:
-     - At (TIM2 frequency)/ (TIM4 period + 1) = 56.250 KHz and a duty cycle
-     equal to TIM4_CCR1/(TIM4_ARR + 1) = 60%
-     
-  * For Value line devices:
-     The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
-     TIM2 frequency = 93.750 KHz,
-     TIM3 frequency = 23.437 KHz,
-     TIM4 frequency = 18.75 KHz     
-  -------------------------------------------------------------------- */
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 255;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 9;
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 4;
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  /* Master Configuration in PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 64;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection */
-  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
-
-  /* Slaves Configuration: PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 3;
-
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM3 */
-  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
-  
-  /* Slave Mode selection: TIM4 */
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM4, TIM_TS_ITR1);
-  
-  /* TIM enable counter */
-  TIM_Cmd(TIM3, ENABLE);
-  TIM_Cmd(TIM2, ENABLE);
-  TIM_Cmd(TIM4, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* TIM2, TIM3 and TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
-                         RCC_APB1Periph_TIM4, ENABLE);
-
-  /* GPIOA, GPIOB, GPIOC and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIO Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /*GPIOB Configuration:  PC6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 ;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
-#else
-/* GPIOA Configuration: PA6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-#endif
-  /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt
deleted file mode 100644
index 4629719..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
-  @page TIM_Parallel_Synchro TIM Parallel Synchro example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/Parallel_Synchro/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM Parallel Synchro example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to synchronize TIM peripherals in parallel mode.
-In this example three timers are used:
-
-Timers synchronisation in parallel mode:
-
-1/TIM2 is configured as Master Timer:
- - PWM Mode is used
- - The TIM2 Update event is used as Trigger Output 
- 
-2/TIM3 and TIM4 are slaves for TIM2,
- - PWM Mode is used
- - The ITR1(TIM2) is used as input trigger for both slaves 
- - Gated mode is used, so starts and stops of slaves counters are controlled 
-   by the Master trigger output signal(update event).
-
-o For Low-density, Medium-density, High-density and Connectivity line devices:
-  The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
-  The Master Timer TIM2 is running at TIM2 frequency:
-  TIM2 frequency = TIM2 counter clock/ (TIM2 period + 1) = 281.250 KHz 
-  and the duty cycle is equal to TIM2_CCR1/(TIM2_ARR + 1) = 25%.
-
-  The TIM3 is running at:
-  (TIM2 frequency)/ (TIM3 period + 1) = 28.1250 KHz and a duty cycle equal to 
-  TIM3_CCR1/(TIM3_ARR + 1) = 30%
-
-  The TIM4 is running at:
-  (TIM2 frequency)/ (TIM4 period + 1) = 56.250 KHz and a duty cycle equal to 
-  TIM4_CCR1/(TIM4_ARR + 1) = 60%
-
-o For Low-Density Value line, Medium-Density Value line and High-Density Value line devices:
-  The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
-  TIM2 frequency = 93.75 KHz 
-  TIM3 frequency = 9.375 KHz 
-  TIM4 frequency = 18.75 KHz 
-  
-@par Directory contents 
-
-  - TIM/Parallel_Synchro/stm32f10x_conf.h    Library Configuration file
-  - TIM/Parallel_Synchro/stm32f10x_it.c      Interrupt handlers
-  - TIM/Parallel_Synchro/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/Parallel_Synchro/main.c              Main program
-  - TIM/Parallel_Synchro/system_stm32f10x.c  STM32F10x system source file
-   
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM3210C-EVAL Set-up 
-    - Connect the pins to an oscilloscope to monitor the different waveforms:
-      - TIM2 CH1 (PA.00)
-      - TIM3 CH1 (PC.06) Remapped pin
-      - TIM4 CH1 (PB.06) 
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the pins to an oscilloscope to monitor the different waveforms:
-      - TIM2 CH1 (PA.00)
-      - TIM3 CH1 (PA.06) 
-      - TIM4 CH1 (PB.06) 
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
deleted file mode 100644
index c0c16e2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *         This file provides template for all exceptions handler and
-  *         peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Parallel_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h
deleted file mode 100644
index dd0ad2d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c
deleted file mode 100644
index edfb4ad..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
deleted file mode 100644
index 4647dfb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM10_PWMOutput/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM10_PWMOutput
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-uint16_t CCR1Val = 249;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* -----------------------------------------------------------------------
-    TIM10 Configuration: generate 1 PWM signal.
-    The TIM10CLK frequency is set to SystemCoreClock (72 MHz), to get TIM10 counter
-    clock at 24 MHz the Prescaler is computed as following:
-     - Prescaler = (TIM10CLK / TIM10 counter clock) - 1
-
-    The TIM10 is running at 36 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1)
-                                                  = 24 MHz / 666 = 36 KHz
-    TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR)* 100 = 37.5%
-  ----------------------------------------------------------------------- */
-  /* Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 665;
-  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM10, &TIM_TimeBaseStructure);
-
-  /* PWM1 Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1Val;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM10, &TIM_OCInitStructure);
-
-  TIM_OC1PreloadConfig(TIM10, TIM_OCPreload_Enable);
-
-  TIM_ARRPreloadConfig(TIM10, ENABLE);
-
-  /* TIM10 enable counter */
-  TIM_Cmd(TIM10, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configure TIM10 pin.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable TIM10 and GPIOF clock */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10 | RCC_APB2Periph_GPIOF |
-                         RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Remap TIM10_CH1 on PF6 pin */
-  GPIO_PinRemapConfig(GPIO_Remap_TIM10, ENABLE);	
-  
-  /* GPIOF Configuration: TIM10 Channel1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c
deleted file mode 100644
index 2deaafa..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM10_PWMOutput/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *         This file provides template for all exceptions handler and
-  *         peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM10_PWMOutput
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h
deleted file mode 100644
index 9bc9dae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM10_PWMOutput/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
deleted file mode 100644
index d04db27..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM10_PWMOutput/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
deleted file mode 100644
index 63f89d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM15_ComplementarySignals/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c
deleted file mode 100644
index e8d9453..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM15_ComplementarySignals/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM15_ComplementarySignals
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h
deleted file mode 100644
index 65efd6f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM15_ComplementarySignals/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
deleted file mode 100644
index 4b7a836..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM1_Synchro/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_TIM1_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* TIM1 and Timers(TIM3 and TIM4) synchronisation in parallel mode -----------
-     1/TIM1 is configured as Master Timer:
-     - PWM Mode is used
-     - The TIM1 Update event is used as Trigger Output
-    
-     2/TIM3 and TIM4 are slaves for TIM1,
-     - PWM Mode is used
-     - The ITR0(TIM1) is used as input trigger for both slaves
-     - Gated mode is used, so starts and stops of slaves counters
-       are controlled by the Master trigger output signal(update event).
-
-  o For Low-density, Medium-density, High-density and Connectivity line devices:
-    The TIMxCLK is fixed to 72 MHz, Prescaler = 0 so the TIM1 counter clock is 72 MHz.
-
-    The Master Timer TIM1 is running at:
-    TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 281.250 KHz
-    and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50%
-
-    The TIM3 is running at: 
-    (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 18.750 KHz and
-    a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3%
-
-    The TIM4 is running at:
-    (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 28.125 KHz and
-    a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50%
-  
-  o For Low-Density Value line and Medium-Density Value line devices:
-    The TIMxCLK is fixed to 24 MHz, Prescaler = 0 so the TIM1 counter clock is 24 MHz.
-    TIM1 frequency = 93.75 KHz
-    TIM3 frequency = 6.25 KHz
-    TIM4 frequency = 9.375 KHz
-  --------------------------------------------------------------------------- */
-
-  /* TIM3 Peripheral Configuration ----------------------------------------*/
-  /* TIM3 Slave Configuration: PWM1 Mode */
-  TIM_TimeBaseStructure.TIM_Period = 2;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 1;
-
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM3 */
-  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0);
-  
-  /* TIM4 Peripheral Configuration ----------------------------------------*/
-  /* TIM4 Slave Configuration: PWM1 Mode */
-  TIM_TimeBaseStructure.TIM_Period = 1;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 1;
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM4 */
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM4, TIM_TS_ITR0);
-  
-  /* TIM1 Peripheral Configuration ----------------------------------------*/
-  /* Time Base configuration */
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseStructure.TIM_Period = 255;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_RepetitionCounter = 4;
-
-  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
-
-  /* Channel 1 Configuration in PWM mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 127;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
-  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
-  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
-  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
-
-  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
-
-  /* Automatic Output enable, Break, dead time and lock configuration*/
-  TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
-  TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
-  TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
-  TIM_BDTRInitStructure.TIM_DeadTime = 5;
-  TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
-  TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
-  TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-
-  TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
-
-  /* Master Mode selection */
-  TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable);
-  
-  /* TIM1 counter enable */
-  TIM_Cmd(TIM1, ENABLE);
-
-  /* TIM enable counter */
-  TIM_Cmd(TIM3, ENABLE);
-  TIM_Cmd(TIM4, ENABLE);
-
-  /* Main Output Enable */
-  TIM_CtrlPWMOutputs(TIM1, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* TIM1, GPIOA and GPIOB clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE |
-                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* TIM3 and TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
-}
-
-/**
-  * @brief  Configures TIM1, TIM3 and TIM4 Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /* GPIOC Configuration: TIM3 channel1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
-  /* GPIOE Configuration: TIM1 channel1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_8;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);	
-
-#else
-
-  /* GPIOA Configuration: TIM1 Channel1 and TIM3 Channel1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-#endif
-
-  /* GPIOB Configuration: TIM4 Channel1 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt
deleted file mode 100644
index cefbfa3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
-  @page TIM_TIM1_Synchro TIM1 Synchro example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/TIM1_Synchro/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM TIM1 Synchro example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode.
-
-Timers synchronisation in parallel mode:
-
-1/ TIM1 is configured as Master Timer:
- - PWM Mode is used
- - The TIM1 Update event is used as Trigger Output 
- 
-2/ TIM3 and TIM4 are slaves for TIM1,
- - PWM Mode is used
- - The ITR0(TIM1) is used as input trigger for both slaves
- - Gated mode is used, so starts and stops of slaves counters
-  are controlled by the Master trigger output signal(update event).
-
-o For Low-density, Medium-density, High-density and Connectivity line devices:
-  The TIMxCLK is fixed to 72 MHz, Prescaler = 0 so the TIM1 counter clock is 72 MHz.
-
-  The Master Timer TIM1 is running at:
-  TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 281.250 KHz
-  and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50%
-
-  The TIM3 is running at: 
-  (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 18.750 KHz and
-  a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3%
-
-  The TIM4 is running at:
-  (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 28.125 KHz and
-  a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50%
-  
-o For Value line devices:
-  The TIMxCLK is fixed to 24 MHz, Prescaler = 0 so the TIM1 counter clock is 24 MHz.
-  TIM1 frequency = 93.75 KHz
-  TIM3 frequency = 6.25 KHz
-  TIM4 frequency = 9.375 KHz
-
-@par Directory contents 
-
-  - TIM/TIM1_Synchro/stm32f10x_conf.h    Library Configuration file
-  - TIM/TIM1_Synchro/stm32f10x_it.c      Interrupt handlers
-  - TIM/TIM1_Synchro/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/TIM1_Synchro/main.c              Main program 
-  - TIM/TIM1_Synchro/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    
-
-  - STM3210C-EVAL Set-up 
-   - Connect the following pins to an oscilloscope to monitor the different waveforms:
-      - TIM1 CH1 (PE.08) Remapped pin
-      - TIM3 CH1 (PC.06) Remapped pin
-      - TIM4 CH1 (PB.06) 
-
-  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
-   - Connect the following pins to an oscilloscope to monitor the different waveforms:
-      - TIM1 CH1 (PA.08)
-      - TIM3 CH1 (PA.06)
-      - TIM4 CH1 (PB.06)  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h
deleted file mode 100644
index 7473e1b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM1_Synchro/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c
deleted file mode 100644
index c825c9e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM1_Synchro/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_TIM1_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h
deleted file mode 100644
index 1dae652..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM1_Synchro/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c
deleted file mode 100644
index 80962ef..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM1_Synchro/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c
deleted file mode 100644
index 6f70494..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM9_OCToggle
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-__IO uint16_t CCR1Val = 32768;
-__IO uint16_t CCR2Val = 16384;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Configure TIM9 pins */
-  GPIO_Configuration();
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-
-  /* ---------------------------------------------------------------------------
-    TIM9 Configuration: Output Compare Toggle Mode:
-    TIM9CLK = SystemCoreClock (72MHz),
-    The objective is to get TIM9 counter clock at 24 MHz:
-     - Prescaler = (TIM9CLK / TIM9 counter clock) - 1
-    CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz
-    CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8 Hz
-  ----------------------------------------------------------------------------*/
-  /* Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 65535;
-  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM9, &TIM_TimeBaseStructure);
-
-  /* Output Compare Toggle Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1Val;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
-  TIM_OC1Init(TIM9, &TIM_OCInitStructure);
-
-  TIM_OC1PreloadConfig(TIM9, TIM_OCPreload_Disable);
-
-  /* Output Compare Toggle Mode configuration: Channel2 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR2Val;
-
-  TIM_OC2Init(TIM9, &TIM_OCInitStructure);
-
-  TIM_OC2PreloadConfig(TIM9, TIM_OCPreload_Disable);
-
-  /* TIM enable counter */
-  TIM_Cmd(TIM9, ENABLE);
-
-  /* TIM IT enable */
-  TIM_ITConfig(TIM9, TIM_IT_CC1 | TIM_IT_CC2, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configure TIM9 pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable TIM9 and GPIOA clock  */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9 | RCC_APB2Periph_GPIOA, ENABLE);
-  
-  /* GPIOA Configuration:TIM9 Channel1 and 2 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configure the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the TIM9 global Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel =  TIM1_BRK_TIM9_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt
deleted file mode 100644
index 8503879..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
-  @page TIM9_OCToggle TIM9 OC Toggle example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/TIM9_OCToggle/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM9 OC Toggle example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM9 peripheral to generate two different 
-signals with two different frequencies.
-
-The TIM9CLK frequency is set to SystemCoreClock (72 MHz), and we want to get TIM9
-counter clock at 24 MHz so the Prescaler is computed as following:
-   - Prescaler = (TIM9CLK / TIM9 counter clock) - 1
-
-The TIM9 CCR1 register value is equal to 32768: 
-CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz,
-so the TIM9 Channel 1 generates a periodic signal with a frequency equal to 366.2 Hz.
-
-The TIM9 CCR2 register is equal to 16384:
-CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8
-so the TIM9 channel 2 generates a periodic signal with a frequency equal to 732.4 Hz.
-
-
-@par Directory contents 
-
-  - TIM/TIM9_OCToggle/stm32f10x_conf.h    Library Configuration file
-  - TIM/TIM9_OCToggle/stm32f10x_it.c      Interrupt handlers
-  - TIM/TIM9_OCToggle/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/TIM9_OCToggle/main.c              Main program
-  - TIM/TIM9_OCToggle/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) 
-    evaluation board and can be easily tailored to any development board.    
-
-  - STM3210E-EVAL Set-up 
-    - Connect the TIM9 pins to an oscilloscope to monitor the different waveforms:
-       - PA.02 (TIM9_CH1)
-       - PA.03 (TIM9_CH2)
-  
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h
deleted file mode 100644
index 2dfb346..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
deleted file mode 100644
index 86fd78c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM9_OCToggle
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t capture = 0;
-extern __IO uint16_t CCR1Val;
-extern __IO uint16_t CCR2Val;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles TIM1 Break and TIM9 interrupts request.
-  * @param  None
-  * @retval None
-  */
-void TIM1_BRK_TIM9_IRQHandler(void)
-{
-  /* TIM9_CH1 toggling with frequency = 366.2 Hz */
-  if (TIM_GetITStatus(TIM9, TIM_IT_CC1) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM9, TIM_IT_CC1 );
-    capture = TIM_GetCapture1(TIM9);
-    TIM_SetCompare1(TIM9, capture + CCR1Val );
-  }
-
-  /* TIM9_CH2 toggling with frequency = 732.4 Hz */
-  if (TIM_GetITStatus(TIM9, TIM_IT_CC2) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM9, TIM_IT_CC2);
-    capture = TIM_GetCapture2(TIM9);
-    TIM_SetCompare2(TIM9, capture + CCR2Val);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c
deleted file mode 100644
index 082a454..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
deleted file mode 100644
index d142cfb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TimeBase/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_TimeBase
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-__IO uint16_t CCR1_Val = 40961;
-__IO uint16_t CCR2_Val = 27309;
-__IO uint16_t CCR3_Val = 13654;
-__IO uint16_t CCR4_Val = 6826;
-uint16_t PrescalerValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* ---------------------------------------------------------------
-    TIM2 Configuration: Output Compare Timing Mode:
-    TIM2 counter clock at 6 MHz
-    CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz
-    CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz
-    CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4 Hz
-    CC4 update rate = TIM2 counter clock / CCR4_Val = 878.9 Hz
-  --------------------------------------------------------------- */
-
-  /* Compute the prescaler value */
-  PrescalerValue = (uint16_t) (SystemCoreClock / 12000000) - 1;
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 65535;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
-  /* Prescaler configuration */
-  TIM_PrescalerConfig(TIM2, PrescalerValue, TIM_PSCReloadMode_Immediate);
-
-  /* Output Compare Timing Mode configuration: Channel1 */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Timing Mode configuration: Channel2 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
-
-  TIM_OC2Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Timing Mode configuration: Channel3 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
-
-  TIM_OC3Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* Output Compare Timing Mode configuration: Channel4 */
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
-
-  TIM_OC4Init(TIM2, &TIM_OCInitStructure);
-
-  TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
-
-  /* TIM IT enable */
-  TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
-
-  /* TIM2 enable counter */
-  TIM_Cmd(TIM2, ENABLE);
-
-  while (1);
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK1 = HCLK/4 */
-  RCC_PCLK1Config(RCC_HCLK_Div4);
-
-  /* TIM2 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
-
-  /* GPIOC clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIO Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* GPIOC Configuration:Pin6, 7, 8 and 9 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configure the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the TIM2 global Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt
deleted file mode 100644
index f893802..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
-  @page TIM_TimeBase TIM Time Base example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/TimeBase/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the TIM Time Base example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to configure the TIM peripheral in Output Compare Timing 
-mode with the corresponding Interrupt requests for each channel in order to generate
-4 different time bases.
-
-The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM2 counter 
-clock at 6 MHz so the Prescaler is computed as following:
-   - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
-SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices and to 24 MHz for Low-Density Value line,
-Medium-Density Value line and High-Density devices.
-
-The TIM2 CC1 register value is equal to 40961, 
-CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz,
-so the TIM2 Channel 1 generates an interrupt each 6.8ms
-
-The TIM2 CC2 register is equal to 27309, 
-CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz
-so the TIM2 Channel 2 generates an interrupt each 4.55ms
-
-The TIM2 CC3 register is equal to 13654, 
-CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4Hz
-so the TIM2 Channel 3 generates an interrupt each 2.27ms
-
-The TIM2 CC4 register is equal to 6826, 
-CC4 update rate = TIM2 counter clock / CCR4_Val =  878.9 Hz
-so the TIM2 Channel 4 generates an interrupt each 1.13ms.
-
-When the counter value reaches the Output compare registers values, the Output 
-Compare interrupts are generated and, in the handler routine, 4 pins(PC.06, PC.07,
-PC.08 and  PC.09) are toggled with the following frequencies: 
-
-- PC.06: 73.24Hz (CC1)
-- PC.07: 109.8Hz (CC2)
-- PC.08: 219.7Hz (CC3) 
-- PC.09: 439.4Hz (CC4)
-
-@par Directory contents 
-
-  - TIM/TimeBase/stm32f10x_conf.h    Library Configuration file
-  - TIM/TimeBase/stm32f10x_it.c      Interrupt handlers
-  - TIM/TimeBase/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/TimeBase/main.c              Main program 
-  - TIM/TimeBase/system_stm32f10x.c  STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-
-  - STM32100E-EVAL, STM3210E-EVAL, STM32100E-EVAL, STM3210B-EVAL and STM3210C-EVAL Set-up 
-    - Connect an oscilloscope on PC.06, PC.07, PC.08 and  PC.09 to show the 
-      different Time Base signals.  
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h
deleted file mode 100644
index c591b11..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TimeBase/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
deleted file mode 100644
index 2d4a7ed..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TimeBase/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_TimeBase
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t capture = 0;
-extern __IO uint16_t CCR1_Val;
-extern __IO uint16_t CCR2_Val;
-extern __IO uint16_t CCR3_Val;
-extern __IO uint16_t CCR4_Val;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles TIM2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM2_IRQHandler(void)
-{
-  if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);
-
-    /* Pin PC.06 toggling with frequency = 73.24 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_6, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_6)));
-    capture = TIM_GetCapture1(TIM2);
-    TIM_SetCompare1(TIM2, capture + CCR1_Val);
-  }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC2);
-
-    /* Pin PC.07 toggling with frequency = 109.8 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_7, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_7)));
-    capture = TIM_GetCapture2(TIM2);
-    TIM_SetCompare2(TIM2, capture + CCR2_Val);
-  }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC3);
-
-    /* Pin PC.08 toggling with frequency = 219.7 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_8, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_8)));
-    capture = TIM_GetCapture3(TIM2);
-    TIM_SetCompare3(TIM2, capture + CCR3_Val);
-  }
-  else
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC4);
-
-    /* Pin PC.09 toggling with frequency = 439.4 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_9, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_9)));
-    capture = TIM_GetCapture4(TIM2);
-    TIM_SetCompare4(TIM2, capture + CCR4_Val);
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h
deleted file mode 100644
index 7009cc3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TimeBase/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void TIM2_IRQHandler(void);
-					 
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
deleted file mode 100644
index 9755d00..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Interrupt/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_DMA_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-uint8_t TxBuffer1[] = "USART DMA Interrupt: USARTy -> USARTz using DMA Tx and Rx Flag";
-uint8_t TxBuffer2[] = "USART DMA Interrupt: USARTz -> USARTy using DMA Tx and Rx Interrupt";
-uint8_t RxBuffer1[TxBufferSize2];
-uint8_t RxBuffer2[TxBufferSize1];
-uint8_t NbrOfDataToRead = TxBufferSize1;
-uint32_t index = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-void DMA_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-       
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Configure the DMA */
-  DMA_Configuration();
-
-/* USARTy and USARTz configuration -------------------------------------------*/
-  /* USARTy and USARTz configured as follow:
-        - BaudRate = 230400 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-
-  USART_InitStructure.USART_BaudRate = 230400;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  
-  /* Configure USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-
-  /* Configure USARTz */
-  USART_Init(USARTz, &USART_InitStructure);
-
-  /* Enable USARTy DMA TX request */
-  USART_DMACmd(USARTy, USART_DMAReq_Tx, ENABLE);
-
-  /* Enable USARTz DMA TX request */
-  USART_DMACmd(USARTz, USART_DMAReq_Tx, ENABLE);
-
-  /* Enable the USARTz Receive Interrupt */
-  USART_ITConfig(USARTz, USART_IT_RXNE, ENABLE);
-  
-  /* Enable USARTy */
-  USART_Cmd(USARTy, ENABLE);
-
-  /* Enable USARTz */
-  USART_Cmd(USARTz, ENABLE);
-
-  /* Enable USARTy DMA TX Channel */
-  DMA_Cmd(USARTy_Tx_DMA_Channel, ENABLE);
-
-  /* Enable USARTz DMA TX Channel */
-  DMA_Cmd(USARTz_Tx_DMA_Channel, ENABLE);
-
-  /* Receive the TxBuffer2 */
-  while(index < TxBufferSize2)
-  {
-     while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
-     {
-     }
-     RxBuffer1[index++] = USART_ReceiveData(USARTy);  
-  }
-
-  /* Wait until USARTy TX DMA1 Channel  Transfer Complete */
-  while (DMA_GetFlagStatus(USARTy_Tx_DMA_FLAG) == RESET)
-  {
-  }
-  /* Wait until USARTz TX DMA1 Channel Transfer Complete */
-  while (DMA_GetFlagStatus(USARTz_Tx_DMA_FLAG) == RESET)
-  {
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
-  /* TransferStatus1 = PASSED, if the data transmitted from USARTz and  
-     received by USARTy are the same */
-  /* TransferStatus1 = FAILED, if the data transmitted from USARTz and 
-     received by USARTy are different */
-  TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
-  /* TransferStatus2 = PASSED, if the data transmitted from USARTy and  
-     received by USARTz are the same */
-  /* TransferStatus2 = FAILED, if the data transmitted from USARTy and 
-     received by USARTz are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{    
-  /* DMA clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-#else
-  /* Enable USARTy Clock */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
-#endif
-  /* Enable USARTz Clock */
-  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-  
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
-#elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif
-
-  /* Configure USARTy Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure USARTz Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-  
-  /* Configure USARTy Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTz Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-}
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-   NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the USARTz Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = USARTz_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Configures the DMA.
-  * @param  None
-  * @retval None
-  */
-void DMA_Configuration(void)
-{
-  DMA_InitTypeDef DMA_InitStructure;
-
-  /* USARTy_Tx_DMA_Channel (triggered by USARTy Tx event) Config */
-  DMA_DeInit(USARTy_Tx_DMA_Channel);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer1;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(USARTy_Tx_DMA_Channel, &DMA_InitStructure);
-  
-  /* USARTz_Tx_DMA_Channel (triggered by USARTz Tx event) Config */
-  DMA_DeInit(USARTz_Tx_DMA_Channel);
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer2;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize2;
-  DMA_Init(USARTz_Tx_DMA_Channel, &DMA_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/platform_config.h
deleted file mode 100644
index 9474a3f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/platform_config.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Interrupt/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL) 
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_DR_Base           0x40004404
-  #define USARTz_IRQn              USART2_IRQn
-
-#elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_DR_Base           0x40004404
-  #define USARTz_IRQn              USART2_IRQn
-
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTy_DR_Base           0x40004404
-
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel2
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC2
-  #define USARTz_DR_Base           0x40004804
-  #define USARTz_IRQn              USART3_IRQn
-
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt
deleted file mode 100644
index 0d6da30..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-/**
-  @page USART_DMA_Interrupt USART DMA Interrupt example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/DMA_Interrupt/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART DMA Interrupt example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication between USARTy and USARTz using DMA 
-capability, flags and interrupts. USARTy and USARTz can be USART1 and USART2 or
-USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
-
-First, the DMA transfers data from TxBuffer2 buffer to USARTz Transmit data register,
-then this data is sent to USARTy. Data received by USARTy is transferred using 
-RXNE flag and stored in RxBuffer1 then compared with the sent ones and
-the result of this comparison is stored in the "TransferStatus1" variable.
- 
-In the same time, the DMA transfers data from TxBuffer1 buffer to USARTy Transmit
-data register, then this data is sent to USARTz. Data received by USARTz is
-transferred using Receive interrupt and stored in RxBuffer2 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus2"
-variable. 
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 230400 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled       
-        
-@par Directory contents 
-
-  - USART/DMA_Interrupt/platform_config.h    Evaluation board specific configuration file
-  - USART/DMA_Interrupt/stm32f10x_conf.h     Library Configuration file
-  - USART/DMA_Interrupt/stm32f10x_it.h       Interrupt handlers header file
-  - USART/DMA_Interrupt/stm32f10x_it.c       Interrupt handlers
-  - USART/DMA_Interrupt/main.c               Main program
-  - USART/DMA_Interrupt/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/DMA_Interrupt/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN5 (USART2).
-      @note Make sure that jumper JP5 is not open.
-      
-  - STM32100B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN9 (USART2).
-      @note In this case USART2 Tx and Rx pins are remapped by software on PD.05 
-            and PD.06 respectively. 
-
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-              
-  - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 (USART1) and 
-      CN8 (USART2).
-    
-  - STM3210B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN6 (USART1) and 
-      CN5 (USART2).
-      - In this case USART2 Tx and Rx pins are remapped by software on PD.05 
-        and PD.06 respectively. 
-			
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 71d01ea..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
deleted file mode 100644
index 7dd43d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Interrupt/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_DMA_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint8_t RxCounter = 0;
-extern uint8_t RxBuffer2[];
-extern uint8_t NbrOfDataToRead;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles USART2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void USART2_IRQHandler(void)
-{
-  if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET)
-  {
-    /* Read one byte from the receive data register */
-    RxBuffer2[RxCounter++] = USART_ReceiveData(USART2);
-
-    if(RxCounter == NbrOfDataToRead)
-    {
-      /* Disable the USART2 Receive interrupt */
-      USART_ITConfig(USART2, USART_IT_RXNE, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  This function handles USART3 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void USART3_IRQHandler(void)
-{
-  if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET)
-  {
-    /* Read one byte from the receive data register */
-    RxBuffer2[RxCounter++] = USART_ReceiveData(USART3);
-
-    if(RxCounter == NbrOfDataToRead)
-    {
-      /* Disable the USART3 Receive interrupt */
-      USART_ITConfig(USART3, USART_IT_RXNE, DISABLE);
-    }
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h
deleted file mode 100644
index 9f6a0d7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Interrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void USART2_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
deleted file mode 100644
index c1fd617..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Polling/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_DMA_Polling
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-uint8_t TxBuffer1[] = "USART DMA Polling: USARTy -> USARTz using DMA";
-uint8_t TxBuffer2[] = "USART DMA Polling: USARTz -> USARTy using DMA";
-uint8_t RxBuffer1[TxBufferSize2];
-uint8_t RxBuffer2[TxBufferSize1];
-volatile TestStatus TransferStatus1 = FAILED;
-volatile TestStatus TransferStatus2 = FAILED; 
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void DMA_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Configure the DMA */
-  DMA_Configuration();
-
-/* USARTy and USARTz configuration ------------------------------------------------------*/
-  /* USARTy and USARTz configured as follow:
-        - BaudRate = 230400 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 230400;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  
-  /* Configure USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-  /* Configure USARTz */
-  USART_Init(USARTz, &USART_InitStructure);
-
-  /* Enable USARTy DMA Rx and TX request */
-  USART_DMACmd(USARTy, USART_DMAReq_Rx | USART_DMAReq_Tx, ENABLE);
-  /* Enable USARTz DMA Rx and TX request */
-  USART_DMACmd(USARTz, USART_DMAReq_Rx | USART_DMAReq_Tx, ENABLE);
-
-  /* Enable USARTy TX DMA1 Channel */
-  DMA_Cmd(USARTy_Tx_DMA_Channel, ENABLE);
-  /* Enable USARTy RX DMA1 Channel */
-  DMA_Cmd(USARTy_Rx_DMA_Channel, ENABLE);
-
-  /* Enable USARTz TX DMA1 Channel */
-  DMA_Cmd(USARTz_Tx_DMA_Channel, ENABLE);
-  /* Enable USARTz RX DMA1 Channel */
-  DMA_Cmd(USARTz_Rx_DMA_Channel, ENABLE);
-
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-  /* Enable the USARTz */
-  USART_Cmd(USARTz, ENABLE);
-
-  /* Wait until USARTy TX DMA1 Channel Transfer Complete */
-  while (DMA_GetFlagStatus(USARTy_Tx_DMA_FLAG) == RESET)
-  {
-  }
-  /* Wait until USARTy RX DMA1 Channel Transfer Complete */
-  while (DMA_GetFlagStatus(USARTy_Rx_DMA_FLAG) == RESET)
-  {
-  }
-
-  /* Wait until USARTz TX DMA1 Channel Transfer Complete */
-  while (DMA_GetFlagStatus(USARTz_Tx_DMA_FLAG) == RESET)
-  {
-  }
-  /* Wait until USARTz RX DMA1 Channel Transfer Complete */
-  while (DMA_GetFlagStatus(USARTz_Rx_DMA_FLAG) == RESET)
-  {
-  }
-
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
-  /* TransferStatus1 = PASSED, if the data transmitted from USARTz and  
-     received by USARTy are the same */
-  /* TransferStatus1 = FAILED, if the data transmitted from USARTz and 
-     received by USARTy are different */
-  TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
-  /* TransferStatus2 = PASSED, if the data transmitted from USARTy and  
-     received by USARTz are the same */
-  /* TransferStatus2 = FAILED, if the data transmitted from USARTy and 
-     received by USARTz are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* DMA clock enable */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-#else
-  /* Enable USARTy Clock */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
-#endif
-  /* Enable USARTz Clock */
-  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-  
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
-#elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif
-
-  /* Configure USARTy Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure USARTz Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-  
-  /* Configure USARTy Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTz Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); 
-}
-
-/**
-  * @brief  Configures the DMA.
-  * @param  None
-  * @retval None
-  */
-void DMA_Configuration(void)
-{
-  DMA_InitTypeDef DMA_InitStructure;
-
-  /* USARTy TX DMA1 Channel (triggered by USARTy Tx event) Config */
-  DMA_DeInit(USARTy_Tx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer1;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(USARTy_Tx_DMA_Channel, &DMA_InitStructure);
-
-  /* USARTy RX DMA1 Channel (triggered by USARTy Rx event) Config */
-  DMA_DeInit(USARTy_Rx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)RxBuffer1;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize2;
-  DMA_Init(USARTy_Rx_DMA_Channel, &DMA_InitStructure);
-  
-  /* USARTz TX DMA1 Channel (triggered by USARTz Tx event) Config */
-  DMA_DeInit(USARTz_Tx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer2;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize2;  
-  DMA_Init(USARTz_Tx_DMA_Channel, &DMA_InitStructure);
-  
-  /* USARTz RX DMA1 Channel (triggered by USARTz Rx event) Config */
-  DMA_DeInit(USARTz_Rx_DMA_Channel);  
-  DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)RxBuffer2;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
-  DMA_Init(USARTz_Rx_DMA_Channel, &DMA_InitStructure);  
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h
deleted file mode 100644
index 2a4cf2f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Polling/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_Rx_DMA_Channel    DMA1_Channel5
-  #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC5  
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_Rx_DMA_Channel    DMA1_Channel6
-  #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC6 
-  #define USARTz_DR_Base           0x40004404
-
-#elif defined USE_STM3210E_EVAL || defined(USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_Rx_DMA_Channel    DMA1_Channel5
-  #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC5  
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_Rx_DMA_Channel    DMA1_Channel6
-  #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC6  
-  #define USARTz_DR_Base           0x40004404
-
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTy_Rx_DMA_Channel    DMA1_Channel6
-  #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC6  
-  #define USARTy_DR_Base           0x40004404
-
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel2
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC2
-  #define USARTz_Rx_DMA_Channel    DMA1_Channel3
-  #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC3  
-  #define USARTz_DR_Base           0x40004804
-  
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt
deleted file mode 100644
index 5f83a83..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
-  @page USART_DMA_Polling USART DMA Polling example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/DMA_Polling/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART DMA Polling example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication between USARTy and USARTz using DMA 
-capability. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3,
-depending on the STMicroelectronics EVAL board you are using.
-
-First, the DMA transfers data from TxBuffer2 buffer to USARTz Transmit data 
-register, then this data is sent to USARTy. Data received by USARTy is transferred
-by DMA and stored in RxBuffer1 then compared with the send ones and the result 
-of this comparison is stored in the "TransferStatus1" variable.
- 
-In the same time, the DMA transfers data from TxBuffer1 buffer to USARTy Transmit
-data register, then this data is sent to USARTz. Data received by USARTz is
-transferred by DMA and stored in RxBuffer2 then compared with the send ones and
-the result of this comparison is stored in the "TransferStatus2" variable. 
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 230400 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled       
-        
-@par Directory contents 
-
-  - USART/DMA_Polling/platform_config.h    Evaluation board specific configuration file
-  - USART/DMA_Polling/stm32f10x_conf.h     Library Configuration file
-  - USART/DMA_Polling/stm32f10x_it.h       Interrupt handlers header file
-  - USART/DMA_Polling/stm32f10x_it.c       Interrupt handlers
-  - USART/DMA_Polling/main.c               Main program
-  - USART/DMA_Polling/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/DMA_Polling/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN5 (USART2).
-      @note Make sure that jumper JP5 is not open.
-      
-  - STM32100B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN9 (USART2).
-      @note In this case USART2 Tx and Rx pins are remapped by software on PD.05 
-            and PD.06 respectively.
-
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-              
-  - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 (USART1) and 
-      CN8 (USART2).
-    
-  - STM3210B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN6 (USART1) and 
-      CN5 (USART2).
-      - In this case USART2 Tx and Rx pins are remapped by software on PD.05 
-        and PD.06 respectively. 
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h
deleted file mode 100644
index af84449..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/DMA_Polling/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
deleted file mode 100644
index a9425cf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HalfDuplex/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_HalfDuplex
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-uint8_t TxBuffer1[] = "USART Half Duplex: USARTy -> USARTz using HalfDuplex mode";
-uint8_t TxBuffer2[] = "USART Half Duplex: USARTz -> USARTy using HalfDuplex mode";
-uint8_t RxBuffer1[TxBufferSize2];
-uint8_t RxBuffer2[TxBufferSize1];
-uint32_t NbrOfDataToRead1 = TxBufferSize2;
-uint32_t NbrOfDataToRead2 = TxBufferSize1;
-uint8_t TxCounter1 = 0, RxCounter1 = 0;
-uint8_t TxCounter2 = 0, RxCounter2 = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;  
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-  
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-/* USARTy and USARTz configuration -------------------------------------------*/
-  /* USARTy and USARTz configured as follow:
-        - BaudRate = 230400 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-
-  */
-  USART_InitStructure.USART_BaudRate = 230400;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  /* Configure USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-  /* Configure USARTz */
-  USART_Init(USARTz, &USART_InitStructure);
-  
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-  /* Enable the USARTz */
-  USART_Cmd(USARTz, ENABLE);
-
-  /* Enable USARTy Half Duplex Mode*/
-  USART_HalfDuplexCmd(USARTy, ENABLE);
-  /* Enable USARTz Half Duplex Mode*/
-  USART_HalfDuplexCmd(USARTz, ENABLE);
-
-  while(NbrOfDataToRead2--)
-  {
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-    {
-    }
-    /* Write one byte in the USARTy Transmit Data Register */
-    USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
-
-    /* Wait the byte is entirely received by USARTz */  
-    while(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer2 */
-    RxBuffer2[RxCounter2++] = USART_ReceiveData(USARTz);
-  }
-
-  /* Clear the USARTy Data Register */
-  USART_ReceiveData(USARTy);
-
-  while(NbrOfDataToRead1--)
-  { 
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTz, USART_FLAG_TXE)== RESET)
-    {
-    }
-    /* Write one byte in the USARTz Transmit Data Register */
-    USART_SendData(USARTz, TxBuffer2[TxCounter2++]);
-
-    /* Wait the byte is entirely received by USARTy */
-    while(USART_GetFlagStatus(USARTy,USART_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer1 */
-    RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
-  /* TransferStatus = PASSED, if the data transmitted from USARTy and  
-     received by USARTz are the same */
-  /* TransferStatus = FAILED, if the data transmitted from USARTy and 
-     received by USARTz are different */
-  TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
-  /* TransferStatus = PASSED, if the data transmitted from USARTz and  
-     received by USARTy are the same */
-  /* TransferStatus = FAILED, if the data transmitted from USARTz and 
-     received by USARTy are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-#else
-  /* Enable USARTy Clock */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
-#endif
-  /* Enable USARTz Clock */
-  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-  
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
-#elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif
-  
-  /* Configure USARTy Tx as alternate function open-drain */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTz Tx as alternate function open-drain */
-  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/platform_config.h
deleted file mode 100644
index 33a58b9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/platform_config.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HalfDuplex/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_TxPin             GPIO_Pin_9
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_TxPin             GPIO_Pin_5
-
-#elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_TxPin             GPIO_Pin_9
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_TxPin             GPIO_Pin_2
-
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_TxPin             GPIO_Pin_5
-
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_TxPin             GPIO_Pin_10
-
-#endif /* USE_STM3210B_EVAL */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt
deleted file mode 100644
index 9c74140..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
-  @page USART_HalfDuplex USART Half Duplex example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/HalfDuplex/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART Half Duplex example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication between USARTy and USARTz in 
-Half-Duplex mode using flags. USARTy and USARTz can be USART1 and USART2 or
-USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
-
-First, the USARTy sends data from TxBuffer1 buffer to USARTz using TXE flag.
-Data received using RXNE flag by USARTz is stored in RxBuffer2 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus1" 
-variable.
- 
-Then, the USARTz sends data from TxBuffer2 buffer to USARTy using TXE flag.
-Data received using RXNE flag by USARTy is stored in RxBuffer1 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus2" 
-variable.     
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 230400 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - Even parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled
-
-@par Directory contents 
-
-  - USART/HalfDuplex/platform_config.h    Evaluation board specific configuration file
-  - USART/HalfDuplex/stm32f10x_conf.h     Library Configuration file
-  - USART/HalfDuplex/stm32f10x_it.h       Interrupt handlers header file
-  - USART/HalfDuplex/stm32f10x_it.c       Interrupt handlers
-  - USART/HalfDuplex/main.c               Main program
-  - USART/HalfDuplex/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/HalfDuplex/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to USART2_Tx(PA.02).
-      
-  - STM32100B-EVAL Set-up   
-    - Connect USART1_Tx(PA.09) to USART2_Tx(PD.05).
- 
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Tx pin (PC.10) and connect a 
-      pull-up resistor to this line (10K).  
-      @note In this case USART3 Tx pin is remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-            
-  - STM3210E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to USART2_Tx(PA.02) and connect a pull-up resistor to 
-      this line (10K).  
-
-  - STM3210B-EVAL Set-up   
-    - Connect USART1_Tx(PA.09) to USART2_Tx(PD.05) and connect a pull-up resistor to 
-      this line (10K). 
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h
deleted file mode 100644
index b3cb77f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HalfDuplex/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c
deleted file mode 100644
index a55707c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HalfDuplex/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h
deleted file mode 100644
index 886b100..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210E_EVAL
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
-#define  GPIOx                    GPIOD
-#define  RCC_APB2Periph_GPIOx     RCC_APB2Periph_GPIOD
-#define  GPIO_RTSPin              GPIO_Pin_4
-#define  GPIO_CTSPin              GPIO_Pin_3
-#define  GPIO_TxPin               GPIO_Pin_5
-#define  GPIO_RxPin               GPIO_Pin_6
-#elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
-#define  GPIOx                    GPIOA
-#define  RCC_APB2Periph_GPIOx     RCC_APB2Periph_GPIOA
-#define  GPIO_RTSPin              GPIO_Pin_1
-#define  GPIO_CTSPin              GPIO_Pin_0
-#define  GPIO_TxPin               GPIO_Pin_2
-#define  GPIO_RxPin               GPIO_Pin_3
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h
deleted file mode 100644
index 9bb440b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
deleted file mode 100644
index f3355b9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_HyperTerminal_HwFlowControl
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
deleted file mode 100644
index 901616e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
deleted file mode 100644
index bd194dc..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
deleted file mode 100644
index 73e2770..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_Interrupt/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_HyperTerminal_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#ifdef USE_STM3210C_EVAL
-  #define USARTx_IRQn   USART2_IRQn
-#else
-  #define USARTx_IRQn   USART1_IRQn
-#endif
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-  
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-              
-  /* NVIC configuration */
-  NVIC_Configuration();
-  
-/* USARTx configuration ------------------------------------------------------*/
-  /* USARTx configured as follow:
-        - BaudRate = 9600 baud  
-        - Word Length = 8 Bits
-        - Two Stop Bit
-        - Odd parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 9600;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_2;
-  USART_InitStructure.USART_Parity = USART_Parity_Odd;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-
-  /* Enable the EVAL_COM1 Transmit interrupt: this interrupt is generated when the 
-     EVAL_COM1 transmit data register is empty */  
-  USART_ITConfig(EVAL_COM1, USART_IT_TXE, ENABLE);
-
-  /* Enable the EVAL_COM1 Receive interrupt: this interrupt is generated when the 
-     EVAL_COM1 receive data register is not empty */
-  USART_ITConfig(EVAL_COM1, USART_IT_RXNE, ENABLE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the USARTx Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = USARTx_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 5c11070..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c
deleted file mode 100644
index 6670253..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_Interrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
deleted file mode 100644
index c2e1295..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-#define RxBufferSize1   TxBufferSize2
-#define RxBufferSize2   TxBufferSize1
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-uint8_t TxBuffer1[] = "USART Interrupt Example: USARTy -> USARTz using Interrupt";
-uint8_t TxBuffer2[] = "USART Interrupt Example: USARTz -> USARTy using Interrupt";
-uint8_t RxBuffer1[RxBufferSize1];
-uint8_t RxBuffer2[RxBufferSize2];
-__IO uint8_t TxCounter1 = 0x00;
-__IO uint8_t TxCounter2 = 0x00;
-__IO uint8_t RxCounter1 = 0x00; 
-__IO uint8_t RxCounter2 = 0x00;
-uint8_t NbrOfDataToTransfer1 = TxBufferSize1;
-uint8_t NbrOfDataToTransfer2 = TxBufferSize2;
-uint8_t NbrOfDataToRead1 = RxBufferSize1;
-uint8_t NbrOfDataToRead2 = RxBufferSize2;
-__IO TestStatus TransferStatus1 = FAILED; 
-__IO TestStatus TransferStatus2 = FAILED;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void NVIC_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief   Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-       
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-/* USARTy and USARTz configuration ------------------------------------------------------*/
-  /* USARTy and USARTz configured as follow:
-        - BaudRate = 9600 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 9600;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  /* Configure USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-  /* Configure USARTz */
-  USART_Init(USARTz, &USART_InitStructure);
-  
-  /* Enable USARTy Receive and Transmit interrupts */
-  USART_ITConfig(USARTy, USART_IT_RXNE, ENABLE);
-  USART_ITConfig(USARTy, USART_IT_TXE, ENABLE);
-
-  /* Enable USARTz Receive and Transmit interrupts */
-  USART_ITConfig(USARTz, USART_IT_RXNE, ENABLE);
-  USART_ITConfig(USARTz, USART_IT_TXE, ENABLE);
-
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-  /* Enable the USARTz */
-  USART_Cmd(USARTz, ENABLE);
-
-  /* Wait until end of transmission from USARTy to USARTz */
-  while(RxCounter2 < RxBufferSize2)
-  {
-  }
-
-  /* Wait until end of transmission from USARTz to USARTy */
-  while(RxCounter1 < RxBufferSize1)
-  {
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, RxBufferSize1);
-  /* TransferStatus1 = PASSED, if the data transmitted from USARTz and  
-     received by USARTy are the same */
-  /* TransferStatus1 = FAILED, if the data transmitted from USARTz and 
-     received by USARTy are different */
-  TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, RxBufferSize2);
-  /* TransferStatus2 = PASSED, if the data transmitted from USARTy and  
-     received by USARTz are the same */
-  /* TransferStatus2 = FAILED, if the data transmitted from USARTy and 
-     received by USARTz are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-#else
-  /* Enable USARTy Clock */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
-#endif
-  /* Enable USARTz Clock */
-  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-  
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
-#elif defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif
-
-  /* Configure USARTy Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure USARTz Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-  
-  /* Configure USARTy Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTz Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-}
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure the NVIC Preemption Priority Bits */  
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-  
-  /* Enable the USARTy Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = USARTy_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Enable the USARTz Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = USARTz_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h
deleted file mode 100644
index b0f39c6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100B_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL  
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- #define USE_STM32100E_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#ifdef USE_STM3210B_EVAL
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-    
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-    
-#elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-  
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-  
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-  #define USARTy_IRQn              USART2_IRQn
-  #define USARTy_IRQHandler        USART2_IRQHandler
-  
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-  #define USARTz_IRQn              USART3_IRQn
-  #define USARTz_IRQHandler        USART3_IRQHandler
-  
-#elif defined USE_STM32100B_EVAL
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-    
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-   
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/readme.txt
deleted file mode 100644
index fa9a2a9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/readme.txt
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
-  @page USART_Interrupt USART Interrupts example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/Interrupt/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART Interrupts example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication between USARTy and USARTz using 
-interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, 
-depending on the STMicroelectronics EVAL board you are using.
-
-USARTz sends TxBuffer2 to USARTy which sends TxBuffer1 to USARTz. The data received 
-by USARTy and USARTz are stored respectively in RxBuffer1 and RxBuffer2. The data
-transfer is managed in USARTy_IRQHandler and USARTz_IRQHandler in stm32f10x_it.c file.
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 9600 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled       
-
-        
-@par Directory contents 
-
-  - USART/Interrupt/platform_config.h    Evaluation board specific configuration file
-  - USART/Interrupt/stm32f10x_conf.h     Library Configuration file
-  - USART/Interrupt/stm32f10x_it.h       Interrupt handlers header file
-  - USART/Interrupt/stm32f10x_it.c       Interrupt handlers
-  - USART/Interrupt/main.c               Main program
-  - USART/Interrupt/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/Interrupt/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN5 (USART2).
-      @note Make sure that jumper JP5 is not open.
-
-  - STM32100B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN9 (USART2).
-      @note In this case USART2 Tx and Rx pins are remapped by software on PD.05
-            and PD.06 respectively. 
-            
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-              
-  - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 (USART1) and 
-      CN8 (USART2).
-    
-  - STM3210B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN6 (USART1) and 
-      CN5 (USART2).
-      - In this case USART2 Tx and Rx pins are remapped by software on PD.05
-        and PD.06 respectively. 
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 96b210c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
deleted file mode 100644
index 91a5c96..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Interrupt
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern uint8_t TxBuffer1[]; 
-extern uint8_t TxBuffer2[]; 
-extern uint8_t RxBuffer1[];
-extern uint8_t RxBuffer2[];
-extern __IO uint8_t TxCounter1;
-extern __IO uint8_t TxCounter2;
-extern __IO uint8_t RxCounter1; 
-extern __IO uint8_t RxCounter2;
-extern uint8_t NbrOfDataToTransfer1;
-extern uint8_t NbrOfDataToTransfer2;
-extern uint8_t NbrOfDataToRead1;
-extern uint8_t NbrOfDataToRead2;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles USARTy global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void USARTy_IRQHandler(void)
-{
-  if(USART_GetITStatus(USARTy, USART_IT_RXNE) != RESET)
-  {
-    /* Read one byte from the receive data register */
-    RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
-
-    if(RxCounter1 == NbrOfDataToRead1)
-    {
-      /* Disable the USARTy Receive interrupt */
-      USART_ITConfig(USARTy, USART_IT_RXNE, DISABLE);
-    }
-  }
-  
-  if(USART_GetITStatus(USARTy, USART_IT_TXE) != RESET)
-  {   
-    /* Write one byte to the transmit data register */
-    USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
-
-    if(TxCounter1 == NbrOfDataToTransfer1)
-    {
-      /* Disable the USARTy Transmit interrupt */
-      USART_ITConfig(USARTy, USART_IT_TXE, DISABLE);
-    }    
-  }
-}
-
-/**
-  * @brief  This function handles USARTz global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void USARTz_IRQHandler(void)
-{
-  if(USART_GetITStatus(USARTz, USART_IT_RXNE) != RESET)
-  {
-    /* Read one byte from the receive data register */
-    RxBuffer2[RxCounter2++] = USART_ReceiveData(USARTz);
-
-    if(RxCounter2 == NbrOfDataToRead1)
-    {
-      /* Disable the USARTz Receive interrupt */
-      USART_ITConfig(USARTz, USART_IT_RXNE, DISABLE);
-    }
-  }
-  
-  if(USART_GetITStatus(USARTz, USART_IT_TXE) != RESET)
-  {   
-    /* Write one byte to the transmit data register */
-    USART_SendData(USARTz, TxBuffer2[TxCounter2++]);
-
-    if(TxCounter2 == NbrOfDataToTransfer2)
-    {
-      /* Disable the USARTz Transmit interrupt */
-      USART_ITConfig(USARTz, USART_IT_TXE, DISABLE);
-    }
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
deleted file mode 100644
index b60caac..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void USART1_IRQHandler(void);
-void USART2_IRQHandler(void);
-void USART3_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c
deleted file mode 100644
index a422301..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt
deleted file mode 100644
index 9b9494b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-/**
-  @page USART_IrDA_Receive USART IrDA Receive example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/IrDA/Receive/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART IrDA Receive example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication USARTy IrDA receive mode. Four leds
-are used to show which byte is received. USARTy can be USART3 or USART2 depending
-on the STMicroelectronics EVAL board you are using.
-
-  - LED1 toggles when 0x05 is received
-  - LED2 toggles when 0x02 is received
-  - LED3 toggles when 0x03 is received
-  - LED4 toggles when 0x04 is received
-  - LED1, LED2, LED3 and LED4 toggle when 0x01 is received        
-
-USARTy configured as follow:
-   - BaudRate = 115200 baud  
-   - Word Length = 8 Bits
-   - One Stop Bit
-   - No parity
-   - Hardware flow control disabled (RTS and CTS signals)
-   - Receive and transmit enabled
-
-The USART IrDA example provides two IrDA program: transmitter&receiver and 
-requires two boards to be able to run the full demonstration:
- - one board will act as IrDA transmitter
- - one board will act as IrDA receiver
-
-
-@par Directory contents 
-
-  - USART/IrDA/Receive/platform_config.h    Evaluation board specific configuration file
-  - USART/IrDA/Receive/stm32f10x_conf.h     Library Configuration file
-  - USART/IrDA/Receive/stm32f10x_it.h       Interrupt handlers header file
-  - USART/IrDA/Receive/stm32f10x_it.c       Interrupt handlers
-  - USART/IrDA/Receive/main.c               Main program
-  - USART/IrDA/Receive/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/IrDA/Receive/platform_config.h or stm32_eval.h file
-
-  - STM32100E-EVAL Set-up 
-    - Use an IrDA transceiver connected to the USART3 Tx pin (U16 connector, JP15 
-      jumper must be fitted).
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07,
-      PC.08 and PC.09 pins 
-      @note In this case USART3 Tx and Rx pins are remapped by software on PC.10 
-            and PC.11 respectively.
-            
-  - STM32100B-EVAL Set-up 
-    - Use an IrDA transceiver connected to the USART3 Tx pin (U14 connector, JP11 
-      jumper must be fitted).
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07,
-      PC.08 and PC.09 pins 
-      @note In this case USART3 Tx and Rx pins are remapped by software on PC.10 
-            and PC.11 respectively. 
-
-  - STM3210C-EVAL Set-up 
-    - Use an IrDA transceiver connected to the USART2 Tx and Rx pins (U12 
-      connector, JP16 should be in position 1<-->2).
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins
-    
-  - STM3210E-EVAL Set-up 
-    - Use an IrDA transceiver connected to the USART3 Tx pin (U13 connector, JP21
-      and JP22 jumper must be fitted).
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7,
-      PF.08 and PF.09 pins
-
-  - STM3210B-EVAL Set-up 
-    - Use an IrDA transceiver connected to the USART3 Tx pin (U11 connector, JP5 
-      jumper must be fitted).
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07,
-      PC.08 and PC.09 pins 
-
-  
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h
deleted file mode 100644
index 6131b68..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Receive/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c
deleted file mode 100644
index 15ed3e7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Receive/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_IrDA_Receive
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h
deleted file mode 100644
index 68af1d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Receive/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c
deleted file mode 100644
index 99474d7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Receive/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
deleted file mode 100644
index b4158f7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Transmit/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_IrDA_Transmit
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-JOYState_TypeDef MyKey = JOY_NONE;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-JOYState_TypeDef ReadKey(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-#ifndef USE_STM3210C_EVAL
-  /* Initialize JoyStick Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_PBInit(BUTTON_UP, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_DOWN, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_LEFT, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_RIGHT, BUTTON_MODE_GPIO);
-  STM_EVAL_PBInit(BUTTON_SEL, BUTTON_MODE_GPIO);
-#else
-  /* Configure the IO Expander */
-  if (IOE_Config())
-  {
-    /* IO Expander config error */
-    while(1);
-  }
-
-#endif  
-     
-/* USARTy configuration ------------------------------------------------------*/
-  /* USARTy configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No ;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  /* Configure the USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-  /* Set the USARTy prescaler */
-  USART_SetPrescaler(USARTy, 0x1);
-  /* Configure the USARTy IrDA mode */
-  USART_IrDAConfig(USARTy, USART_IrDAMode_Normal);
-
-  /* Enable the USARTy IrDA mode */
-  USART_IrDACmd(USARTy, ENABLE);
-
-
-  while (1)
-  {
-    /* Read Key */
-    MyKey = ReadKey();
-
-    switch(MyKey)
-    {
-      case JOY_UP:
-        USART_SendData(USARTy, JOY_UP);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        }
-        break;
-      case JOY_DOWN:
-        USART_SendData(USARTy, JOY_DOWN);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        }
-        break;
-      case JOY_LEFT:
-        USART_SendData(USARTy, JOY_LEFT);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        }
-        break;
-      case JOY_RIGHT:
-        USART_SendData(USARTy, JOY_RIGHT);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        }
-        break;
-      case JOY_SEL:
-        USART_SendData(USARTy, JOY_SEL);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        }
-        break;
-      case JOY_NONE:
-        USART_SendData(USARTy, JOY_NONE);
-        while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-        {
-        } 
-        break;
-      default:
-        break;
-    }
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-  
-  /* Enable USARTy clocks */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Partial Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-#else
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif  
-
-  /* Configure USARTy Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure USARTy Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Reads key from board.
-  * @param  None
-  * @retval Return JOY_RIGHT, JOY_LEFT, JOY_SEL, JOY_UP, JOY_DOWN or JOY_NONE
-  */
-JOYState_TypeDef ReadKey(void)
-{
-#ifndef USE_STM3210C_EVAL
-  /* "right" key is pressed */
-  if(!STM_EVAL_PBGetState(BUTTON_RIGHT))
-  {
-    while(STM_EVAL_PBGetState(BUTTON_RIGHT) == Bit_RESET);
-    return JOY_RIGHT; 
-  }
-  /* "left" key is pressed */
-  if(!STM_EVAL_PBGetState(BUTTON_LEFT))
-  {
-    while(STM_EVAL_PBGetState(BUTTON_LEFT) == Bit_RESET);
-    return JOY_LEFT; 
-  }
-  /* "up" key is pressed */
-  if(!STM_EVAL_PBGetState(BUTTON_UP))
-  {
-    while(STM_EVAL_PBGetState(BUTTON_UP) == Bit_RESET);
-    return JOY_UP; 
-  }
-  /* "down" key is pressed */
-  if(!STM_EVAL_PBGetState(BUTTON_DOWN))
-  {
-    while(STM_EVAL_PBGetState(BUTTON_DOWN) == Bit_RESET);
-    return JOY_DOWN; 
-  }
-  /* "sel" key is pressed */
-  if(!STM_EVAL_PBGetState(BUTTON_SEL))
-  {
-    while(STM_EVAL_PBGetState(BUTTON_SEL) == Bit_RESET);
-    return JOY_SEL; 
-  }
-  /* No key is pressed */
-  else 
-  {
-    return JOY_NONE;
-  }
-#else
-  return IOE_JoyStickGetState();
-#endif  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h
deleted file mode 100644
index cdc0844..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Transmit/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-#ifdef USE_STM3210C_EVAL
- #include "stm3210c_eval_ioe.h"
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL) &&  !defined (USE_STM3210C_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- #define USE_STM32100E_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
-
-  #define USARTy                   USART3
-  #define USARTy_GPIO              GPIOC
-  #define USARTy_CLK               RCC_APB1Periph_USART3
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTy_RxPin             GPIO_Pin_11
-  #define USARTy_TxPin             GPIO_Pin_10
- 
-#elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
-
-  #define USARTy                   USART3
-  #define USARTy_GPIO              GPIOC
-  #define USARTy_CLK               RCC_APB1Periph_USART3
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTy_RxPin             GPIO_Pin_11
-  #define USARTy_TxPin             GPIO_Pin_10
-  
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt
deleted file mode 100644
index c9ea1a8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
-  @page USART_IrDA_Transmit USART IrDA Transmit example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/IrDA/Transmit/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART IrDA Transmit example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication USARTy IrDA transmit mode. Five pins,
-configured in input floating mode, are used to select the byte to be send at 
-each pin state change. USARTy can be USART3 or USART2 depending on the
-STMicroelectronics EVAL board you are using.
-
-These bytes are:
-  - 0x00 if no key (JOY_NONE) pressed
-  - 0x01 if JOY_SEL pin state change
-  - 0x02 if JOY_DOWN pin state change 
-  - 0x03 if JOY_LEFT pin state change 
-  - 0x04 if JOY_RIGHT pin state change 
-  - 0x05 if JOY_UP pin state change 
-
-USARTy configured as follow:
-   - BaudRate = 115200 baud  
-   - Word Length = 8 Bits
-   - One Stop Bit
-   - No parity
-   - Hardware flow control disabled (RTS and CTS signals)
-   - Receive and transmit enabled
-
-The USART IrDA example provides two IrDA program: transmitter&receiver and requires two boards
-to be able to run the full demonstration:
- - one board will act as IrDA transmitter
- - one board will act as IrDA receiver
-
-
-@par Directory contents 
-
-  - USART/IrDA/Transmit/platform_config.h    Evaluation board specific configuration file
-  - USART/IrDA/Transmit/stm32f10x_conf.h     Library Configuration file
-  - USART/IrDA/Transmit/stm32f10x_it.h       Interrupt handlers header file
-  - USART/IrDA/Transmit/stm32f10x_it.c       Interrupt handlers
-  - USART/IrDA/Transmit/main.c               Main program
-  - USART/IrDA/Transmit/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/IrDA/Transmit/platform_config.h or the stm32_eval.h file
-
-  - STM32100E-EVAL Set-up 
-    - Use DOWN push-button connected to pin PD.03
-    - Use UP push-button connected to pin PG.15
-    - Use SEL push-button connected to pin PG.07
-    - Use RIGHT push-button connected to pin PG.13
-    - Use RIGHT push-button connected to pin PG.14   
-    - Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U16 
-      connector, JP15 jumper must be fitted).
-      
-  - STM32100B-EVAL Set-up  
-    - Use DOWN push-button connected to pin PD.14
-    - Use UP push-button connected to pin PD.08
-    - Use SEL push-button connected to pin PD.12
-    - Use RIGHT push-button connected to pin PE.01
-    - Use RIGHT push-button connected to pin PE.00                   
-    - Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U14 
-      connector, JP11 jumper must be fitted).
-
-  - STM3210C-EVAL Set-up 
-    - The JoyStick push buttons are connected to the IO Expander on I2C.  
-    - Use an IrDA transceiver connected to the USART2 Tx and Rx pins (U12 
-      connector, JP16 should be in position 1<-->2).
-          
-  - STM3210E-EVAL Set-up 
-    - Use DOWN push-button connected to pin PD.03
-    - Use UP push-button connected to pin PG.15
-    - Use SEL push-button connected to pin PG.07
-    - Use RIGHT push-button connected to pin PG.13
-    - Use RIGHT push-button connected to pin PG.14   
-    - Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U13 
-      connector, JP21 and JP22 jumper must be fitted).
-
-  - STM3210B-EVAL Set-up  
-    - Use DOWN push-button connected to pin PD.14
-    - Use UP push-button connected to pin PD.08
-    - Use SEL push-button connected to pin PD.12
-    - Use RIGHT push-button connected to pin PE.00
-    - Use RIGHT push-button connected to pin PE.01                   
-    - Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U11 
-      connector, JP5 jumper must be fitted).
-   
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h
deleted file mode 100644
index d40f863..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Transmit/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c
deleted file mode 100644
index e7d47c8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Transmit/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt
deleted file mode 100644
index 42a715c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
-  @page USART_MultiProcessor USART Multi Processor example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/MultiProcessor/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART Multi Processor example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use the USART in multi-processor mode.
-USARTy and USARTz can be USART1 and USART2 or USART2 and USART3 respectively, 
-depending on the STMicroelectronics EVAL board you are using.
-
-First, the USARTy and USARTz address are set to 0x1 and 0x2. The USARTy send 
-continuously the character 0x33 to the USARTz. The USARTz toggle LED1, LED2, LED3 
-and LED4 pins while receiving 0x33.
-
-When a falling edge is applied on BUTTON_KEY EXTI line, an interrupt is generated
-and in the EXTI9_5_IRQHandler routine, the USARTz is entered in mute mode and still
-in this mode (no LED toggling) until a rising edge is applied on BUTTON_WAKEUP 
-EXTI Line 0.
-In this interrupt routine the USARTy send the character of address mark (0x102)
-to wakeup USARTz. The LED restart toggling.
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 9600 baud  
-  - Word Length = 9 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled
-
-@par Directory contents 
-
-  - USART/MultiProcessor/platform_config.h    Evaluation board specific configuration file
-  - USART/MultiProcessor/stm32f10x_conf.h     Library Configuration file
-  - USART/MultiProcessor/stm32f10x_it.h       Interrupt handlers header file
-  - USART/MultiProcessor/stm32f10x_it.c       Interrupt handlers
-  - USART/MultiProcessor/main.c               Main program
-  - USART/MultiProcessor/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/MultiProcessor/platform_config.h or stm32_eval.h file.
-
-  - STM32100E-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN5 and CN10.
-    - Use Key push-button connected to pin PG.08 (EXTI Line8)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07, 
-      PF.08 and PF.09 pins
-      @note Make sure that jumper JP5 is not open.
-            Make sure that jumper JP4 is in position 1<-->2.
-      
-  - STM32100B-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN9 and CN10.
-      @note In this case USART2 Tx and Rx pins are remapped by software on 
-            PD.05 and PD.06 respectively. 
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0) 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins   
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-            Make sure that the Jumper 14 (JP14) is in position 2<-->3. 
-    
-  - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 and CN8.
-    - Use Key push-button connected to pin PG.08 (EXTI Line8)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-      @note Make sure that the Jumper 4 (JP4) is in position 1<-->2. 
-
-  - STM3210B-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN5 and CN6.
-      @note In this case USART2 Tx and Rx pins are remapped by software on 
-            PD.05 and PD.06 respectively. 
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins             
-   
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h
deleted file mode 100644
index e6f5a21..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/MultiProcessor/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c
deleted file mode 100644
index cbd7c97..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Polling
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize   (countof(TxBuffer))
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-uint8_t TxBuffer[] = "Buffer Send from USARTy to USARTz using Flags";
-uint8_t RxBuffer[TxBufferSize];
-__IO uint8_t TxCounter = 0, RxCounter = 0;  
-volatile TestStatus TransferStatus = FAILED;  
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-__IO uint8_t index = 0;
-  
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-/* USARTy and USARTz configuration ------------------------------------------------------*/
-  /* USARTy and USARTz configured as follow:
-        - BaudRate = 230400 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - Even parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 230400;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_Even;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  
-  /* Configure USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-  /* Configure USARTz */
-  USART_Init(USARTz, &USART_InitStructure);
-  
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-
-  /* Enable the USARTz */
-  USART_Cmd(USARTz, ENABLE);
-
-  while(TxCounter < TxBufferSize)
-  {   
-    /* Send one byte from USARTy to USARTz */
-    USART_SendData(USARTy, TxBuffer[TxCounter++]);
-    
-    /* Loop until USARTy DR register is empty */ 
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
-    {
-    }
-    
-    /* Loop until the USARTz Receive Data Register is not empty */
-    while(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) == RESET)
-    {
-    }
-
-    /* Store the received byte in RxBuffer */
-    RxBuffer[RxCounter++] = (USART_ReceiveData(USARTz) & 0x7F);  
-    
-  } 
-  /* Check the received data with the send ones */
-  TransferStatus = Buffercmp(TxBuffer, RxBuffer, TxBufferSize);
-  /* TransferStatus = PASSED, if the data transmitted from USARTy and  
-     received by USARTz are the same */
-  /* TransferStatus = FAILED, if the data transmitted from USARTy and 
-     received by USARTz are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{    
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-#ifndef USE_STM3210C_EVAL
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-#else
-  /* Enable USARTy Clock */
-  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
-#endif
-  /* Enable USARTz Clock */
-  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
-  
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
-#elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
-  /* Enable the USART2 Pins Software Remapping */
-  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-#endif
-
-  /* Configure USARTy Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-  
-  /* Configure USARTz Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
-  
-  /* Configure USARTy Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTz Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
-  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); 
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h
deleted file mode 100644
index 6537dfe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)&&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- #define USE_STM3210C_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL) 
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-
-#elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h
deleted file mode 100644
index ec079bb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c
deleted file mode 100644
index eca689b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Polling
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h
deleted file mode 100644
index d3f6cae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c
deleted file mode 100644
index d5f4697..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h
deleted file mode 100644
index 8e6a316..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file USART/Printf/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c
deleted file mode 100644
index 98947eb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Printf/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Printf
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h
deleted file mode 100644
index b87cab2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Printf/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c
deleted file mode 100644
index 7d87bc2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Printf/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
deleted file mode 100644
index dc1832a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Smartcard/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/* Private define ------------------------------------------------------------*/
-#define T0_PROTOCOL           0x00 /* T0 PROTOCOL */
-#define SETUP_LENGHT          20 
-#define HIST_LENGHT           20
-#define SC_Receive_Timeout    0x4000 /* direction to reader */
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Smartcard
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* ATR STRUCTURE - ANSWER TO RESET */
-typedef  struct 
-{
-  uint8_t TS; /* Bit Convention */
-  uint8_t T0; /* High Nibble = N. of setup byte; low nibble = N. of historical byte */
-  uint8_t T[SETUP_LENGHT]; /* Setup array */
-  uint8_t H[HIST_LENGHT]; /* Historical array */
-  uint8_t Tlenght; /* Setup array dimension */
-  uint8_t Hlenght; /* Historical array dimension */
-} SC_ATR;
-
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-USART_ClockInitTypeDef USART_ClockInitStructure; 
-SC_ATR  SC_A2R;
-__IO uint32_t index = 0, Counter = 0;
-volatile TestStatus ATRDecodeStatus = FAILED;
-__IO uint32_t CardInserted = 0, CardProtocol = 1;
-
-__IO uint8_t DST_Buffer[50]= {
-                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void EXTI_Configuration(void);
-void NVIC_Configuration(void);
-uint8_t SC_decode_Answer2reset(__IO uint8_t *card);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-       
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Configure the EXTI Controller */
-  EXTI_Configuration();
-
-
-/* SC_USART configuration ----------------------------------------------------*/
-  /* SC_USART configured as follow:
-        - Word Length = 9 Bits
-        - 0.5 Stop Bit
-        - Even parity
-        - BaudRate = 12096 baud
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Tx and Rx enabled
-        - USART Clock enabled
-        - USART CPOL Low
-        - USART CPHA on first edge
-        - USART Last Bit Clock Enabled
-  */
-
-  /* SC_USART Clock set to 4.5MHz (PCLK1 = 36 MHZ / 8) */
-  USART_SetPrescaler(SC_USART, 0x04);
-  /* SC_USART Guard Time set to 2 Bit */
-  USART_SetGuardTime(SC_USART, 0x2);
-  
-  USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
-  USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
-  USART_ClockInitStructure.USART_CPHA = USART_CPHA_1Edge;
-  USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
-  USART_ClockInit(SC_USART, &USART_ClockInitStructure);
-
-  USART_InitStructure.USART_BaudRate = 12096;
-  USART_InitStructure.USART_WordLength = USART_WordLength_9b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
-  USART_InitStructure.USART_Parity = USART_Parity_Even;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_Init(SC_USART, &USART_InitStructure);  
-
-  /* Enable the SC_USART Parity Error Interrupt */
-  USART_ITConfig(SC_USART, USART_IT_PE, ENABLE);
-
-  /* Enable SC_USART */
-  USART_Cmd(SC_USART, ENABLE);
-
-  /* Enable the NACK Transmission */
-  USART_SmartCardNACKCmd(SC_USART, ENABLE);
-
-  /* Enable the Smartcard Interface */
-  USART_SmartCardCmd(SC_USART, ENABLE);
-
-  /* Loop while no Smartcard is detected */  
-  while(CardInserted == 0)
-  {
-  }
-
-  /* Read Smartcard ATR response */ 
-  for(index = 0; index < 40; index++, Counter = 0)
-  {
-    while((USART_GetFlagStatus(SC_USART, USART_FLAG_RXNE) == RESET) && (Counter != SC_Receive_Timeout))
-    {
-      Counter++;
-    }
-
-    if(Counter != SC_Receive_Timeout)
-    {
-      DST_Buffer[index] = USART_ReceiveData(SC_USART);
-    }
-  }
-
-  /* Decode ATR */
-  CardProtocol = SC_decode_Answer2reset(DST_Buffer);
-
-  /* Test if the inserted card is ISO7816-3 T=0 compatible */
-  if(CardProtocol == 0)
-  {
-    /* Inserted card is ISO7816-3 T=0 compatible */
-    ATRDecodeStatus = PASSED;
-  }
-  else 
-  { 
-    /* Inserted Smartcard is not ISO7816-3 T=0 compatible */
-    ATRDecodeStatus = FAILED;
-  } 
-
-  while (1)
-  {   
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* Enable GPIO_3_5V, SC_USART_GPIO_CLK, GPIO_CMDVCC, GPIO_RESET, GPIO_OFF and 
-     AFIO clocks */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_3_5V | SC_USART_GPIO_CLK | RCC_APB2Periph_RESET | 
-                         RCC_APB2Periph_CMDVCC | RCC_APB2Periph_OFF | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable SC_USART clocks */
-  RCC_APB1PeriphClockCmd(SC_USART_CLK, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef USE_STM3210C_EVAL
-  /* Enable the USART3 Pins Software Full Remapping */
-  GPIO_PinRemapConfig(GPIO_FullRemap_USART3, ENABLE);
-#endif
-  /* Configure SC_USART CK as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = SC_USART_ClkPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SC_USART_GPIO, &GPIO_InitStructure);
-
-  /* Configure SC_USART Tx as alternate function open-drain */
-  GPIO_InitStructure.GPIO_Pin = SC_USART_TxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(SC_USART_GPIO, &GPIO_InitStructure);
-
-  /* Configure Smartcard Reset  */
-  GPIO_InitStructure.GPIO_Pin = SC_RESET;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(GPIO_RESET, &GPIO_InitStructure);
-
-  /* Set RSTIN HIGH */  
-  GPIO_SetBits(GPIO_RESET, SC_RESET);
-
-  /* Configure Smartcard 3/5V  */
-  GPIO_InitStructure.GPIO_Pin = SC_3_5V;
-  GPIO_Init(GPIO_3_5V, &GPIO_InitStructure);
-
-  /* Select 5 V */  
-  GPIO_SetBits(GPIO_3_5V, SC_3_5V);
-
-  /* Configure Smartcard CMDVCC  */
-  GPIO_InitStructure.GPIO_Pin = SC_CMDVCC;
-  GPIO_Init(GPIO_CMDVCC, &GPIO_InitStructure);
-
-  /* Select Smartcard CMDVCC */ 
-  GPIO_SetBits(GPIO_CMDVCC, SC_CMDVCC);
-
-  /* Select Smartcard OFF */
-  GPIO_InitStructure.GPIO_Pin = SC_OFF;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIO_OFF, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures the External Interrupts controller.
-  * @param  None
-  * @retval None
-  */
-void EXTI_Configuration(void)
-{
-  EXTI_InitTypeDef EXTI_InitStructure;
-
-  /* Smartcard OFF */
-  GPIO_EXTILineConfig(SC_PortSource, SC_PinSource);
-
-  EXTI_StructInit(&EXTI_InitStructure);
-  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
-  EXTI_InitStructure.EXTI_Line = SC_EXTI;
-  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-  EXTI_Init(&EXTI_InitStructure);
-
-  /* Clear SC EXTI Line Pending Bit */
-  EXTI_ClearITPendingBit(SC_EXTI);
-}
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure the NVIC Preemption Priority Bits */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-  /* Clear the SC_EXTI IRQ Pending Bit */
-  NVIC_ClearPendingIRQ(SC_EXTI_IRQ);
-
-  NVIC_InitStructure.NVIC_IRQChannel = SC_EXTI_IRQ;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  NVIC_InitStructure.NVIC_IRQChannel = SC_USART_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Decode the Card ATR Response.
-  * @param  card: pointer to the buffer containing the Card ATR.
-  * @retval Card protocol
-  */
-uint8_t SC_decode_Answer2reset(__IO uint8_t *card)
-{
-  uint32_t i = 0, flag = 0, buf = 0, protocol = 0;
-
-  SC_A2R.TS = 0;
-  SC_A2R.T0 = 0;
-  for (i = 0; i < SETUP_LENGHT; i++)
-  {
-    SC_A2R.T[i] = 0;
-  }
-  for (i = 0;i < HIST_LENGHT; i++)
-  {
-    SC_A2R.H[i] = 0;
-  }
-  SC_A2R.Tlenght = 0;
-  SC_A2R.Hlenght = 0;
-
-  SC_A2R.TS = card[0]; /* INITIAL CHARACTER */
-  SC_A2R.T0 = card[1]; /* FORMAT CHARACTER */
-
-  SC_A2R.Hlenght = SC_A2R.T0 & 0x0F;
-
-  if((SC_A2R.T0 & 0x80) == 0x80) flag = 1;
-
-  for(i = 0; i < 4; i++)
-  {
-    SC_A2R.Tlenght = SC_A2R.Tlenght + (((SC_A2R.T0 & 0xF0) >> (4 + i)) & 0x1);
-  }
-
-  for(i = 0; i < SC_A2R.Tlenght; i++)
-  {
-    SC_A2R.T[i] = card[i + 2];
-  }
-
-  protocol = SC_A2R.T[SC_A2R.Tlenght - 1] & 0x0F; 
-
-  while(flag) 
-  {
-    if ((SC_A2R.T[SC_A2R.Tlenght-1] & 0x80)== 0x80)
-    {
-      flag = 1;
-    }
-    else
-    {
-      flag = 0;
-    }
-    buf = SC_A2R.Tlenght;
-    SC_A2R.Tlenght = 0;
-
-    for(i = 0; i < 4; i++)
-    {
-      SC_A2R.Tlenght = SC_A2R.Tlenght + (((SC_A2R.T[buf - 1] & 0xF0) >> (4 + i)) & 0x1);
-    }
-    for(i = 0; i < SC_A2R.Tlenght; i++)
-    {
-      SC_A2R.T[buf + i] = card[i + 2 + buf];
-    }
-    SC_A2R.Tlenght += buf;
-  }
-
-  for(i = 0;i < SC_A2R.Hlenght; i++)
-  {
-    SC_A2R.H[i] = card[i + 2 + SC_A2R.Tlenght];
-  }
-  
-  return ((uint8_t)protocol);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h
deleted file mode 100644
index e90404d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Smartcard/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- #define USE_STM3210C_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#ifdef USE_STM3210B_EVAL
-  /* Smartcard Inteface USART pins */
-  #define SC_USART                 USART3
-  #define SC_USART_GPIO            GPIOB
-  #define SC_USART_CLK             RCC_APB1Periph_USART3
-  #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOB
-  #define SC_USART_TxPin           GPIO_Pin_10
-  #define SC_USART_ClkPin          GPIO_Pin_12
-  #define SC_USART_IRQn            USART3_IRQn
-  #define SC_USART_IRQHandler      USART3_IRQHandler  
-  /* Smartcard Inteface GPIO pins */
-  #define SC_3_5V                  GPIO_Pin_11 /* GPIOD Pin 11 */
-  #define SC_RESET                 GPIO_Pin_11 /* GPIOB Pin 11 */
-  #define SC_CMDVCC                GPIO_Pin_7  /* GPIOE Pin 7  */
-  #define SC_OFF                   GPIO_Pin_14 /* GPIOE Pin 14 */
-  #define GPIO_3_5V                GPIOD
-  #define GPIO_RESET               GPIOB
-  #define GPIO_CMDVCC              GPIOE
-  #define GPIO_OFF                 GPIOE
-  #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOD
-  #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOB
-  #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOE
-  #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOE
-  #define SC_EXTI                  EXTI_Line14
-  #define SC_PortSource            GPIO_PortSourceGPIOE
-  #define SC_PinSource             GPIO_PinSource14
-  #define SC_EXTI_IRQ              EXTI15_10_IRQn
-#elif defined USE_STM3210E_EVAL
-  /* Smartcard Inteface USART pins */
-  #define SC_USART                 USART3
-  #define SC_USART_GPIO            GPIOB
-  #define SC_USART_CLK             RCC_APB1Periph_USART3
-  #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOB
-  #define SC_USART_TxPin           GPIO_Pin_10
-  #define SC_USART_ClkPin          GPIO_Pin_12
-  #define SC_USART_IRQn            USART3_IRQn 
-  #define SC_USART_IRQHandler      USART3_IRQHandler    
-  /* Smartcard Inteface GPIO pins */
-  #define SC_3_5V                  GPIO_Pin_0  /* GPIOB Pin 0 */
-  #define SC_RESET                 GPIO_Pin_11 /* GPIOB Pin 11 */
-  #define SC_CMDVCC                GPIO_Pin_6  /* GPIOC Pin 6  */
-  #define SC_OFF                   GPIO_Pin_7  /* GPIOC Pin 7 */ 
-  #define GPIO_3_5V                GPIOB
-  #define GPIO_RESET               GPIOB
-  #define GPIO_CMDVCC              GPIOC
-  #define GPIO_OFF                 GPIOC
-  #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOB
-  #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOB
-  #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOC
-  #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOC
-  #define SC_EXTI                  EXTI_Line7
-  #define SC_PortSource            GPIO_PortSourceGPIOC
-  #define SC_PinSource             GPIO_PinSource7
-  #define SC_EXTI_IRQ              EXTI9_5_IRQn
-#elif defined USE_STM3210C_EVAL
-  /* Smartcard Inteface USART pins */
-  #define SC_USART                 USART3
-  #define SC_USART_GPIO            GPIOD
-  #define SC_USART_CLK             RCC_APB1Periph_USART3
-  #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOD
-  #define SC_USART_TxPin           GPIO_Pin_8
-  #define SC_USART_ClkPin          GPIO_Pin_10
-  #define SC_USART_IRQn            USART3_IRQn 
-  #define SC_USART_IRQHandler      USART3_IRQHandler    
-  /* Smartcard Inteface GPIO pins */
-  #define SC_3_5V                  GPIO_Pin_0  /* GPIOC Pin 0 */
-  #define SC_RESET                 GPIO_Pin_9  /* GPIOD Pin 9 */
-  #define SC_CMDVCC                GPIO_Pin_7  /* GPIOD Pin 7  */
-  #define SC_OFF                   GPIO_Pin_7  /* GPIOE Pin 7 */ 
-  #define GPIO_3_5V                GPIOC
-  #define GPIO_RESET               GPIOD
-  #define GPIO_CMDVCC              GPIOD
-  #define GPIO_OFF                 GPIOE
-  #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOC
-  #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOD
-  #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOD
-  #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOE
-  #define SC_EXTI                  EXTI_Line7
-  #define SC_PortSource            GPIO_PortSourceGPIOE
-  #define SC_PinSource             GPIO_PinSource7
-  #define SC_EXTI_IRQ              EXTI9_5_IRQn  
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
deleted file mode 100644
index b0bad82..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Smartcard/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI9_5_IRQHandler(void);
-void USART3_IRQHandler(void);
-void EXTI15_10_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c
deleted file mode 100644
index 0a043eb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Smartcard/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
deleted file mode 100644
index e00afbe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Synchronous
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-#define DYMMY_BYTE      0x00
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-USART_ClockInitTypeDef USART_ClockInitStructure; 
-
-uint8_t TxBuffer1[] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags";
-uint8_t TxBuffer2[] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags";
-uint8_t RxBuffer1[TxBufferSize2];
-uint8_t RxBuffer2[TxBufferSize1];
-__IO uint8_t NbrOfDataToRead1 = TxBufferSize2;
-__IO uint8_t NbrOfDataToRead2 = TxBufferSize1;
-__IO uint8_t TxCounter1 = 0, RxCounter1 = 0;
-__IO uint8_t TxCounter2 = 0, RxCounter2 = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; 
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void SPI_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Configure the SPI */
-  SPI_Configuration();
-
-/* USARTy configuration ------------------------------------------------------*/
-  /* USARTy configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-        - USART Clock Enabled
-        - USART CPOL: Clock is active High
-        - USART CPHA: Data is captured on the second edge 
-        - USART LastBit: The clock pulse of the last data bit is output to 
-                         the SCLK pin
-  */
-  USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
-  USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
-  USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
-  USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
-  USART_ClockInit(USARTy, &USART_ClockInitStructure);
-
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No ;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_Init(USARTy, &USART_InitStructure);
-  
-  /* Configure the USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-
-  while(NbrOfDataToRead2--)
-  {
-    /* Write one byte in the USARTy Transmit Data Register */
-    USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
-    {
-    }
-    /* Wait the byte is entirely received by SPIy */  
-    while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer2 */
-    RxBuffer2[RxCounter2++] = SPI_I2S_ReceiveData(SPIy);
-  }
-
-  /* Clear the USARTy Data Register */
-  USART_ReceiveData(USARTy);
-
-  while(NbrOfDataToRead1--)
-  {
-    /* Wait until end of transmit */
-    while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_TXE)== RESET)
-    {
-    }
-    /* Write one byte in the SPIy Transmit Data Register */
-    SPI_I2S_SendData(SPIy, TxBuffer2[TxCounter2++]);
-
-    /* Send a Dummy byte to generate clock to slave */ 
-    USART_SendData(USARTy, DYMMY_BYTE);
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
-    {
-    }
-    /* Wait the byte is entirely received by USARTy */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer1 */
-    RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
-  /* TransferStatus = PASSED, if the data transmitted from USARTy and  
-     received by SPIy are the same */
-  /* TransferStatus = FAILED, if the data transmitted from USARTy and 
-     received by SPIy are different */
-  TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
-  /* TransferStatus = PASSED, if the data transmitted from SPIy and  
-     received by USARTy are the same */
-  /* TransferStatus = FAILED, if the data transmitted from SPIy and 
-     received by USARTy are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | SPIy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-  /* Enable SPIy Clock */
-  RCC_APB2PeriphClockCmd(SPIy_CLK, ENABLE);    
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure USARTy TX and USARTy CK pins as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin | USARTy_ClkPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure SPI1 pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPIy_SCKPin | SPIy_MISOPin | SPIy_MOSIPin;
-  GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTy RX as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures the SPI.
-  * @param  None
-  * @retval None
-  */
-void SPI_Configuration(void)
-{
-  SPI_InitTypeDef SPI_InitStructure;
-
-  SPI_StructInit(&SPI_InitStructure);
-
-  SPI_I2S_DeInit(SPIy);
-
-  /* SPIy Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
-  
-  /* Configure SPIy */
-  SPI_Init(SPIy, &SPI_InitStructure);
-
-  /* SPIy enable */
-  SPI_Cmd(SPIy, ENABLE);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/readme.txt
deleted file mode 100644
index 7d8dffd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/readme.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
-  @page USART_Synchronous USART Synchronous example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/Synchronous/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART Synchronous example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic communication between USARTy (Synchronous mode) 
-and SPIy using flags. USARTy and SPIy can be USART1 and SPI1 or USART2 and SPI3,
-depending on the STMicroelectronics EVAL board you are using.
-
-First, the USARTy sends data from TxBuffer1 buffer to SPIy using USARTy TXE flag.
-Data received, using RXNE flag, by SPIy is stored in RxBuffer2 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus1" 
-variable.
- 
-Then, the SPIy sends data from TxBuffer2 buffer to USARTy using SPIy TXE flag.
-Data received, using RXNE flag, by USARTy is stored in RxBuffer1 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus2" 
-variable.
-
-USARTy configured as follow:
-  - BaudRate = 115200 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled
-  - USART Clock enabled
-  - USART CPOL: Clock is active high
-  - USART CPHA: Data is captured on the second edge 
-  - USART LastBit: The clock pulse of the last data bit is output to the SCLK pin
-
-SPIy configured as follow:
-  - Direction = 2 Lines FullDuplex
-  - Mode = Slave Mode
-  - DataSize = 8 Bits
-  - CPOL = Clock is active high
-  - CPHA = Data is captured on the second edge 
-  - NSS = NSS Software
-  - First Bit = First Bit is the LSB  
-
-
-@par Directory contents 
-  
-  - USART/Synchronous/platform_config.h    Evaluation board specific configuration file
-  - USART/Synchronous/stm32f10x_conf.h     Library Configuration file
-  - USART/Synchronous/stm32f10x_it.h       Interrupt handlers header file
-  - USART/Synchronous/stm32f10x_it.c       Interrupt handlers
-  - USART/Synchronous/main.c               Main program
-  - USART/Synchronous/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL 
-    (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation 
-    boards and can be easily tailored to any other supported device and development 
-    board.
-    This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation
-    board since the USART CK pins are already used by other on-board modules.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/Synchronous/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).  
-      
-  - STM32100B-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).      
-
-  - STM3210E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
-
-  - STM3210B-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).        
- 
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h
deleted file mode 100644
index 317f17f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c
deleted file mode 100644
index 619e4e9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Synchronous
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h
deleted file mode 100644
index fd123d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c
deleted file mode 100644
index ba73f42..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
deleted file mode 100644
index e95ba1f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    WWDG/WWDG_Reset/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup WWDG_Reset
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t TimingDelay = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize LED1 and Key Button mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
-
-
-  /* Check if the system has resumed from WWDG reset */
-  if (RCC_GetFlagStatus(RCC_FLAG_WWDGRST) != RESET)
-  { 
-    /* WWDGRST flag set */
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-
-    /* Clear reset flags */
-    RCC_ClearFlag();
-  }
-  else
-  {
-    /* WWDGRST flag is not set */
-    /* Turn off LED1 */
-    STM_EVAL_LEDOff(LED1);
-  }
-
-  /* Setup SysTick Timer for 1 msec interrupts  */
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  /* WWDG configuration */
-  /* Enable WWDG clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);
-
-/* On Value line devices, WWDG clock counter = (PCLK1 (24MHz)/4096)/8 = 732 Hz (~1366 us)  */
-/* On other devices, WWDG clock counter = (PCLK1(36MHz)/4096)/8 = 1099 Hz (~910 us)  */
-  WWDG_SetPrescaler(WWDG_Prescaler_8);
-
-  /* Set Window value to 80; WWDG counter should be refreshed only when the counter
-    is below 80 (and greater than 64) otherwise a reset will be generated */
-  WWDG_SetWindowValue(80);
-
-  /* - On Value line devices,
-    Enable WWDG and set counter value to 127, WWDG timeout = ~1366 us * 64 = 87.42 ms 
-    In this case the refresh window is: ~1366us * (127-80) = 64.20 ms < refresh window < ~1366us * 64 = 87.42ms
-     - On other devices
-    Enable WWDG and set counter value to 127, WWDG timeout = ~910 us * 64 = 58.25 ms 
-    In this case the refresh window is: ~910 us * (127-80) = 42.77 ms < refresh window < ~910 us * 64 = 58.25ms     
-  */
-  WWDG_Enable(127);
-   
-  while (1)
-  {
-    /* Toggle LED2 */
-    STM_EVAL_LEDToggle(LED2);
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) 
-    /* Insert 44 ms delay */
-    Delay(44);
-#else
-    /* Insert 66 ms delay */
-    Delay(66);
-#endif    
-
-    /* Update WWDG counter */
-    WWDG_SetCounter(127);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{ 
-  TimingDelay = nTime;
-  while(TimingDelay != 0)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/readme.txt
deleted file mode 100644
index 269ff89..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/readme.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
-  @page WWDG_Reset WWDG Reset example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    WWDG/WWDG_Reset/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the WWDG Reset example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to update at regular period the WWDG counter and how to
-simulate a software fault generating an MCU WWDG reset on expiry of a programmed 
-time period.
-
-The WWDG timeout is set to 65.53ms and the refresh window is set to 80. 
-The WWDG counter is refreshed each 50ms in the main program infinite loop to 
-prevent a WWDG reset.
-LED2 is also toggled each 50ms indicating that the program is running.
-
-An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
-on the rising edge of the signal.
-
-The EXTI Line is used to simulate a software failure: once the EXTI Line event 
-occurs, by pressing the Key push-button, the corresponding interrupt is served.
-In the ISR, a write to invalid address generates a Hardfault exception containing
-an infinite loop and preventing to return to main program (the WWDG counter is 
-not refreshed).
-As a result, when the WWDG counter falls to 63, the WWDG reset occurs.
-If the WWDG reset is generated, after the system resumes from reset, LED1 turns on.
-
-If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed
-in the main program infinite loop, and there is no WWDG reset.
-
-In this example the system clock is set to 24 MHz on Value line devices and to 
-72 MHz on other devices.
-
-
-@par Directory contents
- 
-  - WWDG/WWDG_Reset/stm32f10x_conf.h     Library Configuration file
-  - WWDG/WWDG_Reset/stm32f10x_it.c       Interrupt handlers
-  - WWDG/WWDG_Reset/stm32f10x_it.h       Header for stm32f10x_it.c
-  - WWDG/WWDG_Reset/main.c               Main program
-  - WWDG/WWDG_Reset/system_stm32f10x.c   STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density)and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
-    
-  - STM32100B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1 and LD2 connected respectively to PD.07 and PD.13 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    
-  - STM3210E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-     
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h
deleted file mode 100644
index 3ec9eee..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    WWDG/WWDG_Reset/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
deleted file mode 100644
index 55a2615..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    WWDG/WWDG_Reset/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup WWDG_Reset
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern __IO uint32_t TimingDelay;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-  TimingDelay--;
-}
-
-/******************************************************************************/
-/*            STM32F10x Peripherals Interrupt Handlers                        */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles External lines 9 to 5 interrupt request.
-  * @param  None
-  * @retval None
-  */
-void EXTI9_5_IRQHandler(void)
-{
-  if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
-  {  
-    /* Clear the Key Button EXTI Line Pending Bit */
-    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
-    
-    /* As the following address is invalid (not mapped), a Hardfault exception
-	  will be generated with an infinite loop and when the WWDG counter falls to 63
-    the WWDG reset occurs */
- 	  *(__IO uint32_t *) 0x000000FF = 0xFF;
-  }
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
deleted file mode 100644
index 8fc68df..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    WWDG/WWDG_Reset/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void EXTI9_5_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c
deleted file mode 100644
index 8607cd2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    WWDG/WWDG_Reset/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd
deleted file mode 100644
index 8a9044b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd
+++ /dev/null
@@ -1,4555 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<project>
-  <fileVersion>2</fileVersion>
-  <configuration>
-    <name>STM32100B-EVAL</name>
-    <toolchain>
-      <name>ARM</name>
-    </toolchain>
-    <debug>1</debug>
-    <settings>
-      <name>C-SPY</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>22</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CInput</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CEndian</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCVariant</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MacFile</name>
-          <state></state>
-        </option>
-        <option>
-          <name>MemOverride</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>MemFile</name>
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f100xb.ddf</state>
-        </option>
-        <option>
-          <name>RunToEnable</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>RunToName</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CExtraOptionsCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CExtraOptions</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CFpuProcessor</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCDDFArgumentProducer</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCDownloadSuppressDownload</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDownloadVerifyAll</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCProductVersion</name>
-          <state>5.30.0.51236</state>
-        </option>
-        <option>
-          <name>OCDynDriverList</name>
-          <state>JLINK_ID</state>
-        </option>
-        <option>
-          <name>OCLastSavedByProductVersion</name>
-          <state>5.50.5.51996</state>
-        </option>
-        <option>
-          <name>OCDownloadAttachToProgram</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>UseFlashLoader</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CLowLevel</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCBE8Slave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>MacFile2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>CDevice</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>FlashLoadersV3</name>
-          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F100xB.board</state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesSuppressCheck3</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesPath3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OverrideDefFlashBoard</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesOffset1</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset2</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesOffset3</name>
-          <state></state>
-        </option>
-        <option>
-          <name>OCImagesUse1</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCImagesUse3</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ARMSIM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>1</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCSimDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OCSimEnablePSP</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspOverrideConfig</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCSimPspConfigFile</name>
-          <state></state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>ANGEL_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CCAngelHeartbeat</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommunication</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CAngelCommBaud</name>
-          <version>0</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>CAngelCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ANGELTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoAngelLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>AngelLogFile</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>GDBSERVER_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJTagBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJTagUpdateBreakpoints</name>
-          <state>main</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>IARROM_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>0</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>CRomLogFileCheck</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomLogFileEditB</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CRomCommunication</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CRomCommBaud</name>
-          <version>0</version>
-          <state>7</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>JLINK_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>11</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>JLinkSpeed</name>
-          <state>32</state>
-        </option>
-        <option>
-          <name>CCJLinkDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkLogFile</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCJLinkHWResetDelay</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>JLinkInitialSpeed</name>
-          <state>32</state>
-        </option>
-        <option>
-          <name>CCDoJlinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCScanChainNonARMDevices</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkIRLength</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkCommRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkTCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>CCJLinkSpeedRadioV2</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCUSBDevice</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchUndef</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchSWI</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchData</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchPrefetch</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchIRQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCRDICatchFIQ</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkBreakpointRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkDoUpdateBreakpoints</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCJLinkUpdateBreakpoints</name>
-          <state>main</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCJLinkAttachSlave</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>CCJLinkResetList</name>
-          <version>2</version>
-          <state>7</state>
-        </option>
-        <option>
-          <name>CCJLinkInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCORERESET</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchMMERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchNOCPERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchCHRERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchSTATERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchBUSERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchINTERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchHARDERR</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCCatchDummy</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>LMIFTDI_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>2</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>LmiftdiSpeed</name>
-          <state>500</state>
-        </option>
-        <option>
-          <name>CCLmiftdiDoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiftdiLogFile</name>
-          <state>$PROJ_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceRadio</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CCLmiFtdiInterfaceCmdLine</name>
-          <state>0</state>
-        </option>
-      </data>
-    </settings>
-    <settings>
-      <name>MACRAIGOR_ID</name>
-      <archiveVersion>2</archiveVersion>
-      <data>
-        <version>3</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>jtag</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuSpeed</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>TCPIP</name>
-          <state>aaa.bbb.ccc.ddd</state>
-        </option>
-        <option>
-          <name>DoLogfile</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>LogFile</name>
-          <state>$TOOLKIT_DIR$\cspycomm.log</state>
-        </option>
-        <option>
-          <name>DoEmuMultiTarget</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>EmuMultiTarget</name>
-          <state>0@ARM7TDMI</state>
-        </option>
-        <option>
-          <name>EmuHWReset</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CEmuCommBaud</name>
-          <version>0</version>
-          <state>4</state>
-        </option>
-        <option>
-          <name>CEmuCommPort</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>jtago</name>
-          <version>0</version>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OCDriverInfo</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>UnusedAddr</name>
-          <state>0x00800000</state>
-        </option>
-        <option>
-          <name>CCMacraigorHWResetDelay</name>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp
deleted file mode 100644
index a3650ae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp
+++ /dev/null
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-        <configuration>STM3210E-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-        <configuration>STM3210E-EVAL_XL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nand.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nor.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_sram.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_lcd.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\stm32_eval.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_ee.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210E-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-        <configuration>STM3210E-EVAL_XL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c</name>
-      <excluded>
-        <configuration>STM3210C-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_sdio_sd.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-        <configuration>STM3210B-EVAL</configuration>
-        <configuration>STM32100E-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210C-EVAL</configuration>
-      </excluded>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c</name>
-      <excluded>
-        <configuration>STM32100B-EVAL</configuration>
-        <configuration>STM3210E-EVAL</configuration>
-        <configuration>STM3210E-EVAL_XL</configuration>
-      </excluded>
-    </file>
-  </group>
-  <group>
-    <name>User</name>
-    <file>
-      <name>$PROJ_DIR$\..\main.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\..\stm32f10x_it.c</name>
-    </file>
-  </group>
-</project>
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww
deleted file mode 100644
index e0fd14b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww
+++ /dev/null
@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
-  <project>
-    <path>$WS_DIR$\Project.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt
deleted file mode 100644
index 1127522..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  @page ewarm EWARM Project Template
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with IAR Embedded Workbench for ARM (EWARM)
-  *          software toolchain (version 5.50 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
-
- - project .ewd/.eww/.ewp: A pre-configured project file with the provided library 
-                           structure that produces an executable image with IAR 
-                           Embedded Workbench.
-                
- - stm32f10x_flash.icf : This file is the IAR Linker configuration file used to 
-                         place program code (readonly) in internal FLASH and data
-                         (readwrite, Stack and Heap)in internal SRAM. 
-                         You can customize this file to your need.                    
-                      
- - stm32f10x_flash_extsram.icf: This file is the IAR Linker configuration file 
-                                used to place program code (readonly) in internal 
-                                FLASH and data (readwrite, Stack and Heap)in 
-                                external SRAM. You can customize this file to your need.  
-                                This file is used only with STM32 High-density devices.
-
- - stm32f10x_nor.icf:  This file is the IAR Linker configuration file used to 
-                       place program code (readonly) in external NOR FLASH and data
-                       (readwrite, Stack and Heap)in internal SRAM. 
-                       You can customize this file to your need. 
-                       This file is used only with STM32 High-density devices.                                           
-
- - stm32f10x_ram.icf:  This file is the IAR Linker configuration file used to 
-                       place program code (readonly) and data (readwrite, Stack 
-                       and Heap)in internal SRAM. 
-                       You can customize this file to your need.                    
-                             
- @par How to use it ?
-
- - Open the Project.eww workspace.
- - In the workspace toolbar select the project config:
-     - STM32100B-EVAL: to configure the project for STM32 Medium-density Value 
-       line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL
-           
-     - STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
-
-     - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL
-
-     - STM3210E-EVAL: to configure the project for STM32 High-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL
-
-     - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL
-
-     - STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL           
-
- - Rebuild all files: Project->Rebuild all
- - Load project image: Project->Debug
- - Run program: Debug->Go(F5)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 32 and 128 Kbytes.
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes. 
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.      
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash_extsram.icf b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash_extsram.icf
deleted file mode 100644
index 5e0a239..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash_extsram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__       = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__         = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__       = 0x68000000;
-define symbol __ICFEDIT_region_RAM_end__         = 0x680FFFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__]; /* EXTSRAM_region */
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   {readwrite, block CSTACK, block HEAP }; /* EXTSRAM_region */
-
-                        
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_nor.icf b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_nor.icf
deleted file mode 100644
index 99c15be..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_nor.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x64000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x64000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x64FFFFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf
deleted file mode 100644
index 6aeaf65..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__     = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp
deleted file mode 100644
index b85d35a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp
+++ /dev/null
@@ -1,1152 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F100VB.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722788" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325438" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954578" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="0" y="0"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="787" cy="578"></Size>
-				<Position x="-4" y="-23"></Position>
-			</Rectangle>
-			<Tabs Count="1" Active="0">
-				<Tab Pos="0" PosX="0" PosY="0" Module="readme.txt" TopLine="1" FilePath="$(PROJECTDIR)\readme.txt" Application="Project"/>
-			</Tabs>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-						<Column Id="14" Order="2" Title="Type" Visible="1" RelWidth="0.3856508" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941628" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000448" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059268" Alignment="LEFT"/>
-						<Watches/>
-						<Column Id="14" Order="3" Title="Type" Visible="1" RelWidth="0.3359388" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="_lc_ub_stack"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08000080" Symbol="0x08000080"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x00000000" Symbol="_lc_t2_longveneertarget"/>
-						</Memory>
-						<Header Bold="1"/>
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-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."/>
-							<Control Id="40398" Class="CXTPControlButton"/>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter=".\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText=".\\Settings\\reset_appl.scr"/>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter=".\\Settings\\reset_go_main.scr" TooltipText=".\\Settings\\reset_go_main.scr"/>
-							<Control Id="10053" Class="CControlScriptButton"/>
-							<Control Id="10054" Class="CControlScriptButton"/>
-							<Control Id="10055" Class="CControlScriptButton"/>
-							<Control Id="10056" Class="CControlScriptButton"/>
-							<Control Id="10057" Class="CControlScriptButton"/>
-							<Control Id="10058" Class="CControlScriptButton"/>
-							<Control Id="10059" Class="CControlScriptButton"/>
-							<Control Id="10060" Class="CControlScriptButton"/>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."/>
-								<Control Id="40398" Class="CXTPControlButton"/>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"/>
-								<Control Id="10052" Class="CControlScriptButton"/>
-								<Control Id="10053" Class="CControlScriptButton"/>
-								<Control Id="10054" Class="CControlScriptButton"/>
-								<Control Id="10055" Class="CControlScriptButton"/>
-								<Control Id="10056" Class="CControlScriptButton"/>
-								<Control Id="10057" Class="CControlScriptButton"/>
-								<Control Id="10058" Class="CControlScriptButton"/>
-								<Control Id="10059" Class="CControlScriptButton"/>
-								<Control Id="10060" Class="CControlScriptButton"/>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="32" ScreenSize="1024, 768">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="333, 49" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"/>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"/>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="0, 49" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"/>
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-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="10066" Id8="4004" Count="10"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</ScreenLayouts>
-	<HitopObjects>
-		<Watches>
-			<Watch Id="O3" Expr="RCC"/>
-			<Watch Id="O4" Expr="tmp"/>
-			<Watch Id="O5" Expr="0x1f&amp;0x20"/>
-			<Watch Id="O1" Expr="SCB"/>
-			<Watch Id="O2" Expr="TimingDelay"/>
-		</Watches>
-		<Breakpoints/>
-		<MiniSequences/>
-		<TimerTriggers/>
-	</HitopObjects>
-	<DownloadOptions Verify="0">
-		<PreLoadScript File="" Execute="0" ProjRelative="1"/>
-	</DownloadOptions>
-	<ExceptionAssistant>
-		<Exceptions Id="ARM low vectors" Count="7">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="Undefined Instruction" Number="1"/>
-			<Exception Name="SWI" Number="2"/>
-			<Exception Name="Prefetch Abort" Number="3"/>
-			<Exception Name="Data abort" Number="4"/>
-			<Exception Name="IRQ" Number="5"/>
-			<Exception Name="FIQ" Number="6"/>
-		</Exceptions>
-		<Interrupts Id="STR9 2x ARM - PL190" Count="64" VectorCount="32">
-			<IRQ Name="Watchdog" Number="0"/>
-			<IRQ Name="Software interrupt" Number="1"/>
-			<IRQ Name="Debug Receive Command" Number="2"/>
-			<IRQ Name="Debug Transmit Command" Number="3"/>
-			<IRQ Name="Timer 0" Number="4"/>
-			<IRQ Name="Timer 1" Number="5"/>
-			<IRQ Name="Timer 2" Number="6"/>
-			<IRQ Name="Timer 3" Number="7"/>
-			<IRQ Name="USB" Number="8"/>
-			<IRQ Name="USB" Number="9"/>
-			<IRQ Name="SCU" Number="10"/>
-			<IRQ Name="Ethernet MAC" Number="11"/>
-			<IRQ Name="DMA" Number="12"/>
-			<IRQ Name="CAN" Number="13"/>
-			<IRQ Name="IMC" Number="14"/>
-			<IRQ Name="ADC" Number="15"/>
-			<IRQ Name="UART 0" Number="16"/>
-			<IRQ Name="UART 1" Number="17"/>
-			<IRQ Name="UART 2" Number="18"/>
-			<IRQ Name="I2 C0" Number="19"/>
-			<IRQ Name="I2 C1" Number="20"/>
-			<IRQ Name="SSP 0" Number="21"/>
-			<IRQ Name="SSP 1" Number="22"/>
-			<IRQ Name="SCU" Number="23"/>
-			<IRQ Name="RTC" Number="24"/>
-			<IRQ Name="WIU all" Number="25"/>
-			<IRQ Name="WIU Group 0" Number="26"/>
-			<IRQ Name="WIU Group 1" Number="27"/>
-			<IRQ Name="WIU Group 2" Number="28"/>
-			<IRQ Name="WIU Group 3" Number="29"/>
-			<IRQ Name="USB" Number="30"/>
-			<IRQ Name="PFW-BC" Number="31"/>
-			<IRQ Name="IRQ 32" Number="32"/>
-			<IRQ Name="IRQ 33" Number="33"/>
-			<IRQ Name="IRQ 34" Number="34"/>
-			<IRQ Name="IRQ 35" Number="35"/>
-			<IRQ Name="IRQ 36" Number="36"/>
-			<IRQ Name="IRQ 37" Number="37"/>
-			<IRQ Name="IRQ 38" Number="38"/>
-			<IRQ Name="IRQ 39" Number="39"/>
-			<IRQ Name="IRQ 40" Number="40"/>
-			<IRQ Name="IRQ 41" Number="41"/>
-			<IRQ Name="IRQ 42" Number="42"/>
-			<IRQ Name="IRQ 43" Number="43"/>
-			<IRQ Name="IRQ 44" Number="44"/>
-			<IRQ Name="IRQ 45" Number="45"/>
-			<IRQ Name="IRQ 46" Number="46"/>
-			<IRQ Name="IRQ 47" Number="47"/>
-			<IRQ Name="IRQ 48" Number="48"/>
-			<IRQ Name="IRQ 49" Number="49"/>
-			<IRQ Name="IRQ 50" Number="50"/>
-			<IRQ Name="IRQ 51" Number="51"/>
-			<IRQ Name="IRQ 52" Number="52"/>
-			<IRQ Name="IRQ 53" Number="53"/>
-			<IRQ Name="IRQ 54" Number="54"/>
-			<IRQ Name="IRQ 55" Number="55"/>
-			<IRQ Name="IRQ 56" Number="56"/>
-			<IRQ Name="IRQ 57" Number="57"/>
-			<IRQ Name="IRQ 58" Number="58"/>
-			<IRQ Name="IRQ 59" Number="59"/>
-			<IRQ Name="IRQ 60" Number="60"/>
-			<IRQ Name="IRQ 61" Number="61"/>
-			<IRQ Name="IRQ 62" Number="62"/>
-			<IRQ Name="IRQ 63" Number="63"/>
-		</Interrupts>
-		<Exceptions Id="cortex-M3 vectors" Count="10">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="NMI" Number="1"/>
-			<Exception Name="HardFault" Number="2"/>
-			<Exception Name="MemManage" Number="3"/>
-			<Exception Name="BusFault" Number="4"/>
-			<Exception Name="UsageFault" Number="5"/>
-			<Exception Name="SVCall" Number="6"/>
-			<Exception Name="DebugMon" Number="7"/>
-			<Exception Name="PendSV" Number="8"/>
-			<Exception Name="SysTick" Number="9"/>
-		</Exceptions>
-		<Interrupts Id="STM32_NVIC" Count="43" VectorCount="43">
-			<Vector Number="0" Enabled="0"/>
-			<Vector Number="1" Enabled="0"/>
-			<Vector Number="2" Enabled="0"/>
-			<Vector Number="3" Enabled="0"/>
-			<Vector Number="4" Enabled="0"/>
-			<Vector Number="5" Enabled="0"/>
-			<Vector Number="6" Enabled="0"/>
-			<Vector Number="7" Enabled="0"/>
-			<Vector Number="8" Enabled="0"/>
-			<Vector Number="9" Enabled="0"/>
-			<Vector Number="10" Enabled="0"/>
-			<Vector Number="11" Enabled="0"/>
-			<Vector Number="12" Enabled="0"/>
-			<Vector Number="13" Enabled="0"/>
-			<Vector Number="14" Enabled="0"/>
-			<Vector Number="15" Enabled="0"/>
-			<Vector Number="16" Enabled="0"/>
-			<Vector Number="17" Enabled="0"/>
-			<Vector Number="18" Enabled="0"/>
-			<Vector Number="19" Enabled="0"/>
-			<Vector Number="20" Enabled="0"/>
-			<Vector Number="21" Enabled="0"/>
-			<Vector Number="22" Enabled="0"/>
-			<Vector Number="23" Enabled="0"/>
-			<Vector Number="24" Enabled="0"/>
-			<Vector Number="25" Enabled="0"/>
-			<Vector Number="26" Enabled="0"/>
-			<Vector Number="27" Enabled="0"/>
-			<Vector Number="28" Enabled="0"/>
-			<Vector Number="29" Enabled="0"/>
-			<Vector Number="30" Enabled="0"/>
-			<Vector Number="31" Enabled="0"/>
-			<Vector Number="32" Enabled="0"/>
-			<Vector Number="33" Enabled="0"/>
-			<Vector Number="34" Enabled="0"/>
-			<Vector Number="35" Enabled="0"/>
-			<Vector Number="36" Enabled="0"/>
-			<Vector Number="37" Enabled="0"/>
-			<Vector Number="38" Enabled="0"/>
-			<Vector Number="39" Enabled="0"/>
-			<Vector Number="40" Enabled="0"/>
-			<Vector Number="41" Enabled="0"/>
-			<Vector Number="42" Enabled="0"/>
-			<IRQ Name="WWDG" Number="0"/>
-			<IRQ Name="PVD" Number="1"/>
-			<IRQ Name="TAMPER" Number="2"/>
-			<IRQ Name="RTC" Number="3"/>
-			<IRQ Name="FLASH" Number="4"/>
-			<IRQ Name="RCC" Number="5"/>
-			<IRQ Name="EXTI 0" Number="6"/>
-			<IRQ Name="EXTI 1" Number="7"/>
-			<IRQ Name="EXTI 2" Number="8"/>
-			<IRQ Name="EXTI 3" Number="9"/>
-			<IRQ Name="EXTI 4" Number="10"/>
-			<IRQ Name="DMA Channel 1" Number="11"/>
-			<IRQ Name="DMA Channel 2" Number="12"/>
-			<IRQ Name="DMA Channel 3" Number="13"/>
-			<IRQ Name="DMA Channel 4" Number="14"/>
-			<IRQ Name="DMA Channel 5" Number="15"/>
-			<IRQ Name="DMA Channel 6" Number="16"/>
-			<IRQ Name="DMA Channel 7" Number="17"/>
-			<IRQ Name="ADC" Number="18"/>
-			<IRQ Name="USB_HP_CAN_TX" Number="19"/>
-			<IRQ Name="USB_LP_CAN_RX 0" Number="20"/>
-			<IRQ Name="CAN_RX 1" Number="21"/>
-			<IRQ Name="CAN_SCE" Number="22"/>
-			<IRQ Name="EXTI 5-9" Number="23"/>
-			<IRQ Name="TIM 1 BRK" Number="24"/>
-			<IRQ Name="TIM 1 UP" Number="25"/>
-			<IRQ Name="TIM 1 TRG COM" Number="26"/>
-			<IRQ Name="TIM 1 CC" Number="27"/>
-			<IRQ Name="TIM 2" Number="28"/>
-			<IRQ Name="TIM 3" Number="29"/>
-			<IRQ Name="TIM 4" Number="30"/>
-			<IRQ Name="I2C 1 EV" Number="31"/>
-			<IRQ Name="I2C 1 ER" Number="32"/>
-			<IRQ Name="I2C 2 EV" Number="33"/>
-			<IRQ Name="I2C 2 ER" Number="34"/>
-			<IRQ Name="SPI 1" Number="35"/>
-			<IRQ Name="SPI 2" Number="36"/>
-			<IRQ Name="USART 1" Number="37"/>
-			<IRQ Name="USART 2" Number="38"/>
-			<IRQ Name="USART 3" Number="39"/>
-			<IRQ Name="EXTI 10-15" Number="40"/>
-			<IRQ Name="RTC ALARM" Number="41"/>
-			<IRQ Name="USB Wakeup" Number="42"/>
-		</Interrupts>
-		<Exceptions Id="STM32100" Count="72">
-			<Exception Name="" Number="0"/>
-			<Exception Name="Reset" Number="1"/>
-			<Exception Name="NMI" Number="2"/>
-			<Exception Name="HardFault" Number="3"/>
-			<Exception Name="MemManage" Number="4"/>
-			<Exception Name="BusFault" Number="5"/>
-			<Exception Name="UsageFault" Number="6"/>
-			<Exception Name="Reserved" Number="7"/>
-			<Exception Name="Reserved" Number="8"/>
-			<Exception Name="Reserved" Number="9"/>
-			<Exception Name="Reserved" Number="10"/>
-			<Exception Name="SVCall" Number="11"/>
-			<Exception Name="DebugMon" Number="12"/>
-			<Exception Name="Reserved" Number="13"/>
-			<Exception Name="PendSV" Number="14"/>
-			<Exception Name="SysTick" Number="15"/>
-			<Exception Name="WWDG" Number="16"/>
-			<Exception Name="PVD" Number="17"/>
-			<Exception Name="TAMPER_STAMP" Number="18"/>
-			<Exception Name="RTC_WKUP" Number="19"/>
-			<Exception Name="FLASH" Number="20"/>
-			<Exception Name="RCC" Number="21"/>
-			<Exception Name="EXTI_0" Number="22"/>
-			<Exception Name="EXTI_1" Number="23"/>
-			<Exception Name="EXTI_2" Number="24"/>
-			<Exception Name="EXTI_3" Number="25"/>
-			<Exception Name="EXTI_4" Number="26"/>
-			<Exception Name="DMA1 Channel 1" Number="27"/>
-			<Exception Name="DMA1 Channel 2" Number="28"/>
-			<Exception Name="DMA1 Channel 3" Number="29"/>
-			<Exception Name="DMA1 Channel 4" Number="30"/>
-			<Exception Name="DMA1 Channel 5" Number="31"/>
-			<Exception Name="DMA1 Channel 6" Number="32"/>
-			<Exception Name="DMA1 Channel 7" Number="33"/>
-			<Exception Name="ADC1" Number="34"/>
-			<Exception Name="Reserved" Number="35"/>
-			<Exception Name="Reserved" Number="36"/>
-			<Exception Name="Reserved" Number="37"/>
-			<Exception Name="Reserved" Number="38"/>
-			<Exception Name="EXTI9_5" Number="39"/>
-			<Exception Name="TIM1 BRK TIM15" Number="40"/>
-			<Exception Name="TIM1 UP TIM16" Number="41"/>
-			<Exception Name="TIM1 TRG COM TIM17" Number="42"/>
-			<Exception Name="TIM1 CC" Number="43"/>
-			<Exception Name="TIM 2" Number="44"/>
-			<Exception Name="TIM 3" Number="45"/>
-			<Exception Name="TIM 4" Number="46"/>
-			<Exception Name="I2C 1 EV" Number="47"/>
-			<Exception Name="I2C 1 ER" Number="48"/>
-			<Exception Name="I2C 2 EV" Number="49"/>
-			<Exception Name="I2C 2 ER" Number="50"/>
-			<Exception Name="SPI 1" Number="51"/>
-			<Exception Name="SPI 2" Number="52"/>
-			<Exception Name="USART 1" Number="53"/>
-			<Exception Name="USART 2" Number="54"/>
-			<Exception Name="USART 3" Number="55"/>
-			<Exception Name="EXTI 10-15" Number="56"/>
-			<Exception Name="RTC ALARM" Number="57"/>
-			<Exception Name="CEC" Number="58"/>
-			<Exception Name="Reserved" Number="59"/>
-			<Exception Name="Reserved" Number="60"/>
-			<Exception Name="Reserved" Number="61"/>
-			<Exception Name="Reserved" Number="62"/>
-			<Exception Name="Reserved" Number="63"/>
-			<Exception Name="Reserved" Number="64"/>
-			<Exception Name="Reserved" Number="65"/>
-			<Exception Name="Reserved" Number="66"/>
-			<Exception Name="Reserved" Number="67"/>
-			<Exception Name="Reserved" Number="68"/>
-			<Exception Name="Reserved" Number="69"/>
-			<Exception Name="TIM6 DAC" Number="70"/>
-			<Exception Name="TIM 7" Number="71"/>
-		</Exceptions>
-	</ExceptionAssistant>
-	<HiTOPOpen ComponentId="Semihosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<Directories>
-		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM32100B-EVAL\objects\Project.abs"/>
-	</Directories>
-	<Applications>
-		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="Project">C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM32100B-EVAL\objects\</AppPath>
-	</Applications>
-	<HiTOPOpen ComponentId="SemiHosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<RecentScreenLayouts Active="DebugMode">
-		<Layout Description="IdeMode">
-			<Dockinglayout>
-				<IdeMode>
-					<Summary Panes="9" Client="8" TopContainer="4"/>
-					<Pane-1 ID="40364" Tag="60270280" Type="0" Title="Workspace - ModuleView\nModuleView" DockingCX="200" DockingCY="120" LastHolder="6" DockingHolder="6"/>
-					<Pane-2 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="9" DockingHolder="9"/>
-					<Pane-3 ID="40365" Tag="77359616" Type="0" Title="Workspace - FileView\nFileView" DockingCX="200" DockingCY="120" LastHolder="6" DockingHolder="6"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="9" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="2" Pane-1="6" Pane-2="7" DockingCY="724"/>
-					<Pane-6 Type="1" Panes="2" Pane-1="1" Pane-2="3" Selected="3" DockingCX="200" DockingCY="120"/>
-					<Pane-7 Type="2" Panes="1" Pane-1="8" DockingCX="1076"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="1" Panes="1" Pane-1="2" Selected="2" DockingCX="200" DockingCY="145"/>
-				</IdeMode>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
-						<Position x="0" y="352"/>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="830" cy="485"/>
-						<Position x="0" y="0"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="1084" cy="758"/>
-						<Position x="-4" y="-23"/>
-					</Rectangle>
-				</Window>
-			</Windows>
-			<MainWindow Zoomed="1">
-				<Size cx="991" cy="724"/>
-				<Position x="10" y="6"/>
-			</MainWindow>
-			<CommandBars>
-				<CommandBars>
-					<CommandBar BarID="10066" Class="CScriptToolBar" Flags="63" Style="4194304" Title="Execute Script" MRUWidth="32767" CustomizeDialogPresent="0">
-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."/>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."/>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_appl.scr"/>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\IntroPack\\Project\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_go_main.scr"/>
-							<Control Id="10053" Class="CControlScriptButton"/>
-							<Control Id="10054" Class="CControlScriptButton"/>
-							<Control Id="10055" Class="CControlScriptButton"/>
-							<Control Id="10056" Class="CControlScriptButton"/>
-							<Control Id="10057" Class="CControlScriptButton"/>
-							<Control Id="10058" Class="CControlScriptButton"/>
-							<Control Id="10059" Class="CControlScriptButton"/>
-							<Control Id="10060" Class="CControlScriptButton"/>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."/>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."/>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"/>
-								<Control Id="10052" Class="CControlScriptButton"/>
-								<Control Id="10053" Class="CControlScriptButton"/>
-								<Control Id="10054" Class="CControlScriptButton"/>
-								<Control Id="10055" Class="CControlScriptButton"/>
-								<Control Id="10056" Class="CControlScriptButton"/>
-								<Control Id="10057" Class="CControlScriptButton"/>
-								<Control Id="10058" Class="CControlScriptButton"/>
-								<Control Id="10059" Class="CControlScriptButton"/>
-								<Control Id="10060" Class="CControlScriptButton"/>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."/>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."/>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="32" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="333, 49" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"/>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"/>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="0, 49" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="-1, 32, 432, 58"/>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="10066" Id8="4004" Count="10"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-		<Layout Pos="0" Description="DebugMode">
-			<Dockinglayout>
-				<DebugMode>
-					<Summary Panes="45" Client="25" TopContainer="16"></Summary>
-					<Pane-1 ID="40364" Tag="13194360" Type="0" Title="Workspace - ModuleView\nModuleView\n" DockingCX="200" DockingCY="120" LastHolder="22" DockingHolder="22" FloatingHolder="42"></Pane-1>
-					<Pane-2 ID="40365" Tag="63539944" Type="0" Title="Workspace - FileView\nFileView\n" DockingCX="200" DockingCY="120" LastHolder="22" DockingHolder="22" FloatingHolder="42"></Pane-2>
-					<Pane-3 ID="40100" Tag="38825560" Type="0" Title="Register\n\n" DockingCX="200" DockingCY="120" LastHolder="27" DockingHolder="27"></Pane-3>
-					<Pane-4 ID="40932" Tag="38297592" Type="0" Title="Emulator State\n\n" DockingCX="200" DockingCY="120" LastHolder="28" DockingHolder="28"></Pane-4>
-					<Pane-5 ID="40000" Type="0" Title="Watch - Locals\nLocals\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="33"></Pane-5>
-					<Pane-6 ID="40001" Type="0" Title="Watch - Watch1\nWatch1\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="33"></Pane-6>
-					<Pane-7 ID="40050" Tag="42486464" Type="0" Title="Memory - Mem0\nMem0\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30"></Pane-7>
-					<Pane-8 ID="10001" Type="0" Title="Output\n\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30"></Pane-8>
-					<Pane-9 ID="40051" Type="0" Title="Memory - Flash\nFlash\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="36"></Pane-9>
-					<Pane-10 ID="40052" Type="0" Title="Memory - RAM\nRAM\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30"></Pane-10>
-					<Pane-11 ID="40053" Type="0" Title="Memory - Base\nBase\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="39"></Pane-11>
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-					<Pane-45 Type="1" Panes="0" DockingCX="200" DockingCY="120"></Pane-45>
-				</DebugMode>
-			</Dockinglayout>
-			<MainWindow Zoomed="1">
-				<Position x="10" y="6"/>
-				<Size cx="1004" cy="737"/>
-			</MainWindow>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"></WindowState>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"></Size>
-						<Position x="0" y="352"></Position>
-					</Rectangle>
-					<Rectangle State="Normal">
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-						<Position x="0" y="0"></Position>
-					</Rectangle>
-					<Rectangle State="Maximized">
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-						<Position x="-4" y="-23"></Position>
-					</Rectangle>
-				</Window>
-				<Window Id="SFRWindow">
-					<WindowState State="Normal"/>
-					<Rectangle State="Normal">
-						<Size cx="709" cy="313"/>
-						<Position x="22" y="22"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="871" cy="494"/>
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-					</Rectangle>
-				</Window>
-			</Windows>
-			<CommandBars Schema="36">
-				<CommandBars>
-					<CommandBar BarID="10066" Class="CScriptToolBar" Flags="63" Style="4194304" Title="Execute Script" MRUWidth="32767" CustomizeDialogPresent="0">
-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."></Control>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_appl.scr"></Control>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100B-EVAL\\Settings\\reset_go_main.scr"></Control>
-							<Control Id="10053" Class="CControlScriptButton"></Control>
-							<Control Id="10054" Class="CControlScriptButton"></Control>
-							<Control Id="10055" Class="CControlScriptButton"></Control>
-							<Control Id="10056" Class="CControlScriptButton"></Control>
-							<Control Id="10057" Class="CControlScriptButton"></Control>
-							<Control Id="10058" Class="CControlScriptButton"></Control>
-							<Control Id="10059" Class="CControlScriptButton"></Control>
-							<Control Id="10060" Class="CControlScriptButton"></Control>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."></Control>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"></Control>
-								<Control Id="10052" Class="CControlScriptButton"></Control>
-								<Control Id="10053" Class="CControlScriptButton"></Control>
-								<Control Id="10054" Class="CControlScriptButton"></Control>
-								<Control Id="10055" Class="CControlScriptButton"></Control>
-								<Control Id="10056" Class="CControlScriptButton"></Control>
-								<Control Id="10057" Class="CControlScriptButton"></Control>
-								<Control Id="10058" Class="CControlScriptButton"></Control>
-								<Control Id="10059" Class="CControlScriptButton"></Control>
-								<Control Id="10060" Class="CControlScriptButton"></Control>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="36" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"></BarInfo0>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="334, 49" MRUDockPos="318, 54, 634, 81"></BarInfo1>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"></BarInfo2>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"></BarInfo3>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="1, 49" MRUDockPos="1, 49, 334, 75"></BarInfo4>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"></BarInfo5>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="4004" Id8="10066" Count="10"></DockBar0>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-		<Layout Description="FlashTool">
-			<Dockinglayout>
-				<FlashTool>
-					<Summary Panes="14" Client="8" TopContainer="4"/>
-					<Pane-1 Type="5" Panes="0" Direction="0"/>
-					<Pane-2 Type="5" Panes="0" Direction="1"/>
-					<Pane-3 Type="5" Panes="0" Direction="3"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="12" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="1" Pane-1="6" DockingCY="510"/>
-					<Pane-6 Type="2" Panes="2" Pane-1="7" Pane-2="9" DockingCX="791" DockingCY="510"/>
-					<Pane-7 Type="2" Horiz="1" Panes="1" Pane-1="8" DockingCY="401"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="2" Horiz="1" Panes="1" Pane-1="10" DockingCX="200" DockingCY="105"/>
-					<Pane-10 Type="1" Panes="1" Pane-1="11" Selected="11" DockingCX="200" DockingCY="120"/>
-					<Pane-11 ID="40050" Type="0" Title="Memory - Mem0\nMem0" DockingCX="200" DockingCY="120" LastHolder="10" DockingHolder="10"/>
-					<Pane-12 Type="2" Horiz="1" Panes="1" Pane-1="13" DockingCX="995" DockingCY="101"/>
-					<Pane-13 Type="1" Panes="1" Pane-1="14" Selected="14" DockingCX="728" DockingCY="101"/>
-					<Pane-14 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="13" DockingHolder="13"/>
-				</FlashTool>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="0" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
-						<Position x="0" y="352"/>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="534" cy="471"/>
-						<Position x="-4" y="-23"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="566" cy="421"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-				</Window>
-				<Window Id="SFRWindow">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Normal">
-						<Size cx="300" cy="200"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Position x="-4" y="-30"/>
-						<Size cx="746" cy="219"/>
-					</Rectangle>
-				</Window>
-			</Windows>
-			<CommandBars>
-				<Layout>
-					<DockState Count="5" Version="8" ScreenSize="1024, 768">
-						<BarInfo0 BarId="1" MRUWidth="32767"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="346, 50" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="375, 23" MRUDockPos="374, 23, 610, 50"/>
-						<BarInfo3 BarId="4004" MRUWidth="32767" PointPos="0, 50" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo4 BarId="128" MRUWidth="32767" PointPos="0, 23" MRUDockPos="-12, 27, 363, 54"/>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="9025" Id4="128" Id6="10066" Id7="4004" Count="9"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<Component Id="DataTrace"/>
-	<FlashProgramming RAMBase="0x20000000" RAMLength="0x2000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F100xB" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x08000000" Manufacturer="ST">
-			<Sectors Count="0"/>
-		</FlashDevice>
-	</FlashProgramming>
-	<PowerScale EnableInstrumentation="0"/>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="Project" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM32100B-EVAL">
-			<SymbolLoader ProjRel="1" MessageFile="" LoaderVersion="sparmed54.dll : 5.40.833.0" NeedsSymprepRun="0" SymbolFileFormat="V2.4.0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text=".\source\"/>
-						<Path Text=".\"/>
-						<Path Text=".\Source\"/>
-						<Path Text=".\Settings\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL\"/>
-						<Path Text="..\..\"/>
-						<Path Text="..\STM3210B-EVAL\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\Common\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM32100B-EVAL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="Project.abs" StopBuildOnError="1">
-					<IncludePath Path="..\..\" Position="0"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="4"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL\" Position="6"></IncludePath>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_MD_VL;USE_STM32100B_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -Wc-I&quot;$(TARGETDIR)\..\library\inc&quot; -v -Wa-L1 -Wc-w560 -Wc-w557 -Wc-w507 -Wc-w523  -Wc-t4  "></Compiler>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk
deleted file mode 100644
index 038235e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/stm32f10x_MD_VL.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr
deleted file mode 100644
index 3e9c066..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr
+++ /dev/null
@@ -1,12 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application & Go main 
-
-// Reset    
-RESET TARGET
-
-
-// execute program till main
-Go UNTIL main
-wait
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/readme.txt
deleted file mode 100644
index 54aaec8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/readme.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
-  @page HiTOP5_STM32100B HiTOP Project Template for STM32F10x Medium-density Value line devices
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with HiTOP software toolchain (version 5.40 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
-@par Directory contents
-
- - Project.htp: A pre-configured project file with the provided library 
-                structure that produces an executable image with HiTOP
-
- - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized
-                      sections from ROM to RAM.                 
-
- - Objects: This mandatory directory contains the executable images.
-
- - Settings: This directory contains the linker and script files.                  
-     - arm_arch.lsl: This file is used to place program code (readonly)
-                     in internal FLASH and data (readwrite, Stack and Heap)
-                     in internal SRAM.
-
-     - link.lnk: This file is the HiTOP linker it invokes the stm32f10x_MD_VL.lsl.
-                                   
-     - reset_appl.scr: This file is a HiTOP script it performs a target reset.
-     
-     - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
-                          Counter at the "main" instruction.
-
-     - StartupScript.scr: This file is a HiTOP script and it performs a target 
-                          reset before loading The executable image.
-
-     - stm32f10x_MD_VL.lsl: This file is used to place program code (readonly)
-                            in internal FLASH and data (readwrite, Stack and Heap)
-                            in internal SRAM.
-                            It contains also the vector table of the STM32 
-                            Medium-density Value line devices.
-                            You can customize this file to your need.                                                              
-
-@par How to use it ?
-
-- Open the HiTOP toolchain.
-- Browse to open the project.htp
-- A "Download application" window is displayed, click "cancel".
-- Rebuild all files: Project->Rebuild all
-- Load project image : Click "ok" in the "Download application" window.
-- Run the "RESET_GO_MAIN" script to set the PC at the "main"
-- Run program: Debug->Go(F5).
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes. 
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp
deleted file mode 100644
index eedf13a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp
+++ /dev/null
@@ -1,1242 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F100ZE.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722878" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325528" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954668" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="0" y="0"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="787" cy="578"></Size>
-				<Position x="-4" y="-23"></Position>
-			</Rectangle>
-			<Tabs Count="0" Active="0"/>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-						<Column Id="14" Order="2" Title="Type" Visible="1" RelWidth="0.3856508" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941628" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000448" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059268" Alignment="LEFT"/>
-						<Watches/>
-						<Column Id="14" Order="3" Title="Type" Visible="1" RelWidth="0.3359388" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="0x20004C00"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08000060" Symbol="0x08000060"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x00000000" Symbol="_lc_t2_longveneertarget"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Emulator State">
-			<Tabs>
-				<Tab Pos="0">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="3">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="5">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="2">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occurred" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Breakpoint">
-			<Tabs Sel="0">
-				<Tab Pos="0" Title="Code">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500088" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106148" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833418" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560698" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Data">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500018" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106078" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833348" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560628" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="TraceFilter">
-			<Tabs>
-				<Tab Pos="0">
-					<Triggers/>
-				</Tab>
-				<Tab Pos="1">
-					<Regions/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Profile">
-			<Tabs>
-				<Tab Pos="0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Id" Visible="1" RelWidth="0.2275868" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.2827598" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Activity" Visible="1" RelWidth="0.4000008" Alignment="LEFT"/>
-						<Column Id="14" Order="3" Title="Time" Visible="1" RelWidth="0.0896558" Alignment="LEFT"/>
-					</List>
-					<State ModeAbsolute="0" UpdateEnabled="0"/>
-				</Tab>
-			</Tabs>
-			<List Id=""/>
-		</Window>
-		<Window Id="FileView" RelativePath="Relative2Project">
-			<ApplFolder Id="Project" State="Expanded">
-				<Folder Id="CMSIS" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c"/>
-					<File Id="..\..\system_stm32f10x.c"/>
-				</Folder>
-				<Folder Id="Doc" State="Not_Expanded">
-					<File Id=".\readme.txt"/>
-				</Folder>
-				<Folder Id="StdPeriph_Driver" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c"/>
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-			<IRQ Name="IRQ 49" Number="49"/>
-			<IRQ Name="IRQ 50" Number="50"/>
-			<IRQ Name="IRQ 51" Number="51"/>
-			<IRQ Name="IRQ 52" Number="52"/>
-			<IRQ Name="IRQ 53" Number="53"/>
-			<IRQ Name="IRQ 54" Number="54"/>
-			<IRQ Name="IRQ 55" Number="55"/>
-			<IRQ Name="IRQ 56" Number="56"/>
-			<IRQ Name="IRQ 57" Number="57"/>
-			<IRQ Name="IRQ 58" Number="58"/>
-			<IRQ Name="IRQ 59" Number="59"/>
-			<IRQ Name="IRQ 60" Number="60"/>
-			<IRQ Name="IRQ 61" Number="61"/>
-			<IRQ Name="IRQ 62" Number="62"/>
-			<IRQ Name="IRQ 63" Number="63"/>
-		</Interrupts>
-		<Exceptions Id="cortex-M3 vectors" Count="10">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="NMI" Number="1"/>
-			<Exception Name="HardFault" Number="2"/>
-			<Exception Name="MemManage" Number="3"/>
-			<Exception Name="BusFault" Number="4"/>
-			<Exception Name="UsageFault" Number="5"/>
-			<Exception Name="SVCall" Number="6"/>
-			<Exception Name="DebugMon" Number="7"/>
-			<Exception Name="PendSV" Number="8"/>
-			<Exception Name="SysTick" Number="9"/>
-		</Exceptions>
-		<Interrupts Id="STM32_NVIC" Count="43" VectorCount="43">
-			<Vector Number="0" Enabled="0"/>
-			<Vector Number="1" Enabled="0"/>
-			<Vector Number="2" Enabled="0"/>
-			<Vector Number="3" Enabled="0"/>
-			<Vector Number="4" Enabled="0"/>
-			<Vector Number="5" Enabled="0"/>
-			<Vector Number="6" Enabled="0"/>
-			<Vector Number="7" Enabled="0"/>
-			<Vector Number="8" Enabled="0"/>
-			<Vector Number="9" Enabled="0"/>
-			<Vector Number="10" Enabled="0"/>
-			<Vector Number="11" Enabled="0"/>
-			<Vector Number="12" Enabled="0"/>
-			<Vector Number="13" Enabled="0"/>
-			<Vector Number="14" Enabled="0"/>
-			<Vector Number="15" Enabled="0"/>
-			<Vector Number="16" Enabled="0"/>
-			<Vector Number="17" Enabled="0"/>
-			<Vector Number="18" Enabled="0"/>
-			<Vector Number="19" Enabled="0"/>
-			<Vector Number="20" Enabled="0"/>
-			<Vector Number="21" Enabled="0"/>
-			<Vector Number="22" Enabled="0"/>
-			<Vector Number="23" Enabled="0"/>
-			<Vector Number="24" Enabled="0"/>
-			<Vector Number="25" Enabled="0"/>
-			<Vector Number="26" Enabled="0"/>
-			<Vector Number="27" Enabled="0"/>
-			<Vector Number="28" Enabled="0"/>
-			<Vector Number="29" Enabled="0"/>
-			<Vector Number="30" Enabled="0"/>
-			<Vector Number="31" Enabled="0"/>
-			<Vector Number="32" Enabled="0"/>
-			<Vector Number="33" Enabled="0"/>
-			<Vector Number="34" Enabled="0"/>
-			<Vector Number="35" Enabled="0"/>
-			<Vector Number="36" Enabled="0"/>
-			<Vector Number="37" Enabled="0"/>
-			<Vector Number="38" Enabled="0"/>
-			<Vector Number="39" Enabled="0"/>
-			<Vector Number="40" Enabled="0"/>
-			<Vector Number="41" Enabled="0"/>
-			<Vector Number="42" Enabled="0"/>
-			<IRQ Name="WWDG" Number="0"/>
-			<IRQ Name="PVD" Number="1"/>
-			<IRQ Name="TAMPER" Number="2"/>
-			<IRQ Name="RTC" Number="3"/>
-			<IRQ Name="FLASH" Number="4"/>
-			<IRQ Name="RCC" Number="5"/>
-			<IRQ Name="EXTI 0" Number="6"/>
-			<IRQ Name="EXTI 1" Number="7"/>
-			<IRQ Name="EXTI 2" Number="8"/>
-			<IRQ Name="EXTI 3" Number="9"/>
-			<IRQ Name="EXTI 4" Number="10"/>
-			<IRQ Name="DMA Channel 1" Number="11"/>
-			<IRQ Name="DMA Channel 2" Number="12"/>
-			<IRQ Name="DMA Channel 3" Number="13"/>
-			<IRQ Name="DMA Channel 4" Number="14"/>
-			<IRQ Name="DMA Channel 5" Number="15"/>
-			<IRQ Name="DMA Channel 6" Number="16"/>
-			<IRQ Name="DMA Channel 7" Number="17"/>
-			<IRQ Name="ADC" Number="18"/>
-			<IRQ Name="USB_HP_CAN_TX" Number="19"/>
-			<IRQ Name="USB_LP_CAN_RX 0" Number="20"/>
-			<IRQ Name="CAN_RX 1" Number="21"/>
-			<IRQ Name="CAN_SCE" Number="22"/>
-			<IRQ Name="EXTI 5-9" Number="23"/>
-			<IRQ Name="TIM 1 BRK" Number="24"/>
-			<IRQ Name="TIM 1 UP" Number="25"/>
-			<IRQ Name="TIM 1 TRG COM" Number="26"/>
-			<IRQ Name="TIM 1 CC" Number="27"/>
-			<IRQ Name="TIM 2" Number="28"/>
-			<IRQ Name="TIM 3" Number="29"/>
-			<IRQ Name="TIM 4" Number="30"/>
-			<IRQ Name="I2C 1 EV" Number="31"/>
-			<IRQ Name="I2C 1 ER" Number="32"/>
-			<IRQ Name="I2C 2 EV" Number="33"/>
-			<IRQ Name="I2C 2 ER" Number="34"/>
-			<IRQ Name="SPI 1" Number="35"/>
-			<IRQ Name="SPI 2" Number="36"/>
-			<IRQ Name="USART 1" Number="37"/>
-			<IRQ Name="USART 2" Number="38"/>
-			<IRQ Name="USART 3" Number="39"/>
-			<IRQ Name="EXTI 10-15" Number="40"/>
-			<IRQ Name="RTC ALARM" Number="41"/>
-			<IRQ Name="USB Wakeup" Number="42"/>
-		</Interrupts>
-		<Exceptions Id="STM32100" Count="72">
-			<Exception Name="" Number="0"/>
-			<Exception Name="Reset" Number="1"/>
-			<Exception Name="NMI" Number="2"/>
-			<Exception Name="HardFault" Number="3"/>
-			<Exception Name="MemManage" Number="4"/>
-			<Exception Name="BusFault" Number="5"/>
-			<Exception Name="UsageFault" Number="6"/>
-			<Exception Name="Reserved" Number="7"/>
-			<Exception Name="Reserved" Number="8"/>
-			<Exception Name="Reserved" Number="9"/>
-			<Exception Name="Reserved" Number="10"/>
-			<Exception Name="SVCall" Number="11"/>
-			<Exception Name="DebugMon" Number="12"/>
-			<Exception Name="Reserved" Number="13"/>
-			<Exception Name="PendSV" Number="14"/>
-			<Exception Name="SysTick" Number="15"/>
-			<Exception Name="WWDG" Number="16"/>
-			<Exception Name="PVD" Number="17"/>
-			<Exception Name="TAMPER_STAMP" Number="18"/>
-			<Exception Name="RTC_WKUP" Number="19"/>
-			<Exception Name="FLASH" Number="20"/>
-			<Exception Name="RCC" Number="21"/>
-			<Exception Name="EXTI_0" Number="22"/>
-			<Exception Name="EXTI_1" Number="23"/>
-			<Exception Name="EXTI_2" Number="24"/>
-			<Exception Name="EXTI_3" Number="25"/>
-			<Exception Name="EXTI_4" Number="26"/>
-			<Exception Name="DMA1 Channel 1" Number="27"/>
-			<Exception Name="DMA1 Channel 2" Number="28"/>
-			<Exception Name="DMA1 Channel 3" Number="29"/>
-			<Exception Name="DMA1 Channel 4" Number="30"/>
-			<Exception Name="DMA1 Channel 5" Number="31"/>
-			<Exception Name="DMA1 Channel 6" Number="32"/>
-			<Exception Name="DMA1 Channel 7" Number="33"/>
-			<Exception Name="ADC1" Number="34"/>
-			<Exception Name="Reserved" Number="35"/>
-			<Exception Name="Reserved" Number="36"/>
-			<Exception Name="Reserved" Number="37"/>
-			<Exception Name="Reserved" Number="38"/>
-			<Exception Name="EXTI9_5" Number="39"/>
-			<Exception Name="TIM1 BRK TIM15" Number="40"/>
-			<Exception Name="TIM1 UP TIM16" Number="41"/>
-			<Exception Name="TIM1 TRG COM TIM17" Number="42"/>
-			<Exception Name="TIM1 CC" Number="43"/>
-			<Exception Name="TIM 2" Number="44"/>
-			<Exception Name="TIM 3" Number="45"/>
-			<Exception Name="TIM 4" Number="46"/>
-			<Exception Name="I2C 1 EV" Number="47"/>
-			<Exception Name="I2C 1 ER" Number="48"/>
-			<Exception Name="I2C 2 EV" Number="49"/>
-			<Exception Name="I2C 2 ER" Number="50"/>
-			<Exception Name="SPI 1" Number="51"/>
-			<Exception Name="SPI 2" Number="52"/>
-			<Exception Name="USART 1" Number="53"/>
-			<Exception Name="USART 2" Number="54"/>
-			<Exception Name="USART 3" Number="55"/>
-			<Exception Name="EXTI 10-15" Number="56"/>
-			<Exception Name="RTC ALARM" Number="57"/>
-			<Exception Name="CEC" Number="58"/>
-			<Exception Name="Reserved" Number="59"/>
-			<Exception Name="Reserved" Number="60"/>
-			<Exception Name="Reserved" Number="61"/>
-			<Exception Name="Reserved" Number="62"/>
-			<Exception Name="Reserved" Number="63"/>
-			<Exception Name="Reserved" Number="64"/>
-			<Exception Name="Reserved" Number="65"/>
-			<Exception Name="Reserved" Number="66"/>
-			<Exception Name="Reserved" Number="67"/>
-			<Exception Name="Reserved" Number="68"/>
-			<Exception Name="Reserved" Number="69"/>
-			<Exception Name="TIM6 DAC" Number="70"/>
-			<Exception Name="TIM 7" Number="71"/>
-		</Exceptions>
-		<Exceptions Id="STM32100_C_D_E" Count="76">
-			<Exception Name="" Number="0"/>
-			<Exception Name="Reset" Number="1"/>
-			<Exception Name="NMI" Number="2"/>
-			<Exception Name="HardFault" Number="3"/>
-			<Exception Name="MemManage" Number="4"/>
-			<Exception Name="BusFault" Number="5"/>
-			<Exception Name="UsageFault" Number="6"/>
-			<Exception Name="Reserved" Number="7"/>
-			<Exception Name="Reserved" Number="8"/>
-			<Exception Name="Reserved" Number="9"/>
-			<Exception Name="Reserved" Number="10"/>
-			<Exception Name="SVCall" Number="11"/>
-			<Exception Name="DebugMon" Number="12"/>
-			<Exception Name="Reserved" Number="13"/>
-			<Exception Name="PendSV" Number="14"/>
-			<Exception Name="SysTick" Number="15"/>
-			<Exception Name="WWDG" Number="16"/>
-			<Exception Name="PVD" Number="17"/>
-			<Exception Name="TAMPER_STAMP" Number="18"/>
-			<Exception Name="RTC_WKUP" Number="19"/>
-			<Exception Name="FLASH" Number="20"/>
-			<Exception Name="RCC" Number="21"/>
-			<Exception Name="EXTI_0" Number="22"/>
-			<Exception Name="EXTI_1" Number="23"/>
-			<Exception Name="EXTI_2" Number="24"/>
-			<Exception Name="EXTI_3" Number="25"/>
-			<Exception Name="EXTI_4" Number="26"/>
-			<Exception Name="DMA1 Channel 1" Number="27"/>
-			<Exception Name="DMA1 Channel 2" Number="28"/>
-			<Exception Name="DMA1 Channel 3" Number="29"/>
-			<Exception Name="DMA1 Channel 4" Number="30"/>
-			<Exception Name="DMA1 Channel 5" Number="31"/>
-			<Exception Name="DMA1 Channel 6" Number="32"/>
-			<Exception Name="DMA1 Channel 7" Number="33"/>
-			<Exception Name="ADC1" Number="34"/>
-			<Exception Name="Reserved" Number="35"/>
-			<Exception Name="Reserved" Number="36"/>
-			<Exception Name="Reserved" Number="37"/>
-			<Exception Name="Reserved" Number="38"/>
-			<Exception Name="EXTI9_5" Number="39"/>
-			<Exception Name="TIM1 BRK TIM15" Number="40"/>
-			<Exception Name="TIM1 UP TIM16" Number="41"/>
-			<Exception Name="TIM1 TRG COM TIM17" Number="42"/>
-			<Exception Name="TIM1 CC" Number="43"/>
-			<Exception Name="TIM 2" Number="44"/>
-			<Exception Name="TIM 3" Number="45"/>
-			<Exception Name="TIM 4" Number="46"/>
-			<Exception Name="I2C 1 EV" Number="47"/>
-			<Exception Name="I2C 1 ER" Number="48"/>
-			<Exception Name="I2C 2 EV" Number="49"/>
-			<Exception Name="I2C 2 ER" Number="50"/>
-			<Exception Name="SPI 1" Number="51"/>
-			<Exception Name="SPI 2" Number="52"/>
-			<Exception Name="USART 1" Number="53"/>
-			<Exception Name="USART 2" Number="54"/>
-			<Exception Name="USART 3" Number="55"/>
-			<Exception Name="EXTI 10-15" Number="56"/>
-			<Exception Name="RTC ALARM" Number="57"/>
-			<Exception Name="CEC" Number="58"/>
-			<Exception Name="TIM 12" Number="59"/>
-			<Exception Name="TIM 13" Number="60"/>
-			<Exception Name="TIM 14" Number="61"/>
-			<Exception Name="Reserved" Number="62"/>
-			<Exception Name="Reserved" Number="63"/>
-			<Exception Name="FSMC" Number="64"/>
-			<Exception Name="Reserved" Number="65"/>
-			<Exception Name="TIM 5" Number="66"/>
-			<Exception Name="SPI 3" Number="67"/>
-			<Exception Name="UART 4" Number="68"/>
-			<Exception Name="UART 5" Number="69"/>
-			<Exception Name="TIM6 DAC" Number="70"/>
-			<Exception Name="TIM 7" Number="71"/>
-			<Exception Name="DMA2 Channel 1" Number="72"/>
-			<Exception Name="DMA2 Channel 2" Number="73"/>
-			<Exception Name="DMA2 Channel 3" Number="74"/>
-			<Exception Name="DMA2 Channel 4_5" Number="75"/>
-		</Exceptions>
-	</ExceptionAssistant>
-	<HiTOPOpen ComponentId="Semihosting">
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-		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="Project">C:\PWA_2007\IntroPack\Project\STM32F10x_StdPeriph_Template\HiTOP\STM32100E-EVAL\objects\</AppPath>
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-					<Pane-19 Type="2" Panes="1" Pane-1="20" DockingCX="1032"></Pane-19>
-					<Pane-20 Type="2" Horiz="1" Panes="2" Pane-1="21" Pane-2="24" DockingCX="904" DockingCY="342"></Pane-20>
-					<Pane-21 Type="2" Panes="2" Pane-1="22" Pane-2="23" DockingCX="249" DockingCY="454"></Pane-21>
-					<Pane-22 Type="1" Panes="2" Pane-1="1" Pane-2="2" Selected="2" DockingCX="192" DockingCY="305"></Pane-22>
-					<Pane-23 Type="1" Panes="1" Pane-1="12" Selected="12" DockingCX="200" DockingCY="145"></Pane-23>
-					<Pane-24 Type="2" Panes="1" Pane-1="25" DockingCX="779"></Pane-24>
-					<Pane-25 Type="4"></Pane-25>
-					<Pane-26 Type="2" Panes="2" Pane-1="27" Pane-2="28" DockingCX="244" DockingCY="454"></Pane-26>
-					<Pane-27 Type="1" Panes="1" Pane-1="3" Selected="3" DockingCX="200" DockingCY="319"></Pane-27>
-					<Pane-28 Type="1" Panes="1" Pane-1="4" Selected="4" DockingCX="287" DockingCY="131"></Pane-28>
-					<Pane-29 Type="2" Horiz="1" Panes="1" Pane-1="30" DockingCX="1280" DockingCY="325"></Pane-29>
-					<Pane-30 Type="1" Panes="5" Pane-1="5" Pane-2="7" Pane-3="6" Pane-4="8" Pane-5="9" Selected="8" DockingCX="1103" DockingCY="101"></Pane-30>
-					<Pane-31 Type="3" TopContaner="32" WindowRectTopPos="486" WindowRectLeftPos="608" WindowRectRightPos="1246" WindowRectBottomPos="691"></Pane-31>
-					<Pane-32 Type="2" Horiz="1" Panes="1" Pane-1="33" DockingCX="200" DockingCY="120"></Pane-32>
-					<Pane-33 Type="1" Panes="0" DockingCX="200" DockingCY="120"></Pane-33>
-					<Pane-34 Type="3" TopContaner="35" WindowRectTopPos="560" WindowRectLeftPos="0" WindowRectRightPos="638" WindowRectBottomPos="882"></Pane-34>
-					<Pane-35 Type="2" Horiz="1" Panes="1" Pane-1="36" DockingCX="200" DockingCY="120"></Pane-35>
-					<Pane-36 Type="1" Panes="0" DockingCX="200" DockingCY="120"></Pane-36>
-					<Pane-37 Type="3" TopContaner="38" WindowRectTopPos="560" WindowRectLeftPos="0" WindowRectRightPos="638" WindowRectBottomPos="882"></Pane-37>
-					<Pane-38 Type="2" Horiz="1" Panes="1" Pane-1="39" DockingCX="200" DockingCY="120"></Pane-38>
-					<Pane-39 Type="1" Panes="0" DockingCX="200" DockingCY="120"></Pane-39>
-					<Pane-40 Type="3" TopContaner="41" WindowRectTopPos="164" WindowRectLeftPos="67" WindowRectRightPos="259" WindowRectBottomPos="580"></Pane-40>
-					<Pane-41 Type="2" Horiz="1" Panes="1" Pane-1="42" DockingCX="192" DockingCY="120"></Pane-41>
-					<Pane-42 Type="1" Panes="0" DockingCX="192" DockingCY="120"></Pane-42>
-					<Pane-43 Type="3" TopContaner="44" WindowRectTopPos="215" WindowRectLeftPos="389" WindowRectRightPos="581" WindowRectBottomPos="343"></Pane-43>
-					<Pane-44 Type="2" Horiz="1" Panes="1" Pane-1="45" DockingCX="200" DockingCY="120"></Pane-44>
-					<Pane-45 Type="1" Panes="0" DockingCX="200" DockingCY="120"></Pane-45>
-				</DebugMode>
-			</Dockinglayout>
-			<MainWindow Zoomed="1">
-				<Position x="10" y="6"/>
-				<Size cx="1018" cy="751"/>
-			</MainWindow>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"></WindowState>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"></Size>
-						<Position x="0" y="352"></Position>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="830" cy="485"></Size>
-						<Position x="0" y="0"></Position>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="787" cy="578"></Size>
-						<Position x="-4" y="-23"></Position>
-					</Rectangle>
-				</Window>
-				<Window Id="SFRWindow">
-					<WindowState State="Normal"/>
-					<Rectangle State="Normal">
-						<Size cx="709" cy="313"/>
-						<Position x="22" y="22"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="871" cy="494"/>
-						<Position x="-4" y="-23"/>
-					</Rectangle>
-				</Window>
-			</Windows>
-			<CommandBars Schema="36">
-				<CommandBars>
-					<CommandBar BarID="10066" Class="CScriptToolBar" Flags="63" Style="4194304" Title="Execute Script" MRUWidth="32767" CustomizeDialogPresent="0">
-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."></Control>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100E-EVAL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100E-EVAL\\Settings\\reset_appl.scr"></Control>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100E-EVAL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM32100E-EVAL\\Settings\\reset_go_main.scr"></Control>
-							<Control Id="10053" Class="CControlScriptButton"></Control>
-							<Control Id="10054" Class="CControlScriptButton"></Control>
-							<Control Id="10055" Class="CControlScriptButton"></Control>
-							<Control Id="10056" Class="CControlScriptButton"></Control>
-							<Control Id="10057" Class="CControlScriptButton"></Control>
-							<Control Id="10058" Class="CControlScriptButton"></Control>
-							<Control Id="10059" Class="CControlScriptButton"></Control>
-							<Control Id="10060" Class="CControlScriptButton"></Control>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."></Control>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"></Control>
-								<Control Id="10052" Class="CControlScriptButton"></Control>
-								<Control Id="10053" Class="CControlScriptButton"></Control>
-								<Control Id="10054" Class="CControlScriptButton"></Control>
-								<Control Id="10055" Class="CControlScriptButton"></Control>
-								<Control Id="10056" Class="CControlScriptButton"></Control>
-								<Control Id="10057" Class="CControlScriptButton"></Control>
-								<Control Id="10058" Class="CControlScriptButton"></Control>
-								<Control Id="10059" Class="CControlScriptButton"></Control>
-								<Control Id="10060" Class="CControlScriptButton"></Control>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="36" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"></BarInfo0>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="334, 49" MRUDockPos="318, 54, 634, 81"></BarInfo1>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"></BarInfo2>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"></BarInfo3>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="1, 49" MRUDockPos="1, 49, 334, 75"></BarInfo4>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"></BarInfo5>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="4004" Id8="10066" Count="10"></DockBar0>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-		<Layout Description="FlashTool">
-			<Dockinglayout>
-				<FlashTool>
-					<Summary Panes="14" Client="8" TopContainer="4"/>
-					<Pane-1 Type="5" Panes="0" Direction="0"/>
-					<Pane-2 Type="5" Panes="0" Direction="1"/>
-					<Pane-3 Type="5" Panes="0" Direction="3"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="12" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="1" Pane-1="6" DockingCY="510"/>
-					<Pane-6 Type="2" Panes="2" Pane-1="7" Pane-2="9" DockingCX="791" DockingCY="510"/>
-					<Pane-7 Type="2" Horiz="1" Panes="1" Pane-1="8" DockingCY="401"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="2" Horiz="1" Panes="1" Pane-1="10" DockingCX="200" DockingCY="105"/>
-					<Pane-10 Type="1" Panes="1" Pane-1="11" Selected="11" DockingCX="200" DockingCY="120"/>
-					<Pane-11 ID="40050" Type="0" Title="Memory - Mem0\nMem0" DockingCX="200" DockingCY="120" LastHolder="10" DockingHolder="10"/>
-					<Pane-12 Type="2" Horiz="1" Panes="1" Pane-1="13" DockingCX="995" DockingCY="101"/>
-					<Pane-13 Type="1" Panes="1" Pane-1="14" Selected="14" DockingCX="728" DockingCY="101"/>
-					<Pane-14 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="13" DockingHolder="13"/>
-				</FlashTool>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="0" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
-						<Position x="0" y="352"/>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="534" cy="471"/>
-						<Position x="-4" y="-23"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="566" cy="421"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-				</Window>
-				<Window Id="SFRWindow">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Normal">
-						<Size cx="300" cy="200"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Position x="-4" y="-30"/>
-						<Size cx="746" cy="219"/>
-					</Rectangle>
-				</Window>
-			</Windows>
-			<CommandBars>
-				<Layout>
-					<DockState Count="5" Version="8" ScreenSize="1024, 768">
-						<BarInfo0 BarId="1" MRUWidth="32767"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="346, 50" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="375, 23" MRUDockPos="374, 23, 610, 50"/>
-						<BarInfo3 BarId="4004" MRUWidth="32767" PointPos="0, 50" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo4 BarId="128" MRUWidth="32767" PointPos="0, 23" MRUDockPos="-12, 27, 363, 54"/>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="9025" Id4="128" Id6="10066" Id7="4004" Count="9"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<Component Id="DataTrace"/>
-	<PowerScale EnableInstrumentation="0"/>
-	<FlashProgramming RAMBase="0x20000000" RAMLength="0x3000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F100xE" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x08000000" Manufacturer="ST">
-			<Sectors Count="0"/>
-		</FlashDevice>
-	</FlashProgramming>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="Project" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM32100E-EVAL">
-			<SymbolLoader ProjRel="1" MessageFile="" NeedsSymprepRun="0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text=".\source\"/>
-						<Path Text=".\"/>
-						<Path Text=".\Source\"/>
-						<Path Text=".\Settings\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\Common\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM32100E-EVAL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="Project.abs" StopBuildOnError="1">
-					<IncludePath Path="..\..\" Position="0"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="4"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\" Position="6"></IncludePath>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_HD_VL;USE_STM32100E_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -Wc-I&quot;$(TARGETDIR)\..\library\inc&quot; -v -Wa-L1 -Wc-w560 -Wc-w557 -Wc-w507 -Wc-w523  -Wc-t4  "></Compiler>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr
deleted file mode 100644
index e3dbe23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl
deleted file mode 100644
index 3e6d303..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl
+++ /dev/null
@@ -1,287 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  arm_arch.lsl
-//
-//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
-//
-//  Description :  Generic LSL file for ARM architectures
-//
-//  Copyright 2008-2009 Altium BV
-//
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __STACK
-#  define __STACK                       32k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        32k
-#endif
-#ifndef __STACK_FIQ
-#  define __STACK_FIQ                   8
-#endif
-#ifndef __STACK_IRQ
-#  define __STACK_IRQ                   8
-#endif
-#ifndef __STACK_SVC
-#  define __STACK_SVC                   8
-#endif
-#ifndef __STACK_ABT
-#  define __STACK_ABT                   8
-#endif
-#ifndef __STACK_UND
-#  define __STACK_UND                   8
-#endif
-#ifndef __PROCESSOR_MODE
-#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
-#endif
-#ifndef __IRQ_BIT
-#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
-#endif
-#ifndef __FIQ_BIT
-#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
-#endif
-
-#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
-
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_ADDR
-#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
-#endif
-
-#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-#  ifndef __NR_OF_VECTORS
-#    define __NR_OF_VECTORS             16
-#  endif
-#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
-#else
-#  ifdef __PIC_VECTORS
-#    define __VECTOR_TABLE_SIZE         64
-#  else
-#    ifdef __FIQ_HANDLER_INLINE
-#      define __VECTOR_TABLE_SIZE       28
-#      define __NR_OF_VECTORS           7
-#    else
-#      define __VECTOR_TABLE_SIZE       32
-#      define __NR_OF_VECTORS           8
-#    endif
-#  endif
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_SPACE
-#  undef __VECTOR_TABLE_RAM_COPY
-#endif
-
-#ifndef __XVWBUF
-#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
-#endif
-
-#define BOUNDS_GROUP_NAME       grp_bounds
-#define BOUNDS_GROUP_SELECT     "bounds"
-
-architecture ARM
-{
-        endianness
-        {
-                little;
-                big;
-        }
-
-        space linear
-        {
-                id = 1;
-                mau = 8;
-                map (size = 4G, dest = bus:local_bus);
-
-                copytable
-                (
-                        align = 4,
-                        copy_unit = 1,
-                        dest = linear
-                );
-
-                start_address
-                (
-                        // It is not strictly necessary to define a run_addr for _START
-                        // because hardware starts execution at address 0x0 which should
-                        // be the vector table with a jump to the relocatable _START, but
-                        // an absolute address can prevent the branch to be out-of-range.
-                        // Or _START may be the entry point at reset and the reset handler
-                        // copies the vector table to address 0x0 after some ROM/RAM memory
-                        // re-mapping. In that case _START should be at a fixed address
-                        // in ROM, specifically the alias of address 0x0 before memory
-                        // re-mapping.
-#ifdef __START
-                        run_addr = __START,
-#endif
-                        symbol = "_START"
-                );
-
-                stack "stack"
-                (
-#ifdef __STACK_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size = __STACK,
-                        grows = high_to_low
-                );
-
-                heap "heap"
-                (
-#ifdef __HEAP_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size=__HEAP
-                );
-
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                stack "stack_fiq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_FIQ,
-                        grows = high_to_low
-                );
-                stack "stack_irq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_IRQ,
-                        grows = high_to_low
-                );
-                stack "stack_svc"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_SVC,
-                        grows = high_to_low
-                );
-                stack "stack_abt"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_ABT,
-                        grows = high_to_low
-                );
-                stack "stack_und"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_UND,
-                        grows = high_to_low
-                );
-#endif
-
-#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
-# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                }
-#  else
-#    ifdef __PIC_VECTORS
-                // vector table with ldrpc instructions from handler table
-                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_ldrpc",
-                                              template_symbol = "_lc_vector_ldrpc",
-                                              vector_prefix = "_vector_ldrpc_",
-                                              fill = loop
-                                            )
-                {
-                }
-                // subsequent vector table (data pool) with addresses of handlers
-                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
-                                               template = ".text.handler_address",
-                                               template_symbol = "_lc_vector_handler",
-                                               vector_prefix = "_vector_",
-                                               fill = loop[-32],
-                                               no_inline
-                                             )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    else
-                // vector table with branch instructions to handlers
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_branch",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    endif
-#  endif
-#endif
-                section_layout
-                {
-#if defined(__NO_AUTO_VECTORS)
-                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
-                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
-#endif
-#ifdef __VECTOR_TABLE_RAM_SPACE
-                        // reserve space to copy vector table from ROM to RAM
-                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
-                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
-#endif
-#ifdef __VECTOR_TABLE_RAM_COPY
-                        // provide copy address symbols for copy routine
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
-#else
-                        // prevent copy: copy address equals orig address
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
-#endif
-                        // define buffer for string input via Crossview Pro debugger
-                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
-
-                        // define labels for bounds begin and end as used in C library
-#ifndef BOUNDS_GROUP_REDEFINED
-                        group BOUNDS_GROUP_NAME (ordered, contiguous)
-                        {
-                                select BOUNDS_GROUP_SELECT;
-                        }
-#endif
-                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
-                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
-
-#ifdef __HEAPADDR
-                        group ( ordered, run_addr=__HEAPADDR )
-                        {
-                                select "heap";
-                        }
-#endif
-#ifdef __STACKADDR
-                        group ( ordered, run_addr=__STACKADDR )
-                        {
-                                select "stack";
-                        }
-#endif
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                        // symbol to set mode bits and interrupt disable bits
-                        // in cstart module before calling the application (main)
-                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
-#endif
-                }
-        }
-
-        bus local_bus
-        {
-                mau = 8;
-                width = 32;
-        }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk
deleted file mode 100644
index a253595..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/stm32f10x_hd_vl.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk
deleted file mode 100644
index 9ac15b9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/stm32f10x_hd_vl_extsram.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl
deleted file mode 100644
index 9038512..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl
+++ /dev/null
@@ -1,158 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 32k;
-    map ( size = 32k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                   // ADC1 
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );        // TIM1_BRK_TIM15_IRQHandler
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );              // TIM1_UP_TIM16_IRQHandler
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );         // TIM1_TRG_COM_TIM17_IRQHandler
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                 // CEC_IRQHandler
-                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );             // TIM12_IRQHandler
-                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );              // TIM13_IRQHandler
-                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );             // TIM14_IRQHandler
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );                 // TIM6_DAC_IRQHandler
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl_extsram.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl_extsram.lsl
deleted file mode 100644
index ebc4fb7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl_extsram.lsl
+++ /dev/null
@@ -1,173 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       2k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 1024k;
-    map ( size = 1024k, dest_offset=0x68000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp
deleted file mode 100644
index 4c9ed12..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp
+++ /dev/null
@@ -1,1001 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<!-- ======================================================================= -->
-<!-- ** DON'T EDIT THIS FILE! IT WILL BE AUTOMATICALY GENERATED BY HITOP! ** -->
-<!-- ======================================================================= -->
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103VB.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722848" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325498" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954638" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="-4" y="-30"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="844" cy="627"></Size>
-				<Position x="-4" y="-30"></Position>
-			</Rectangle>
-			<Tabs Count="0" Active="0"/>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-						<Column Id="14" Order="2" Title="Type" Visible="1" RelWidth="0.3856508" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941648" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000468" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059288" Alignment="LEFT"/>
-						<Watches>
-							<Watch Id="O1" Appl="Project"/>
-							<Watch Id="O2" Appl="Project"/>
-							<Watch Id="O3" Appl="Project"/>
-							<Watch Id="O4" Appl="Project"/>
-						</Watches>
-						<Column Id="14" Order="3" Title="Type" Visible="1" RelWidth="0.3359388" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="_lc_ub_stack"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08000080" Symbol="0x08000080"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x00000000" Symbol="_lc_t2_longveneertarget"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Emulator State">
-			<Tabs>
-				<Tab Pos="0">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occurred" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Breakpoint">
-			<Tabs Sel="0">
-				<Tab Pos="0" Title="Code">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500088" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106148" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833418" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560698" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Data">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500018" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106078" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833348" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560628" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="TraceFilter">
-			<Tabs>
-				<Tab Pos="0">
-					<Triggers/>
-				</Tab>
-				<Tab Pos="1">
-					<Regions/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Profile">
-			<Tabs>
-				<Tab Pos="0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Id" Visible="1" RelWidth="0.2275868" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.2827598" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Activity" Visible="1" RelWidth="0.4000008" Alignment="LEFT"/>
-						<Column Id="14" Order="3" Title="Time" Visible="1" RelWidth="0.0896558" Alignment="LEFT"/>
-					</List>
-					<State ModeAbsolute="0" UpdateEnabled="0"/>
-				</Tab>
-			</Tabs>
-			<List Id=""/>
-		</Window>
-		<Window Id="FileView" RelativePath="Relative2Project">
-			<ApplFolder Id="Project" State="Expanded">
-				<Folder Id="CMSIS" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c"/>
-					<File Id="..\..\system_stm32f10x.c"/>
-				</Folder>
-				<Folder Id="Doc" State="Not_Expanded">
-					<File Id=".\readme.txt"/>
-				</Folder>
-				<Folder Id="StdPeriph_Driver" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c"/>
-				</Folder>
-				<Folder Id="STM32_EVAL" State="Not_Expanded">
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_lcd.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\stm32_eval.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c"/>
-				</Folder>
-				<Folder Id="User" State="Not_Expanded">
-					<File Id="..\..\main.c"/>
-					<File Id="..\..\stm32f10x_it.c"/>
-				</Folder>
-				<Folder Id="HiTOP" State="Not_Expanded">
-					<File Id=".\cstart_thumb2.asm"/>
-				</Folder>
-				<Folder Id="Source Files" State="Not_Expanded" RelativePath=""/>
-			</ApplFolder>
-		</Window>
-	</Windows>
-	<Version>V5.20</Version>
-	<DebugDevice>
-		<TargetProcessor Id="PARM"/>
-		<Derivative Id="STM32F103VB" File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\.\..\Arm\Default.drv" Vendor="ST Microelectronics">
-			<InternalFlash Count="1">
-				<Device Id="STM32F103VB" Index="0" Manufacturer="ST"></Device>
-			</InternalFlash>
-		</Derivative>
-		<Communication>
-			<Port>USB</Port>
-			<DeviceName>Tantino for Cortex-10083</DeviceName>
-			<PortAddress Value="-2147483648"/>
-			<BaudRate Value="0"/>
-		</Communication>
-		<SystemDir Path="C:\Program Files\Hitex\HiTOP54-CTX\Tantino-Cortex"/>TANTINO_CORTEX_M3
-		<RecentDerivative SWJDP="1" Vendor="ST Microelectronics" ProcType="30" Endianess="0" Derivative="STM32F103VB"/>
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-			<IRQ Name="EXTI 10-15" Number="40"/>
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-			<IRQ Name="USB Wakeup" Number="42"/>
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-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="6"></IncludePath>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_MD;USE_STM3210B_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -Wc-I&quot;$(TARGETDIR)\..\library\inc&quot; -v -Wa-L1 -Wc-w557 -Wc-w505 -Wc-w529 -Wc-w560 -Wc-w523  -Wc-t4  "></Compiler>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl
deleted file mode 100644
index 0eab7a9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl
+++ /dev/null
@@ -1,149 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 128k;
-    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 20k;
-    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr
deleted file mode 100644
index e3dbe23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl
deleted file mode 100644
index 3e6d303..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl
+++ /dev/null
@@ -1,287 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  arm_arch.lsl
-//
-//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
-//
-//  Description :  Generic LSL file for ARM architectures
-//
-//  Copyright 2008-2009 Altium BV
-//
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __STACK
-#  define __STACK                       32k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        32k
-#endif
-#ifndef __STACK_FIQ
-#  define __STACK_FIQ                   8
-#endif
-#ifndef __STACK_IRQ
-#  define __STACK_IRQ                   8
-#endif
-#ifndef __STACK_SVC
-#  define __STACK_SVC                   8
-#endif
-#ifndef __STACK_ABT
-#  define __STACK_ABT                   8
-#endif
-#ifndef __STACK_UND
-#  define __STACK_UND                   8
-#endif
-#ifndef __PROCESSOR_MODE
-#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
-#endif
-#ifndef __IRQ_BIT
-#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
-#endif
-#ifndef __FIQ_BIT
-#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
-#endif
-
-#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
-
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_ADDR
-#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
-#endif
-
-#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-#  ifndef __NR_OF_VECTORS
-#    define __NR_OF_VECTORS             16
-#  endif
-#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
-#else
-#  ifdef __PIC_VECTORS
-#    define __VECTOR_TABLE_SIZE         64
-#  else
-#    ifdef __FIQ_HANDLER_INLINE
-#      define __VECTOR_TABLE_SIZE       28
-#      define __NR_OF_VECTORS           7
-#    else
-#      define __VECTOR_TABLE_SIZE       32
-#      define __NR_OF_VECTORS           8
-#    endif
-#  endif
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_SPACE
-#  undef __VECTOR_TABLE_RAM_COPY
-#endif
-
-#ifndef __XVWBUF
-#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
-#endif
-
-#define BOUNDS_GROUP_NAME       grp_bounds
-#define BOUNDS_GROUP_SELECT     "bounds"
-
-architecture ARM
-{
-        endianness
-        {
-                little;
-                big;
-        }
-
-        space linear
-        {
-                id = 1;
-                mau = 8;
-                map (size = 4G, dest = bus:local_bus);
-
-                copytable
-                (
-                        align = 4,
-                        copy_unit = 1,
-                        dest = linear
-                );
-
-                start_address
-                (
-                        // It is not strictly necessary to define a run_addr for _START
-                        // because hardware starts execution at address 0x0 which should
-                        // be the vector table with a jump to the relocatable _START, but
-                        // an absolute address can prevent the branch to be out-of-range.
-                        // Or _START may be the entry point at reset and the reset handler
-                        // copies the vector table to address 0x0 after some ROM/RAM memory
-                        // re-mapping. In that case _START should be at a fixed address
-                        // in ROM, specifically the alias of address 0x0 before memory
-                        // re-mapping.
-#ifdef __START
-                        run_addr = __START,
-#endif
-                        symbol = "_START"
-                );
-
-                stack "stack"
-                (
-#ifdef __STACK_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size = __STACK,
-                        grows = high_to_low
-                );
-
-                heap "heap"
-                (
-#ifdef __HEAP_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size=__HEAP
-                );
-
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                stack "stack_fiq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_FIQ,
-                        grows = high_to_low
-                );
-                stack "stack_irq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_IRQ,
-                        grows = high_to_low
-                );
-                stack "stack_svc"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_SVC,
-                        grows = high_to_low
-                );
-                stack "stack_abt"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_ABT,
-                        grows = high_to_low
-                );
-                stack "stack_und"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_UND,
-                        grows = high_to_low
-                );
-#endif
-
-#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
-# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                }
-#  else
-#    ifdef __PIC_VECTORS
-                // vector table with ldrpc instructions from handler table
-                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_ldrpc",
-                                              template_symbol = "_lc_vector_ldrpc",
-                                              vector_prefix = "_vector_ldrpc_",
-                                              fill = loop
-                                            )
-                {
-                }
-                // subsequent vector table (data pool) with addresses of handlers
-                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
-                                               template = ".text.handler_address",
-                                               template_symbol = "_lc_vector_handler",
-                                               vector_prefix = "_vector_",
-                                               fill = loop[-32],
-                                               no_inline
-                                             )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    else
-                // vector table with branch instructions to handlers
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_branch",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    endif
-#  endif
-#endif
-                section_layout
-                {
-#if defined(__NO_AUTO_VECTORS)
-                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
-                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
-#endif
-#ifdef __VECTOR_TABLE_RAM_SPACE
-                        // reserve space to copy vector table from ROM to RAM
-                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
-                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
-#endif
-#ifdef __VECTOR_TABLE_RAM_COPY
-                        // provide copy address symbols for copy routine
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
-#else
-                        // prevent copy: copy address equals orig address
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
-#endif
-                        // define buffer for string input via Crossview Pro debugger
-                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
-
-                        // define labels for bounds begin and end as used in C library
-#ifndef BOUNDS_GROUP_REDEFINED
-                        group BOUNDS_GROUP_NAME (ordered, contiguous)
-                        {
-                                select BOUNDS_GROUP_SELECT;
-                        }
-#endif
-                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
-                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
-
-#ifdef __HEAPADDR
-                        group ( ordered, run_addr=__HEAPADDR )
-                        {
-                                select "heap";
-                        }
-#endif
-#ifdef __STACKADDR
-                        group ( ordered, run_addr=__STACKADDR )
-                        {
-                                select "stack";
-                        }
-#endif
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                        // symbol to set mode bits and interrupt disable bits
-                        // in cstart module before calling the application (main)
-                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
-#endif
-                }
-        }
-
-        bus local_bus
-        {
-                mau = 8;
-                width = 32;
-        }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr
deleted file mode 100644
index 3e9c066..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr
+++ /dev/null
@@ -1,12 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application & Go main 
-
-// Reset    
-RESET TARGET
-
-
-// execute program till main
-Go UNTIL main
-wait
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl
deleted file mode 100644
index a85d784..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl
+++ /dev/null
@@ -1,166 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 84
-
-
-#ifndef __STACK
-#  define __STACK                       2k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        1k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 256k;
-    map ( size = 256k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 64k;
-    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              //  CAN1 TX
-                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "OTG_FS_WKUP_IRQHandler" );          // USB OTG FS Wakeup through EXTI line
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );      // DMA2 Channel4 
-		             	vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );      // DMA2 Channel5 
-			            vector ( id = 77, optional, fill = "ETH_IRQHandler" );                  // Ethernet
-					    vector ( id = 78, optional, fill = "ETH_WKUP_IRQHandler" );         // ETH_WKUP_IRQHandler
-			            vector ( id = 79, optional, fill = "CAN2_TX_IRQHandler " );              // CAN2 TX
-			            vector ( id = 80, optional, fill = "CAN2_RX0_IRQHandler" );              // CAN2 RX0
-			            vector ( id = 81, optional, fill = "CAN2_RX1_IRQHandler" );              // CAN2 RX1
-			            vector ( id = 82, optional, fill = "CAN2_SCE_IRQHandler" );              // CAN2 SCE
-			            vector ( id = 83, optional, fill = "OTG_FS_IRQHandler" );                // USB OTG FS
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr
deleted file mode 100644
index e3dbe23..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr
deleted file mode 100644
index 3e9c066..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr
+++ /dev/null
@@ -1,12 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application & Go main 
-
-// Reset    
-RESET TARGET
-
-
-// execute program till main
-Go UNTIL main
-wait
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt
deleted file mode 100644
index 33c0957..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
-  @page HiTOP5_STM3210C HiTOP Project Template for STM32F10x Connectivity line devices
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with HiTOP software toolchain (version 5.40 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
-@par Directory contents
-
- - Project.htp: A pre-configured project file with the provided library 
-                structure that produces an executable image with HiTOP
-
- - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized
-                      sections from ROM to RAM.                 
-
- - Objects: This mandatory directory contains the executable images.
-
- - Settings: This directory contains the linker and script files.                  
-     - arm_arch.lsl: This file is used to place program code (readonly)
-                     in internal FLASH and data (readwrite, Stack and Heap)
-                     in internal SRAM.
-
-     - link.lnk: This file is the HiTOP linker it invokes the STM32F10x_cl.lsl.
-                                   
-     - reset_appl.scr: This file is a HiTOP script it performs a target reset.
-     
-     - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
-                          Counter at the "main" instruction.
-
-     - StartupScript.scr: This file is a HiTOP script and it performs a target 
-                          reset before loading The executable image.
-
-     - STM32F10x_cl.lsl: This file is used to place program code (readonly)
-                         in internal FLASH and data (readwrite, Stack and Heap)
-                         in internal SRAM.
-                         It contains also the vector table of the STM32 
-                         Connectivity line devices.
-                         You can customize this file to your need. 
-
-
-@par How to use it ?
-
-- Open the HiTOP toolchain.
-- Browse to open the project.htp
-- A "Download application" window is displayed, click "cancel".
-- Rebuild all files: Project->Rebuild all
-- Load project image : Click "ok" in the "Download application" window.
-- Run the "RESET_GO_MAIN" script to set the PC at the "main"
-- Run program: Debug->Go(F5).
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_extsram.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_extsram.lsl
deleted file mode 100644
index adaac37..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_extsram.lsl
+++ /dev/null
@@ -1,174 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR        0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset= 0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 1024k;
-    map ( size = 1024k, dest_offset=0x68000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl
deleted file mode 100644
index 77a6526..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl
+++ /dev/null
@@ -1,165 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 64k;
-    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/arm_arch.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/arm_arch.lsl
deleted file mode 100644
index 3e6d303..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/arm_arch.lsl
+++ /dev/null
@@ -1,287 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  arm_arch.lsl
-//
-//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
-//
-//  Description :  Generic LSL file for ARM architectures
-//
-//  Copyright 2008-2009 Altium BV
-//
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __STACK
-#  define __STACK                       32k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        32k
-#endif
-#ifndef __STACK_FIQ
-#  define __STACK_FIQ                   8
-#endif
-#ifndef __STACK_IRQ
-#  define __STACK_IRQ                   8
-#endif
-#ifndef __STACK_SVC
-#  define __STACK_SVC                   8
-#endif
-#ifndef __STACK_ABT
-#  define __STACK_ABT                   8
-#endif
-#ifndef __STACK_UND
-#  define __STACK_UND                   8
-#endif
-#ifndef __PROCESSOR_MODE
-#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
-#endif
-#ifndef __IRQ_BIT
-#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
-#endif
-#ifndef __FIQ_BIT
-#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
-#endif
-
-#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
-
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_ADDR
-#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
-#endif
-
-#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-#  ifndef __NR_OF_VECTORS
-#    define __NR_OF_VECTORS             16
-#  endif
-#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
-#else
-#  ifdef __PIC_VECTORS
-#    define __VECTOR_TABLE_SIZE         64
-#  else
-#    ifdef __FIQ_HANDLER_INLINE
-#      define __VECTOR_TABLE_SIZE       28
-#      define __NR_OF_VECTORS           7
-#    else
-#      define __VECTOR_TABLE_SIZE       32
-#      define __NR_OF_VECTORS           8
-#    endif
-#  endif
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_SPACE
-#  undef __VECTOR_TABLE_RAM_COPY
-#endif
-
-#ifndef __XVWBUF
-#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
-#endif
-
-#define BOUNDS_GROUP_NAME       grp_bounds
-#define BOUNDS_GROUP_SELECT     "bounds"
-
-architecture ARM
-{
-        endianness
-        {
-                little;
-                big;
-        }
-
-        space linear
-        {
-                id = 1;
-                mau = 8;
-                map (size = 4G, dest = bus:local_bus);
-
-                copytable
-                (
-                        align = 4,
-                        copy_unit = 1,
-                        dest = linear
-                );
-
-                start_address
-                (
-                        // It is not strictly necessary to define a run_addr for _START
-                        // because hardware starts execution at address 0x0 which should
-                        // be the vector table with a jump to the relocatable _START, but
-                        // an absolute address can prevent the branch to be out-of-range.
-                        // Or _START may be the entry point at reset and the reset handler
-                        // copies the vector table to address 0x0 after some ROM/RAM memory
-                        // re-mapping. In that case _START should be at a fixed address
-                        // in ROM, specifically the alias of address 0x0 before memory
-                        // re-mapping.
-#ifdef __START
-                        run_addr = __START,
-#endif
-                        symbol = "_START"
-                );
-
-                stack "stack"
-                (
-#ifdef __STACK_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size = __STACK,
-                        grows = high_to_low
-                );
-
-                heap "heap"
-                (
-#ifdef __HEAP_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size=__HEAP
-                );
-
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                stack "stack_fiq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_FIQ,
-                        grows = high_to_low
-                );
-                stack "stack_irq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_IRQ,
-                        grows = high_to_low
-                );
-                stack "stack_svc"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_SVC,
-                        grows = high_to_low
-                );
-                stack "stack_abt"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_ABT,
-                        grows = high_to_low
-                );
-                stack "stack_und"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_UND,
-                        grows = high_to_low
-                );
-#endif
-
-#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
-# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                }
-#  else
-#    ifdef __PIC_VECTORS
-                // vector table with ldrpc instructions from handler table
-                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_ldrpc",
-                                              template_symbol = "_lc_vector_ldrpc",
-                                              vector_prefix = "_vector_ldrpc_",
-                                              fill = loop
-                                            )
-                {
-                }
-                // subsequent vector table (data pool) with addresses of handlers
-                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
-                                               template = ".text.handler_address",
-                                               template_symbol = "_lc_vector_handler",
-                                               vector_prefix = "_vector_",
-                                               fill = loop[-32],
-                                               no_inline
-                                             )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    else
-                // vector table with branch instructions to handlers
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_branch",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    endif
-#  endif
-#endif
-                section_layout
-                {
-#if defined(__NO_AUTO_VECTORS)
-                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
-                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
-#endif
-#ifdef __VECTOR_TABLE_RAM_SPACE
-                        // reserve space to copy vector table from ROM to RAM
-                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
-                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
-#endif
-#ifdef __VECTOR_TABLE_RAM_COPY
-                        // provide copy address symbols for copy routine
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
-#else
-                        // prevent copy: copy address equals orig address
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
-#endif
-                        // define buffer for string input via Crossview Pro debugger
-                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
-
-                        // define labels for bounds begin and end as used in C library
-#ifndef BOUNDS_GROUP_REDEFINED
-                        group BOUNDS_GROUP_NAME (ordered, contiguous)
-                        {
-                                select BOUNDS_GROUP_SELECT;
-                        }
-#endif
-                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
-                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
-
-#ifdef __HEAPADDR
-                        group ( ordered, run_addr=__HEAPADDR )
-                        {
-                                select "heap";
-                        }
-#endif
-#ifdef __STACKADDR
-                        group ( ordered, run_addr=__STACKADDR )
-                        {
-                                select "stack";
-                        }
-#endif
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                        // symbol to set mode bits and interrupt disable bits
-                        // in cstart module before calling the application (main)
-                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
-#endif
-                }
-        }
-
-        bus local_bus
-        {
-                mau = 8;
-                width = 32;
-        }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr
deleted file mode 100644
index 4dbe250..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr
+++ /dev/null
@@ -1,102 +0,0 @@
-// Hitex/We/04.02.2008
-//      
-// StartupScript Script file for HiTOP Debugger
-// Target Hitex evaluation board with STM32Fxxx
-// Flash application
-
-//#########################################################################################
-// Enable APB2 GPIOA .. GPIOG + AFIO Peripheral Clock
-// 
-// Register RCC_APB2ENR		Adr: 0x40021000 + Offs. 0x18	value 0x1FD    
-//#########################################################################################
-OUTPUT DWORD TO 0x40021014 = 0x00000114
-OUTPUT DWORD TO 0x40021018 = 0x000001FD 
-
-
-//#########################################################################################
-//	NOR Datalines GPIOD, GPIOE
-// 
-// Set Bits 0,1,8,9,10,14,15 of Port D to PushPull, 50Mhz Speed
-// Register GPIOD_CRL		Adr: 0x40011400 + Offs. 0x00	value 0x444444BB
-// Register GPIOD_CRH		Adr: 0x40011400 + Offs. 0x04	value 0xBB444BBB
-//
-// Set Bits 7,8,9,10,11,12,13,14,15 of Port E to PushPull, 50Mhz Speed
-// Register GPIOD_CRL		Adr: 0x40011800 + Offs. 0x00	value 0xB4444444
-// Register GPIOD_CRH		Adr: 0x40011800 + Offs. 0x04	value 0xBBBBBBBB
-//   
-//#########################################################################################
-// Port D
-OUTPUT DWORD TO 0x40011400 = 0x44BB44BB
-OUTPUT DWORD TO 0x40011404 = 0xBBBBBBBB
-// Port E 
-OUTPUT DWORD TO 0x40011800 = 0xBBBBBB44
-OUTPUT DWORD TO 0x40011804 = 0xBBBBBBBB
- 
-//#########################################################################################
-//	NOR Addresslines GPIOF, GPIOG
-// 
-// Set Bits 0,1,2,3,4,5,12,13,14,15 of Port F to PushPull, 50Mhz Speed
-// Register GPIOF_CRL		Adr: 0x40011C00 + Offs. 0x00	value 0x444BBBBB
-// Register GPIOF_CRH		Adr: 0x40011C00 + Offs. 0x04	value 0xBBBB4444
-//
-// Set Bits 0,1,2,3,4,5,13,14 of Port G to PushPull, 50Mhz Speed
-// Register GPIOG_CRL		Adr: 0x40012000 + Offs. 0x00	value 0x44BBBBBB
-// Register GPIOG_CRH		Adr: 0x40012000 + Offs. 0x04	value 0x4BB44444
-// 
-// Set Bits 11,12,13 of Port D to PushPull, 50Mhz Speed
-// Register GPIOD_CRH		Adr: 0x40011400 + Offs. 0x04	value 0xBBBBBBBB
-//
-// Set Bits 2,3,4,5,6 of Port E to PushPull, 50Mhz Speed
-// Register GPIOD_CRL		Adr: 0x40011800 + Offs. 0x00	value 0xB4444444
-//#########################################################################################
-// Port F
-OUTPUT DWORD TO 0x40011C00 = 0x44BBBBBB
-OUTPUT DWORD TO 0x40011C04 = 0xBBBB4444
-// Port G 
-OUTPUT DWORD TO 0x40012000 = 0x44BBBBBB
-OUTPUT DWORD TO 0x40012004 = 0x4BB444B4
-// Port D
-//OUTPUT DWORD TO 0x40011404 = 0xBBBBBBBB
-// Port E 
-//OUTPUT DWORD TO 0x40011800 = 0xBBBBBBB4
-
-//#########################################################################################
-//	NOE and NWE Configuration GPIOD
-// 
-// Set Bits 4,5 of Port D to PushPull, 50Mhz Speed
-// Register GPIOD_CRL		Adr: 0x40011400 + Offs. 0x00	value 0x44BB44BB
-//
-//#########################################################################################
-// Port D
-//OUTPUT DWORD TO 0x40011400 = 0x44BB44BB
-
-//#########################################################################################
-//	NE2 Configuration GPIOG
-// 
-// Set Bits 9 Port G to PushPull, 50Mhz Speed
-// Register GPIOD_CRH		Adr: 0x40012000 + Offs. 0x04	value 0x4BB444B4
-//
-//#########################################################################################
-// Port G
-//OUTPUT DWORD TO 0x40012004 = 0x4BB444B4
-
-//#########################################################################################
-//	FSMC Configuration
-//
-//	Bank1 is used
-//  if another Bank is required, then adjust the Register Addresses
-// 
-// Register FSMC_BCR				value 0x00001059
-// Register FSMC_BTR				value 0x00010112
-// Register FSMC_BWTR			value 0x0FFFFFFF
-//#########################################################################################
-
-OUTPUT DWORD TO 0xA0000000 = 0x000030DB
-
-
-OUTPUT DWORD TO 0xA0000008 = 0x00001059
-
-OUTPUT DWORD TO 0xA000000C= 0x30010112
-
-OUTPUT DWORD TO 0xA0000104 = 0x0FFFFFFF
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linkextsram.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linkextsram.lnk
deleted file mode 100644
index 6dbf95a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linkextsram.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_extsram.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk
deleted file mode 100644
index c14afff..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10xnor.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt
deleted file mode 100644
index 7e4c10b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-/**
-  @page HiTOP5_STM3210E HiTOP Project Template for STM32F10x High-density devices
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripherals 
-  *          Library and working with HiTOP software toolchain (version 5.40 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
-@par Directory contents
-
- - Project.htp: A pre-configured project file with the provided library 
-                structure that produces an executable image with HiTOP
-
- - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized
-                      sections from ROM to RAM.                 
-
- - Objects: This mandatory directory contains the executable images.
-
- - Settings: This directory contains the linker and script files.                  
-     - arm_arch.lsl: This file is used to place program code (readonly)
-                     in internal FLASH and data (readwrite, Stack and Heap)
-                     in internal SRAM.
-
-     - flash_nor.scr:  This file is a HiTOP script allowing the FSMC configuration.
-                       It should be executed before programming the NOR flash of the 
-                       STM32 High-density devices.
-                       
-     - link.lnk: This file is the HiTOP linker it invokes the STM32F10x_hd.lsl.
-
-     - linkextsram.lnk: This file is the HiTOP linker it invokes the STM32F10x_extsram.lsl.
-     
-     - linknor.lnk: This file is the HiTOP linker it invokes the STM32F10xnor.lsl.      
-                                   
-     - reset_appl.scr: This file is a HiTOP script it performs a target reset.
-     
-     - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
-                          Counter at the "main" instruction.
-
-     - StartupScript.scr: This file is a HiTOP script and it performs a target 
-                          reset before loading The executable image.
-
-     - STM32F10x_extsram.lsl: This file  used to place program code (readonly) in 
-                              internal FLASH and data (readwrite, Stack and Heap)
-                              in external SRAM.
-                              It contains also the vector table of the STM32 high-density
-                              devices. 
-                              You can customize this file to your need. 
-                              This file is used only with STM32 High-density devices.
-                                 
-     - STM32F10x_hd.lsl: This file is used to place program code (readonly)
-                         in internal FLASH and data (readwrite, Stack and Heap)
-                         in internal SRAM.
-                         It contains also the vector table of the STM32 
-                         High-Density devices.
-                         You can customize this file to your need. 
-
-     - STM32F10xnor.lsl: This file  used to place program code (readonly) in 
-                         external NOR FLASH and data (readwrite, Stack and Heap)
-                         in internal SRAM.
-                         It contains also the vector table of the STM32 high-density
-                         devices. 
-                         You can customize this file to your need. 
-                         This file is used only with STM32 High-density devices.                                
-                             
-@par How to use it ?
-
-- Open the HiTOP toolchain.
-- Browse to open the project.htp
-- A "Download application" window is displayed, click "cancel".
-- Rebuild all files: Project->Rebuild all
-- Load project image : Click "ok" in the "Download application" window.
-- Run the "RESET_GO_MAIN" script to set the PC at the "main"
-- Run program: Debug->Go(F5).
-
-- When using High-density devices, it is mandatory to reset the target before 
-  loading the project into  target
-- It is recommended to run the reset script ( click on TR button in the toolbar menu)
-  after loading the project into target. 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Project.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Project.htp
deleted file mode 100644
index 28de448..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Project.htp
+++ /dev/null
@@ -1,988 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103ZG.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722628" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325278" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954418" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="0" y="0"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="844" cy="623"></Size>
-				<Position x="-4" y="-23"></Position>
-			</Rectangle>
-			<Tabs Count="1" Active="0">
-				<Tab Pos="0" PosX="0" PosY="0" Module="readme.txt" TopLine="1" FilePath="$(PROJECTDIR)\readme.txt" Application="Project"/>
-			</Tabs>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-						<Column Id="14" Order="2" Title="Type" Visible="1" RelWidth="0.3856508" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941628" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000448" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059268" Alignment="LEFT"/>
-						<Watches/>
-						<Column Id="14" Order="3" Title="Type" Visible="1" RelWidth="0.3359388" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="_lc_ub_stack"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08000080" Symbol="0x08000080"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
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-			<Watch Id="O4" Expr="tmp"/>
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-			<Watch Id="O1" Expr="SCB"/>
-			<Watch Id="O2" Expr="TimingDelay"/>
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-	<DownloadOptions Verify="0">
-		<PreLoadScript File="" Execute="0" ProjRelative="1"/>
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-	<ExceptionAssistant>
-		<Exceptions Id="ARM low vectors" Count="7">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="Undefined Instruction" Number="1"/>
-			<Exception Name="SWI" Number="2"/>
-			<Exception Name="Prefetch Abort" Number="3"/>
-			<Exception Name="Data abort" Number="4"/>
-			<Exception Name="IRQ" Number="5"/>
-			<Exception Name="FIQ" Number="6"/>
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-			<IRQ Name="Watchdog" Number="0"/>
-			<IRQ Name="Software interrupt" Number="1"/>
-			<IRQ Name="Debug Receive Command" Number="2"/>
-			<IRQ Name="Debug Transmit Command" Number="3"/>
-			<IRQ Name="Timer 0" Number="4"/>
-			<IRQ Name="Timer 1" Number="5"/>
-			<IRQ Name="Timer 2" Number="6"/>
-			<IRQ Name="Timer 3" Number="7"/>
-			<IRQ Name="USB" Number="8"/>
-			<IRQ Name="USB" Number="9"/>
-			<IRQ Name="SCU" Number="10"/>
-			<IRQ Name="Ethernet MAC" Number="11"/>
-			<IRQ Name="DMA" Number="12"/>
-			<IRQ Name="CAN" Number="13"/>
-			<IRQ Name="IMC" Number="14"/>
-			<IRQ Name="ADC" Number="15"/>
-			<IRQ Name="UART 0" Number="16"/>
-			<IRQ Name="UART 1" Number="17"/>
-			<IRQ Name="UART 2" Number="18"/>
-			<IRQ Name="I2 C0" Number="19"/>
-			<IRQ Name="I2 C1" Number="20"/>
-			<IRQ Name="SSP 0" Number="21"/>
-			<IRQ Name="SSP 1" Number="22"/>
-			<IRQ Name="SCU" Number="23"/>
-			<IRQ Name="RTC" Number="24"/>
-			<IRQ Name="WIU all" Number="25"/>
-			<IRQ Name="WIU Group 0" Number="26"/>
-			<IRQ Name="WIU Group 1" Number="27"/>
-			<IRQ Name="WIU Group 2" Number="28"/>
-			<IRQ Name="WIU Group 3" Number="29"/>
-			<IRQ Name="USB" Number="30"/>
-			<IRQ Name="PFW-BC" Number="31"/>
-			<IRQ Name="IRQ 32" Number="32"/>
-			<IRQ Name="IRQ 33" Number="33"/>
-			<IRQ Name="IRQ 34" Number="34"/>
-			<IRQ Name="IRQ 35" Number="35"/>
-			<IRQ Name="IRQ 36" Number="36"/>
-			<IRQ Name="IRQ 37" Number="37"/>
-			<IRQ Name="IRQ 38" Number="38"/>
-			<IRQ Name="IRQ 39" Number="39"/>
-			<IRQ Name="IRQ 40" Number="40"/>
-			<IRQ Name="IRQ 41" Number="41"/>
-			<IRQ Name="IRQ 42" Number="42"/>
-			<IRQ Name="IRQ 43" Number="43"/>
-			<IRQ Name="IRQ 44" Number="44"/>
-			<IRQ Name="IRQ 45" Number="45"/>
-			<IRQ Name="IRQ 46" Number="46"/>
-			<IRQ Name="IRQ 47" Number="47"/>
-			<IRQ Name="IRQ 48" Number="48"/>
-			<IRQ Name="IRQ 49" Number="49"/>
-			<IRQ Name="IRQ 50" Number="50"/>
-			<IRQ Name="IRQ 51" Number="51"/>
-			<IRQ Name="IRQ 52" Number="52"/>
-			<IRQ Name="IRQ 53" Number="53"/>
-			<IRQ Name="IRQ 54" Number="54"/>
-			<IRQ Name="IRQ 55" Number="55"/>
-			<IRQ Name="IRQ 56" Number="56"/>
-			<IRQ Name="IRQ 57" Number="57"/>
-			<IRQ Name="IRQ 58" Number="58"/>
-			<IRQ Name="IRQ 59" Number="59"/>
-			<IRQ Name="IRQ 60" Number="60"/>
-			<IRQ Name="IRQ 61" Number="61"/>
-			<IRQ Name="IRQ 62" Number="62"/>
-			<IRQ Name="IRQ 63" Number="63"/>
-		</Interrupts>
-		<Exceptions Id="cortex-M3 vectors" Count="10">
-			<Exception Name="Reset" Number="0"/>
-			<Exception Name="NMI" Number="1"/>
-			<Exception Name="HardFault" Number="2"/>
-			<Exception Name="MemManage" Number="3"/>
-			<Exception Name="BusFault" Number="4"/>
-			<Exception Name="UsageFault" Number="5"/>
-			<Exception Name="SVCall" Number="6"/>
-			<Exception Name="DebugMon" Number="7"/>
-			<Exception Name="PendSV" Number="8"/>
-			<Exception Name="SysTick" Number="9"/>
-		</Exceptions>
-		<Interrupts Id="STM32_NVIC" Count="43" VectorCount="43">
-			<Vector Number="0" Enabled="0"/>
-			<Vector Number="1" Enabled="0"/>
-			<Vector Number="2" Enabled="0"/>
-			<Vector Number="3" Enabled="0"/>
-			<Vector Number="4" Enabled="0"/>
-			<Vector Number="5" Enabled="0"/>
-			<Vector Number="6" Enabled="0"/>
-			<Vector Number="7" Enabled="0"/>
-			<Vector Number="8" Enabled="0"/>
-			<Vector Number="9" Enabled="0"/>
-			<Vector Number="10" Enabled="0"/>
-			<Vector Number="11" Enabled="0"/>
-			<Vector Number="12" Enabled="0"/>
-			<Vector Number="13" Enabled="0"/>
-			<Vector Number="14" Enabled="0"/>
-			<Vector Number="15" Enabled="0"/>
-			<Vector Number="16" Enabled="0"/>
-			<Vector Number="17" Enabled="0"/>
-			<Vector Number="18" Enabled="0"/>
-			<Vector Number="19" Enabled="0"/>
-			<Vector Number="20" Enabled="0"/>
-			<Vector Number="21" Enabled="0"/>
-			<Vector Number="22" Enabled="0"/>
-			<Vector Number="23" Enabled="0"/>
-			<Vector Number="24" Enabled="0"/>
-			<Vector Number="25" Enabled="0"/>
-			<Vector Number="26" Enabled="0"/>
-			<Vector Number="27" Enabled="0"/>
-			<Vector Number="28" Enabled="0"/>
-			<Vector Number="29" Enabled="0"/>
-			<Vector Number="30" Enabled="0"/>
-			<Vector Number="31" Enabled="0"/>
-			<Vector Number="32" Enabled="0"/>
-			<Vector Number="33" Enabled="0"/>
-			<Vector Number="34" Enabled="0"/>
-			<Vector Number="35" Enabled="0"/>
-			<Vector Number="36" Enabled="0"/>
-			<Vector Number="37" Enabled="0"/>
-			<Vector Number="38" Enabled="0"/>
-			<Vector Number="39" Enabled="0"/>
-			<Vector Number="40" Enabled="0"/>
-			<Vector Number="41" Enabled="0"/>
-			<Vector Number="42" Enabled="0"/>
-			<IRQ Name="WWDG" Number="0"/>
-			<IRQ Name="PVD" Number="1"/>
-			<IRQ Name="TAMPER" Number="2"/>
-			<IRQ Name="RTC" Number="3"/>
-			<IRQ Name="FLASH" Number="4"/>
-			<IRQ Name="RCC" Number="5"/>
-			<IRQ Name="EXTI 0" Number="6"/>
-			<IRQ Name="EXTI 1" Number="7"/>
-			<IRQ Name="EXTI 2" Number="8"/>
-			<IRQ Name="EXTI 3" Number="9"/>
-			<IRQ Name="EXTI 4" Number="10"/>
-			<IRQ Name="DMA Channel 1" Number="11"/>
-			<IRQ Name="DMA Channel 2" Number="12"/>
-			<IRQ Name="DMA Channel 3" Number="13"/>
-			<IRQ Name="DMA Channel 4" Number="14"/>
-			<IRQ Name="DMA Channel 5" Number="15"/>
-			<IRQ Name="DMA Channel 6" Number="16"/>
-			<IRQ Name="DMA Channel 7" Number="17"/>
-			<IRQ Name="ADC" Number="18"/>
-			<IRQ Name="USB_HP_CAN_TX" Number="19"/>
-			<IRQ Name="USB_LP_CAN_RX 0" Number="20"/>
-			<IRQ Name="CAN_RX 1" Number="21"/>
-			<IRQ Name="CAN_SCE" Number="22"/>
-			<IRQ Name="EXTI 5-9" Number="23"/>
-			<IRQ Name="TIM 1 BRK" Number="24"/>
-			<IRQ Name="TIM 1 UP" Number="25"/>
-			<IRQ Name="TIM 1 TRG COM" Number="26"/>
-			<IRQ Name="TIM 1 CC" Number="27"/>
-			<IRQ Name="TIM 2" Number="28"/>
-			<IRQ Name="TIM 3" Number="29"/>
-			<IRQ Name="TIM 4" Number="30"/>
-			<IRQ Name="I2C 1 EV" Number="31"/>
-			<IRQ Name="I2C 1 ER" Number="32"/>
-			<IRQ Name="I2C 2 EV" Number="33"/>
-			<IRQ Name="I2C 2 ER" Number="34"/>
-			<IRQ Name="SPI 1" Number="35"/>
-			<IRQ Name="SPI 2" Number="36"/>
-			<IRQ Name="USART 1" Number="37"/>
-			<IRQ Name="USART 2" Number="38"/>
-			<IRQ Name="USART 3" Number="39"/>
-			<IRQ Name="EXTI 10-15" Number="40"/>
-			<IRQ Name="RTC ALARM" Number="41"/>
-			<IRQ Name="USB Wakeup" Number="42"/>
-		</Interrupts>
-		<Exceptions Id="STM32xxx_C_D_E" Count="0"/>
-	</ExceptionAssistant>
-	<HiTOPOpen ComponentId="Semihosting">
-		<Configuration>
-			<General Showed="0"/>
-		</Configuration>
-	</HiTOPOpen>
-	<Directories>
-		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210E-EVAL_XL\objects\Project.abs"/>
-	</Directories>
-	<Applications>
-		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="Project">C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210E-EVAL_XL\objects\</AppPath>
-	</Applications>
-	<FlashProgramming RAMBase="0x20000000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F103xG" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x8000000" Manufacturer="ST">
-			<Sectors/>
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-	</FlashProgramming>
-	<Component Id="DataTrace"/>
-	<HiTOPOpen ComponentId="SemiHosting">
-		<Configuration>
-			<General Showed="0"/>
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-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."></Control>
-							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_appl.scr"></Control>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_go_main.scr"></Control>
-							<Control Id="10053" Class="CControlScriptButton"></Control>
-							<Control Id="10054" Class="CControlScriptButton"></Control>
-							<Control Id="10055" Class="CControlScriptButton"></Control>
-							<Control Id="10056" Class="CControlScriptButton"></Control>
-							<Control Id="10057" Class="CControlScriptButton"></Control>
-							<Control Id="10058" Class="CControlScriptButton"></Control>
-							<Control Id="10059" Class="CControlScriptButton"></Control>
-							<Control Id="10060" Class="CControlScriptButton"></Control>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."></Control>
-								<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"></Control>
-								<Control Id="10052" Class="CControlScriptButton"></Control>
-								<Control Id="10053" Class="CControlScriptButton"></Control>
-								<Control Id="10054" Class="CControlScriptButton"></Control>
-								<Control Id="10055" Class="CControlScriptButton"></Control>
-								<Control Id="10056" Class="CControlScriptButton"></Control>
-								<Control Id="10057" Class="CControlScriptButton"></Control>
-								<Control Id="10058" Class="CControlScriptButton"></Control>
-								<Control Id="10059" Class="CControlScriptButton"></Control>
-								<Control Id="10060" Class="CControlScriptButton"></Control>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]" TooltipText="Execute script file" DescriptionText="Execute a HiSCRIPT script file."></Control>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="36" ScreenSize="1280, 1024">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"></BarInfo0>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="333, 49" MRUDockPos="318, 54, 634, 81"></BarInfo1>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"></BarInfo2>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"></BarInfo3>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="0, 49" MRUDockPos="-4, 57, 319, 84"></BarInfo4>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"></BarInfo5>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="10066" Id8="4004" Count="10"></DockBar0>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-		<Layout Description="FlashTool">
-			<Dockinglayout>
-				<FlashTool>
-					<Summary Panes="14" Client="8" TopContainer="4"/>
-					<Pane-1 Type="5" Panes="0" Direction="0"/>
-					<Pane-2 Type="5" Panes="0" Direction="1"/>
-					<Pane-3 Type="5" Panes="0" Direction="3"/>
-					<Pane-4 Type="2" Panes="2" Pane-1="5" Pane-2="12" DockingCY="615"/>
-					<Pane-5 Type="2" Horiz="1" Panes="1" Pane-1="6" DockingCY="510"/>
-					<Pane-6 Type="2" Panes="2" Pane-1="7" Pane-2="9" DockingCX="791" DockingCY="510"/>
-					<Pane-7 Type="2" Horiz="1" Panes="1" Pane-1="8" DockingCY="401"/>
-					<Pane-8 Type="4"/>
-					<Pane-9 Type="2" Horiz="1" Panes="1" Pane-1="10" DockingCX="200" DockingCY="105"/>
-					<Pane-10 Type="1" Panes="1" Pane-1="11" Selected="11" DockingCX="200" DockingCY="120"/>
-					<Pane-11 ID="40050" Type="0" Title="Memory - Mem0\nMem0" DockingCX="200" DockingCY="120" LastHolder="10" DockingHolder="10"/>
-					<Pane-12 Type="2" Horiz="1" Panes="1" Pane-1="13" DockingCX="995" DockingCY="101"/>
-					<Pane-13 Type="1" Panes="1" Pane-1="14" Selected="14" DockingCX="728" DockingCY="101"/>
-					<Pane-14 ID="10001" Type="0" Title="Output" DockingCX="200" DockingCY="120" LastHolder="13" DockingHolder="13"/>
-				</FlashTool>
-			</Dockinglayout>
-			<Windows>
-				<MDIState RTOS="0" Trace="0" Source="0" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-				<Window Id="Source">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Minimized">
-						<Size cx="160" cy="24"/>
-						<Position x="0" y="352"/>
-					</Rectangle>
-					<Rectangle State="Normal">
-						<Size cx="534" cy="471"/>
-						<Position x="-4" y="-23"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Size cx="566" cy="421"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-				</Window>
-				<Window Id="SFRWindow">
-					<WindowState State="Maximized"/>
-					<Rectangle State="Normal">
-						<Size cx="300" cy="200"/>
-						<Position x="-4" y="-30"/>
-					</Rectangle>
-					<Rectangle State="Maximized">
-						<Position x="-4" y="-30"/>
-						<Size cx="746" cy="219"/>
-					</Rectangle>
-				</Window>
-			</Windows>
-			<CommandBars>
-				<Layout>
-					<DockState Count="5" Version="8" ScreenSize="1024, 768">
-						<BarInfo0 BarId="1" MRUWidth="32767"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="346, 50" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="375, 23" MRUDockPos="374, 23, 610, 50"/>
-						<BarInfo3 BarId="4004" MRUWidth="32767" PointPos="0, 50" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo4 BarId="128" MRUWidth="32767" PointPos="0, 23" MRUDockPos="-12, 27, 363, 54"/>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="9025" Id4="128" Id6="10066" Id7="4004" Count="9"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<PowerScale EnableInstrumentation="0"/>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="Project" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM32F10X_XL">
-			<SymbolLoader ProjRel="1" MessageFile="" NeedsSymprepRun="0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text=".\"/>
-						<Path Text="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\"/>
-						<Path Text="..\..\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\Common\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM32F10X_XL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="Project.abs" StopBuildOnError="1">
-					<IncludePath Path="..\..\" Position="0"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="4"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\" Position="6"></IncludePath>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_XL;USE_STM3210E_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -v -Wa-L1 -Wc-t4   -Wc-w560 -Wc-w557 -Wc-w523 "></Compiler>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl
deleted file mode 100644
index 2cddf36..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl
+++ /dev/null
@@ -1,165 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 0x100000;
-    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 96k;
-    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl
deleted file mode 100644
index 5bf6ca2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl
+++ /dev/null
@@ -1,174 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  stm32f103_cmsis.lsl
-//
-//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
-//
-//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
-//
-//  Copyright 2009 Altium BV     
-//
-//  NOTE:
-//      This file is derived from cm3.lsl and stm32f103.lsl.
-//      It is assumed that the user works with the ARMv7M architecture.
-//      Other architectures will not work with this lsl file.
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-// We do not want the vectors as defined in arm_arch.lsl
-//
-#define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
-
-
-#ifndef __STACK
-#  define __STACK                       8k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        2k
-#endif
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR        0x08000000
-#endif
-#ifndef __XVWBUF
-#define __XVWBUF                        256             /* buffer used by CrossView */
-#endif
-
-#include <arm_arch.lsl>
-
-////////////////////////////////////////////////////////////////////////////
-//
-// In the STM32F10x, 3 different boot modes can be selected
-// - User Flash memory is selected as boot space
-// - SystemMemory is selected as boot space
-// - Embedded SRAM is selected as boot space
-//
-// This aliases the physical memory associated with each boot mode to Block
-// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
-// the related memory (Flash memory or SRAM) is still accessible at its
-// original memory space.
-//
-// If no memory is defined yet use the following memory settings
-//
-#ifndef __MEMORY
-
-memory stm32f103flash
-{
-    mau = 8;
-    type = rom;
-    size = 0x100000;
-    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
-}
-memory stm32f103ram
-{
-    mau = 8;
-    type = ram;
-    size = 1024k;
-    map ( size = 1024k, dest_offset=0x68000000, dest=bus:ARM:local_bus);
-}
-
-#endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
-
-
-//
-// Custom vector table defines interrupts according to CMSIS standard
-//
-# if defined(__CPU_ARMV7M__)
-section_setup ::linear
-{
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                       vector ( id = 1, fill = "_START" );
-                        vector ( id = 2, optional, fill = "NMI_Handler" );
-                        vector ( id = 3, optional, fill = "HardFault_Handler" );
-                        vector ( id = 4, optional, fill = "MemManage_Handler" );
-                        vector ( id = 5, optional, fill = "BusFault_Handler" );
-                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
-                        vector ( id = 11, optional, fill = "SVC_Handler" );
-                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
-                        vector ( id = 14, optional, fill = "PendSV_Handler" );
-                        vector ( id = 15, optional, fill = "SysTick_Handler" );
-
-                        // External Interrupts :
-                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
-                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
-                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
-                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
-                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
-                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
-                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
-                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
-                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
-                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
-                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
-                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
-                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
-                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
-                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
-                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
-                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
-                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
-                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
-                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
-                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
-                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
-                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
-                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
-                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
-                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
-                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
-                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
-                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
-                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
-                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
-                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
-                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
-                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
-                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
-                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
-                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
-                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
-                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
-                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
-                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
-                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
-                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
-                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
-                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
-                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
-                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
-                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
-                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
-                }
-}
-# endif
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl
deleted file mode 100644
index 3e6d303..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl
+++ /dev/null
@@ -1,287 +0,0 @@
-////////////////////////////////////////////////////////////////////////////
-//
-//  File        :  arm_arch.lsl
-//
-//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
-//
-//  Description :  Generic LSL file for ARM architectures
-//
-//  Copyright 2008-2009 Altium BV
-//
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __STACK
-#  define __STACK                       32k
-#endif
-#ifndef __HEAP
-#  define __HEAP                        32k
-#endif
-#ifndef __STACK_FIQ
-#  define __STACK_FIQ                   8
-#endif
-#ifndef __STACK_IRQ
-#  define __STACK_IRQ                   8
-#endif
-#ifndef __STACK_SVC
-#  define __STACK_SVC                   8
-#endif
-#ifndef __STACK_ABT
-#  define __STACK_ABT                   8
-#endif
-#ifndef __STACK_UND
-#  define __STACK_UND                   8
-#endif
-#ifndef __PROCESSOR_MODE
-#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
-#endif
-#ifndef __IRQ_BIT
-#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
-#endif
-#ifndef __FIQ_BIT
-#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
-#endif
-
-#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
-
-#ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_ADDR
-#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
-#endif
-
-#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-#  ifndef __NR_OF_VECTORS
-#    define __NR_OF_VECTORS             16
-#  endif
-#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
-#else
-#  ifdef __PIC_VECTORS
-#    define __VECTOR_TABLE_SIZE         64
-#  else
-#    ifdef __FIQ_HANDLER_INLINE
-#      define __VECTOR_TABLE_SIZE       28
-#      define __NR_OF_VECTORS           7
-#    else
-#      define __VECTOR_TABLE_SIZE       32
-#      define __NR_OF_VECTORS           8
-#    endif
-#  endif
-#endif
-
-#ifndef __VECTOR_TABLE_RAM_SPACE
-#  undef __VECTOR_TABLE_RAM_COPY
-#endif
-
-#ifndef __XVWBUF
-#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
-#endif
-
-#define BOUNDS_GROUP_NAME       grp_bounds
-#define BOUNDS_GROUP_SELECT     "bounds"
-
-architecture ARM
-{
-        endianness
-        {
-                little;
-                big;
-        }
-
-        space linear
-        {
-                id = 1;
-                mau = 8;
-                map (size = 4G, dest = bus:local_bus);
-
-                copytable
-                (
-                        align = 4,
-                        copy_unit = 1,
-                        dest = linear
-                );
-
-                start_address
-                (
-                        // It is not strictly necessary to define a run_addr for _START
-                        // because hardware starts execution at address 0x0 which should
-                        // be the vector table with a jump to the relocatable _START, but
-                        // an absolute address can prevent the branch to be out-of-range.
-                        // Or _START may be the entry point at reset and the reset handler
-                        // copies the vector table to address 0x0 after some ROM/RAM memory
-                        // re-mapping. In that case _START should be at a fixed address
-                        // in ROM, specifically the alias of address 0x0 before memory
-                        // re-mapping.
-#ifdef __START
-                        run_addr = __START,
-#endif
-                        symbol = "_START"
-                );
-
-                stack "stack"
-                (
-#ifdef __STACK_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size = __STACK,
-                        grows = high_to_low
-                );
-
-                heap "heap"
-                (
-#ifdef __HEAP_FIXED
-                        fixed,
-#endif
-                        align = 4,
-                        min_size=__HEAP
-                );
-
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                stack "stack_fiq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_FIQ,
-                        grows = high_to_low
-                );
-                stack "stack_irq"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_IRQ,
-                        grows = high_to_low
-                );
-                stack "stack_svc"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_SVC,
-                        grows = high_to_low
-                );
-                stack "stack_abt"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_ABT,
-                        grows = high_to_low
-                );
-                stack "stack_und"
-                (
-                        fixed,
-                        align = 4,
-                        min_size = __STACK_UND,
-                        grows = high_to_low
-                );
-#endif
-
-#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
-# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
-                // vector table with handler addresses
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.handler_address",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop,
-                                              no_inline
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
-                }
-#  else
-#    ifdef __PIC_VECTORS
-                // vector table with ldrpc instructions from handler table
-                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_ldrpc",
-                                              template_symbol = "_lc_vector_ldrpc",
-                                              vector_prefix = "_vector_ldrpc_",
-                                              fill = loop
-                                            )
-                {
-                }
-                // subsequent vector table (data pool) with addresses of handlers
-                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
-                                               template = ".text.handler_address",
-                                               template_symbol = "_lc_vector_handler",
-                                               vector_prefix = "_vector_",
-                                               fill = loop[-32],
-                                               no_inline
-                                             )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    else
-                // vector table with branch instructions to handlers
-                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
-                                              template = ".text.vector_branch",
-                                              template_symbol = "_lc_vector_handler",
-                                              vector_prefix = "_vector_",
-                                              fill = loop
-                                            )
-                {
-                        vector ( id = 0, fill = "_START" );
-                }
-#    endif
-#  endif
-#endif
-                section_layout
-                {
-#if defined(__NO_AUTO_VECTORS)
-                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
-                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
-#endif
-#ifdef __VECTOR_TABLE_RAM_SPACE
-                        // reserve space to copy vector table from ROM to RAM
-                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
-                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
-#endif
-#ifdef __VECTOR_TABLE_RAM_COPY
-                        // provide copy address symbols for copy routine
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
-#else
-                        // prevent copy: copy address equals orig address
-                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
-                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
-#endif
-                        // define buffer for string input via Crossview Pro debugger
-                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
-
-                        // define labels for bounds begin and end as used in C library
-#ifndef BOUNDS_GROUP_REDEFINED
-                        group BOUNDS_GROUP_NAME (ordered, contiguous)
-                        {
-                                select BOUNDS_GROUP_SELECT;
-                        }
-#endif
-                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
-                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
-
-#ifdef __HEAPADDR
-                        group ( ordered, run_addr=__HEAPADDR )
-                        {
-                                select "heap";
-                        }
-#endif
-#ifdef __STACKADDR
-                        group ( ordered, run_addr=__STACKADDR )
-                        {
-                                select "stack";
-                        }
-#endif
-#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
-                        // symbol to set mode bits and interrupt disable bits
-                        // in cstart module before calling the application (main)
-                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
-#endif
-                }
-        }
-
-        bus local_bus
-        {
-                mau = 8;
-                width = 32;
-        }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/link.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/link.lnk
deleted file mode 100644
index 6451b8c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/link.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/STM32F10x_XL.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_appl.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_appl.scr
deleted file mode 100644
index d90eb15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_appl.scr
+++ /dev/null
@@ -1,8 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application 
-
-// Reset    
-RESET TARGET
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_go_main.scr b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_go_main.scr
deleted file mode 100644
index 3e9c066..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_go_main.scr
+++ /dev/null
@@ -1,12 +0,0 @@
-// Hitex/Lue/11.02.2008 
-// Executable Script file for HiTOP Debugger
-// Reset application & Go main 
-
-// Reset    
-RESET TARGET
-
-
-// execute program till main
-Go UNTIL main
-wait
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm
deleted file mode 100644
index 12dc0d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm
+++ /dev/null
@@ -1,148 +0,0 @@
-
-
-;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
-;;        we will only use 16-bit Thumb intructions.
-
-        .extern _lc_ub_stack            ; usr/sys mode stack pointer
-        .extern _lc_ue_stack            ; symbol required by debugger
-        .extern _lc_ub_table            ; ROM to RAM copy table
-        .extern main
-        .extern _Exit
-        .extern exit
-        .weak   exit
-        .global __get_argcv
-        .weak   __get_argcv
-        .extern __argcvbuf
-        .weak   __argcvbuf
-        .extern __init_hardware
-        .extern __init_vector_table
-		.extern  SystemInit
-        
-    .if @defined('__PROF_ENABLE__')
-        .extern __prof_init
-    .endif
-    .if @defined('__POSIX__')
-        .extern posix_main
-        .extern _posix_boot_stack_top
-    .endif
-
-        .global _START
-
-        .section .text.cstart
-
-        .thumb
-_START: 
-        ;; anticipate possible ROM/RAM remapping
-        ;; by loading the 'real' program address
-        ldr     r1,=_Next
-        bx      r1
-_Next:
-        ;; initialize the stack pointer
-        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
-        mov     sp,r1
-
-        ;; call a user function which initializes hardware
-        ;; such as ROM/RAM re-mapping or MMU configuration
-        bl      __init_hardware
-
-		;ldr    r0, =SystemInit
-        ;bx     r0
-		bl  SystemInit
-
-        ;; copy initialized sections from ROM to RAM
-        ;; and clear uninitialized data sections in RAM
-
-        ldr     r3,=_lc_ub_table
-        movs    r0,#0
-cploop:
-        ldr     r4,[r3,#0]      ; load type
-        ldr     r5,[r3,#4]      ; dst address
-        ldr     r6,[r3,#8]      ; src address
-        ldr     r7,[r3,#12]     ; size
-
-        cmp     r4,#1
-        beq     copy
-        cmp     r4,#2
-        beq     clear
-        b       done
-
-copy:
-        subs    r7,r7,#1
-        ldrb    r1,[r6,r7]
-        strb    r1,[r5,r7]
-        bne     copy
-
-        adds    r3,r3,#16
-        b       cploop
-
-clear:
-        subs    r7,r7,#1
-        strb    r0,[r5,r7]
-        bne     clear
-        
-        adds    r3,r3,#16
-        b       cploop
-        
-done:   
-        ;; initialize or copy the vector table
-        bl      __init_vector_table
- 
-      .if @defined('__POSIX__')
-        
-        ;; posix stack buffer for system upbringing
-        ldr     r0,=_posix_boot_stack_top
-        ldr     r0, [r0]
-        mov     sp,r0
-     
-     .else
-        
-        ;; load r10 with end of USR/SYS stack, which is
-        ;; needed in case stack overflow checking is on
-        ;; NOTE: use 16-bit instructions only, for ARMv6M
-        ldr     r0,=_lc_ue_stack
-        mov     r10,r0
-     
-     .endif
-
-    .if @defined('__PROF_ENABLE__')
-        bl      __prof_init
-    .endif
-
-    .if @defined('__POSIX__')
-        ;; call posix_main with no arguments
-        bl      posix_main
-    .else
-        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
-        bl      __get_argcv
-        ldr     r1,=__argcvbuf
-        ;; call main
-        bl       main
-    .endif
-
-        ;; call exit using the return value from main()
-        ;; Note. Calling exit will also run all functions
-        ;; that were supplied through atexit().
-        bl      exit
-        
-__get_argcv:                    ; weak definition
-        movs     r0,#0
-        bx      lr
-
-        .ltorg
-        .endsec
-
-        .calls  '_START','__init_hardware'
-        .calls  '_START','__init_vector_table'
-    .if @defined('__PROF_ENABLE__')
-        .calls  '_START','__prof_init'
-    .endif
-    .if @defined('__POSIX__')
-        .calls  '_START','posix_main'
-    .else
-        .calls  '_START','__get_argcv'
-        .calls  '_START','main'
-    .endif
-        .calls  '_START','exit'
-        .calls  '_START','',0
-
-        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt
deleted file mode 100644
index d6e6324..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
-  @page HiTOP5_STM3210E_XL HiTOP Project Template for STM32F10x XL-density devices
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with HiTOP software toolchain (version 5.40 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
-@par Directory contents
-
- - Project.htp: A pre-configured project file with the provided library 
-                structure that produces an executable image with HiTOP
-
- - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized
-                      sections from ROM to RAM.                 
-
- - Objects: This mandatory directory contains the executable images.
-
- - Settings: This directory contains the linker and script files.                  
-     - arm_arch.lsl: This file is used to place program code (readonly)
-                     in internal FLASH and data (readwrite, Stack and Heap)
-                     in internal SRAM.
-
-     - link.lnk: This file is the HiTOP linker it invokes the STM32F10x_XL.lsl.
-                                   
-     - reset_appl.scr: This file is a HiTOP script it performs a target reset.
-     
-     - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
-                          Counter at the "main" instruction.
-
-     - StartupScript.scr: This file is a HiTOP script and it performs a target 
-                          reset before loading The executable image.
-
-     - STM32F10x_Xl.lsl: This file is used to place program code (readonly)
-                         in internal FLASH and data (readwrite, Stack and Heap)
-                         in internal SRAM.
-                         It contains also the vector table of the STM32 
-                         XL-density line devices.
-                         You can customize this file to your need. 
-
-
-@par How to use it ?
-
-- Open the HiTOP toolchain.
-- Browse to open the project.htp
-- A "Download application" window is displayed, click "cancel".
-- Rebuild all files: Project->Rebuild all
-- Load project image : Click "ok" in the "Download application" window.
-- Run the "RESET_GO_MAIN" script to set the PC at the "main"
-- Run program: Debug->Go(F5).
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvproj b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvproj
deleted file mode 100644
index 302b754..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvproj
+++ /dev/null
@@ -1,8693 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>STM32100E-EVAL</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>STM32F100ZE</Device>
-          <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>STM32F100xE_lib.SFR</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile></SFDFile>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath>ST\STM32F100xE\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F100xE\</DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\STM32100E-EVAL\</OutputDirectory>
-          <OutputName>STM32100E-EVAL</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM32100E-EVAL\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments></SimDllArguments>
-          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments></SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
-          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments></TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>1</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>BIN\UL2CM3.DLL</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4096</DriverSelection>
-          </Flash1>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M3"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>4</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>2</wLevel>
-            <uThumb>0</uThumb>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL</Define>
-              <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL;..\..\..\Utilities\STM32_EVAL\Common</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>User</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
-              <FileName>misc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
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-                    <NoWarn>2</NoWarn>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define></Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Aads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-            <File>
-              <FileName>startup_stm32f10x_hd_vl.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd_vl.s</FilePath>
-              <FileOption>
-                <CommonProperty>
-                  <UseCPPCompiler>2</UseCPPCompiler>
-                  <RVCTCodeConst>0</RVCTCodeConst>
-                  <RVCTZI>0</RVCTZI>
-                  <RVCTOtherData>0</RVCTOtherData>
-                  <ModuleSelection>0</ModuleSelection>
-                  <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
-                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
-                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
-                  <PublicsOnly>2</PublicsOnly>
-                  <StopOnExitCode>11</StopOnExitCode>
-                  <CustomArgument></CustomArgument>
-                  <IncludeLibraryModules></IncludeLibraryModules>
-                </CommonProperty>
-                <FileArmAds>
-                  <Aads>
-                    <interw>2</interw>
-                    <Ropi>2</Ropi>
-                    <Rwpi>2</Rwpi>
-                    <thumb>2</thumb>
-                    <SplitLS>2</SplitLS>
-                    <SwStkChk>2</SwStkChk>
-                    <NoWarn>2</NoWarn>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define></Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Aads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Doc</GroupName>
-          <Files>
-            <File>
-              <FileName>readme.txt</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt
deleted file mode 100644
index af8e3e7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-/**
-  @page note Note for MDK-ARM
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    note.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the needed steps to use the default startup file
-  *          provided by RealView Microcontroller Development Kit(MDK-ARM).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-
-
-With MDK-ARM toolchain, a simple putchar function executes a SWI and activates 
-a low level putchar function. 
-You have to redirect the low level to your own implementation of these functions.
-
-To guarantee that no functions using the semihosting SWI are included in your 
-application, either:
-
-1. Ensure that the MicroLib option is checked since the microlib does not support
-semihosting
-or 
-2. Use
-- IMPORT __use_no_semihosting_swi from assembly language
-- #pragma import(__use_no_semihosting_swi) from C.
- 
- @endverbatim
- 
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt
deleted file mode 100644
index c647c15..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
-  @page mdkarm MDK-ARM Project Template
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed 
-  *          to create a new project linked with the STM32F10x Standard Peripheral  
-  *          Library and working with RealView MDK-ARM toolchain (Version 4.12 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
- 
- - Project.Uv2/.Opt: A pre-configured project file with the provided library structure
-                     that produces an executable image with MDK-ARM
-
-Enabling "Options for Target 'Output' Browser Information" is useful for quick 
-source files navigation but may slow the compilation time.  
-              
-@note the @subpage note file contains the needed steps to follow when using the 
-default startup file provided by MDK-ARM when creating new projects.
-      
- @par How to use it ?
- 
- - Open the Project.uvproj project
- - In the build toolbar select the project config:
-     - STM32100B-EVAL: to configure the project for STM32 Medium-density Value 
-       line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL
-
-     - STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
-
-     - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL
-
-     - STM3210E-EVAL: to configure the project for STM32 High-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL
-
-     - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL
-
-     - STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL
-           
- - Rebuild all files: Project->Rebuild all target files
- - Load project image: Debug->Start/Stop Debug Session
- - Run program: Debug->Run (F5)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.  
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp
deleted file mode 100644
index 20cb2fa..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp
+++ /dev/null
@@ -1,1928 +0,0 @@
-
-<ApplicationBuild Header="Project" Extern=".\Project.rapp" Path=".\Project.rapp" OutputFile=".\STM32100E-EVAL\Project.elf" sate="98" Config="STM32100E-EVAL" AsyncBuild="" >
-	<Group Header="Doc" Marker="-1" OutputFile="" sate="0" AsyncBuild="" >
-		<NodeText Path=".\readme.txt" Header="readme.txt" Marker="-1" OutputFile="" sate="0" AsyncBuild="" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																													
-	</Group>
-	<Configs>
-		<Config Header="STM3210B-EVAL" />
-		<Config Header="STM3210E-EVAL" />
-		<Config Header="STM3210C-EVAL" />
-		<Config Header="STM32100B-EVAL" />
-		<Config Header="STM3210E-EVAL_XL" />
-		<Config Header="STM32100E-EVAL" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																	
-	</Configs>
-	<Group Header="CMSIS" Marker="-1" OutputFile="" sate="0" AsyncBuild="" >
-		<NodeC Path="..\system_stm32f10x.c" Header="system_stm32f10x.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\system_stm32f10x.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c" Header="core_cm3.c" Marker="-1" OutputFile=".\STM32100E-EVAL\core_cm3.o" sate="0" AsyncBuild="" />
-																																																																																																																																																																																																																							
-	</Group>
-	<Group Header="StdPeriph_Driver" Marker="-1" OutputFile="" sate="0" AsyncBuild="" >
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c" Header="stm32f10x_rcc.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_rcc.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c" Header="stm32f10x_gpio.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_gpio.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c" Header="stm32f10x_usart.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_usart.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c" Header="misc.c" Marker="-1" OutputFile=".\STM32100E-EVAL\misc.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c" Header="stm32f10x_i2c.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_i2c.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c" Header="stm32f10x_spi.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_spi.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c" Header="stm32f10x_exti.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_exti.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c" Header="stm32f10x_dma.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_dma.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c" Header="stm32f10x_fsmc.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_fsmc.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c" Header="stm32f10x_sdio.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_sdio.o" sate="0" AsyncBuild="" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c" Header="stm32f10x_adc.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_adc.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c" Header="stm32f10x_bkp.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_bkp.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c" Header="stm32f10x_can.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_can.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c" Header="stm32f10x_cec.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_cec.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c" Header="stm32f10x_crc.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_crc.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c" Header="stm32f10x_dac.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_dac.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c" Header="stm32f10x_dbgmcu.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_dbgmcu.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c" Header="stm32f10x_flash.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_flash.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c" Header="stm32f10x_iwdg.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_iwdg.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c" Header="stm32f10x_pwr.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_pwr.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c" Header="stm32f10x_rtc.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_rtc.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c" Header="stm32f10x_tim.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_tim.o" sate="0" />
-		<NodeC Path="..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c" Header="stm32f10x_wwdg.c" Marker="-1" AsyncBuild="" OutputFile=".\STM32100E-EVAL\stm32f10x_wwdg.o" sate="0" />
-																																																																																																																																																																																																														
-	</Group>
-	<Group Header="User" Marker="-1" OutputFile="" sate="0" AsyncBuild="" >
-		<NodeC Path="..\stm32f10x_it.c" Header="stm32f10x_it.c" Marker="-1" OutputFile=".\STM32100E-EVAL\stm32f10x_it.o" sate="0" AsyncBuild="" >																						</NodeC>
-		<NodeC Path="..\main.c" Header="main.c" Marker="-1" OutputFile=".\STM32100E-EVAL\main.o" sate="0" AsyncBuild="" />
-																																																																																																																																																																																																																		
-	</Group>
-	<Group Header="RIDE" Marker="-1" OutputFile="" sate="0" AsyncBuild="" >
-		<NodeASM Path="..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\gcc_ride7\startup_stm32f10x_cl.s" Header="startup_stm32f10x_cl.s" Marker="0" OutputFile=".\STM32100E-EVAL\startup_stm32f10x_cl.o" sate="0" AsyncBuild="" >
-			<Options>
-				<Config Header="STM32100B-EVAL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
-							<Property Header="Exclude" Value="Yes" Removable="1" />
-							<Property Header="LinkExclude" Value="Yes" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																							
-						</Section>
-																																																																																																																																																																																																																																																																																																																																																																																																																																									
-					</Set>
-																																																																																																																																																																																																																																																																																																																																																						
-				</Config>
-				<Config Header="STM3210B-EVAL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
-							<Property Header="Exclude" Value="Yes" Removable="1" />
-							<Property Header="LinkExclude" Value="Yes" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																							
-						</Section>
-																																																																																																																																																																																																																																																																																																																																																																																																																																									
-					</Set>
-																																																																																																																																																																																																																																																																																																																																																						
-				</Config>
-				<Config Header="STM3210E-EVAL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
-							<Property Header="Exclude" Value="Yes" Removable="1" />
-							<Property Header="LinkExclude" Value="Yes" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																																							
-						</Section>
-																																																																																																																																																																																																																																																																																																																																																																																																																																									
-					</Set>
-																																																																																																																																																																																																																																																																																																																																																						
-				</Config>
-				<Config Header="STM3210E-EVAL_XL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
-							<Property Header="Exclude" Value="Yes" Removable="1" />
-							<Property Header="LinkExclude" Value="Yes" Removable="1" />
-																																																																																																																																																																																																												
-						</Section>
-																																																																																																																																																																												
-					</Set>
-																																																																																																																																							
-				</Config>
-				<Config Header="STM32100E-EVAL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
-							<Property Header="Exclude" Value="Yes" Removable="1" />
-							<Property Header="LinkExclude" Value="Yes" Removable="1" />
-																																																																																																																																											
-						</Section>
-																																																																																																																					
-					</Set>
-																																																																																										
-				</Config>
-																																																																						
-			</Options>
-																																																																																																																																																																																														
-		</NodeASM>
-		<NodeASM Path="..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\gcc_ride7\startup_stm32f10x_hd.s" Header="startup_stm32f10x_hd.s" Marker="0" OutputFile=".\STM32100E-EVAL\startup_stm32f10x_hd.o" sate="0" AsyncBuild="" >
-			<Options>
-				<Config Header="STM32100B-EVAL" >
-					<Set Header="NodeASM" >
-						<Section Header="Build" >
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-																																																																																																																																																																																																																																																																																																																									
-				</Section>
-				<Section Header="OPTIMIZE" >
-					<Property Header="Optimize" Value="-Os" Removable="1" />
-																																																																																																																																																																																																																																								
-				</Section>
-				<Section Header="WARNINGS" >
-					<Property Header="NOWARNINGS" Value="" Removable="1" />
-							
-				</Section>
-					
-			</Set>
-			<Set Header="LD" >
-				<Section Header="Startup" >
-					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																																																									
-				</Section>
-				<Section Header="Scripts" >
-					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-					<Property Header="StarterKitLimit" Value="No" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																																																																																																																																									
-				</Section>
-																																																																																																																																																																																																																																																																																																																																																																			
-			</Set>
-		</Config>
-		<Config Header="STM32100B-EVAL" >
-			<Set Header="Target" >
-				<Section Header="ProcessorARM" >
-					<Property Header="Processor" Value="STM32F100VB" />
-																																																																																																																																																																																																																																																																																																																																																													
-				</Section>
-																																																																																																																																																																																																																																																																															
-			</Set>
-			<Set Header="ApplicationBuild" >
-				<Section Header="Directories" >
-					<Property Header="IncDir" Value="..;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL" Removable="1" />
-					<Property Header="OutDir" Value="$(ApplicationDir)\STM32100B-EVAL" Removable="1" />
-					<Property Header="ListDir" Value="$(ApplicationDir)\STM32100B-EVAL" Removable="1" />
-																																																																																																																																																																																																																						
-				</Section>
-																																																																																																																																																																						
-			</Set>
-			<Set Header="GCC" >
-				<Section Header="Defines" >
-					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32F10X_MD_VL; USE_STM32100B_EVAL" Removable="1" />
-																																																																																																																																																																																																																																																	
-				</Section>
-				<Section Header="OPTIMIZE" >
-					<Property Header="Optimize" Value="-Os" Removable="1" />
-																																																																																																																																																																																		
-				</Section>
-																																																																																																																																										
-			</Set>
-			<Set Header="LD" >
-				<Section Header="Scripts" >
-					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-					<Property Header="StarterKitLimit" Value="No" Removable="1" />
-																																																																																																																																																																																																																																																																																																																									
-				</Section>
-				<Section Header="Startup" >
-					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-																																																																																																																																																																																																																																																																																																																																																													
-				</Section>
-																																																																																																																																																																																																																																																			
-			</Set>
-																																																																																															
-		</Config>
-		<Config Header="STM3210E-EVAL_XL" >
-			<Set Header="ApplicationBuild" >
-				<Section Header="Directories" >
-					<Property Header="IncDir" Value="..;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL" Removable="1" />
-					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
-					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
-																									
-				</Section>
-																			
-			</Set>
-			<Set Header="Target" >
-				<Section Header="ProcessorARM" >
-					<Property Header="Processor" Value="STM32F103ZGT6" />
-																																																																																																																			
-				</Section>
-																																																																																									
-			</Set>
-			<Set Header="GCC" >
-				<Section Header="Defines" >
-					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32F10X_XL; USE_STM3210E_EVAL" Removable="1" />
-																																																																																																																																														
-				</Section>
-				<Section Header="OPTIMIZE" >
-					<Property Header="Optimize" Value="-Os" Removable="1" />
-																																																																																																																																														
-				</Section>
-				<Section Header="WARNINGS" >
-					<Property Header="UNUSEDWARNINGS" Value="-Wunused" Removable="1" />
-																																																																																																																																					
-				</Section>
-																																																																																																							
-			</Set>
-			<Set Header="LD" >
-				<Section Header="Scripts" >
-					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-					<Property Header="StarterKitLimit" Value="No" Removable="1" />
-																																																																																																																																														
-				</Section>
-				<Section Header="Startup" >
-					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-																																																																																																																																														
-				</Section>
-																																																																																																														
-			</Set>
-										
-		</Config>
-		<Config Header="STM32100E-EVAL" >
-			<Set Header="Target" >
-				<Section Header="ProcessorARM" >
-					<Property Header="Processor" Value="STM32F100ZE" />
-																																																																																																	
-				</Section>
-																																																																											
-			</Set>
-			<Set Header="ApplicationBuild" >
-				<Section Header="Directories" >
-					<Property Header="OutDir" Value="$(ApplicationDir)\STM32100E-EVAL" Removable="1" />
-					<Property Header="ListDir" Value="$(ApplicationDir)\STM32100E-EVAL" Removable="1" />
-					<Property Header="IncDir" Value="..;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL" Removable="1" />
-																																																				
-				</Section>
-																																								
-			</Set>
-			<Set Header="GCC" >
-				<Section Header="Defines" >
-					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F10X_HD_VL;USE_STM32100E_EVAL" Removable="1" />
-																																																																																																	
-				</Section>
-				<Section Header="OPTIMIZE" >
-					<Property Header="Optimize" Value="-Os" Removable="1" />
-																																																																																																	
-				</Section>
-																																																																											
-			</Set>
-			<Set Header="LD" >
-				<Section Header="Startup" >
-					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-																																																																																																	
-				</Section>
-				<Section Header="Scripts" >
-					<Property Header="StarterKitLimit" Value="No" Removable="1" />
-					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
-					<Property Header="File" Value="" Removable="1" />
-																																																																																								
-				</Section>
-																																																																				
-			</Set>
-																									
-		</Config>
-	</Options>
-</ApplicationBuild>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/readme.txt
deleted file mode 100644
index ddbe3c5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/readme.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-/**
-  @page ride7 RIDE Project Template
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files 
-  *          needed to create a new project linked with the STM32F10x  
-  *          Standard Peripheral Library and working with RIDE7 software 
-  *          toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
- 
- - project .rprj/.rapp: A pre-configured project file with the provided library 
-                        structure that produces an executable image with RIDE7.
-                
- - stm32f10x_flash_extsram.ld: This file is the RAISONANCE linker script used to 
-                               place program code (readonly) in internal FLASH 
-                               and data (readwrite, Stack and Heap)in external 
-                               SRAM. 
-                               You can customize this file to your need.
-                           
- @par How to use it ?
- 
- - Open the Project.rprj project.
- - In the configuration toolbar(Project->properties) select the project config:
-     - STM32100E-EVAL: to configure the project for STM32 Value Line High-density devices
-     - STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices
-     - STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
-     - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
-     - STM3210E-EVAL: to configure the project for STM32 High-density devices
-     - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
- - Rebuild all files: Project->build project
- - Load project image: Debug->start(ctrl+D)
- - Run program: Debug->Run(ctrl+F9)  
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/stm32f10x_flash_extsram.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/stm32f10x_flash_extsram.ld
deleted file mode 100644
index 1a60104..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/stm32f10x_flash_extsram.ld
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
-Default linker script for STM32F10x_1024K_1024K
-Copyright RAISONANCE S.A.S. 2008
-*/
-
-/* include the common STM32F10x sub-script */
-
-/* Common part of the linker scripts for STM32 devices*/
-
-
-/* default stack sizes. 
-
-These are used by the startup in order to allocate stacks for the different modes.
-*/
-
-__Stack_Size = 1024 ;
-
-PROVIDE ( _Stack_Size = __Stack_Size ) ;
-
-__Stack_Init = _estack  - __Stack_Size ;
-
-/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
-PROVIDE ( _Stack_Init = __Stack_Init ) ;
-
-/*
-There will be a link error if there is not this amount of RAM free at the end.
-*/
-_Minimum_Stack_Size = 0x100 ;
-
-
-/* include the memory spaces definitions sub-script */
-/*
-Linker subscript for STM32F10x definitions with 1024K Flash and 1024K External SRAM */
-
-/* Memory Spaces Definitions */
-
-MEMORY
-{
-  RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 1024K
-  FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
-  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-}
-
-/* higher address of the user mode stack */
-_estack = 0x68100000;
-
-
-
-/* include the sections management sub-script for FLASH mode */
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
-    .isr_vector :
-    {
-	. = ALIGN(4);
-        KEEP(*(.isr_vector))            /* Startup code */
-	. = ALIGN(4);
-    } >FLASH
- 
-    /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
-    .flashtext :
-    {
-	. = ALIGN(4);
-        *(.flashtext)            /* Startup code */
-	. = ALIGN(4);
-    } >FLASH
- 
-    
-    /* the program code is stored in the .text section, which goes to Flash */
-    .text :
-    {
-	    . = ALIGN(4);
-	    
-        *(.text)                   /* remaining code */
-        *(.text.*)                   /* remaining code */
-        *(.rodata)                 /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-
-	    . = ALIGN(4);
-   	 _etext = .;
-	    /* This is used by the startup in order to initialize the .data secion */
-   	 _sidata = _etext;
-    } >FLASH
-    
- 
-
-    /* This is the initialized data section
-    The program executes knowing that the data is in the RAM
-    but the loader puts the initial values in the FLASH (inidata).
-    It is one task of the startup to copy the initial values from FLASH to RAM. */
-    .data  : AT ( _sidata )
-    {
-	    . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _sdata = . ;
-        
-        *(.data)
-        *(.data.*)
-
-	    . = ALIGN(4);
-	    /* This is used by the startup in order to initialize the .data secion */
-   	 _edata = . ;
-    } >RAM
-    
-    
-
-    /* This is the uninitialized data section */
-    .bss :
-    {
-	    . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _sbss = .;
-        
-        *(.bss)
-        *(COMMON)
-        
-	    . = ALIGN(4);
-	    /* This is used by the startup in order to initialize the .bss secion */
-   	 _ebss = . ;
-    } >RAM
-    
-    PROVIDE ( end = _ebss );
-    PROVIDE ( _end = _ebss );
-    
-    /* This is the user stack section 
-    This is just to check that there is enough RAM left for the User mode stack
-    It should generate an error if it's full.
-     */
-    ._usrstack :
-    {
-	    . = ALIGN(4);
-        _susrstack = . ;
-        
-        . = . + _Minimum_Stack_Size ;
-        
-	    . = ALIGN(4);
-        _eusrstack = . ;
-    } >RAM
-    
-
-   
-    /* this is the FLASH Bank1 */
-    /* the C or assembly source must explicitly place the code or data there
-    using the "section" attribute */
-    .b1text :
-    {
-        *(.b1text)                   /* remaining code */
-        *(.b1rodata)                 /* read-only data (constants) */
-        *(.b1rodata*)
-    } >FLASHB1
-    
-    /* this is the EXTMEM */
-    /* the C or assembly source must explicitly place the code or data there
-    using the "section" attribute */
-    
-    /* EXTMEM Bank0 */
-    .eb0text :
-    {
-        *(.eb0text)                   /* remaining code */
-        *(.eb0rodata)                 /* read-only data (constants) */
-        *(.eb0rodata*)
-    } >EXTMEMB0
-    
-    /* EXTMEM Bank1 */
-    .eb1text :
-    {
-        *(.eb1text)                   /* remaining code */
-        *(.eb1rodata)                 /* read-only data (constants) */
-        *(.eb1rodata*)
-    } >EXTMEMB1
-    
-    /* EXTMEM Bank2 */
-    .eb2text :
-    {
-        *(.eb2text)                   /* remaining code */
-        *(.eb2rodata)                 /* read-only data (constants) */
-        *(.eb2rodata*)
-    } >EXTMEMB2
-    
-    /* EXTMEM Bank0 */
-    .eb3text :
-    {
-        *(.eb3text)                   /* remaining code */
-        *(.eb3rodata)                 /* read-only data (constants) */
-        *(.eb3rodata*)
-    } >EXTMEMB3
-    
-    
-    
-    /* after that it's only debugging information. */
-    
-    /* remove the debugging information from the standard libraries */
-    DISCARD :
-    {
-     libc.a ( * )
-     libm.a ( * )
-     libgcc.a ( * )
-     }
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/Release_Notes.html b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/Release_Notes.html
deleted file mode 100644
index f880e3c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/Release_Notes.html
+++ /dev/null
@@ -1,294 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
-
-
-
-
-
-
-
-
-
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-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x Standard Peripherals Library Template
-(StdPeriph_Template)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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-<tr style="">
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
-Template
-update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;">
-</span>
-            
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
-Peripherals Library Template update History</span></h2>
-            <br>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 08-April-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-              <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Template projects updated to save configuration time and easy the examples use.</span><br>
-<span style="font-family: Verdana; font-size: 10pt;"></span></li>
-              <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">system_stm32f10x.c</span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add more 
-comments on how to use this driver.</span></li></ul>
-              </li>
-              <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">stm32f10x_conf.h</span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">All 
-peripheral header files inclusion enabled.</span></li></ul><span style="font-family: Verdana; font-size: 10pt;"><br>
-                </span></li>
-
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
-            <ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High Density Value Line </span>devices.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span> file moved to project template directory.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">"<span style="font-weight: bold;">STM32F10X_XL</span>" workspace name changed to "<span style="font-weight: bold;">STM3210E-EVAL_XL</span>" in all projects.<br>
-                </span></li>
-
-
-            </ul>
-            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template:&nbsp; Template projects</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-
-            
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM)&nbsp;toolchain</span>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v5.50</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use High-density value line devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line</span><span style="font-size: 10pt; font-family: Verdana;"> devices: </span><span style="font-size: 10pt; font-family: Verdana;">STM32F100E-EVAL</span></li>
-</ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span>
-            <ul style="margin-top: 0in;" type="disc">
-            </ul>
-
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Hitex&nbsp;IDE/Debugger </span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">HiTOP</span><span style="font-size: 10pt; font-family: Verdana;">)&nbsp;toolchain</span>
-              </li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">5.40</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for </span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line</span><span style="font-size: 10pt; font-family: Verdana;"> devices: </span><span style="font-size: 10pt; font-family: Verdana;">STM32F100E-EVAL</span></li>
-              </ul>
-</ul><span style="font-size: 10pt; font-family: Verdana;"></span>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RealView Microcontroller Development Kit (MDK-ARM)&nbsp;toolchain</span>
-              </li>
-<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">4.12</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line </span><span style="font-size: 10pt; font-family: Verdana;">devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line</span><span style="font-size: 10pt; font-family: Verdana;"> devices: STM32F100E-EVAL</span></li></ul>
-            </ul>
-
-            <ul style="margin-top: 0in;" type="disc">
-              
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7 (RIDE)&nbsp;toolchain</span>
-              </li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="color: rgb(255, 102, 102);"><span style="color: black;"><span style="font-style: italic;">RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10</span> and later</span></span></span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for </span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line</span><span style="font-size: 10pt; font-family: Verdana;"> devices: </span><span style="font-size: 10pt; font-family: Verdana;">STM32F100E-EVAL</span></li>
-              </ul>
-</ul><span style="font-size: 10pt; font-family: Verdana;"></span>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Atollic TrueSTUDIO STM32 (TrueSTUDIO)&nbsp;toolchain</span>
-              </li>
-
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">1.4.0</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line </span><span style="font-size: 10pt; font-family: Verdana;">devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">High-density value line</span><span style="font-size: 10pt; font-family: Verdana;"> devices: STM32F100E-EVAL</span></li>
-              </ul>
-
-            
-            
-            </ul>
-
-
-            <span style="font-size: 10pt; font-family: Verdana;"></span>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">04/16/2010</span></h3>
-
-<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add template project for <span style="font-weight: bold;">TrueSTUDIO</span> toolchain<br></span></li></ul><ol style="margin-top: 0in; list-style-type: decimal;" start="3"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template:&nbsp; Template projects</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-
-            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM)&nbsp;toolchain</span>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v5.41</span>&nbsp;</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use&nbsp;XL-density devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x XL-density&nbsp;devices: STM32F10X_XL</span></li></ul></ul><ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Hitex&nbsp;IDE/Debugger </span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">HiTOP</span><span style="font-size: 10pt; font-family: Verdana;">)&nbsp;toolchain</span>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">5.32</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x XL-density&nbsp;devices: STM32F10X_XL</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RealView Microcontroller Development Kit (MDK-ARM)&nbsp;toolchain</span>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> <span style="font-style: italic;">v</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">4.10</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use&nbsp;XL-density devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x XL-density&nbsp;devices: STM32F10X_XL</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7 (RIDE)&nbsp;toolchain</span>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="color: rgb(255, 102, 102);"><span style="color: black;"><span style="font-style: italic;">RIDE7 IDE:7.28.10.0075, RKitARM for RIDE7:1.24.10</span> and later</span></span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x XL-density&nbsp;devices: STM32F10X_XL</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Atolic TrueSTUDIO toolchain</span>
-              </li><ul><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">Used version:</span> </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">v1.1.0</span></li></ul><ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">A software patch is needed to use&nbsp;XL-density devices with this&nbsp;version, click <a href="http://www.st.com/stonline/stappl/resourceSelector/app?page=resourceSelectorPage&amp;doctype=FIRMWARE&amp;SubClassID=1169" target="_blank">here</a> to download</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Workspaces provided for all supported STM32F10x devices</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><br></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update different projects to the latest toolchains versions. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-</ul>
-<ol style="margin-top: 0in;" start="2" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template:&nbsp; Template source</span></i></b></li>
-</ol>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">main.c file updated to support the STM32 Value line devices and STM32100B-EVAL board.</span><br>
-              </li>
-            </ul>
-            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template:&nbsp; Template projects</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) software toolchain</span>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Version 5.41</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.</span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">Hitex HiTOP IDE/Debugger </span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">HiTOP</span><span style="font-size: 10pt; font-family: Verdana;">) software toolchain</span>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Version 5.32</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add cstart_thumb2.asm file to support new CMSIS V1.30 version. This file includes the SystemInit() function call.<br>
-</span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7 (RIDE) software toolchain</span>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Version: RIDE7 IDE:7.24.09, RKitARM for RIDE7:1.24.10</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.</span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RealView Microcontroller Development Kit (RVMDK) software toolchain</span>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Version 4.03</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.</span></li>
-              </ul>
-
-            </ul>
-
-<ul style="margin-top: 0in;" type="disc">
-
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.cproject b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.cproject
deleted file mode 100644
index 4131fd2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.cproject
+++ /dev/null
@@ -1,280 +0,0 @@
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-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
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-								<outputEntries>
-									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
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-							<option id="com.atollic.truestudio.gcc.misc.otherflags.797062063" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os -w" valueType="string"/>
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-						</tool>
-					</fileInfo>
-					<fileInfo id="com.atollic.truestudio.exe.debug.1518366166.1009875117" name="stm32100b_eval_lcd.c" rcbsApplicability="disable" resourcePath="STM32_EVAL/stm32100b_eval_lcd.c" toolsToInvoke="com.atollic.truestudio.exe.debug.toolchain.gcc.1836874447.836608037">
-						<tool id="com.atollic.truestudio.exe.debug.toolchain.gcc.1836874447.836608037" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.1836874447">
-							<option id="com.atollic.truestudio.gcc.misc.otherflags.847040183" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os -w" valueType="string"/>
-							<inputType id="com.atollic.truestudio.gcc.input.1124296954" superClass="com.atollic.truestudio.gcc.input"/>
-						</tool>
-					</fileInfo>
-					<sourceEntries>
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-				</scannerConfigBuildInfo>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="STM32100B-EVAL.com.atollic.truestudio.exe.1549124020" name="Executable" projectType="com.atollic.truestudio.exe"/>
-	</storageModule>
-</cproject>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 04e9dba..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM32100B-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F100VB
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld
deleted file mode 100644
index 747dfd0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32_flash.ld
-**
-**  Abstract    : Linker script for STM32F100VB Device with
-**                128KByte FLASH, 8KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20002000;    /* end of 8K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x100; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project
deleted file mode 100644
index b09714a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project
+++ /dev/null
@@ -1,305 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>STM32100E-EVAL</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-				<dictionary>
-					<key>?children?</key>
-					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
-				</dictionary>
-				<dictionary>
-					<key>?name?</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.append_environment</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildArguments</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildCommand</key>
-					<value>make</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildLocation</key>
-					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.contents</key>
-					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
-					<value>false</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.stopOnError</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
-					<value>true</value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>CMSIS</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>Doc</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32100e_eval_cec.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32100e_eval_fsmc_onenand.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32100e_eval_fsmc_sram.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32100e_eval_ioe.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32100e_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_ee.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_tsensor.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_sdio_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_adc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_bkp.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_can.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_cec.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_crc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dac.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dbgmcu.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_iwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_pwr.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rtc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_tim.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_wwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_hd_vl.s</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 34b3d6f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM32100E-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F100ZE
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt
deleted file mode 100644
index 04b0397..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
-  @page TrueSTUDIO_STM32100E TrueSTUDIO Project Template for High-density Value line devices
- 
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files 
-  *          needed to create a new project linked with the STM32F10x  
-  *          Standard Peripheral Library and working with TrueSTUDIO software 
-  *          toolchain (Version 2.0.1 and later)
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
- 
- - project .cproject/.project: A pre-configured project file with the provided 
-                               library structure that produces an executable 
-                               image with TrueSTUDIO.
-
- - stm32_flash.ld: 			       This file is the TrueSTUDIO linker script used to 
-                               place program code (readonly) in internal FLASH 
-                               and data (readwrite, Stack and Heap)in internal 
-                               SRAM. 
-                               You can customize this file to your need.
-                           
- @par How to use it ?
-
- - Open the TrueSTUDIO toolchain.
- - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
-   directory.
- - Click on File->Import, select General->'Existing Projects into Workspace' 
-   and then click "Next". 
- - Browse to the TrueSTUDIO workspace directory and select the project: 
-   - STM32100E-EVAL: to configure the project for STM32 High-density Value 
-     line devices.
- - Under Windows->Preferences->General->Workspace->Linked Resources, add 
-   a variable path named "CurPath" which points to the folder containing
-   "Libraries", "Project" and "Utilities" folders.
- - Rebuild all project files: Select the project in the "Project explorer" 
-   window then click on Project->build project menu.
- - Run program: Select the project in the "Project explorer" window then click 
-   Run->Debug (F11)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld
deleted file mode 100644
index aa77c9f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32_flash.ld
-**
-**  Abstract    : Linker script for High-density value line Devices (STM32F100xE)
-**                with 512KByte FLASH, 32KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20008000;    /* end of 32K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size  = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x100;  /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-	*(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject
deleted file mode 100644
index fa5f17b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject
+++ /dev/null
@@ -1,280 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
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-					<key>org.eclipse.cdt.make.core.buildCommand</key>
-					<value>make</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildLocation</key>
-					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.contents</key>
-					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
-					<value>false</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.stopOnError</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
-					<value>true</value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>CMSIS</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>Doc</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210b_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_ee.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_tsensor.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_sdio_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_adc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_bkp.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_can.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_cec.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_crc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dac.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dbgmcu.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_iwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_pwr.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rtc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_tim.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_wwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 5667d56..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM3210B-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F103VB
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt
deleted file mode 100644
index 0038a2e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
-  @page TrueSTUDIO_STM3210B TrueSTUDIO Project Template for Medium-density devices
- 
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files 
-  *          needed to create a new project linked with the STM32F10x  
-  *          Standard Peripheral Library and working with TrueSTUDIO software 
-  *          toolchain (Version 2.0.1 and later)
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
- 
- - project .cproject/.project: A pre-configured project file with the provided 
-                               library structure that produces an executable 
-                               image with TrueSTUDIO.
-
- - stm32_flash.ld: 			       This file is the TrueSTUDIO linker script used to 
-                               place program code (readonly) in internal FLASH 
-                               and data (readwrite, Stack and Heap)in internal 
-                               SRAM. 
-                               You can customize this file to your need.
-                           
- @par How to use it ?
-
- - Open the TrueSTUDIO toolchain.
- - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
-   directory.
- - Click on File->Import, select General->'Existing Projects into Workspace' 
-   and then click "Next". 
- - Browse to the TrueSTUDIO workspace directory and select the project: 
-   - STM3210B-EVAL: to configure the project for STM32 Medium-density devices.
- - Under Windows->Preferences->General->Workspace->Linked Resources, add 
-   a variable path named "CurPath" which points to the folder containing
-   "Libraries", "Project" and "Utilities" folders.
- - Rebuild all project files: Select the project in the "Project explorer" 
-   window then click on Project->build project menu.
- - Run program: Select the project in the "Project explorer" window then click 
-   Run->Debug (F11)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject
deleted file mode 100644
index f746548..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject
+++ /dev/null
@@ -1,281 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.atollic.truestudio.exe.debug.151717401">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.151717401" moduleId="org.eclipse.cdt.core.settings" name="Debug">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="STM3210C-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.151717401" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
-					<folderInfo id="com.atollic.truestudio.exe.debug.151717401." name="/" resourcePath="">
-						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.666364917" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.949535934" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
-							<builder buildPath="${workspace_loc:/STM3210C-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.958132216" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
-								<outputEntries>
-									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
-								</outputEntries>
-							</builder>
-							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1839546215" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
-								<option id="com.atollic.truestudio.common_options.target.endianess.1090285170" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-								<option id="com.atollic.truestudio.common_options.target.mcpu.1187261376" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F107VC" valueType="enumerated"/>
-								<option id="com.atollic.truestudio.common_options.target.instr_set.1202647352" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-								<option id="com.atollic.truestudio.as.general.incpath.705945778" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
-								<inputType id="com.atollic.truestudio.as.input.1496059861" name="Input" superClass="com.atollic.truestudio.as.input"/>
-							</tool>
-							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.905676832" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
-								<option id="com.atollic.truestudio.gcc.directories.select.926005095" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;../..\..\&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\CMSIS\CM3\CoreSupport&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x&quot;"/>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project
deleted file mode 100644
index e181d6d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project
+++ /dev/null
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-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210c_eval_ioe.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210c_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_ee.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_tsensor.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_sdio_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_adc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_bkp.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_can.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_cec.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_crc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dac.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dbgmcu.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_iwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_pwr.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rtc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_tim.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_wwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_cl.s</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 2e8d862..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM3210C-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F107VC
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld
deleted file mode 100644
index aa88229..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32_flash.ld
-**
-**  Abstract    : Linker script for STM32F107VC Device with
-**                256KByte FLASH, 64KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20010000;    /* end of 64K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
-  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject
deleted file mode 100644
index f53986f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject
+++ /dev/null
@@ -1,358 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="STM3210E-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
-					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
-						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
-							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
-								<outputEntries>
-									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
-								</outputEntries>
-							</builder>
-							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
-								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
-								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
-								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
-								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
-							</tool>
-							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
-								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;../..\..\&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\CMSIS\CM3\CoreSupport&quot;"/>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.project b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.project
deleted file mode 100644
index bb77738..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.project
+++ /dev/null
@@ -1,300 +0,0 @@
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-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildArguments</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildCommand</key>
-					<value>make</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildLocation</key>
-					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.contents</key>
-					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
-					<value>false</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.stopOnError</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
-					<value>true</value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>CMSIS</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>Doc</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>User</name>
-			<type>2</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/.metadata/Link</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/core_cm3.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c</locationURI>
-		</link>
-		<link>
-			<name>CMSIS/system_stm32f10x.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c</locationURI>
-		</link>
-		<link>
-			<name>Doc/readme.txt</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/readme.txt</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_fsmc_nand.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_fsmc_nor.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_fsmc_sram.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm3210e_eval_lcd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/stm32_eval.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_ee.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_i2c_tsensor.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_sdio_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c</locationURI>
-		</link>
-		<link>
-			<name>STM32_EVAL/stm32_eval_spi_sd.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/misc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_adc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_bkp.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_can.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_cec.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_crc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dac.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dbgmcu.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_dma.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_exti.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_flash.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_fsmc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_gpio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_i2c.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_iwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_pwr.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rcc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_rtc.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_sdio.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_spi.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_tim.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_usart.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
-		</link>
-		<link>
-			<name>StdPeriph_Driver/stm32f10x_wwdg.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c</locationURI>
-		</link>
-		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
-			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
-		</link>
-		<link>
-			<name>User/main.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/main.c</locationURI>
-		</link>
-		<link>
-			<name>User/stm32f10x_it.c</name>
-			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c</locationURI>
-		</link>
-	</linkedResources>
-</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 79946f6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ /dev/null
@@ -1,11 +0,0 @@
-#Tue Jul 13 09:06:52 GMT+01:00 2010
-BOARD=STM3210E-EVAL
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F103ZE
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=1
-TARGET=STM32
-VERSION=1.4.0
-eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt
deleted file mode 100644
index 90e46d2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
-  @page note Note for TrueSTUDIO
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-  * @file    note.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the needed step to use "printf" with TrueSTUDIO 
-  *          toolchain.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
-
-The C runtime library include many functions, including some that typically 
-handle I/O. The I/O related runtime functions include printf(), fopen(), fclose(),
-and many others.
-
-It is common to redirect the I/O from these functions to the actual embedded 
-platform, such as redirecting printf() output to an LCD display or a serial cable,
-or to redirect file operations like fopen() and fclose() to some Flash file 
-system middleware.
-
-The free Lite version of TrueSTUDIO do not support I/O redirection, and instead 
-have do-nothing stubs compiled into the C runtime library.
-
-To support printf() redirection in the professional version, you should do the following:
- - Open TrueSTUDIO professional and load your project. 
- - In the Project explorer, Right click on the project and select New->Other...
- - Expand System calls
- - Select Minimal System Calls Implementation and click next.
- - Click on Finish and verify that "syscalls.c" is added to your project.
- - Add the following code in the _write() function in "syscalls.c". 
-
-  @code
-   /*****************************************/
-   int Index;
-  
-   for (Index = 0; Index < len; Index++)
-   {
-      __io_putchar( *ptr++ );
-   }
-
-   return len;
-   /*****************************************/
-   @endcode
-   
- - Finally, Rebuild your project.
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 
-  
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld
deleted file mode 100644
index 1431182..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32f10x_flash_extsram.ld
-**
-**  Abstract    : Linker script for STM32F10x XL-density Devices with
-**                1MByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the Atollic TrueSTUDIO(R) toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x68100000;    /* end of 1024K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
-  RAM (xrw)       : ORIGIN = 0x68000000, LENGTH = 1024K
-  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-
-   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-    .ARM : {
-    __exidx_start = .;
-      *(.ARM.exidx*)
-      __exidx_end = .;
-    } >FLASH
-
-  .ARM.attributes : { *(.ARM.attributes) } > FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array*))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = .;
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : AT ( _sidata )
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  PROVIDE ( end = _ebss );
-  PROVIDE ( _end = _ebss );
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* MEMORY_bank1 section, code must be located here explicitly            */
-  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
-  .memory_b1_text :
-  {
-    *(.mb1text)        /* .mb1text sections (code) */
-    *(.mb1text*)       /* .mb1text* sections (code)  */
-    *(.mb1rodata)      /* read-only data (constants) */
-    *(.mb1rodata*)
-  } >MEMORY_B1
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
deleted file mode 100644
index cbb8819..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
deleted file mode 100644
index 18acee1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Template
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
deleted file mode 100644
index 8890262..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
deleted file mode 100644
index d6875a3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *         and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *         and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html
deleted file mode 100644
index bb906bc..0000000
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-<div class="Section1">
-<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br></o:p></span><a href="../../../DOC/Others/FWLib/CHM_Generator/Library_html/index.html"></a></p>
-<div align="center">
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
-<tbody>
-<tr style="">
-<td style="padding: 0cm;" valign="top">
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-<td style="padding: 1.5pt;">
-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x Standard Peripherals Library (StdPeriph_Lib)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img id="_x0000_i1025" src="_htmresc/logo.bmp" style="border-style: solid; border-width: 0px; height: 65px; width: 86px;" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr style="">
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
-update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;"></span>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
-Peripherals Library update History</span></h2><br>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 08-April-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Specific system_stm32f10x.c file provided for each example</span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HTML file containing the examples list, with main features, provided in the root folder (allow search on key word/feature)</span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Template projects updated to save configuration time and easy the examples use</span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Refreshed example list vs. previous version:</span></li>
-              <ul>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add two new Examples: MPU and TIM DMA Burst &nbsp;&nbsp;&nbsp; <br>
-                  </span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">xWDG examples enhanced, ex. accurate IWDG timeout thanks to LSI freq measure w/ Timer</span></li>
-                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">NVIC and SysTick examples enhanced to provide more details how to use them w/ CMSIS layer<br>
-                  </span></li>
-              </ul>
-
-            </ul>
-            
-
-            <span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Contents<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">ARM CM3 CMSIS V1.30 (<a href="Libraries%5CCMSIS%5CCMSIS_changes.htm">release
-notes</a>)</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS V3.5.0 (<a href="Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html">release
-notes</a>)</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver V3.5.0 (<a href="Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html">release
-notes</a>)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples V3.5.0 (<a href="Project/STM32F10x_StdPeriph_Examples/Release_Notes.html">release
-notes</a>)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template V3.5.0 (<a href="Project/STM32F10x_StdPeriph_Template/Release_Notes.html">release
-notes</a>)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL V4.5.0 (<a href="Utilities/STM32_EVAL/Release_Notes.html">release
-notes</a>)</span></li>
-            </ul>
-            
-            <span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Development Toolchains and Compilers<o:p></o:p></span></u></b></p>
-
-            
-            
-            
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) toolchain V5.50.5<br>
-</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Hitex&nbsp;IDE/Debugger 
-                </span><span style="font-size: 10pt; font-family: Verdana;">(</span><span style="font-size: 10pt; font-family: Verdana;">HiTOP</span><span style="font-size: 10pt; font-family: Verdana;">)&nbsp;toolchain V5.40.0051</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RealView Microcontroller 
-Development Kit (MDK-ARM)&nbsp;toolchain V4.13
-  </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7 
-(RIDE)&nbsp;toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)</span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Atollic TrueSTUDIO STM32 
-(TrueSTUDIO)&nbsp;toolchain V1.4.0</span></li>
-
-            </ul>
-
-            
-
-            
-            
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0 - 10/15/2010</span></h3>
-
-    
-            <ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density Value line</span> devices. <br>
-</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add 3 examples: FSMC OneNAND, I2C TSENSOR (Temperature Sensro) and I2C IOExpander.<br>
-</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Utilities STM32&nbsp; EVAL drivers enhancements:</span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C EEPROM, Temperature Sensor and IO Expander drivers updated to use the DMA for read/write transfer and add more robustness.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SD Card (SDIO) driver updated to add more robustness.<br>
-</span></li>
-              </ul>
-
-            </ul>
-
-    
-            <ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Libraries</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">CMSIS</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html">Release Notes for STM32F10x CMSIS</a></span></li></ul>
-            </ul>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Drive</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;">r</span></u><u><span style="font-size: 10pt;"></span></u></li>
-            </ul>
-
-    
-    
-            <ul style="margin-top: 0in;" type="disc">
-<ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Driver</a></span><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b></li></ul>
-            </ul>
-            <ol start="3">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Project</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Examples/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Examples</a></span></li></ul>
-            </ul>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"></span></u></li>
-            </ul>
-
-    
-    
-            <ul>
-<ul><li><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Template/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Template</a></span></li></ul>
-            </ul>
-            <ol start="4">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-
-    
-            <ul style="margin-top: 0in;" type="disc">
-<ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Utilities/STM32_EVAL/Release_Notes.html">Release Notes_for_STM32_EVAL</a></span></li></ul>
-            </ul>
-            <br>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0 - 04/16/2010</span></h3>
-    <ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density</span> devices.&nbsp;</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add template project for <span style="font-weight: bold;">TrueSTUDIO</span> toolchain. </span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul>
-    <ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Libraries</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">CMSIS</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html">Release Notes for STM32F10x CMSIS</a></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Drive</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;">r</span></u><u><span style="font-size: 10pt;"></span></u></li></ul>
-    
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Driver</a></span><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b></li></ul></ul><ol start="3"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Project</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Examples/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Examples</a></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"></span></u></li></ul>
-    
-    <ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Template/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Template</a></span></li></ul></ul><ol start="4"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Utilities/STM32_EVAL/Release_Notes.html">Release Notes_for_STM32_EVAL</a></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0 - 03/01/2010</span></h3>
-    <ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New <span style="font-weight: bold;">CMSIS V1.30</span> release </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ul>
-    <ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Libraries</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">CMSIS</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html">Release Notes for STM32F10x CMSIS</a></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Drive</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;">r</span></u><u><span style="font-size: 10pt;"></span></u></li></ul>
-    
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See <a href="Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Driver</a></span><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b></li></ul></ul><ol start="3"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Project</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Examples/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Examples</a></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Template</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"></span></u><u><span style="font-size: 10pt;"></span></u></li></ul>
-    
-    <ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Project/STM32F10x_StdPeriph_Template/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Template</a></span></li></ul></ul><ol start="4"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">See&nbsp;<a href="Utilities/STM32_EVAL/Release_Notes.html">Release Notes for STM32F10x_StdPeriph_Utilities</a></span></li></ul></ul>
-    <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.1.2 -
-    09/28/2009</span></h3>
-    <ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <b>Hitex
-         Development Tools HiTOP</b>. </span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul>
-    <ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Libraries</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">CMSIS</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">system_stm32f10x.c: <i>SetSysClockTo56()</i>
-          function, change the flash latency to 2&nbsp;instead of 1</span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Drive</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;">r</span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c: in <i>TIM_OCxInit()</i>&nbsp;functions,
-          add new instruction to set the <i>CCxS</i> bits&nbsp;(x= 1, 2, 3, 4)
-          to 0, i.e. the channel CCx is configured as output. In the previous
-          version these functions was assuming that the<i> CCxS</i> bits are
-          reset; if a channel was previously configured in input, a call to
-          this function doesn't allow using it in output mode. This is resolved
-          with this modification.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h: <i>I2S_InitTypeDef</i>
-          structure, change the&nbsp;type of&nbsp;<i>I2S_AudioFreq</i> field
-          to&nbsp;uint32_t instead of&nbsp;uint16_t. This modification is
-          needed to support I2S 96KHz frequency (available in&nbsp;Connectivity
-          Line devices). </span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.c: <i>FLASH_EraseOptionBytes()</i>
-          function, add&nbsp;note to clarify this function behavior.</span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul></ul>
-    <ol style="margin-top: 0in;" start="3" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Project</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Examples</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"> </span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C\EEPROM example</span><span style="font-size: 10pt;"><o:p></o:p></span></li><ul style="margin-top: 0in;" type="square"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">i2c_ee.c: <i>I2C_EE_BufferRead()</i>
-           function, the following line was removed &nbsp; &nbsp; &nbsp; &nbsp;
-           &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
-           &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
-           &nbsp; &nbsp; &nbsp;</span><span style="font-size: 10pt; font-family: &quot;Courier New&quot;;"><span style=""></span><span style=""></span><span style=""></span><span style=""></span><span style=""></span><span style=""></span></span></li></ul></ul></ul><p class="MsoNormal" style="margin-left: 1.25in;"><span style="font-size: 10pt;"><span style="">&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span><span style="font-size: 10pt; font-family: &quot;Courier New&quot;;">/* Clear EV6 by setting
-    again the PE bit */<br>
-    &nbsp; &nbsp;&nbsp;&nbsp;&nbsp; I2C_Cmd(I2C_EE, ENABLE);</span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-    <ul style="margin-top: 0in;" type="disc"><ul style="margin-top: 0in;" type="circle"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC example</span><span style="font-size: 10pt;"><o:p></o:p></span></li><ul style="margin-top: 0in;" type="square"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">main.c:&nbsp;<i>SetSysClockTo56()</i>
-           function, change the flash latency to 2&nbsp;instead of 1</span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul></ul></ul>
-    <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">Template</span></u></i><u><span style="font-size: 10pt; font-family: Verdana;"> </span></u><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li></ul>
-    <ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add template projects
-          for <span style="font-weight: bold;">HiTOP</span> toolchain to support <span style="font-style: italic;">Medium-density</span> (Template\HiTOP\STM3210B-EVAL),
-          <span style="font-style: italic;">High-density</span> (Template\HiTOP\STM3210E-EVAL) and <span style="font-style: italic;">Connectivity line</span>
-          (Template\HiTOP\STM3210C-EVAL) devices.</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.1.0
-- 06/19/2009</span></h3><ol style="font-style: italic;"><li><big><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">General</span> </span></big></li></ol><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update to support the additional peripherals and features embedded in the <span style="font-weight: bold;">STM32F10x Connectivity Line devices</span>. </span></li><li><span style="font-size: 10pt; font-family: Verdana;">Doxygen
-documentation enhanced to give more detail about driver function&#8217;s
-parameters: description, allowed values and required preconditions.
-This is mainly relevant for peripheral initialization structure&#8217;s
-members (PPP_InitTypeDef). </span></li><li><span style="font-size: 10pt; font-family: Verdana;">C++ support </span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ol style="font-weight: bold; font-style: italic;" start="2"><li><span style="font-size: 10pt; font-family: Verdana;">Libraries</span></li></ol><ul style="text-decoration: underline;"><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CMSIS</span></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">stm32f10x.h</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new define STM32F10X_CL to configure the library for Connectivity Line devices (default configuration)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Interrupt Number Definition (IRQn)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add definition for Connectivity Line devices peripheral&#8217;s interrupts</span></li><li><span style="font-size: 10pt; font-family: Verdana;">For STM32 Low Density Devices, the SPI2_IRQn was removed since there is no SPI2 in these devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add register's definitions, bits definitions and memory mapping for new peripherals (Ethernet and CAN2) </span></li><li><span style="font-size: 10pt; font-family: Verdana;">RCC, DBGMCU, EXTI, CAN, GPIO and AFIO bits definitions updated</span></li><li><span style="font-size: 10pt; font-family: Verdana;">AFIO_MAPR_SPI1 _REMAP define declaration corrected to AFIO_MAPR_SPI1_REMAP</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Tailor HSE_Value to the to the selected device</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">system_stm32f10x.c</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Clock configuration functions updated to support Connectivity line devices</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Change SetSysClockTo20 function to SetSysClockTo24</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">startup</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new startup files startup_stm32f10x_cl.s&nbsp; for Connectivity Line devices</span></li><li><span style="font-size: 10pt; font-family: Verdana;">For STM32 Low Density Devices, the SPI2_IRQHandler was removed since there is no SPI2 in these devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Use CMSIS Core Peripheral Access Layer V1.20</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="text-decoration: underline;"><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F10x_StdPeriph_Drive</span>r</span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">CAN: update to support CAN2 peripheral, with no impact on the API</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new instance CAN2 </span></li><li><span style="font-size: 10pt; font-family: Verdana;">Filter number updated</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add new function CAN_SlaveStartBank</span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC: update to support Connectivity Line devices, with no impact on the API</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_DeInit and RCC_GetSYSCLKSource functions updated</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Function&#8217;s parameters list updated </span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add new functions</span></li></ul></ul></ul><ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_PREDIV1Config, RCC_PREDIV2Config</span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_PLL2Config, RCC_PLL2Cmd</span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_PLL3Config, RCC_PLL3Cmd</span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_OTGFSCLKConfig </span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_I2S2CLKConfig, RCC_I2S3CLKConfig</span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_AHBPeriphResetCmd</span></li></ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC_APB2Periph_ALL and RCC_APB1Periph_ALL parameters removed</span></li></ul></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">GPIO</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update GPIO_PinRemapConfig function with 4 new AF remap</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add new function GPIO_ETH_MediaInterfaceConfig</span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">EXTI</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new internal EXTI Line 19 connected to ETH wakeup</span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">DBGMCU</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new define DBGMCU_CAN2_STOP</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">DAC</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add
-new define DAC_Trigger_T3_TRGO (to be used instead of
-DAC_Trigger_T8_TRGO, since TIM8 not available in Connectivity Line
-devices)</span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">SPI/I2S</span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">I2S_Init function updated to support new clock scheme implemented in Connectivity Line devices</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update I2S_AudioFreq defines to support frequency up to 96 KHz</span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">FLASH </span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_EnableWriteProtection function header and parameter list&nbsp; to support Connectivity Line devices</span></li></ul></ul></ul><ol start="3" style="font-style: italic;"><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Project</span> </span></li></ol><ul style="text-decoration: underline;"><ul><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F10x_StdPeriph_Examples</span> </span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Almost
-examples updated to run on Connectivity Line devices and
-STMicroelectronics STM3210C-EVAL evaluation board. Refer to the readme
-file provided within each example for more information on how to use
-the example with a specific board.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">TIM: add new example TIM_Input_Capture</span></li><li><span style="font-size: 10pt; font-family: Verdana;">I2C: M24C08_EEPROM example renamed to EEPROM</span></li></ul></ul></ul><ul style="text-decoration: underline;"><ul><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Template</span> </span></li></ul></ul><ul><ul><ul><li><span style="font-size: 10pt; font-family: Verdana;">Template
-projects for EWARMv5, RIDE and RVMDK updated to support Connectivity
-Line devices and STMicroelectronics STM3210C-EVAL evaluation board. </span></li></ul></ul></ul><span style="font-size: 10pt; font-family: Verdana;"> </span><ol start="4" style="font-style: italic;"><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Utilities</span></span></li></ol><ul><li><span style="font-size: 10pt; font-family: Verdana;">Implement
-a new abstraction layer to interact with the Human Interface resources;
-buttons, LEDs, LCD and COM ports (USARTs) available on
-STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL
-(High-Density) and STM3210B-EVAL (Medium-Density) evaluation boards.
-The stm32_eval.c driver provides a common API to interact with buttons,
-LEDs and COM ports, while these resources hardware&nbsp; definitions is
-made in the header file of each evaluation board (stm3210x_eval.h). A
-common API is provided to manage the LCD across the supported boards,
-with a separate driver for each board stm3210x_eval_lcd.c.</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.0.0
-- 04/06/2009<o:p></o:p></span></h3>
-<ol style="font-weight: bold; font-style: italic;"><li><span style="color: black;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;">General</span></li></ol><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span class="SpellE"><span class="spelle"><span style="font-family: Verdana;"></span></span></span></span><span style="font-size: 10pt; font-family: Verdana;">STM3210x FW Library renamed to STM32F10x Standard Peripherals Library (<span style="font-weight: bold; font-style: italic;">StdPeriph_Lib</span>)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x Standard Peripherals Library is full CMSIS compliant</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x Standard Peripherals Library Structure is updated.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x Standard Peripherals Package Architecture is enhanced</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM32F10x Standard Peripherals Library User Manual&nbsp; with *.chm format</span></li></ul><ol style="font-weight: bold; font-style: italic;" start="2"><li><span style="font-size: 10pt; font-family: Verdana;">library</span></li></ol><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN driver updated</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN driver was updated to support STM32F10xxx connectivity line products.</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN peripheral was renamed as CAN1. All occurrences related to CAN were also renamed as CAN1 in the different drivers.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C driver</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C event assert macro missing in stm32f10x_i2c.h file.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">DBGMCU</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Wrong
-defines in stm32f10x_dbgmcu.h: DBGMCU_TIM5_STOP, DBGMCU_TIM6_STOP,
-DBGMCU_TIM7_STOP and&nbsp; DBGMCU_TIM8_STOP defines values are wrong.<br><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">FSMC</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the FSMC AddressLowMapping configuration</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><ol start="3" style="font-weight: bold; font-style: italic;"><li><span style="font-size: 10pt; font-family: Verdana;">examples</span></li></ol><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">FSMC NOR driver Timings are updated.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add CAN "Normal" example</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">TIM "6Steps" example wave forms updated</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">NVIC "CM3_LPModes" and "System_Handlers" examples removed<br></span></li></ul><p class="MsoNormal"></p><p class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">For more details, please
-refer to <a href="http://www.st.com/mcu/familiesdocs-110.html" target="_blank">AN2953</a> "How to migrate from the STM32F10xxx firmware library
-V2.0.3 to the STM32F10xxx standard peripheral library V3.0.0".</span></p>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.3
-- 09/22/2008<o:p></o:p></span></h3>
-<ol style="margin-top: 0cm; font-weight: bold; font-style: italic;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">General</span><span style="font-size: 10pt; font-family: Verdana;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10xfwlib_contents_html
-file updated:<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Description
-of firmware library package content<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Easy-to-use
-firmware library examples: add description of how to use the project
-template to run the selected example<o:p></o:p></span></li>
-</ul>
-</ul>
-<ol style="font-weight: bold; font-style: italic;" start="2" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">library</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_map.h:
-add all STM32 Hardware registers bits definitions<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_conf.h:
-add a define for <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">HSEStartUp_TimeOut</span></span></span><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c:<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">FSMC_MemoryType_CRAM</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> is changed
-to <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">FSMC_MemoryType_PSRAM</span></span></span><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">FSMC_AsyncWait</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> member
-removed from <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">FSMC_NORSRAMInitTypeDef</span></span></span>
-structure<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">FSMC_BusTurnAroundDuration</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> parameter
-removed in case of write configuration<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c:<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RCC_FLAG_HSIRDY
-define value changed to 0x21.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">StartUpCounterand</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">HSEStatus</span></span></span>
-variables are now local for <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">RCC_WaitForHSEStartUp</span></span></span>
-function. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c:
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-event: EV8: I2C_EVENT_MASTER_BYTE_TRANSMITTING<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c:
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">"=" operator
-changed to "|=" inside <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_SelectOCxM</span></span></span>
-function<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.c:
-Definitions names changed<o:p></o:p></span></li>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="3" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">examples</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C Interrupt
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-updated according to I2C driver update<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C
-M24C08_EEPROM example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">i2c_ee.c
-file: add a loop on I2C_FLAG_BUSY in I2C_EE_PageWrite and<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_EE_BufferRead
-functions<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">i2c_ee.c
-file: add STOP condition in I2C_EE_WaitEepromStandbyState function<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SDIO example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-updated to support SD Card V2.0 and SD High Capacity cards.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART Polling
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART TC flag
-check changed by USART TXE flag check<o:p></o:p></span></li>
-</ul>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.2
-- 07/11/2008<o:p></o:p></span></h3>
-<ol style="font-style: italic; font-weight: bold;" start="1" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">library</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SPI_I2S_ClearFlag
-function: some flags are removed from the possible flags parameters
-list. This function can clear only CRCERR flag.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SPI_I2S_ClearITPendingBit
-function: some pending bits are removed from&nbsp;the possible
-pending bits parameters list. This function can clear only CRCERR
-pending
-bit.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp;<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_ClearFlag
-function: some flags are removed from the possible flags parameters
-list. This function can clear only SMBALER, TIMEOUT, PECERR, OVR, AF,
-ARLO and BERR flags. The passed parameter can be any combination of
-above flags.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_GetITStatus
-function checks on interrupt pending bit and the interrupt enable bit.<o:p></o:p></span></li>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_ClearITPendingBit
-function: some pending bits are removed from the possible pending bits
-parameters list. This function can clear only SMBALER, TIMEOUT, PECERR,
-OVR, AF, ARLO and BERR pending bits. The passed parameter can be any
-combination of above pending bits.&nbsp;<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;stm32f10x_usart.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">USART_ClearFlag</span></span></span>
-function: some flags are removed from the possible flags parameters
-list. This function can clear only CTS, LBD, TC and RXNE
-flags.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp;<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">USART_GetITStatus</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function:
-IS_USART_IT macro is changed to IS_USART_GET_IT<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">USART_ClearITPendingBit</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function:
-some pending bits are removed from the possible pending bits parameters
-list. This function can clear only CTS, LBD, TC and RXNE pending
-bits.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp;<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">remove</span></span></span><span style="font-size: 10pt; font-family: Verdana;">
-IS_TIM_PERIPH_FLAG(<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIMx</span></span></span>,
-TIM_FLAG) macro from <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ClearFlag</span></span></span>&nbsp;function.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_wwdg.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">use</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> register
-direct access in the <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">WWDG_GetFlagStatus</span></span></span>
-function instead of bit banding access.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">GPIO_Init</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function
-update.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="2" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">examples</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C Interrupt
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">The example
-is changed to provide a description of how to manage
-data&nbsp;transfer from master transmitter to slave receiver and
-from slave transmitter to master receiver using interrupts.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">add</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">main.h</span></span></span>
-file.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C
-10bitAddress example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-according to the I2C driver update.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">DualAddress</span></span></span>
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-according to the I2C driver update.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">SMBus</span></span></span>
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-according to the I2C driver update<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">DMA_Interrupt</span></span></span>
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-according to the USART driver update.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART
-Smartcard example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-according to the USART driver update.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">DAC Examples<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">GPIO_Configuration</span></span></span>
-function updated: Once the DAC channel is enabled, the corresponding
-GPIO pin is automatically connected to the DAC converter. In order to
-avoid parasitic consumption, the GPIO pin should<span class="GramE"><span class="grame"><span style="font-family: Verdana;">&nbsp;
-be</span></span></span> configured in analog.<o:p></o:p></span></li>
-</ul>
-</ul>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">LSI_Calib</span></span></span>
-example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-Update: add <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">main.h</span></span></span>
-file.<o:p></o:p></span></li>
-</ul>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1
-- 06/13/2008<o:p></o:p></span></h3>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the
-Firmware License Agreement file.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update the
-source <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">files's</span></span></span>
-header to remove reference to the License.<o:p></o:p></span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0
-- 05/23/2008<o:p></o:p></span></h3>
-<ol style="font-style: italic; font-weight: bold;" start="1" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">General</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">The <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">FWLib</span></span></span>
-V2.0 is an update of the V1.0 to support the extra peripherals and
-features embedded in the STM32 High-density
-devices.&nbsp;&nbsp;&nbsp; <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Firmware
-License Agreement file.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">For more
-details about the Firmware Library, please refer to the User. <span class="GramE"><span class="grame"><span style="font-family: Verdana;">manual</span></span></span>
-"UM0427 ARM«-based 32-bit MCU STM32F101xx and STM32F103xx
-Firmware&nbsp; Library"&nbsp; available for download from the
-ST microcontrollers website: <a href="http://www.st.com/stm32">www.st.com/stm32</a>.
-<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Glossary<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Medium-density
-devices are STM32F101xx and STM32F103xx microcontrollers where the
-Flash memory density ranges between 32 and 128 Kbytes.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">High-density
-devices are STM32F101xx and STM32F103xx microcontrollers where the
-Flash memory density ranges between 256 and 512
-Kbytes.&nbsp;&nbsp;&nbsp; <o:p></o:p></span></li>
-</ul>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="2" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">library</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add driver
-for new peripherals: FSMC, SDIO and DAC.&nbsp;<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support new I2S functionality.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add driver
-for DBGMCU and CRC modules&nbsp;&nbsp;&nbsp;&nbsp; <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support DMA2 channels.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_adc.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support ADC3. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_usart.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support UART4 and UART5.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">new</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">USART_ClockInitTypeDef</span></span></span>
-structure derived from <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">USART_InitTypeDef</span></span></span>
-one (for USART synchronous parameters). <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Timer
-peripherals driver<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim1.c
-/.h and stm32f10x_tim.c /.h drivers merged in one single driver:
-stm32f10x_tim.c /.h<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">update</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> to support
-new timer peripherals: TIM5, TIM6, TIM7 and TIM8.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">add</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> new macro
-for function parameters test. <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">TIM_TimeBaseInit</span></span></span><span style="font-size: 10pt; font-family: Verdana;">, <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_PrescalerConfig</span></span></span>
-and <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_GenerateEvent</span></span></span>
-functions updated.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">TIM_TIxExternalClockConfig</span></span></span><span style="font-size: 10pt; font-family: Verdana;">,
-TIM_ETRClockMode1Config, TIM_ETRClockMode2Config, <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ETRConfig</span></span></span>,
-TIM_SetIC1Prescaler, TIM_SetIC2Prescaler, TIM_SetIC3Prescaler and
-TIM_SetIC4Prescaler functions prototype update.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support GPIOF and GPIOG. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_lib.c
-/.h, stm32f10x_map.h, stm32f10x_conf.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">update</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> to add new
-peripherals register declarations and header files inclusion.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_nvic.c
-/.h&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;stm32f10x_itc.c
-/.h<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_vector.c
-/.s&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">update</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> to support
-the new peripherals interrupt vector.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support new peripherals clock &amp; reset enable/disable. <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HSE
-Oscillator start up timeout increased to 0x01FF.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">RCC_DeInit</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function
-update. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.c
-/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">driver</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> update to
-support the new 32 backup registers. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_map.h<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.c
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN register
-numbering update<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">update</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> macro
-"IS_FLASH_ADDRESS" to support memory size up to 512KB.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.c
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">FLASH_EnableWriteProtection</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function:
-update "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">FLASH_Pages</span></span></span>"
-<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">paramter</span></span></span>
-values<span class="GramE"><span class="grame"><span style="font-family: Verdana;">&nbsp; description</span></span></span>.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_exti.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">EXTI_Init</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> function
-update.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_type.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'S32_MIN'
-type corrected to "#define S32_MIN ((s32)-2147483648)".<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_ppp.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">in</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> all macros,
-put the passed parameter between parenthesis.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">extended</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> ID coded in
-29-bit long.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN
-initialization acknowledge error fixed.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_usart.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">change</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> "&amp;="
-instead of "="&nbsp; in <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">USART_ClearITPendingBit</span></span></span>&nbsp;
-and <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">USART_ClearFlag</span></span></span>
-functions.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_adc.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">replace</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> "&amp;="
-by "="&nbsp; in <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">ADC_ClearITPendingBit</span></span></span>
-and <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">ADC_ClearFlag</span></span></span>
-functions.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">replace</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> "&amp;="
-by "="&nbsp; in I2C_ClearITPendingBit and I2C_ClearFlag functions. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">replace</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> "&amp;="
-by "="&nbsp; in <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ClearITPendingBit</span></span></span>
-and <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ClearFlag</span></span></span>
-functions. <o:p></o:p></span></li>
-</ul>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="3" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">project<o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_it.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">update</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> file
-description. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add template
-projects for EWARM v5 and <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">HiTOP</span></span></span>
-<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">toolchains</span></span></span>.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-<o:p></o:p></span></li>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="4" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">examples<o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="SpellE"><span class="spelle"><span style="font-size: 10pt; font-family: Verdana;">FWLib</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> V1.0
-examples ported to run on STMicroelectronics STM3210E-EVAL evaluation
-board (in addition to STM3210B-EVAL)<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-examples for FSMC, SDIO, DAC and I2S (run only on High-density
-devices). <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-examples for ADC, DMA and RTC peripherals.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-example for CRC module. <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Examples
-folder renamed, use of short name instead of <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">examplex</span></span></span>
-(x: 1 2 ...).<o:p></o:p></span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0
-- 10/08/2007<o:p></o:p></span></h3>
-<ol style="font-style: italic; font-weight: bold;" start="1" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">library<o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add template
-project with RIDE <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">toolchain</span></span></span>.
-<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In all
-stm32f10x_ppp.c and stm32f10x_conf.h files: change "assert" macro name
-to "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">assert_param</span></span></span>".<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;
-Note: If you are using the FW Library V0.3 in your application and you
-want to migrate to V1.0, you have to update your applications
-ôstm32f10x_conf.h file with the latest one (provided with V1.0).<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_conf.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove '#<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">undef</span></span></span>
-assert' <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change
-'#define DEBUG' by '#define DEBUG&nbsp;&nbsp;&nbsp; 1'<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_type.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-types: sc32, sc16, sc8, vsc32, vsc16 and vsc8&nbsp; <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_it.c
-<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add basic
-fault exception handling: in "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">HardFaultException</span></span></span>",
-"<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">MemManageException</span></span></span>",&nbsp;
-"<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">BusFaultException</span></span></span>"
-and "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">UsageFaultException</span></span></span>"
-ISR the following code was added:<o:p></o:p></span></li>
-</ul>
-</ul>
-<div style="margin-left: 150pt;">
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: Arial; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;
-/* Go to infinite loop when exception occurs */<br>
-&nbsp;&nbsp;&nbsp;&nbsp; while (1)<br>
-&nbsp;&nbsp;&nbsp;&nbsp; {<br>
-&nbsp;&nbsp;&nbsp;&nbsp; }</span><span style="font-family: Arial; color: black;"><o:p></o:p></span></p>
-</div>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.c<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">"<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">RCC_</span></span><span class="GramE"><span class="grame"><span style="font-family: Verdana;">WaitForHSEStartUp</span></span></span></span><span class="GramE"><span class="grame"><span style="font-family: Verdana;">(</span></span></span>)"
-function updated to resolve issue with high GNU compiler optimization. <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'#define
-GPIO_Remap1_CAN ((u32)0x001D2000)' changed to '#define GPIO_Remap1_CAN
-((u32)0x001D4000)'.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.c/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">"<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">RTC_GetPrescaler</span></span></span>"
-function removed.<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.c/.h<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span class="GramE"><span class="grame"><span style="font-size: 10pt; font-family: Verdana;">add</span></span></span><span style="font-size: 10pt; font-family: Verdana;"> "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">BKP_RTCOutputConfig</span></span></span>()"
-function to allow to select the RTC output source(<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">Calib</span></span></span>
-clock, RTC Alarm or RTC Second) to output on Tamper pin and remove "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">BKP_RTCCalibrationClockOutputCmd</span></span></span>()"
-function.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN
-synchronization jump width defines updated<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'#define
-CAN_SJW_0tq' ==&gt; '#define CAN_SJW_1tq'<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'#define
-CAN_SJW_1tq' ==&gt; '#define CAN_SJW_2tq'<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'#define
-CAN_SJW_2tq' ==&gt; '#define CAN_SJW_3tq'<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">'#define
-CAN_SJW_3tq' ==&gt; '#define CAN_SJW_4tq'<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim1.c/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">"TIM1_OCxNPolarityConfig(u16
-TIM1_OCPolarity)" function: change parameter name to 'TIM1_OCNPolarity'
-<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change
-'TIM1_ICSelection_TRGI' by 'TIM1_ICSelection_TRC'<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c/.h<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change '<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ICSelection_TRGI</span></span></span>'
-by '<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">TIM_ICSelection_TRC</span></span></span>'<o:p></o:p></span></li>
-</ul>
-</ul>
-<ol style="font-style: italic; font-weight: bold;" start="2" type="1">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">examples<o:p></o:p></span></li>
-</ol>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">ADC examples
-3 &amp; 4 updated&nbsp;&nbsp;&nbsp; <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">DEBUG example<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-modified to support RIDE specific <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">printf</span></span></span>
-function implementation<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C example5<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">i2c_ee.c: add
-the following function prototypes: "void <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">GPIO_Configuration</span></span></span>(void)"&nbsp;
-add "void I2C_Configuration(void)"<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add GPIO pin
-toggle example.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">BKP, CAN,
-DMA, NVIC and I2C examples readme files updated.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Use decimal
-(instead of hexadecimal) values constants in TIM, TIM1 and IWDG
-examples.<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">example 12<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">USART3 ISR
-updated <o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Timeout
-define "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">SC_Receive_Timeout</span></span></span>"
-updated to 0x4000<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">example 7<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-modified to support RIDE specific <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">printf</span></span></span>
-function implementation<o:p></o:p></span></li>
-</ul>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Example
-modified to support RIDE specific <span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">printf</span></span></span>
-function implementation<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">BKP_RTCCalibrationClockOutputCmd</span></span></span>()"
-function&nbsp; by "<span class="SpellE"><span class="spelle"><span style="font-family: Verdana;">RTC_ClockOutput</span></span></span>()"<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LSI removed
-as RTC clock source<o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IWDG example<o:p></o:p></span></li>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LSI frequency
-value changed from 32 KHz to 40 KHz&nbsp; <o:p></o:p></span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update the
-STM32F10x evaluation board name from STM32F10x-EVAL to STM3210B-EVAL <o:p></o:p></span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">V0.3
-- 05/21/2007<o:p></o:p></span></h3>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created.<o:p></o:p></span></li>
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c
deleted file mode 100644
index 04c5560..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c
+++ /dev/null
@@ -1,997 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    fonts.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides text fonts for STM32xx-EVAL's LCD driver. 
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-
-/** @addtogroup FONTS
-  * @brief      This file includes the Fonts driver of STM32-EVAL boards.
-  * @{
-  */  
-
-/** @defgroup FONTS_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FONTS_Private_Defines
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FONTS_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup FONTS_Private_Variables
-  * @{
-  */
-const uint16_t ASCII16x24_Table [] = {
-/** 
-  * @brief        Space ' '  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '!'  
-  */ 
-         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '"'  
-  */ 
-         0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '#'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
-         0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
-         0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
-/** 
-  * @brief        '$'  
-  */ 
-         0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
-         0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
-         0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '%'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
-         0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
-         0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '&'  
-  */ 
-         0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
-         0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
-         0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '''  
-  */ 
-         0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '('  
-  */ 
-         0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
-         0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
-         0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
-/** 
-  * @brief        ')'  
-  */ 
-         0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
-         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
-         0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
-/** 
-  * @brief        '*'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
-         0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '+'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        ','  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
-/** 
-  * @brief        '-'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '.'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '/'  
-  */ 
-         0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
-         0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
-         0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '0'  
-  */ 
-         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
-         0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
-         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '1'  
-  */ 
-         0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '2'  
-  */ 
-         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
-         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
-         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '3'  
-  */ 
-         0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
-         0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
-         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '4'  
-  */ 
-         0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
-         0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
-         0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '5'  
-  */ 
-         0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
-         0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
-         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '6'  
-  */ 
-         0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
-         0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
-         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '7'  
-  */ 
-         0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
-         0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
-         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '8'  
-  */ 
-         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
-         0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
-         0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '9'  
-  */ 
-         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
-         0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
-         0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        ':'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        ';'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '<'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
-         0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '='  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '>'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
-         0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '?'  
-  */ 
-         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
-         0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
-         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '@'  
-  */ 
-         0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
-         0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
-         0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'A'  
-  */ 
-         0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
-         0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
-         0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'B'  
-  */ 
-         0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
-         0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
-         0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'C'  
-  */ 
-         0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
-         0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
-         0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'D'  
-  */ 
-         0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
-         0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
-         0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'E'  
-  */ 
-         0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
-         0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
-         0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'F'  
-  */ 
-         0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
-         0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
-         0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'G'  
-  */ 
-         0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
-         0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
-         0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'H'  
-  */ 
-         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
-         0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
-         0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'I'  
-  */ 
-         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'J'  
-  */ 
-         0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
-         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
-         0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'K'  
-  */ 
-         0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
-         0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
-         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'L'  
-  */ 
-         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
-         0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
-         0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'M'  
-  */ 
-         0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
-         0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
-         0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'N'  
-  */ 
-         0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
-         0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
-         0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'O'  
-  */ 
-         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
-         0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
-         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'P'  
-  */ 
-         0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
-         0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
-         0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'Q'  
-  */ 
-         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
-         0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
-         0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'R'  
-  */ 
-         0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
-         0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
-         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'S'  
-  */ 
-         0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
-         0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
-         0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'T'  
-  */ 
-         0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'U'  
-  */ 
-         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
-         0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
-         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'V'  
-  */ 
-         0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
-         0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
-         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'W'  
-  */ 
-         0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
-         0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
-         0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'X'  
-  */ 
-         0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
-         0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
-         0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'Y'  
-  */ 
-         0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
-         0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'Z'  
-  */ 
-         0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
-         0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
-         0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '['  
-  */ 
-         0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
-         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
-         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
-/** 
-  * @brief        '\'  
-  */ 
-         0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
-         0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
-         0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        ']'  
-  */ 
-         0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
-         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
-         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
-/** 
-  * @brief        '^'  
-  */ 
-         0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
-         0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '_'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '''  
-  */ 
-         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'a'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
-         0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
-         0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'b'  
-  */ 
-         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
-         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
-         0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'c'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
-         0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
-         0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'd'  
-  */ 
-         0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
-         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
-         0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'e'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
-         0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
-         0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'f'  
-  */ 
-         0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'g'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
-         0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
-         0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
-/** 
-  * @brief        'h'  
-  */ 
-         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
-         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
-         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'i'  
-  */ 
-         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'j'  
-  */ 
-         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
-/** 
-  * @brief        'k'  
-  */ 
-         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
-         0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
-         0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'l'  
-  */ 
-         0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'm'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
-         0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
-         0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'n'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
-         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
-         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'o'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
-         0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
-         0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'p'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
-         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
-         0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
-/** 
-  * @brief        'q'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
-         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
-         0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
-/** 
-  * @brief        'r'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
-         0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
-         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        's'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
-         0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
-         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        't'  
-  */ 
-         0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'u'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
-         0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
-         0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'v'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
-         0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
-         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'w'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
-         0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
-         0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'x'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
-         0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
-         0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        'y'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
-         0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
-         0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
-/** 
-  * @brief        'z'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
-         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
-         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-/** 
-  * @brief        '{'  
-  */ 
-         0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
-         0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
-         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
-/** 
-  * @brief        '|'  
-  */ 
-         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
-/** 
-  * @brief        '}'  
-  */ 
-         0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
-         0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
-         0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
-/** 
-  * @brief        '~'  
-  */ 
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
-
-const uint16_t ASCII12x12_Table [] = {
-    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,
-    0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000,
-    0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000,
-    0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000,
-    0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000,
-    0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,
-    0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000,
-    0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
-    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
-    0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000,
-    0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
-    0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000,
-    0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000,
-    0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000,
-    0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
-    0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000,
-    0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000,
-    0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
-    0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000,
-    0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000,
-    0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040,
-    0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000,
-    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000,
-    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000,
-    0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000,
-    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
-    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
-    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000,
-    0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000,
-    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
-    0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000,
-    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
-    0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000,
-    0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000,
-    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
-    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
-    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000,
-    0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000,
-    0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000,
-    0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
-    0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
-    0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000,
-    0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000,
-    0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000,
-    0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
-    0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000,
-    0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
-    0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000,
-    0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
-    0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00,
-    0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000,
-    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000,
-    0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400,
-    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
-    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
-    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,
-    0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000,
-    0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000,
-    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400,
-    0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000,
-    0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000,
-    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000,
-    0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000,
-    0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,
-    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
-    0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,
-    0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
-    0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000};
-
-const uint16_t ASCII8x12_Table [] = {
-    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,
-    0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00,
-    0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10,
-    0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00,
-    0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00,
-    0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
-    0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
-    0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,
-    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,
-    0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00,
-    0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00,
-    0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40,
-    0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00,
-    0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00,
-    0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41,
-    0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00,
-    0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00,
-    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00,
-    0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00,
-    0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00,
-    0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00,
-    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00,
-    0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00,
-    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00,
-    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00,
-    0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00,
-    0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00,
-    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
-    0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04,
-    0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00,
-    0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00,
-    0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,
-    0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
-    0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00,
-    0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
-    0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00,
-    0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00,
-    0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00,
-    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
-    0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00,
-    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
-    0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,
-    0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00,
-    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00,
-    0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
-    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
-    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
-    0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00,
-    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00,
-    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80,
-    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
-    0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00,
-    0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00,
-    0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00,
-    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20,
-    0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00,
-    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80,
-    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
-    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40,
-    0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00,
-    0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00};
-
-const uint16_t ASCII8x8_Table [] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40,
-    0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48,
-    0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38,
-    0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24,
-    0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30,
-    0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08,
-    0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10,
-    0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00,
-    0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,
-    0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,
-    0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20,
-    0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18,
-    0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08,
-    0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c,
-    0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18,
-    0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04,
-    0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18,
-    0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18,
-    0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10,
-    0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18,
-    0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18,
-    0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00,
-    0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00,
-    0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00,
-    0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00,
-    0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00,
-    0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10,
-    0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38,
-    0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44,
-    0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78,
-    0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c,
-    0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70,
-    0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c,
-    0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20,
-    0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c,
-    0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44,
-    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18,
-    0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c,
-    0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92,
-    0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42,
-    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
-    0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40,
-    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a,
-    0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42,
-    0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38,
-    0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
-    0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10,
-    0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
-    0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42,
-    0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c,
-    0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c,
-    0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04,
-    0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c,
-    0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c,
-    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28,
-    0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18,
-    0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14,
-    0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18,
-    0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10,
-    0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18,
-    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
-    0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10,
-    0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24,
-    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92,
-    0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
-    0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18,
-    0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20,
-    0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04,
-    0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20,
-    0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18,
-    0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18,
-    0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14,
-    0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10,
-    0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
-    0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44,
-    0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10,
-    0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c,
-    0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08,
-    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
-    0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10,
-    0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00,
-    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
-
-sFONT Font16x24 = {
-  ASCII16x24_Table,
-  16, /* Width */
-  24, /* Height */
-};
-
-sFONT Font12x12 = {
-  ASCII12x12_Table,
-  12, /* Width */
-  12, /* Height */
-};
-
-sFONT Font8x12 = {
-  ASCII8x12_Table,
-  8, /* Width */
-  12, /* Height */
-};
-
-
-sFONT Font8x8 = {
-  ASCII8x8_Table,
-  8, /* Width */
-  8, /* Height */
-};
-   
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FONTS_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FONTS_Private_Functions
-  * @{
-  */
-    
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h
deleted file mode 100644
index f6ca7ce..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    fonts.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   Header for fonts.c
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __FONTS_H
-#define __FONTS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include <stdint.h>
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-
-/** @addtogroup FONTS
-  * @{
-  */ 
-
-/** @defgroup FONTS_Exported_Types
-  * @{
-  */ 
-typedef struct _tFont
-{    
-  const uint16_t *table;
-  uint16_t Width;
-  uint16_t Height;
-  
-} sFONT;
-
-extern sFONT Font16x24;
-extern sFONT Font12x12;
-extern sFONT Font8x12;
-extern sFONT Font8x8;
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FONTS_Exported_Constants
-  * @{
-  */ 
-#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FONTS_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup FONTS_Exported_Functions
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-  
-#endif /* __FONTS_H */
- 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */      
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c
deleted file mode 100644
index 027653d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c
+++ /dev/null
@@ -1,854 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_i2c_ee.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the I2C M24CXX 
-  *          EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this memory). 
-  *          
-  *          ===================================================================      
-  *          Note: This driver is intended for STM32F10x families devices only.
-  *          ===================================================================
-  *            
-  *          It implements a high level communication layer for read and write 
-  *          from/to this memory. The needed STM32 hardware resources (I2C and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in sEE_LowLevel_Init() function declared in stm32xx_eval.c 
-  *          file.
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          sEE_LowLevel_Init() function. 
-  *        
-  *          @note In this driver, basic read and write functions (sEE_ReadBuffer() 
-  *                and sEE_WritePage()) use the DMA to perform the data transfer 
-  *                to/from EEPROM memory (except when number of requested data is
-  *                equal to 1). Thus, after calling these two functions, user 
-  *                application may perform other tasks while DMA is transferring
-  *                data. The application should then monitor the variable holding 
-  *                the number of data in order to determine when the transfer is
-  *                completed (variable decremented to 0). Stopping transfer tasks
-  *                are performed into DMA interrupt handlers (which are integrated
-  *                into this driver).
-  *            
-  *     +-----------------------------------------------------------------+
-  *     |                        Pin assignment                           |                 
-  *     +---------------------------------------+-----------+-------------+
-  *     |  STM32 I2C Pins                       |   sEE     |   Pin       |
-  *     +---------------------------------------+-----------+-------------+
-  *     | .                                     |   E0(GND) |    1  (0V)  |
-  *     | .                                     |   E1(GND) |    2  (0V)  |
-  *     | .                                     |   E2(GND) |    3  (0V)  |
-  *     | .                                     |   E0(VSS) |    4  (0V)  |
-  *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
-  *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
-  *     | .                                     |   /WC(VDD)|    7 (3.3V) |
-  *     | .                                     |   VDD     |    8 (3.3V) |
-  *     +---------------------------------------+-----------+-------------+  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_i2c_ee.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_I2C_EE
-  * @brief      This file includes the I2C EEPROM driver of STM32-EVAL boards.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Defines
-  * @{
-  */  
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Variables
-  * @{
-  */
-__IO uint16_t  sEEAddress = 0;   
-__IO uint32_t  sEETimeout = sEE_LONG_TIMEOUT;   
-__IO uint16_t* sEEDataReadPointer;   
-__IO uint8_t*  sEEDataWritePointer;  
-__IO uint8_t   sEEDataNum;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_I2C_EE_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_DeInit(void)
-{
-  sEE_LowLevel_DeInit(); 
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_Init(void)
-{ 
-  I2C_InitTypeDef  I2C_InitStructure;
-  
-  sEE_LowLevel_Init();
-  
-  /*!< I2C configuration */
-  /* sEE_I2C configuration */
-  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
-  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
-  I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7;
-  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
-  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-  I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
-  
-  /* sEE_I2C Peripheral Enable */
-  I2C_Cmd(sEE_I2C, ENABLE);
-  /* Apply sEE_I2C configuration after enabling it */
-  I2C_Init(sEE_I2C, &I2C_InitStructure);
-
-  /* Enable the sEE_I2C peripheral DMA requests */
-  I2C_DMACmd(sEE_I2C, ENABLE);
-  
-#if defined (sEE_M24C64_32)
-  /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */
-  sEEAddress = sEE_HW_ADDRESS;  
-#elif defined (sEE_M24C08)
-  /*!< depending on the sEE Address selected in the i2c_ee.h file */
- #ifdef sEE_Block0_ADDRESS
-  /*!< Select the sEE Block0 to write on */
-  sEEAddress = sEE_Block0_ADDRESS;
- #endif
-  
- #ifdef sEE_Block1_ADDRESS
-  /*!< Select the sEE Block1 to write on */
-  sEEAddress = sEE_Block1_ADDRESS;
- #endif
-
- #ifdef sEE_Block2_ADDRESS
-  /*!< Select the sEE Block2 to write on */
-  sEEAddress = sEE_Block2_ADDRESS;
- #endif
-  
- #ifdef sEE_Block3_ADDRESS
-  /*!< Select the sEE Block3 to write on */
-  sEEAddress = sEE_Block3_ADDRESS;
- #endif 
-#endif /*!< sEE_M24C64_32 */    
-}
-
-/**
-  * @brief  Reads a block of data from the EEPROM.
-  * @param  pBuffer : pointer to the buffer that receives the data read from 
-  *         the EEPROM.
-  * @param  ReadAddr : EEPROM's internal address to start reading from.
-  * @param  NumByteToRead : pointer to the variable holding number of bytes to 
-  *         be read from the EEPROM.
-  * 
-  *        @note The variable pointed by NumByteToRead is reset to 0 when all the 
-  *              data are read from the EEPROM. Application should monitor this 
-  *              variable in order know when the transfer is complete.
-  * 
-  * @note When number of data to be read is higher than 1, this function just 
-  *       configures the communication and enable the DMA channel to transfer data.
-  *       Meanwhile, the user application may perform other tasks.
-  *       When number of data to be read is 1, then the DMA is not used. The byte
-  *       is read in polling mode.
-  * 
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
-{  
-  /* Set the pointer to the Number of data to be read. This pointer will be used 
-      by the DMA Transfer Completer interrupt Handler in order to reset the 
-      variable to 0. User should check on this variable in order to know if the 
-      DMA transfer has been complete or not. */
-  sEEDataReadPointer = NumByteToRead;
-  
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send START condition */
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send EEPROM address for write */
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-
-  /*!< Test on EV6 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  } 
-
-#ifdef sEE_M24C08  
-  
-  /*!< Send the EEPROM's internal address to read from: Only one byte address */
-  I2C_SendData(sEE_I2C, ReadAddr);  
-
-#elif defined (sEE_M24C64_32)
-
-  /*!< Send the EEPROM's internal address to read from: MSB of the address first */
-  I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8));    
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-  /*!< Send the EEPROM's internal address to read from: LSB of the address */
-  I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF));    
-  
-#endif /*!< sEE_M24C08 */
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET)
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send STRAT condition a second time */  
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  } 
-  
-  /*!< Send EEPROM address for read */
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver);  
-  
-  /* If number of data to be read is 1, then DMA couldn't be used */
-  /* One Byte Master Reception procedure (POLLING) ---------------------------*/
-  if ((uint16_t)(*NumByteToRead) < 2)
-  {
-    /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }     
-    
-    /*!< Disable Acknowledgement */
-    I2C_AcknowledgeConfig(sEE_I2C, DISABLE);   
-
-    /* Call User callback for critical section start (should typically disable interrupts) */
-    sEE_EnterCriticalSection_UserCallback();
-    
-    /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
-    (void)sEE_I2C->SR2;
-    
-    /*!< Send STOP Condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);
-   
-    /* Call User callback for critical section end (should typically re-enable interrupts) */
-    sEE_ExitCriticalSection_UserCallback();
-    
-    /* Wait for the byte to be received */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }
-    
-    /*!< Read the byte received from the EEPROM */
-    *pBuffer = I2C_ReceiveData(sEE_I2C);
-    
-    /*!< Decrement the read bytes counter */
-    (uint16_t)(*NumByteToRead)--;        
-    
-    /* Wait to make sure that STOP control bit has been cleared */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(sEE_I2C->CR1 & I2C_CR1_STOP)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }  
-    
-    /*!< Re-Enable Acknowledgement to be ready for another reception */
-    I2C_AcknowledgeConfig(sEE_I2C, ENABLE);    
-  }
-  else/* More than one Byte Master Reception procedure (DMA) -----------------*/
-  {
-    /*!< Test on EV6 and clear it */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }  
-    
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX);
-    
-    /* Inform the DMA that the next End Of Transfer Signal will be the last one */
-    I2C_DMALastTransferCmd(sEE_I2C, ENABLE); 
-    
-    /* Enable the DMA Rx Channel */
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);  
-  }
-  
-  /* If all operations OK, return sEE_OK (0) */
-  return sEE_OK;
-}
-
-/**
-  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
-  *
-  * @note   The number of bytes (combined to write start address) must not 
-  *         cross the EEPROM page boundary. This function can only write into
-  *         the boundaries of an EEPROM page.
-  *         This function doesn't check on boundaries condition (in this driver 
-  *         the function sEE_WriteBuffer() which calls sEE_WritePage() is 
-  *         responsible of checking on Page boundaries).
-  * 
-  * @param  pBuffer : pointer to the buffer containing the data to be written to 
-  *         the EEPROM.
-  * @param  WriteAddr : EEPROM's internal address to write to.
-  * @param  NumByteToWrite : pointer to the variable holding number of bytes to 
-  *         be written into the EEPROM. 
-  * 
-  *        @note The variable pointed by NumByteToWrite is reset to 0 when all the 
-  *              data are written to the EEPROM. Application should monitor this 
-  *              variable in order know when the transfer is complete.
-  * 
-  * @note This function just configure the communication and enable the DMA 
-  *       channel to transfer data. Meanwhile, the user application may perform 
-  *       other tasks in parallel.
-  * 
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
-{ 
-  /* Set the pointer to the Number of data to be written. This pointer will be used 
-      by the DMA Transfer Completer interrupt Handler in order to reset the 
-      variable to 0. User should check on this variable in order to know if the 
-      DMA transfer has been complete or not. */
-  sEEDataWritePointer = NumByteToWrite;  
-  
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send START condition */
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send EEPROM address for write */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-
-  /*!< Test on EV6 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-#ifdef sEE_M24C08
-  
-  /*!< Send the EEPROM's internal address to write to : only one byte Address */
-  I2C_SendData(sEE_I2C, WriteAddr);
-  
-#elif defined(sEE_M24C64_32)
-  
-  /*!< Send the EEPROM's internal address to write to : MSB of the address first */
-  I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8));
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;  
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }  
-  
-  /*!< Send the EEPROM's internal address to write to : LSB of the address */
-  I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF));
-  
-#endif /*!< sEE_M24C08 */  
-  
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT; 
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }  
-  
-  /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-  sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX);
-    
-  /* Enable the DMA Tx Channel */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE);
-  
-  /* If all operations OK, return sEE_OK (0) */
-  return sEE_OK;
-}
-
-/**
-  * @brief  Writes buffer of data to the I2C EEPROM.
-  * @param  pBuffer : pointer to the buffer  containing the data to be written 
-  *         to the EEPROM.
-  * @param  WriteAddr : EEPROM's internal address to write to.
-  * @param  NumByteToWrite : number of bytes to write to the EEPROM.
-  * @retval None
-  */
-void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
-{
-  uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0;
-  uint16_t Addr = 0;
-
-  Addr = WriteAddr % sEE_PAGESIZE;
-  count = sEE_PAGESIZE - Addr;
-  NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
-  NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
- 
-  /*!< If WriteAddr is sEE_PAGESIZE aligned  */
-  if(Addr == 0) 
-  {
-    /*!< If NumByteToWrite < sEE_PAGESIZE */
-    if(NumOfPage == 0) 
-    {
-      /* Store the number of data to be written */
-      sEEDataNum = NumOfSingle;
-      /* Start writing data */
-      sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-      /* Wait transfer through DMA to be complete */
-      sEETimeout = sEE_LONG_TIMEOUT;
-      while (sEEDataNum > 0)
-      {
-        if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-      }
-      sEE_WaitEepromStandbyState();
-    }
-    /*!< If NumByteToWrite > sEE_PAGESIZE */
-    else  
-    {
-      while(NumOfPage--)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = sEE_PAGESIZE;        
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }      
-        sEE_WaitEepromStandbyState();
-        WriteAddr +=  sEE_PAGESIZE;
-        pBuffer += sEE_PAGESIZE;
-      }
-
-      if(NumOfSingle!=0)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;          
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }    
-        sEE_WaitEepromStandbyState();
-      }
-    }
-  }
-  /*!< If WriteAddr is not sEE_PAGESIZE aligned  */
-  else 
-  {
-    /*!< If NumByteToWrite < sEE_PAGESIZE */
-    if(NumOfPage== 0) 
-    {
-      /*!< If the number of data to be written is more than the remaining space 
-      in the current page: */
-      if (NumByteToWrite > count)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = count;        
-        /*!< Write the data conained in same page */
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }          
-        sEE_WaitEepromStandbyState();      
-        
-        /* Store the number of data to be written */
-        sEEDataNum = (NumByteToWrite - count);          
-        /*!< Write the remaining data in the following page */
-        sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }     
-        sEE_WaitEepromStandbyState();        
-      }      
-      else      
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;         
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }          
-        sEE_WaitEepromStandbyState();        
-      }     
-    }
-    /*!< If NumByteToWrite > sEE_PAGESIZE */
-    else
-    {
-      NumByteToWrite -= count;
-      NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
-      NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
-      
-      if(count != 0)
-      {  
-        /* Store the number of data to be written */
-        sEEDataNum = count;         
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }     
-        sEE_WaitEepromStandbyState();
-        WriteAddr += count;
-        pBuffer += count;
-      } 
-      
-      while(NumOfPage--)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = sEE_PAGESIZE;          
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }        
-        sEE_WaitEepromStandbyState();
-        WriteAddr +=  sEE_PAGESIZE;
-        pBuffer += sEE_PAGESIZE;  
-      }
-      if(NumOfSingle != 0)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;           
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }         
-        sEE_WaitEepromStandbyState();
-      }
-    }
-  }  
-}
-
-/**
-  * @brief  Wait for EEPROM Standby state.
-  * 
-  * @note  This function allows to wait and check that EEPROM has finished the 
-  *        last Write operation. It is mostly used after Write operation: after 
-  *        receiving the buffer to be written, the EEPROM may need additional 
-  *        time to actually perform the write operation. During this time, it 
-  *        doesn't answer to I2C packets addressed to it. Once the write operation 
-  *        is complete the EEPROM responds to its address.
-  *        
-  * @note  It is not necessary to call this function after sEE_WriteBuffer() 
-  *        function (sEE_WriteBuffer() already calls this function after each
-  *        write page operation).    
-  * 
-  * @param  None
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_WaitEepromStandbyState(void)      
-{
-  __IO uint16_t tmpSR1 = 0;
-  __IO uint32_t sEETrials = 0;
-
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-  /* Keep looping till the slave acknowledge his address or maximum number 
-     of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
-     in stm32_eval_i2c_ee.h file) */
-  while (1)
-  {
-    /*!< Send START condition */
-    I2C_GenerateSTART(sEE_I2C, ENABLE);
-
-    /*!< Test on EV5 and clear it */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }    
-
-    /*!< Send EEPROM address for write */
-    I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-    
-    /* Wait for ADDR flag to be set (Slave acknowledged his address) */
-    sEETimeout = sEE_LONG_TIMEOUT;
-    do
-    {     
-      /* Get the current value of the SR1 register */
-      tmpSR1 = sEE_I2C->SR1;
-      
-      /* Update the timeout value and exit if it reach 0 */
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }
-    /* Keep looping till the Address is acknowledged or the AF flag is 
-       set (address not acknowledged at time) */
-    while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0);
-     
-    /* Check if the ADDR flag has been set */
-    if (tmpSR1 & I2C_SR1_ADDR)
-    {
-      /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already 
-         been read) */
-      (void)sEE_I2C->SR2;
-      
-      /*!< STOP condition */    
-      I2C_GenerateSTOP(sEE_I2C, ENABLE);
-        
-      /* Exit the function */
-      return sEE_OK;
-    }
-    else
-    {
-      /*!< Clear AF flag */
-      I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF);                  
-    }
-    
-    /* Check if the maximum allowed numbe of trials has bee reached */
-    if (sEETrials++ == sEE_MAX_TRIALS_NUMBER)
-    {
-      /* If the maximum number of trials has been reached, exit the function */
-      return sEE_TIMEOUT_UserCallback();
-    }
-  }
-}
-
-/**
-  * @brief  This function handles the DMA Tx Channel interrupt Handler.
-  * @param  None
-  * @retval None
-  */
-void sEE_I2C_DMA_TX_IRQHandler(void)
-{
-  /* Check if the DMA transfer is complete */ 
-  if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET)
-  {  
-    /* Disable the DMA Tx Channel and Clear all its Flags */  
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-    DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL);
-
-    /*!< Wait till all data have been physically transferred on the bus */
-    sEETimeout = sEE_LONG_TIMEOUT;
-    while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF))
-    {
-      if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback();
-    }
-    
-    /*!< Send STOP condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);
-    
-    /* Perform a read on SR1 and SR2 register to clear eventualaly pending flags */
-    (void)sEE_I2C->SR1;
-    (void)sEE_I2C->SR2;
-    
-    /* Reset the variable holding the number of data to be written */
-    *sEEDataWritePointer = 0;  
-  }
-}
-
-/**
-  * @brief  This function handles the DMA Rx Channel interrupt Handler.
-  * @param  None
-  * @retval None
-  */
-void sEE_I2C_DMA_RX_IRQHandler(void)
-{
-  /* Check if the DMA transfer is complete */
-  if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET)
-  {      
-    /*!< Send STOP Condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);    
-    
-    /* Disable the DMA Rx Channel and Clear all its Flags */  
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-    DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL);
-    
-    /* Reset the variable holding the number of data to be read */
-    *sEEDataReadPointer = 0;
-  }
-}
-
-#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
-  * @brief  Basic management of the timeout situation.
-  * @param  None.
-  * @retval None.
-  */
-uint32_t sEE_TIMEOUT_UserCallback(void)
-{
-  /* Block communication and all processes */
-  while (1)
-  {   
-  }
-}
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-
-#ifdef USE_DEFAULT_CRITICAL_CALLBACK
-/**
-  * @brief  Start critical section: these callbacks should be typically used
-  *         to disable interrupts when entering a critical section of I2C communication
-  *         You may use default callbacks provided into this driver by uncommenting the 
-  *         define USE_DEFAULT_CRITICAL_CALLBACK.
-  *         Or you can comment that line and implement these callbacks into your 
-  *         application.
-  * @param  None.
-  * @retval None.
-  */
-void sEE_EnterCriticalSection_UserCallback(void)
-{
-  __disable_irq();  
-}
-
-/**
-  * @brief  Start and End of critical section: these callbacks should be typically used
-  *         to re-enable interrupts when exiting a critical section of I2C communication
-  *         You may use default callbacks provided into this driver by uncommenting the 
-  *         define USE_DEFAULT_CRITICAL_CALLBACK.
-  *         Or you can comment that line and implement these callbacks into your 
-  *         application.
-  * @param  None.
-  * @retval None.
-  */
-void sEE_ExitCriticalSection_UserCallback(void)
-{
-  __enable_irq();
-}
-#endif /* USE_DEFAULT_CRITICAL_CALLBACK */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h
deleted file mode 100644
index fa00fb7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_i2c_ee.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32_eval_i2c_ee
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_I2C_EE_H
-#define __STM32_EVAL_I2C_EE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_I2C_EE
-  * @{
-  */  
-
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Types
-  * @{
-  */ 
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Constants
-  * @{
-  */
-  
-/* Uncomment this line to use the default start and end of critical section 
-   callbacks (it disables then enabled all interrupts) */
-#define USE_DEFAULT_CRITICAL_CALLBACK 
-/* Start and End of critical section: these callbacks should be typically used
-   to disable interrupts when entering a critical section of I2C communication
-   You may use default callbacks provided into this driver by uncommenting the 
-   define USE_DEFAULT_CRITICAL_CALLBACK.
-   Or you can comment that line and implement these callbacks into your 
-   application */
-
-/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() 
-   function implemented in stm32_evel_i2c_ee.c file.
-   sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
-   occure during communication (waiting on an event that doesn't occur, bus 
-   errors, busy devices ...). */   
-/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
-   
-#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32)
-/* Use the defines below the choose the EEPROM type */
-/* #define sEE_M24C08*/  /* Support the device: M24C08. */
-/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and 
-   HW address are correctly defined*/
-#define sEE_M24C64_32  /* Support the devices: M24C32 and M24C64 */
-#endif
-
-#ifdef sEE_M24C64_32
-/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device 
-  address selection (ne need for additional address lines). According to the 
-  Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */
-
- #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */ 
-
-#elif defined (sEE_M24C08)
-/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 
-   EEPROM Addresses defines */
- #define sEE_Block0_ADDRESS     0xA0   /* E2 = 0 */ 
- /*#define sEE_Block1_ADDRESS     0xA2*/ /* E2 = 0 */  
- /*#define sEE_Block2_ADDRESS     0xA4*/ /* E2 = 0 */
- /*#define sEE_Block3_ADDRESS     0xA6*/ /* E2 = 0 */
-
-#endif /* sEE_M24C64_32 */
-
-#define I2C_SPEED               300000
-#define I2C_SLAVE_ADDRESS7      0xA0
-
-#if defined (sEE_M24C08)
- #define sEE_PAGESIZE           16
-#elif defined (sEE_M24C64_32)
- #define sEE_PAGESIZE           32
-#endif
-   
-/* Maximum Timeout values for flags and events waiting loops. These timeouts are
-   not based on accurate values, they just guarantee that the application will 
-   not remain stuck if the I2C communication is corrupted.
-   You may modify these timeout values depending on CPU frequency and application
-   conditions (interrupts routines ...). */   
-#define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
-#define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
-
-/* Maximum number of trials for sEE_WaitEepromStandbyState() function */
-#define sEE_MAX_TRIALS_NUMBER     150
-   
-/* Defintions for the state of the DMA transfer */   
-#define sEE_STATE_READY           0
-#define sEE_STATE_BUSY            1
-#define sEE_STATE_ERROR           2
-   
-#define sEE_OK                    0
-#define sEE_FAIL                  1   
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Macros
-  * @{
-  */    
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Functions
-  * @{
-  */ 
-void     sEE_DeInit(void);
-void     sEE_Init(void);
-uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
-uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
-void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
-uint32_t sEE_WaitEepromStandbyState(void);
-
-/* USER Callbacks: These are functions for which prototypes only are declared in
-   EEPROM driver and that should be implemented into user applicaiton. */  
-/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
-   occure during communication (waiting on an event that doesn't occur, bus 
-   errors, busy devices ...).
-   You can use the default timeout callback implementation by uncommenting the 
-   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file.
-   Typically the user implementation of this callback should reset I2C peripheral
-   and re-initialize communication or in worst case reset all the application. */
-uint32_t sEE_TIMEOUT_UserCallback(void);
-
-/* Start and End of critical section: these callbacks should be typically used
-   to disable interrupts when entering a critical section of I2C communication
-   You may use default callbacks provided into this driver by uncommenting the 
-   define USE_DEFAULT_CRITICAL_CALLBACK in stm32_evel_i2c_ee.h file..
-   Or you can comment that line and implement these callbacks into your 
-   application */
-void sEE_EnterCriticalSection_UserCallback(void);
-void sEE_ExitCriticalSection_UserCallback(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_EVAL_I2C_EE_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c
deleted file mode 100644
index 2db762e..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c
+++ /dev/null
@@ -1,977 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_i2c_tsensor.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the I2C LM75 
-  *          temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this sensor). 
-  *          It implements a high level communication layer for read and write 
-  *          from/to this sensor. The needed STM32 hardware resources (I2C and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c 
-  *          file.
-  *            
-  *          Note:
-  *          -----    
-  *          This driver uses the DMA method to send and receive data on I2C bus,
-  *          which allows higher efficiency and reliability  of the communication.
-  *                 
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          LM75_LowLevel_Init() function.
-  *
-  *     +-----------------------------------------------------------------+
-  *     |                        Pin assignment                           |                 
-  *     +---------------------------------------+-----------+-------------+
-  *     |  STM32 I2C Pins                       |   STLM75  |   Pin       |
-  *     +---------------------------------------+-----------+-------------+
-  *     | LM75_I2C_SDA_PIN/ SDA                 |   SDA     |    1        |
-  *     | LM75_I2C_SCL_PIN/ SCL                 |   SCL     |    2        |
-  *     | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT  |   OS/INT  |    3        |
-  *     | .                                     |   GND     |    4  (0V)  |
-  *     | .                                     |   GND     |    5  (0V)  |
-  *     | .                                     |   GND     |    6  (0V)  |
-  *     | .                                     |   GND     |    7  (0V)  |
-  *     | .                                     |   VDD     |    8  (3.3V)|
-  *     +---------------------------------------+-----------+-------------+
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_i2c_tsensor.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_I2C_TSENSOR
-  * @brief      This file includes the LM75 Temperature Sensor driver of 
-  *             STM32-EVAL boards.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */
-
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Defines
-  * @{
-  */ 
-#define LM75_SD_SET                0x01 /*!< Set SD bit in the configuration register */
-#define LM75_SD_RESET              0xFE /*!< Reset SD bit in the configuration register */
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Variables
-  * @{
-  */ 
-  
-__IO uint32_t  LM75_Timeout = LM75_LONG_TIMEOUT; 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes
-  * @{
-  */ 
-static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData);
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_DeInit(void)
-{
-  LM75_LowLevel_DeInit();
-}
-
-/**
-  * @brief  Initializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_Init(void)
-{
-  I2C_InitTypeDef   I2C_InitStructure;
-  
-  LM75_LowLevel_Init();
-  
-  I2C_DeInit(LM75_I2C);
-
-  /*!< LM75_I2C Init */
-  I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost;
-  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
-  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
-  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
-  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-  I2C_InitStructure.I2C_ClockSpeed = LM75_I2C_SPEED;
-  I2C_Init(LM75_I2C, &I2C_InitStructure);
-
-  /*!< Enable SMBus Alert interrupt */
-  I2C_ITConfig(LM75_I2C, I2C_IT_ERR, ENABLE);
-
-  /*!< LM75_I2C Init */
-  I2C_Cmd(LM75_I2C, ENABLE);
-}
-
-
-/**
-  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
-  * @param  None
-  * @retval None
-  */
-
-static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData)
-{
-  DMA_InitTypeDef DMA_InitStructure;
-  
-  RCC_AHBPeriphClockCmd(LM75_DMA_CLK, ENABLE);
-  
-  /* Initialize the DMA_PeripheralBaseAddr member */
-  DMA_InitStructure.DMA_PeripheralBaseAddr = LM75_I2C_DR;
-  /* Initialize the DMA_MemoryBaseAddr member */
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
-   /* Initialize the DMA_PeripheralInc member */
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  /* Initialize the DMA_MemoryInc member */
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  /* Initialize the DMA_PeripheralDataSize member */
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  /* Initialize the DMA_MemoryDataSize member */
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  /* Initialize the DMA_Mode member */
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  /* Initialize the DMA_Priority member */
-  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  /* Initialize the DMA_M2M member */
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  
-  /* If using DMA for Reception */
-  if (Direction == LM75_DMA_RX)
-  {
-    /* Initialize the DMA_DIR member */
-    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-    
-    /* Initialize the DMA_BufferSize member */
-    DMA_InitStructure.DMA_BufferSize = NumData;
-    
-    DMA_DeInit(LM75_DMA_RX_CHANNEL);
-    
-    DMA_Init(LM75_DMA_RX_CHANNEL, &DMA_InitStructure);
-  }
-   /* If using DMA for Transmission */
-  else if (Direction == LM75_DMA_TX)
-  { 
-    /* Initialize the DMA_DIR member */
-    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-    
-    /* Initialize the DMA_BufferSize member */
-    DMA_InitStructure.DMA_BufferSize = NumData;
-    
-    DMA_DeInit(LM75_DMA_TX_CHANNEL);
-    
-    DMA_Init(LM75_DMA_TX_CHANNEL, &DMA_InitStructure);
-  }
-}
-
-
-/**
-  * @brief  Checks the LM75 status.
-  * @param  None
-  * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS).
-  */
-ErrorStatus LM75_GetStatus(void)
-{
-  uint32_t I2C_TimeOut = I2C_TIMEOUT;
-
-  /*!< Clear the LM75_I2C AF flag */
-  I2C_ClearFlag(LM75_I2C, I2C_FLAG_AF);
-
-  /*!< Enable LM75_I2C acknowledgement if it is already disabled by other function */
-  I2C_AcknowledgeConfig(LM75_I2C, ENABLE);
-
-  /*---------------------------- Transmission Phase ---------------------------*/
-
-  /*!< Send LM75_I2C START condition */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-
-  /*!< Test on LM75_I2C EV5 and clear it */
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) && I2C_TimeOut)  /*!< EV5 */
-  {
-    I2C_TimeOut--;
-  }
-  if (I2C_TimeOut == 0)
-  {
-    return ERROR;
-  }
-  
-  I2C_TimeOut = I2C_TIMEOUT;
-
-  /*!< Send STLM75 slave address for write */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-
-  while ((!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && I2C_TimeOut)/* EV6 */
-  {
-    I2C_TimeOut--;
-  }
-
-  if ((I2C_GetFlagStatus(LM75_I2C, I2C_FLAG_AF) != 0x00) || (I2C_TimeOut == 0))
-  {
-    return ERROR;
-  }
-  else
-  {
-    return SUCCESS;
-  }
-}
-/**
-  * @brief  Read the specified register from the LM75.
-  * @param  RegName: specifies the LM75 register to be read.
-  *              This member can be one of the following values:  
-  *                  - LM75_REG_TEMP: temperature register
-  *                  - LM75_REG_TOS: Over-limit temperature register
-  *                  - LM75_REG_THYS: Hysteresis temperature register
-  * @retval LM75 register value.
-  */
-uint16_t LM75_ReadReg(uint8_t RegName)
-{   
-  uint8_t LM75_BufferRX[2] ={0,0};
-  uint16_t tmp = 0;    
-  
-   /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
-  
-  /* Enable DMA NACK automatic generation */
-  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send device address for write */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send the device's internal address to write to */
-  I2C_SendData(LM75_I2C, RegName);  
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send START condition a second time */  
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send LM75 address for read */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }        
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA RX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
-  
-  /*!< Store LM75_I2C received data */
-  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
-  tmp |= LM75_BufferRX[1];
-  
-  /* return a Reg value */
-  return (uint16_t)tmp;  
-}
-
-/**
-  * @brief  Write to the specified register of the LM75.
-  * @param  RegName: specifies the LM75 register to be written.
-  *              This member can be one of the following values:    
-  *                  - LM75_REG_TOS: Over-limit temperature register
-  *                  - LM75_REG_THYS: Hysteresis temperature register
-  * @param  RegValue: value to be written to LM75 register.  
-  * @retval None
-  */
-uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue)
-{   
-  uint8_t LM75_BufferTX[2] ={0,0};
-  LM75_BufferTX[0] = (uint8_t)(RegValue >> 8);
-  LM75_BufferTX[1] = (uint8_t)(RegValue);
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)LM75_BufferTX, 2);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the slave address and enable writing operation */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the first address for r/w operations */
-  I2C_SendData(LM75_I2C, RegName);
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }  
-  
-  /* Wait until BTF Flag is set before generating STOP */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA TX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
-  
-  return LM75_OK;
-}
-
-/**
-  * @brief  Read Temperature register of LM75: double temperature value.
-  * @param  None
-  * @retval LM75 measured temperature value.
-  */
-uint16_t LM75_ReadTemp(void)
-{   
-  uint8_t LM75_BufferRX[2] ={0,0};
-  uint16_t tmp = 0;
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
-  
-  /* Enable DMA NACK automatic generation */
-  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send device address for write */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send the device's internal address to write to */
-  I2C_SendData(LM75_I2C, LM75_REG_TEMP);  
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send START condition a second time */  
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send LM75 address for read */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }        
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA RX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
-  
-  /*!< Store LM75_I2C received data */
-  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
-  tmp |= LM75_BufferRX[1];    
-  
-  /*!< Return Temperature value */
-  return (uint16_t)(tmp >> 7);
-}
-
-/**
-  * @brief  Read the configuration register from the LM75.
-  * @param  None
-  * @retval LM75 configuration register value.
-  */
-uint8_t LM75_ReadConfReg(void)
-{   
-  uint8_t LM75_BufferRX[2] ={0,0}; 
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
-  
-  /* Enable DMA NACK automatic generation */
-  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send device address for write */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send the device's internal address to write to */
-  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send START condition a second time */  
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send LM75 address for read */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }        
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA RX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
-  
-  /*!< Return Temperature value */
-  return (uint8_t)LM75_BufferRX[0];
-}
-
-/**
-  * @brief  Write to the configuration register of the LM75.
-  * @param  RegValue: sepecifies the value to be written to LM75 configuration 
-  *         register.
-  * @retval None
-  */
-uint8_t LM75_WriteConfReg(uint8_t RegValue)
-{   
-  uint8_t LM75_BufferTX = 0;  
-  LM75_BufferTX = (uint8_t)(RegValue);
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the slave address and enable writing operation */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the first address for r/w operations */
-  I2C_SendData(LM75_I2C, LM75_REG_CONF);
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }  
-  
-  /* Wait until BTF Flag is set before generating STOP */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA TX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
-  
-  return LM75_OK;
-  
-}
-
-/**
-  * @brief  Enables or disables the LM75.
-  * @param  NewState: specifies the LM75 new status. This parameter can be ENABLE
-  *         or DISABLE.  
-  * @retval None
-  */
-uint8_t LM75_ShutDown(FunctionalState NewState)
-{   
-  uint8_t LM75_BufferRX[2] ={0,0};
-  uint8_t LM75_BufferTX = 0;
-  __IO uint8_t RegValue = 0;    
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
-  
-  /* Enable DMA NACK automatic generation */
-  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send device address for write */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send the device's internal address to write to */
-  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send START condition a second time */  
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send LM75 address for read */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }        
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA RX Channel */
-  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA RX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
-  
-  /*!< Get received data */
-  RegValue = (uint8_t)LM75_BufferRX[0];
-  
-  /*---------------------------- Transmission Phase ---------------------------*/
-  
-  /*!< Enable or disable SD bit */
-  if (NewState != DISABLE)
-  {
-    /*!< Enable LM75 */
-    LM75_BufferTX = RegValue & LM75_SD_RESET;
-  }
-  else
-  {
-    /*!< Disable LM75 */
-    LM75_BufferTX = RegValue | LM75_SD_SET;
-  }  
-  
-  /* Test on BUSY Flag */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Configure DMA Peripheral */
-  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
-  
-  /* Enable the I2C peripheral */
-  I2C_GenerateSTART(LM75_I2C, ENABLE);
-  
-  /* Test on SB Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the slave address and enable writing operation */
-  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
-  
-  /* Test on ADDR Flag */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Transmit the first address for r/w operations */
-  I2C_SendData(LM75_I2C, LM75_REG_CONF);
-  
-  /* Test on TXE FLag (data sent) */
-  LM75_Timeout = LM75_FLAG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Enable I2C DMA request */
-  I2C_DMACmd(LM75_I2C,ENABLE);
-  
-  /* Enable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
-  
-  /* Wait until DMA Transfer Complete */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }  
-  
-  /* Wait until BTF Flag is set before generating STOP */
-  LM75_Timeout = LM75_LONG_TIMEOUT;
-  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
-  {
-    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
-  }
-  
-  /* Send STOP Condition */
-  I2C_GenerateSTOP(LM75_I2C, ENABLE);
-  
-  /* Disable DMA TX Channel */
-  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
-  
-  /* Disable I2C DMA request */  
-  I2C_DMACmd(LM75_I2C,DISABLE);
-  
-  /* Clear DMA TX Transfer Complete Flag */
-  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
-  
-  return LM75_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c
deleted file mode 100644
index 424d2d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c
+++ /dev/null
@@ -1,2502 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_sdio_sd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the SDIO SD 
-  *          Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this memory). 
-  *          
-  *            
-  *  @verbatim
-  *
-  *          ===================================================================
-  *                                   How to use this driver
-  *          ===================================================================
-  *          It implements a high level communication layer for read and write 
-  *          from/to this memory. The needed STM32 hardware resources (SDIO and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in SD_LowLevel_Init() function declared in stm32xx_eval.c 
-  *          file.
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          SD_LowLevel_Init() function.
-  *            
-  *          A - SD Card Initialization and configuration
-  *          ============================================    
-  *            - To initialize the SD Card, use the SD_Init() function.  It 
-  *              Initializes the SD Card and put it into StandBy State (Ready 
-  *              for data transfer). This function provide the following operations:
-  *           
-  *              1 - Apply the SD Card initialization process at 400KHz and check
-  *                  the SD Card type (Standard Capacity or High Capacity). You 
-  *                  can change or adapt this frequency by adjusting the 
-  *                  "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file. 
-  *                  The SD Card frequency (SDIO_CK) is computed as follows:
-  *                    
-  *                     +---------------------------------------------+    
-  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
-  *                     +---------------------------------------------+  
-  *                          
-  *                  In initialization mode and according to the SD Card standard, 
-  *                  make sure that the SDIO_CK frequency don't exceed 400KHz.        
-  *         
-  *              2 - Get the SD CID and CSD data. All these information are
-  *                  managed by the SDCardInfo structure. This structure provide
-  *                  also ready computed SD Card capacity and Block size.   
-  *
-  *              3 - Configure the SD Card Data transfer frequency. By Default,
-  *                  the card transfer frequency is set to 24MHz. You can change
-  *                  or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" 
-  *                  define inside the stm32xx_eval.h file.
-  *                  The SD Card frequency (SDIO_CK) is computed as follows:
-  *                    
-  *                     +---------------------------------------------+    
-  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
-  *                     +---------------------------------------------+     
-  *                                    
-  *                  In transfer mode and according to the SD Card standard, 
-  *                  make sure that the SDIO_CK frequency don't exceed 25MHz
-  *                  and 50MHz in High-speed mode switch.
-  *                  To be able to use a frequency higher than 24MHz, you should
-  *                  use the SDIO peripheral in bypass mode. Refer to the 
-  *                  corresponding reference manual for more details.
-  *                    
-  *              4 -  Select the corresponding SD Card according to the address
-  *                   read with the step 2.
-  *                                   
-  *              5 -  Configure the SD Card in wide bus mode: 4-bits data.                
-  *
-  *          B - SD Card Read operation
-  *          ========================== 
-  *           - You can read SD card by using two function: SD_ReadBlock() and
-  *             SD_ReadMultiBlocks() functions. These functions support only
-  *             512-byte block length.
-  *           - The SD_ReadBlock() function read only one block (512-byte). This
-  *             function can transfer the data using DMA controller or using 
-  *             polling mode. To select between DMA or polling mode refer to 
-  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
-  *             file and uncomment the corresponding line. By default the SD DMA
-  *             mode is selected          
-  *           - The SD_ReadMultiBlocks() function read only mutli blocks (multiple 
-  *             of 512-byte). 
-  *           - Any read operation should be followed by two functions to check
-  *             if the DMA Controller and SD Card status.
-  *              - SD_ReadWaitOperation(): this function insure that the DMA
-  *                controller has finished all data transfer.
-  *              - SD_GetStatus(): to check that the SD Card has finished the 
-  *                data transfer and it is ready for data.
-  *                  
-  *           - The DMA transfer is finished by the SDIO Data End interrupt. User
-  *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
-  *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.      
-  *                
-  *          C - SD Card Write operation
-  *          =========================== 
-  *           - You can write SD card by using two function: SD_WriteBlock() and
-  *             SD_WriteMultiBlocks() functions. These functions support only
-  *             512-byte block length.   
-  *           - The SD_WriteBlock() function write only one block (512-byte). This
-  *             function can transfer the data using DMA controller or using 
-  *             polling mode. To select between DMA or polling mode refer to 
-  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
-  *             file and uncomment the corresponding line. By default the SD DMA
-  *             mode is selected          
-  *           - The SD_WriteMultiBlocks() function write only mutli blocks (multiple 
-  *             of 512-byte). 
-  *           - Any write operation should be followed by two functions to check
-  *             if the DMA Controller and SD Card status.
-  *              - SD_ReadWaitOperation(): this function insure that the DMA
-  *                controller has finished all data transfer.
-  *              - SD_GetStatus(): to check that the SD Card has finished the 
-  *                data transfer and it is ready for data.         
-  *                
-  *           - The DMA transfer is finished by the SDIO Data End interrupt. User
-  *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
-  *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.      
-               
-  *             
-  *          D - SD card status
-  *          ================== 
-  *           - At any time, you can check the SD Card status and get the SD card
-  *             state by using the SD_GetStatus() function. This function checks
-  *             first if the SD card is still connected and then get the internal
-  *             SD Card transfer state.     
-  *           - You can also get the SD card SD Status register by using the 
-  *             SD_SendSDStatus() function.       
-  *               
-  *          E - Programming Model
-  *          ===================== 
-  *             Status = SD_Init(); // Initialization Step as described in section A
-  *               
-  *             // SDIO Interrupt ENABLE
-  *             NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
-  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  *             NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  *             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  *             NVIC_Init(&NVIC_InitStructure);
-  *             
-  *             // Write operation as described in Section C
-  *             Status = SD_WriteBlock(buffer, address, 512);
-  *             Status = SD_WaitWriteOperation();
-  *             while(SD_GetStatus() != SD_TRANSFER_OK); 
-  *             
-  *             Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
-  *             Status = SD_WaitWriteOperation();
-  *             while(SD_GetStatus() != SD_TRANSFER_OK);     
-  *             
-  *             // Read operation as described in Section B
-  *             Status = SD_ReadBlock(buffer, address, 512);
-  *             Status = SD_WaitReadOperation();
-  *             while(SD_GetStatus() != SD_TRANSFER_OK);
-  *             
-  *             Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
-  *             Status = SD_WaitReadOperation();
-  *             while(SD_GetStatus() != SD_TRANSFER_OK);            
-  *               
-  *                                     
-  *          STM32 SDIO Pin assignment
-  *          =========================    
-  *          +-----------------------------------------------------------+
-  *          |                     Pin assignment                        |
-  *          +-----------------------------+---------------+-------------+
-  *          |  STM32 SDIO Pins            |     SD        |    Pin      |
-  *          +-----------------------------+---------------+-------------+
-  *          |      SDIO D2                |   D2          |    1        |
-  *          |      SDIO D3                |   D3          |    2        |
-  *          |      SDIO CMD               |   CMD         |    3        |
-  *          |                             |   VCC         |    4 (3.3 V)|
-  *          |      SDIO CLK               |   CLK         |    5        |
-  *          |                             |   GND         |    6 (0 V)  |
-  *          |      SDIO D0                |   D0          |    7        |
-  *          |      SDIO D1                |   D1          |    8        |  
-  *          +-----------------------------+---------------+-------------+  
-  *              
-  *  @endverbatim                
-  *             
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_sdio_sd.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SDIO_SD
-  * @brief      This file provides all the SD Card driver firmware functions.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Defines
-  * @{
-  */ 
-/** 
-  * @brief  SDIO Static flags, TimeOut, FIFO Address  
-  */
-#define NULL 0
-#define SDIO_STATIC_FLAGS               ((uint32_t)0x000005FF)
-#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
-
-/** 
-  * @brief  Mask for errors Card Status R1 (OCR Register) 
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO                      ((uint32_t)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Command Class Supported 
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SDIO_SEND_IF_COND               ((uint32_t)0x00000008)
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Variables
-  * @{
-  */
-static uint32_t CardType =  SDIO_STD_CAPACITY_SD_CARD_V1_1;
-static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0;
-static uint8_t SDSTATUS_Tab[16];
-__IO uint32_t StopCondition = 0;
-__IO SD_Error TransferError = SD_OK;
-__IO uint32_t TransferEnd = 0;
-SD_CardInfo SDCardInfo;
-
-SDIO_InitTypeDef SDIO_InitStructure;
-SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
-SDIO_DataInitTypeDef SDIO_DataInitStructure;   
-/**
-  * @}			     
-  */ 
-
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Function_Prototypes
-  * @{
-  */
-static SD_Error CmdError(void);
-static SD_Error CmdResp1Error(uint8_t cmd);
-static SD_Error CmdResp7Error(void);
-static SD_Error CmdResp3Error(void);
-static SD_Error CmdResp2Error(void);
-static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca);
-static SD_Error SDEnWideBus(FunctionalState NewState);
-static SD_Error IsCardProgramming(uint8_t *pstatus);
-static SD_Error FindSCR(uint16_t rca, uint32_t *pscr);
-uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes);
-  
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SDIO_SD_Private_Functions
-  * @{
-  */  
-
-/**
-  * @brief  DeInitializes the SDIO interface.
-  * @param  None
-  * @retval None
-  */
-void SD_DeInit(void)
-{ 
-  SD_LowLevel_DeInit();
-}
-
-/**
-  * @brief  Initializes the SD Card and put it into StandBy State (Ready for data 
-  *         transfer).
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_Init(void)
-{
-  SD_Error errorstatus = SD_OK;
-  
-  /* SDIO Peripheral Low Level Init */
-  SD_LowLevel_Init();
-
-  SDIO_DeInit();
-
-  errorstatus = SD_PowerON();
-
-  if (errorstatus != SD_OK)
-  {
-    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
-    return(errorstatus);
-  }
-
-  errorstatus = SD_InitializeCards();
-
-  if (errorstatus != SD_OK)
-  {
-    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
-    return(errorstatus);
-  }
-
-  /*!< Configure the SDIO peripheral */
-  /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */
-  /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */  
-  SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
-  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
-  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
-  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
-  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
-  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-  SDIO_Init(&SDIO_InitStructure);
-  
-  if (errorstatus == SD_OK)
-  {
-    /*----------------- Read CSD/CID MSD registers ------------------*/
-    errorstatus = SD_GetCardInfo(&SDCardInfo);
-  }
-
-  if (errorstatus == SD_OK)
-  {
-    /*----------------- Select Card --------------------------------*/
-    errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16));
-  }
-
-  if (errorstatus == SD_OK)
-  {
-    errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b);
-  }  
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Gets the cuurent sd card data transfer status.
-  * @param  None
-  * @retval SDTransferState: Data Transfer state.
-  *   This value can be: 
-  *        - SD_TRANSFER_OK: No data transfer is acting
-  *        - SD_TRANSFER_BUSY: Data transfer is acting
-  */
-SDTransferState SD_GetStatus(void)
-{
-  SDCardState cardstate =  SD_CARD_TRANSFER;
-
-  cardstate = SD_GetState();
-  
-  if (cardstate == SD_CARD_TRANSFER)
-  {
-    return(SD_TRANSFER_OK);
-  }
-  else if(cardstate == SD_CARD_ERROR)
-  {
-    return (SD_TRANSFER_ERROR);
-  }
-  else
-  {
-    return(SD_TRANSFER_BUSY);
-  }
-}
-
-/**
-  * @brief  Returns the current card's state.
-  * @param  None
-  * @retval SDCardState: SD Card Error or SD Card Current State.
-  */
-SDCardState SD_GetState(void)
-{
-  uint32_t resp1 = 0;
-  
-  if(SD_Detect()== SD_PRESENT)
-  {
-    if (SD_SendStatus(&resp1) != SD_OK)
-    {
-      return SD_CARD_ERROR;
-    }
-    else
-    {
-      return (SDCardState)((resp1 >> 9) & 0x0F);
-    }
-  }
-  else
-  {
-    return SD_CARD_ERROR;
-  }
-}
-
-/**
- * @brief  Detect if SD card is correctly plugged in the memory slot.
- * @param  None
- * @retval Return if SD is detected or not
- */
-uint8_t SD_Detect(void)
-{
-  __IO uint8_t status = SD_PRESENT;
-
-  /*!< Check GPIO to detect SD */
-  if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET)
-  {
-    status = SD_NOT_PRESENT;
-  }
-  return status;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures 
-  *   clock controls.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_PowerON(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t response = 0, count = 0, validvoltage = 0;
-  uint32_t SDType = SD_STD_CAPACITY;
-
-  /*!< Power ON Sequence -----------------------------------------------------*/
-  /*!< Configure the SDIO peripheral */
-  /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV) */
-  /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */
-  /*!< SDIO_CK for initialization should not exceed 400 KHz */  
-  SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV;
-  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
-  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
-  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
-  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
-  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-  SDIO_Init(&SDIO_InitStructure);
-
-  /*!< Set Power State to ON */
-  SDIO_SetPowerState(SDIO_PowerState_ON);
-
-  /*!< Enable SDIO Clock */
-  SDIO_ClockCmd(ENABLE);
-
-  /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/
-  /*!< No CMD response required */
-  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdError();
-
-  if (errorstatus != SD_OK)
-  {
-    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
-    return(errorstatus);
-  }
-
-  /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/
-  /*!< Send CMD8 to verify SD card interface operating condition */
-  /*!< Argument: - [31:12]: Reserved (shall be set to '0')
-               - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-               - [7:0]: Check Pattern (recommended 0xAA) */
-  /*!< CMD Response: R7 */
-  SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp7Error();
-
-  if (errorstatus == SD_OK)
-  {
-    CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */
-    SDType = SD_HIGH_CAPACITY;
-  }
-  else
-  {
-    /*!< CMD55 */
-    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-    errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-  }
-  /*!< CMD55 */
-  SDIO_CmdInitStructure.SDIO_Argument = 0x00;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-  /*!< If errorstatus is Command TimeOut, it is a MMC card */
-  /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if (errorstatus == SD_OK)
-  {
-    /*!< SD CARD */
-    /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-
-      /*!< SEND CMD55 APP_CMD with RCA as 0 */
-      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-      SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-      errorstatus = CmdResp3Error();
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-
-      response = SDIO_GetResponse(SDIO_RESP1);
-      validvoltage = (((response >> 31) == 1) ? 1 : 0);
-      count++;
-    }
-    if (count >= SD_MAX_VOLT_TRIAL)
-    {
-      errorstatus = SD_INVALID_VOLTRANGE;
-      return(errorstatus);
-    }
-
-    if (response &= SD_HIGH_CAPACITY)
-    {
-      CardType = SDIO_HIGH_CAPACITY_SD_CARD;
-    }
-
-  }/*!< else MMC Card */
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Turns the SDIO output signals off.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_PowerOFF(void)
-{
-  SD_Error errorstatus = SD_OK;
-
-  /*!< Set Power State to OFF */
-  SDIO_SetPowerState(SDIO_PowerState_OFF);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Intialises all cards or single card as the case may be Card(s) come 
-  *         into standby state.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_InitializeCards(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint16_t rca = 0x01;
-
-  if (SDIO_GetPowerState() == SDIO_PowerState_OFF)
-  {
-    errorstatus = SD_REQUEST_NOT_APPLICABLE;
-    return(errorstatus);
-  }
-
-  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
-  {
-    /*!< Send CMD2 ALL_SEND_CID */
-    SDIO_CmdInitStructure.SDIO_Argument = 0x0;
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-    errorstatus = CmdResp2Error();
-
-    if (SD_OK != errorstatus)
-    {
-      return(errorstatus);
-    }
-
-    CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
-    CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
-    CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
-    CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) ||  (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) ||  (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType)
-      ||  (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
-  {
-    /*!< Send CMD3 SET_REL_ADDR with argument 0 */
-    /*!< SD Card publishes its RCA. */
-    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-    errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca);
-
-    if (SD_OK != errorstatus)
-    {
-      return(errorstatus);
-    }
-  }
-
-  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
-  {
-    RCA = rca;
-
-    /*!< Send CMD9 SEND_CSD with argument as card's RCA */
-    SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16);
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-    errorstatus = CmdResp2Error();
-
-    if (SD_OK != errorstatus)
-    {
-      return(errorstatus);
-    }
-
-    CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
-    CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
-    CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
-    CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
-  }
-
-  errorstatus = SD_OK; /*!< All cards get intialized */
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD card 
-  *         information.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
-{
-  SD_Error errorstatus = SD_OK;
-  uint8_t tmp = 0;
-
-  cardinfo->CardType = (uint8_t)CardType;
-  cardinfo->RCA = (uint16_t)RCA;
-
-  /*!< Byte 0 */
-  tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24);
-  cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6;
-  cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2;
-  cardinfo->SD_csd.Reserved1 = tmp & 0x03;
-
-  /*!< Byte 1 */
-  tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16);
-  cardinfo->SD_csd.TAAC = tmp;
-
-  /*!< Byte 2 */
-  tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8);
-  cardinfo->SD_csd.NSAC = tmp;
-
-  /*!< Byte 3 */
-  tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF);
-  cardinfo->SD_csd.MaxBusClkFrec = tmp;
-
-  /*!< Byte 4 */
-  tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24);
-  cardinfo->SD_csd.CardComdClasses = tmp << 4;
-
-  /*!< Byte 5 */
-  tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);
-  cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4;
-  cardinfo->SD_csd.RdBlockLen = tmp & 0x0F;
-
-  /*!< Byte 6 */
-  tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);
-  cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7;
-  cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6;
-  cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5;
-  cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4;
-  cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */
-
-  if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0))
-  {
-    cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
-
-    /*!< Byte 7 */
-    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
-    cardinfo->SD_csd.DeviceSize |= (tmp) << 2;
-
-    /*!< Byte 8 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
-    cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
-
-    cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
-    cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
-
-    /*!< Byte 9 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
-    cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
-    cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
-    cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
-    /*!< Byte 10 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
-    cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
-    
-    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
-    cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
-    cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
-    cardinfo->CardCapacity *= cardinfo->CardBlockSize;
-  }
-  else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    /*!< Byte 7 */
-    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
-    cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
-
-    /*!< Byte 8 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
-
-    cardinfo->SD_csd.DeviceSize |= (tmp << 8);
-
-    /*!< Byte 9 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
-
-    cardinfo->SD_csd.DeviceSize |= (tmp);
-
-    /*!< Byte 10 */
-    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
-    
-    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024;
-    cardinfo->CardBlockSize = 512;    
-  }
-
-
-  cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
-  cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
-
-  /*!< Byte 11 */
-  tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF);
-  cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
-  cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
-
-  /*!< Byte 12 */
-  tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24);
-  cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
-  cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
-  cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
-  cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
-
-  /*!< Byte 13 */
-  tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16);
-  cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
-  cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
-  cardinfo->SD_csd.Reserved3 = 0;
-  cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-
-  /*!< Byte 14 */
-  tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8);
-  cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
-  cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
-  cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
-  cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
-  cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
-  cardinfo->SD_csd.ECC = (tmp & 0x03);
-
-  /*!< Byte 15 */
-  tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF);
-  cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
-  cardinfo->SD_csd.Reserved4 = 1;
-
-
-  /*!< Byte 0 */
-  tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24);
-  cardinfo->SD_cid.ManufacturerID = tmp;
-
-  /*!< Byte 1 */
-  tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16);
-  cardinfo->SD_cid.OEM_AppliID = tmp << 8;
-
-  /*!< Byte 2 */
-  tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8);
-  cardinfo->SD_cid.OEM_AppliID |= tmp;
-
-  /*!< Byte 3 */
-  tmp = (uint8_t)(CID_Tab[0] & 0x000000FF);
-  cardinfo->SD_cid.ProdName1 = tmp << 24;
-
-  /*!< Byte 4 */
-  tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24);
-  cardinfo->SD_cid.ProdName1 |= tmp << 16;
-
-  /*!< Byte 5 */
-  tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16);
-  cardinfo->SD_cid.ProdName1 |= tmp << 8;
-
-  /*!< Byte 6 */
-  tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8);
-  cardinfo->SD_cid.ProdName1 |= tmp;
-
-  /*!< Byte 7 */
-  tmp = (uint8_t)(CID_Tab[1] & 0x000000FF);
-  cardinfo->SD_cid.ProdName2 = tmp;
-
-  /*!< Byte 8 */
-  tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24);
-  cardinfo->SD_cid.ProdRev = tmp;
-
-  /*!< Byte 9 */
-  tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16);
-  cardinfo->SD_cid.ProdSN = tmp << 24;
-
-  /*!< Byte 10 */
-  tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8);
-  cardinfo->SD_cid.ProdSN |= tmp << 16;
-
-  /*!< Byte 11 */
-  tmp = (uint8_t)(CID_Tab[2] & 0x000000FF);
-  cardinfo->SD_cid.ProdSN |= tmp << 8;
-
-  /*!< Byte 12 */
-  tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24);
-  cardinfo->SD_cid.ProdSN |= tmp;
-
-  /*!< Byte 13 */
-  tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16);
-  cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
-  cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-
-  /*!< Byte 14 */
-  tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8);
-  cardinfo->SD_cid.ManufactDate |= tmp;
-
-  /*!< Byte 15 */
-  tmp = (uint8_t)(CID_Tab[3] & 0x000000FF);
-  cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
-  cardinfo->SD_cid.Reserved2 = 1;
-  
-  return(errorstatus);
-}
-
-/**
-  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
-  *         card.
-  * @param  WideMode: Specifies the SD card wide bus mode. 
-  *   This parameter can be one of the following values:
-  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
-  *     @arg SDIO_BusWide_4b: 4-bit data transfer
-  *     @arg SDIO_BusWide_1b: 1-bit data transfer
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus)
-{
-  SD_Error errorstatus = SD_OK;
-  uint8_t tmp = 0;
-
-  errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab);
-
-  if (errorstatus  != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  /*!< Byte 0 */
-  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6);
-  cardstatus->DAT_BUS_WIDTH = tmp;
-
-  /*!< Byte 0 */
-  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5);
-  cardstatus->SECURED_MODE = tmp;
-
-  /*!< Byte 2 */
-  tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF));
-  cardstatus->SD_CARD_TYPE = tmp << 8;
-
-  /*!< Byte 3 */
-  tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF));
-  cardstatus->SD_CARD_TYPE |= tmp;
-
-  /*!< Byte 4 */
-  tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF);
-  cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24;
-
-  /*!< Byte 5 */
-  tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF);
-  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16;
-
-  /*!< Byte 6 */
-  tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF);
-  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8;
-
-  /*!< Byte 7 */
-  tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF);
-  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp;
-
-  /*!< Byte 8 */
-  tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF));
-  cardstatus->SPEED_CLASS = tmp;
-
-  /*!< Byte 9 */
-  tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF));
-  cardstatus->PERFORMANCE_MOVE = tmp;
-
-  /*!< Byte 10 */
-  tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4);
-  cardstatus->AU_SIZE = tmp;
-
-  /*!< Byte 11 */
-  tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF);
-  cardstatus->ERASE_SIZE = tmp << 8;
-
-  /*!< Byte 12 */
-  tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF);
-  cardstatus->ERASE_SIZE |= tmp;
-
-  /*!< Byte 13 */
-  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2);
-  cardstatus->ERASE_TIMEOUT = tmp;
-
-  /*!< Byte 13 */
-  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3));
-  cardstatus->ERASE_OFFSET = tmp;
- 
-  return(errorstatus);
-}
-
-/**
-  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
-  *         card.
-  * @param  WideMode: Specifies the SD card wide bus mode. 
-  *   This parameter can be one of the following values:
-  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
-  *     @arg SDIO_BusWide_4b: 4-bit data transfer
-  *     @arg SDIO_BusWide_1b: 1-bit data transfer
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_EnableWideBusOperation(uint32_t WideMode)
-{
-  SD_Error errorstatus = SD_OK;
-
-  /*!< MMC Card doesn't support this feature */
-  if (SDIO_MULTIMEDIA_CARD == CardType)
-  {
-    errorstatus = SD_UNSUPPORTED_FEATURE;
-    return(errorstatus);
-  }
-  else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
-  {
-    if (SDIO_BusWide_8b == WideMode)
-    {
-      errorstatus = SD_UNSUPPORTED_FEATURE;
-      return(errorstatus);
-    }
-    else if (SDIO_BusWide_4b == WideMode)
-    {
-      errorstatus = SDEnWideBus(ENABLE);
-
-      if (SD_OK == errorstatus)
-      {
-        /*!< Configure the SDIO peripheral */
-        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
-        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
-        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
-        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
-        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
-        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-        SDIO_Init(&SDIO_InitStructure);
-      }
-    }
-    else
-    {
-      errorstatus = SDEnWideBus(DISABLE);
-
-      if (SD_OK == errorstatus)
-      {
-        /*!< Configure the SDIO peripheral */
-        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
-        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
-        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
-        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
-        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
-        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
-        SDIO_Init(&SDIO_InitStructure);
-      }
-    }
-  }
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Selects od Deselects the corresponding card.
-  * @param  addr: Address of the Card to be selected.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_SelectDeselect(uint32_t addr)
-{
-  SD_Error errorstatus = SD_OK;
-
-  /*!< Send CMD7 SDIO_SEL_DESEL_CARD */
-  SDIO_CmdInitStructure.SDIO_Argument =  addr;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to read one block from a specified address in a card. The Data
-  *         transfer can be managed by DMA mode or Polling mode. 
-  * @note   This operation should be followed by two functions to check if the 
-  *         DMA Controller and SD Card status.
-  *          - SD_ReadWaitOperation(): this function insure that the DMA
-  *            controller has finished all data transfer.
-  *          - SD_GetStatus(): to check that the SD Card has finished the 
-  *            data transfer and it is ready for data.            
-  * @param  readbuff: pointer to the buffer that will contain the received data
-  * @param  ReadAddr: Address from where data are to be read.  
-  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
-{
-  SD_Error errorstatus = SD_OK;
-#if defined (SD_POLLING_MODE) 
-  uint32_t count = 0, *tempbuff = (uint32_t *)readbuff;
-#endif
-
-  TransferError = SD_OK;
-  TransferEnd = 0;
-  StopCondition = 0;
-  
-  SDIO->DCTRL = 0x0;
-
-  
-  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-  /*!< Send CMD17 READ_SINGLE_BLOCK */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-#if defined (SD_POLLING_MODE)  
-  /*!< In case of single block transfer, no need of stop transfer at all.*/
-  /*!< Polling mode */
-  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
-  {
-    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
-    {
-      for (count = 0; count < 8; count++)
-      {
-        *(tempbuff + count) = SDIO_ReadData();
-      }
-      tempbuff += 8;
-    }
-  }
-
-  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
-    errorstatus = SD_DATA_TIMEOUT;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
-    errorstatus = SD_DATA_CRC_FAIL;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
-    errorstatus = SD_RX_OVERRUN;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
-    errorstatus = SD_START_BIT_ERR;
-    return(errorstatus);
-  }
-  while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
-  {
-    *tempbuff = SDIO_ReadData();
-    tempbuff++;
-  }
-  
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-#elif defined (SD_DMA_MODE)
-    SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
-    SDIO_DMACmd(ENABLE);
-    SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize);
-#endif
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to read blocks from a specified address  in a card.  The Data
-  *         transfer can be managed by DMA mode or Polling mode. 
-  * @note   This operation should be followed by two functions to check if the 
-  *         DMA Controller and SD Card status.
-  *          - SD_ReadWaitOperation(): this function insure that the DMA
-  *            controller has finished all data transfer.
-  *          - SD_GetStatus(): to check that the SD Card has finished the 
-  *            data transfer and it is ready for data.   
-  * @param  readbuff: pointer to the buffer that will contain the received data.
-  * @param  ReadAddr: Address from where data are to be read.
-  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
-  * @param  NumberOfBlocks: number of blocks to be read.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SD_Error errorstatus = SD_OK;
-  TransferError = SD_OK;
-  TransferEnd = 0;
-  StopCondition = 1;
-	
-  SDIO->DCTRL = 0x0;
-
-  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-
-  /*!< Set Block Size for Card */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
-
-  if (SD_OK != errorstatus)
-  {
-    return(errorstatus);
-  }
-    
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-  /*!< Send CMD18 READ_MULT_BLOCK with argument data address */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
-  SDIO_DMACmd(ENABLE);
-  SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize));
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  This function waits until the SDIO DMA data transfer is finished. 
-  *         This function should be called after SDIO_ReadMultiBlocks() function
-  *         to insure that all data sent by the card are already transferred by 
-  *         the DMA controller.        
-  * @param  None.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_WaitReadOperation(void)
-{
-  SD_Error errorstatus = SD_OK;
-
-  while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK))
-  {}
-
-  if (TransferError != SD_OK)
-  {
-    return(TransferError);
-  }
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to write one block starting from a specified address in a card.
-  *         The Data transfer can be managed by DMA mode or Polling mode.
-  * @note   This operation should be followed by two functions to check if the 
-  *         DMA Controller and SD Card status.
-  *          - SD_ReadWaitOperation(): this function insure that the DMA
-  *            controller has finished all data transfer.
-  *          - SD_GetStatus(): to check that the SD Card has finished the 
-  *            data transfer and it is ready for data.      
-  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
-  * @param  WriteAddr: Address from where data are to be read.   
-  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
-{
-  SD_Error errorstatus = SD_OK;
-
-#if defined (SD_POLLING_MODE)
-  uint32_t bytestransferred = 0, count = 0, restwords = 0;
-  uint32_t *tempbuff = (uint32_t *)writebuff;
-#endif
-
-  TransferError = SD_OK;
-  TransferEnd = 0;
-  StopCondition = 0;
-  
-  SDIO->DCTRL = 0x0;
-
-
-  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
-  
-  /*!< Send CMD24 WRITE_SINGLE_BLOCK */
-  SDIO_CmdInitStructure.SDIO_Argument = WriteAddr;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-  /*!< In case of single data block transfer no need of stop command at all */
-#if defined (SD_POLLING_MODE) 
-  while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR)))
-  {
-    if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET)
-    {
-      if ((512 - bytestransferred) < 32)
-      {
-        restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 -  bytestransferred) / 4 + 1);
-        for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4)
-        {
-          SDIO_WriteData(*tempbuff);
-        }
-      }
-      else
-      {
-        for (count = 0; count < 8; count++)
-        {
-          SDIO_WriteData(*(tempbuff + count));
-        }
-        tempbuff += 8;
-        bytestransferred += 32;
-      }
-    }
-  }
-  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
-    errorstatus = SD_DATA_TIMEOUT;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
-    errorstatus = SD_DATA_CRC_FAIL;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_TXUNDERR);
-    errorstatus = SD_TX_UNDERRUN;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
-    errorstatus = SD_START_BIT_ERR;
-    return(errorstatus);
-  }
-#elif defined (SD_DMA_MODE)
-  SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
-  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize);
-  SDIO_DMACmd(ENABLE);
-#endif
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to write blocks starting from a specified address in a card.
-  *         The Data transfer can be managed by DMA mode only. 
-  * @note   This operation should be followed by two functions to check if the 
-  *         DMA Controller and SD Card status.
-  *          - SD_ReadWaitOperation(): this function insure that the DMA
-  *            controller has finished all data transfer.
-  *          - SD_GetStatus(): to check that the SD Card has finished the 
-  *            data transfer and it is ready for data.     
-  * @param  WriteAddr: Address from where data are to be read.
-  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
-  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
-  * @param  NumberOfBlocks: number of blocks to be written.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SD_Error errorstatus = SD_OK;
-  __IO uint32_t count = 0;
-
-  TransferError = SD_OK;
-  TransferEnd = 0;
-  StopCondition = 1;
-  
-  SDIO->DCTRL = 0x0;
-
-  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
-
-  /*!< To improve performance */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16);
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-
-  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-  /*!< To improve performance */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-
-  /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK);
-
-  if (SD_OK != errorstatus)
-  {
-    return(errorstatus);
-  }
-
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-  SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
-  SDIO_DMACmd(ENABLE);    
-  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize));
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  This function waits until the SDIO DMA data transfer is finished. 
-  *         This function should be called after SDIO_WriteBlock() and
-  *         SDIO_WriteMultiBlocks() function to insure that all data sent by the 
-  *         card are already transferred by the DMA controller.        
-  * @param  None.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_WaitWriteOperation(void)
-{
-  SD_Error errorstatus = SD_OK;
-
-  while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK))
-  {}
-
-  if (TransferError != SD_OK)
-  {
-    return(TransferError);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Gets the cuurent data transfer state.
-  * @param  None
-  * @retval SDTransferState: Data Transfer state.
-  *   This value can be: 
-  *        - SD_TRANSFER_OK: No data transfer is acting
-  *        - SD_TRANSFER_BUSY: Data transfer is acting
-  */
-SDTransferState SD_GetTransferState(void)
-{
-  if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT))
-  {
-    return(SD_TRANSFER_BUSY);
-  }
-  else
-  {
-    return(SD_TRANSFER_OK);
-  }
-}
-
-/**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_StopTransfer(void)
-{
-  SD_Error errorstatus = SD_OK;
-
-  /*!< Send CMD12 STOP_TRANSMISSION  */
-  SDIO->ARG = 0x0;
-  SDIO->CMD = 0x44C;
-  errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to erase memory area specified for the given card.
-  * @param  startaddr: the start address.
-  * @param  endaddr: the end address.
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t delay = 0;
-  __IO uint32_t maxdelay = 0;
-  uint8_t cardstate = 0;
-
-  /*!< Check if the card coomnd class supports erase command */
-  if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0)
-  {
-    errorstatus = SD_REQUEST_NOT_APPLICABLE;
-    return(errorstatus);
-  }
-
-  maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2);
-
-  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
-  {
-    errorstatus = SD_LOCK_UNLOCK_FAILED;
-    return(errorstatus);
-  }
-
-  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512;
-    endaddr /= 512;
-  }
-  
-  /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
-  {
-    /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    SDIO_CmdInitStructure.SDIO_Argument = startaddr;
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START);
-    if (errorstatus != SD_OK)
-    {
-      return(errorstatus);
-    }
-
-    /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    SDIO_CmdInitStructure.SDIO_Argument = endaddr;
-    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END;
-    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-    SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END);
-    if (errorstatus != SD_OK)
-    {
-      return(errorstatus);
-    }
-  }
-
-  /*!< Send CMD38 ERASE */
-  SDIO_CmdInitStructure.SDIO_Argument = 0;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_ERASE);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  for (delay = 0; delay < maxdelay; delay++)
-  {}
-
-  /*!< Wait till the card is in programming state */
-  errorstatus = IsCardProgramming(&cardstate);
-
-  while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate)))
-  {
-    errorstatus = IsCardProgramming(&cardstate);
-  }
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  pcardstatus: pointer to the buffer that will contain the SD card 
-  *         status (Card Status register).
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_SendStatus(uint32_t *pcardstatus)
-{
-  SD_Error errorstatus = SD_OK;
-
-  SDIO->ARG = (uint32_t) RCA << 16;
-  SDIO->CMD = 0x44D;
-  
-  errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  *pcardstatus = SDIO->RESP1;
-  return(errorstatus);
-}
-
-/**
-  * @brief  Returns the current SD card's status.
-  * @param  psdstatus: pointer to the buffer that will contain the SD card status 
-  *         (SD Status register).
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_SendSDStatus(uint32_t *psdstatus)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t count = 0;
-
-  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
-  {
-    errorstatus = SD_LOCK_UNLOCK_FAILED;
-    return(errorstatus);
-  }
-
-  /*!< Set block size for card if it is not equal to current block size for card. */
-  SDIO_CmdInitStructure.SDIO_Argument = 64;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  /*!< CMD55 */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = 64;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-  /*!< Send ACMD13 SD_APP_STAUS  with argument as card's RCA.*/
-  SDIO_CmdInitStructure.SDIO_Argument = 0;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-  errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
-  {
-    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
-    {
-      for (count = 0; count < 8; count++)
-      {
-        *(psdstatus + count) = SDIO_ReadData();
-      }
-      psdstatus += 8;
-    }
-  }
-
-  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
-    errorstatus = SD_DATA_TIMEOUT;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
-    errorstatus = SD_DATA_CRC_FAIL;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
-    errorstatus = SD_RX_OVERRUN;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
-    errorstatus = SD_START_BIT_ERR;
-    return(errorstatus);
-  }
-
-  while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
-  {
-    *psdstatus = SDIO_ReadData();
-    psdstatus++;
-  }
-
-  /*!< Clear all the static status flags*/
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Allows to process all the interrupts that are high.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-SD_Error SD_ProcessIRQSrc(void)
-{
-  if (StopCondition == 1)
-  {
-    SDIO->ARG = 0x0;
-    SDIO->CMD = 0x44C;
-    TransferError = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
-  }
-  else
-  {
-    TransferError = SD_OK;
-  }
-  SDIO_ClearITPendingBit(SDIO_IT_DATAEND);
-  SDIO_ITConfig(SDIO_IT_DATAEND, DISABLE);
-  TransferEnd = 1;
-  return(TransferError);
-}
-
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdError(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t timeout;
-
-  timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */
-
-  while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET))
-  {
-    timeout--;
-  }
-
-  if (timeout == 0)
-  {
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    return(errorstatus);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdResp7Error(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t status;
-  uint32_t timeout = SDIO_CMD0TIMEOUT;
-
-  status = SDIO->STA;
-
-  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0))
-  {
-    timeout--;
-    status = SDIO->STA;
-  }
-
-  if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT))
-  {
-    /*!< Card is not V2.0 complient or card does not support the set voltage range */
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
-    return(errorstatus);
-  }
-
-  if (status & SDIO_FLAG_CMDREND)
-  {
-    /*!< Card is SD V2.0 compliant */
-    errorstatus = SD_OK;
-    SDIO_ClearFlag(SDIO_FLAG_CMDREND);
-    return(errorstatus);
-  }
-  return(errorstatus);
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  cmd: The sent command index.
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdResp1Error(uint8_t cmd)
-{
-  while (!(SDIO->STA & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
-  {
-  }
-
-  SDIO->ICR = SDIO_STATIC_FLAGS;
-
-  return (SD_Error)(SDIO->RESP1 &  SD_OCR_ERRORBITS);
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdResp3Error(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t status;
-
-  status = SDIO->STA;
-
-  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
-  {
-    status = SDIO->STA;
-  }
-
-  if (status & SDIO_FLAG_CTIMEOUT)
-  {
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
-    return(errorstatus);
-  }
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-  return(errorstatus);
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  None
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdResp2Error(void)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t status;
-
-  status = SDIO->STA;
-
-  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
-  {
-    status = SDIO->STA;
-  }
-
-  if (status & SDIO_FLAG_CTIMEOUT)
-  {
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
-    return(errorstatus);
-  }
-  else if (status & SDIO_FLAG_CCRCFAIL)
-  {
-    errorstatus = SD_CMD_CRC_FAIL;
-    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
-    return(errorstatus);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  cmd: The sent command index.
-  * @param  prca: pointer to the variable that will contain the SD card relative 
-  *         address RCA. 
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca)
-{
-  SD_Error errorstatus = SD_OK;
-  uint32_t status;
-  uint32_t response_r1;
-
-  status = SDIO->STA;
-
-  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
-  {
-    status = SDIO->STA;
-  }
-
-  if (status & SDIO_FLAG_CTIMEOUT)
-  {
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
-    return(errorstatus);
-  }
-  else if (status & SDIO_FLAG_CCRCFAIL)
-  {
-    errorstatus = SD_CMD_CRC_FAIL;
-    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
-    return(errorstatus);
-  }
-
-  /*!< Check response received is of desired command */
-  if (SDIO_GetCommandResponse() != cmd)
-  {
-    errorstatus = SD_ILLEGAL_CMD;
-    return(errorstatus);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  /*!< We have received response, retrieve it.  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-
-  if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)))
-  {
-    *prca = (uint16_t) (response_r1 >> 16);
-    return(errorstatus);
-  }
-
-  if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-
-  if (response_r1 & SD_R6_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-
-  if (response_r1 & SD_R6_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Enables or disables the SDIO wide bus mode.
-  * @param  NewState: new state of the SDIO wide bus mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error SDEnWideBus(FunctionalState NewState)
-{
-  SD_Error errorstatus = SD_OK;
-
-  uint32_t scr[2] = {0, 0};
-
-  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
-  {
-    errorstatus = SD_LOCK_UNLOCK_FAILED;
-    return(errorstatus);
-  }
-
-  /*!< Get SCR Register */
-  errorstatus = FindSCR(RCA, scr);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  /*!< If wide bus operation to be enabled */
-  if (NewState == ENABLE)
-  {
-    /*!< If requested card supports wide bus operation */
-    if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
-    {
-      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
-      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-
-      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-      SDIO_CmdInitStructure.SDIO_Argument = 0x2;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
-
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-      return(errorstatus);
-    }
-    else
-    {
-      errorstatus = SD_REQUEST_NOT_APPLICABLE;
-      return(errorstatus);
-    }
-  }   /*!< If wide bus operation to be disabled */
-  else
-  {
-    /*!< If requested card supports 1 bit mode operation */
-    if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
-    {
-      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
-      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-
-      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-
-      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
-      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
-      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-      SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
-
-      if (errorstatus != SD_OK)
-      {
-        return(errorstatus);
-      }
-
-      return(errorstatus);
-    }
-    else
-    {
-      errorstatus = SD_REQUEST_NOT_APPLICABLE;
-      return(errorstatus);
-    }
-  }
-}
-
-/**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  pstatus: pointer to the variable that will contain the SD card state.
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error IsCardProgramming(uint8_t *pstatus)
-{
-  SD_Error errorstatus = SD_OK;
-  __IO uint32_t respR1 = 0, status = 0;
-
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  status = SDIO->STA;
-  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
-  {
-    status = SDIO->STA;
-  }
-
-  if (status & SDIO_FLAG_CTIMEOUT)
-  {
-    errorstatus = SD_CMD_RSP_TIMEOUT;
-    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
-    return(errorstatus);
-  }
-  else if (status & SDIO_FLAG_CCRCFAIL)
-  {
-    errorstatus = SD_CMD_CRC_FAIL;
-    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
-    return(errorstatus);
-  }
-
-  status = (uint32_t)SDIO_GetCommandResponse();
-
-  /*!< Check response received is of desired command */
-  if (status != SD_CMD_SEND_STATUS)
-  {
-    errorstatus = SD_ILLEGAL_CMD;
-    return(errorstatus);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-
-  /*!< We have received response, retrieve it for analysis  */
-  respR1 = SDIO_GetResponse(SDIO_RESP1);
-
-  /*!< Find out card status */
-  *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F);
-
-  if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return(errorstatus);
-  }
-
-  if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-
-  if (respR1 & SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-
-  if (respR1 & SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-
-  if (respR1 & SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-
-  if (respR1 & SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-
-  if (respR1 & SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-
-  if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-
-  if (respR1 & SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-
-  if (respR1 & SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-
-  if (respR1 & SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-
-  if (respR1 & SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-
-  if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-
-  if (respR1 & SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-
-  if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-
-  if (respR1 & SD_OCR_CID_CSD_OVERWRIETE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-
-  if (respR1 & SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-
-  if (respR1 & SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-
-  if (respR1 & SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-
-  if (respR1 & SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Find the SD card SCR register value.
-  * @param  rca: selected card address.
-  * @param  pscr: pointer to the buffer that will contain the SCR value.
-  * @retval SD_Error: SD Card Error code.
-  */
-static SD_Error FindSCR(uint16_t rca, uint32_t *pscr)
-{
-  uint32_t index = 0;
-  SD_Error errorstatus = SD_OK;
-  uint32_t tempscr[2] = {0, 0};
-
-  /*!< Set Block Size To 8 Bytes */
-  /*!< Send CMD55 APP_CMD with argument as card's RCA */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  /*!< Send CMD55 APP_CMD with argument as card's RCA */
-  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
-  SDIO_DataInitStructure.SDIO_DataLength = 8;
-  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b;
-  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
-  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
-  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
-  SDIO_DataConfig(&SDIO_DataInitStructure);
-
-
-  /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
-  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR;
-  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
-  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
-  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
-  SDIO_SendCommand(&SDIO_CmdInitStructure);
-
-  errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR);
-
-  if (errorstatus != SD_OK)
-  {
-    return(errorstatus);
-  }
-
-  while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
-  {
-    if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
-    {
-      *(tempscr + index) = SDIO_ReadData();
-      index++;
-    }
-  }
-
-  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
-    errorstatus = SD_DATA_TIMEOUT;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
-    errorstatus = SD_DATA_CRC_FAIL;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
-    errorstatus = SD_RX_OVERRUN;
-    return(errorstatus);
-  }
-  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
-  {
-    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
-    errorstatus = SD_START_BIT_ERR;
-    return(errorstatus);
-  }
-
-  /*!< Clear all the static flags */
-  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
-
-  *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-
-  *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-
-  return(errorstatus);
-}
-
-/**
-  * @brief  Converts the number of bytes in power of two and returns the power.
-  * @param  NumberOfBytes: number of bytes.
-  * @retval None
-  */
-uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes)
-{
-  uint8_t count = 0;
-
-  while (NumberOfBytes != 1)
-  {
-    NumberOfBytes >>= 1;
-    count++;
-  }
-  return(count);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h
deleted file mode 100644
index d673165..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_sdio_sd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the SD Card 
-  *          stm32_eval_sdio_sd driver firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_SDIO_SD_H
-#define __STM32_EVAL_SDIO_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SDIO_SD
-  * @{
-  */  
-
-/** @defgroup STM32_EVAL_SDIO_SD_Exported_Types
-  * @{
-  */ 
-typedef enum
-{
-/** 
-  * @brief  SDIO specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
-  SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
-  SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
-  SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
-  SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
-  SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
-  SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
-  SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
-  SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
-  SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
-  SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
-  SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
-  SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
-  SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
-  SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18), /*!< Internal card controller error */
-  SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
-  SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
-  SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
-  SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
-  SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
-  SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDIO_DISABLED                   = (30),
-  SD_SDIO_FUNCTION_BUSY              = (31),
-  SD_SDIO_FUNCTION_FAILED            = (32),
-  SD_SDIO_UNKNOWN_FUNCTION           = (33),
-
-/** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR, 
-  SD_NOT_CONFIGURED,
-  SD_REQUEST_PENDING, 
-  SD_REQUEST_NOT_APPLICABLE, 
-  SD_INVALID_PARAMETER,  
-  SD_UNSUPPORTED_FEATURE,  
-  SD_UNSUPPORTED_HW,  
-  SD_ERROR,  
-  SD_OK = 0 
-} SD_Error;
-
-/** 
-  * @brief  SDIO Transfer state  
-  */   
-typedef enum
-{
-  SD_TRANSFER_OK  = 0,
-  SD_TRANSFER_BUSY = 1,
-  SD_TRANSFER_ERROR
-} SDTransferState;
-
-/** 
-  * @brief  SD Card States 
-  */   
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001),
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
-}SDCardState;
-
-
-/** 
-  * @brief  Card Specific Data: CSD Register   
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
-  __IO uint8_t  Reserved1;            /*!< Reserved */
-  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
-  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
-  __IO uint8_t  Reserved2;            /*!< Reserved */
-  __IO uint32_t DeviceSize;           /*!< Device Size */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
-  __IO uint8_t  Reserved3;            /*!< Reserded */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
-  __IO uint8_t  FileFormat;           /*!< File Format */
-  __IO uint8_t  ECC;                  /*!< ECC code */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
-  __IO uint8_t  Reserved4;            /*!< always 1*/
-} SD_CSD;
-
-/** 
-  * @brief  Card Identification Data: CID Register   
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
-  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
-  __IO uint32_t ProdName1;            /*!< Product Name part1 */
-  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
-  __IO uint8_t  ProdRev;              /*!< Product Revision */
-  __IO uint32_t ProdSN;               /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;            /*!< Reserved1 */
-  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
-  __IO uint8_t  CID_CRC;              /*!< CID CRC */
-  __IO uint8_t  Reserved2;            /*!< always 1 */
-} SD_CID;
-
-/** 
-  * @brief SD Card Status 
-  */
-typedef struct
-{
-  __IO uint8_t DAT_BUS_WIDTH;
-  __IO uint8_t SECURED_MODE;
-  __IO uint16_t SD_CARD_TYPE;
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;
-  __IO uint8_t SPEED_CLASS;
-  __IO uint8_t PERFORMANCE_MOVE;
-  __IO uint8_t AU_SIZE;
-  __IO uint16_t ERASE_SIZE;
-  __IO uint8_t ERASE_TIMEOUT;
-  __IO uint8_t ERASE_OFFSET;
-} SD_CardStatus;
-
-
-/** 
-  * @brief SD Card information 
-  */
-typedef struct
-{
-  SD_CSD SD_csd;
-  SD_CID SD_cid;
-  uint32_t CardCapacity;  /*!< Card Capacity */
-  uint32_t CardBlockSize; /*!< Card Block Size */
-  uint16_t RCA;
-  uint8_t CardType;
-} SD_CardInfo;
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_SDIO_SD_Exported_Constants
-  * @{
-  */ 
-
-/** 
-  * @brief SDIO Commands  Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
-#define SD_CMD_SET_DSR                             ((uint8_t)4)
-#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6)
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
-#define SD_CMD_SEND_CSD                            ((uint8_t)9)
-#define SD_CMD_SEND_CID                            ((uint8_t)10)
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13)
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
-#define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27)
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
-                                                                  block to be erased. (For SD card only) */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
-                                                                  continuous range to be erased. (For SD card only) */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
-                                                                  (For MMC card only spec 3.31) */
-
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
-                                                                  continuous range to be erased. (For MMC card only spec 3.31) */
-
-#define SD_CMD_ERASE                               ((uint8_t)38)
-#define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
-#define SD_CMD_APP_CMD                             ((uint8_t)55)
-#define SD_CMD_GEN_CMD                             ((uint8_t)56)
-#define SD_CMD_NO_CMD                              ((uint8_t)64)
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
-#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
-#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
-#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
-  
-/* Uncomment the following line to select the SDIO Data transfer mode */  
-#define SD_DMA_MODE                                ((uint32_t)0x00000000)
-/*#define SD_POLLING_MODE                            ((uint32_t)0x00000002)*/
-
-/**
-  * @brief  SD detection on its memory slot
-  */
-#define SD_PRESENT                                 ((uint8_t)0x01)
-#define SD_NOT_PRESENT                             ((uint8_t)0x00)
-
-/** 
-  * @brief Supported SD Memory Cards 
-  */
-#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_SDIO_SD_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_SDIO_SD_Exported_Functions
-  * @{
-  */ 
-void SD_DeInit(void);
-SD_Error SD_Init(void);
-SDTransferState SD_GetStatus(void);
-SDCardState SD_GetState(void);
-uint8_t SD_Detect(void);
-SD_Error SD_PowerON(void);
-SD_Error SD_PowerOFF(void);
-SD_Error SD_InitializeCards(void);
-SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
-SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
-SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
-SD_Error SD_SelectDeselect(uint32_t addr);
-SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize);
-SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
-SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize);
-SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
-SDTransferState SD_GetTransferState(void);
-SD_Error SD_StopTransfer(void);
-SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
-SD_Error SD_SendStatus(uint32_t *pcardstatus);
-SD_Error SD_SendSDStatus(uint32_t *psdstatus);
-SD_Error SD_ProcessIRQSrc(void);
-SD_Error SD_WaitReadOperation(void);
-SD_Error SD_WaitWriteOperation(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_EVAL_SDIO_SD_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c
deleted file mode 100644
index 878144d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c
+++ /dev/null
@@ -1,541 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_spi_flash.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the SPI M25Pxxx
-  *          FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this memory). 
-  *          It implements a high level communication layer for read and write 
-  *          from/to this memory. The needed STM32 hardware resources (SPI and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c 
-  *          file.
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          sFLASH_LowLevel_Init() function.
-  *            
-  *          +-----------------------------------------------------------+
-  *          |                     Pin assignment                        |
-  *          +-----------------------------+---------------+-------------+
-  *          |  STM32 SPI Pins             |     sFLASH    |    Pin      |
-  *          +-----------------------------+---------------+-------------+
-  *          | sFLASH_CS_PIN               | ChipSelect(/S)|    1        |
-  *          | sFLASH_SPI_MISO_PIN / MISO  |   DataOut(Q)  |    2        |
-  *          |                             |   VCC         |    3 (3.3 V)|
-  *          |                             |   GND         |    4 (0 V)  |
-  *          | sFLASH_SPI_MOSI_PIN / MOSI  |   DataIn(D)   |    5        |
-  *          | sFLASH_SPI_SCK_PIN / SCLK   |   Clock(C)    |    6        |
-  *          |                             |    VCC        |    7 (3.3 V)|
-  *          |                             |    VCC        |    8 (3.3 V)|  
-  *          +-----------------------------+---------------+-------------+  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_spi_flash.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SPI_FLASH
-  * @brief      This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards.
-  * @{
-  */  
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Defines
-  * @{
-  */  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_DeInit(void)
-{
-  sFLASH_LowLevel_DeInit();
-}
-
-/**
-  * @brief  Initializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_Init(void)
-{
-  SPI_InitTypeDef  SPI_InitStructure;
-
-  sFLASH_LowLevel_Init();
-    
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-
-  /*!< SPI configuration */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-#else
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
-#endif
-
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(sFLASH_SPI, &SPI_InitStructure);
-
-  /*!< Enable the sFLASH_SPI  */
-  SPI_Cmd(sFLASH_SPI, ENABLE);
-}
-
-/**
-  * @brief  Erases the specified FLASH sector.
-  * @param  SectorAddr: address of the sector to erase.
-  * @retval None
-  */
-void sFLASH_EraseSector(uint32_t SectorAddr)
-{
-  /*!< Send write enable instruction */
-  sFLASH_WriteEnable();
-
-  /*!< Sector Erase */
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-  /*!< Send Sector Erase instruction */
-  sFLASH_SendByte(sFLASH_CMD_SE);
-  /*!< Send SectorAddr high nibble address byte */
-  sFLASH_SendByte((SectorAddr & 0xFF0000) >> 16);
-  /*!< Send SectorAddr medium nibble address byte */
-  sFLASH_SendByte((SectorAddr & 0xFF00) >> 8);
-  /*!< Send SectorAddr low nibble address byte */
-  sFLASH_SendByte(SectorAddr & 0xFF);
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-
-  /*!< Wait the end of Flash writing */
-  sFLASH_WaitForWriteEnd();
-}
-
-/**
-  * @brief  Erases the entire FLASH.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_EraseBulk(void)
-{
-  /*!< Send write enable instruction */
-  sFLASH_WriteEnable();
-
-  /*!< Bulk Erase */
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-  /*!< Send Bulk Erase instruction  */
-  sFLASH_SendByte(sFLASH_CMD_BE);
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-
-  /*!< Wait the end of Flash writing */
-  sFLASH_WaitForWriteEnd();
-}
-
-/**
-  * @brief  Writes more than one byte to the FLASH with a single WRITE cycle 
-  *         (Page WRITE sequence).
-  * @note   The number of byte can't exceed the FLASH page size.
-  * @param  pBuffer: pointer to the buffer  containing the data to be written
-  *         to the FLASH.
-  * @param  WriteAddr: FLASH's internal address to write to.
-  * @param  NumByteToWrite: number of bytes to write to the FLASH, must be equal
-  *         or less than "sFLASH_PAGESIZE" value.
-  * @retval None
-  */
-void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
-{
-  /*!< Enable the write access to the FLASH */
-  sFLASH_WriteEnable();
-
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-  /*!< Send "Write to Memory " instruction */
-  sFLASH_SendByte(sFLASH_CMD_WRITE);
-  /*!< Send WriteAddr high nibble address byte to write to */
-  sFLASH_SendByte((WriteAddr & 0xFF0000) >> 16);
-  /*!< Send WriteAddr medium nibble address byte to write to */
-  sFLASH_SendByte((WriteAddr & 0xFF00) >> 8);
-  /*!< Send WriteAddr low nibble address byte to write to */
-  sFLASH_SendByte(WriteAddr & 0xFF);
-
-  /*!< while there is data to be written on the FLASH */
-  while (NumByteToWrite--)
-  {
-    /*!< Send the current byte */
-    sFLASH_SendByte(*pBuffer);
-    /*!< Point on the next byte to be written */
-    pBuffer++;
-  }
-
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-
-  /*!< Wait the end of Flash writing */
-  sFLASH_WaitForWriteEnd();
-}
-
-/**
-  * @brief  Writes block of data to the FLASH. In this function, the number of
-  *         WRITE cycles are reduced, using Page WRITE sequence.
-  * @param  pBuffer: pointer to the buffer  containing the data to be written
-  *         to the FLASH.
-  * @param  WriteAddr: FLASH's internal address to write to.
-  * @param  NumByteToWrite: number of bytes to write to the FLASH.
-  * @retval None
-  */
-void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
-{
-  uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
-
-  Addr = WriteAddr % sFLASH_SPI_PAGESIZE;
-  count = sFLASH_SPI_PAGESIZE - Addr;
-  NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
-  NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
-
-  if (Addr == 0) /*!< WriteAddr is sFLASH_PAGESIZE aligned  */
-  {
-    if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
-    {
-      sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
-    }
-    else /*!< NumByteToWrite > sFLASH_PAGESIZE */
-    {
-      while (NumOfPage--)
-      {
-        sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
-        WriteAddr +=  sFLASH_SPI_PAGESIZE;
-        pBuffer += sFLASH_SPI_PAGESIZE;
-      }
-
-      sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
-    }
-  }
-  else /*!< WriteAddr is not sFLASH_PAGESIZE aligned  */
-  {
-    if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
-    {
-      if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE */
-      {
-        temp = NumOfSingle - count;
-
-        sFLASH_WritePage(pBuffer, WriteAddr, count);
-        WriteAddr +=  count;
-        pBuffer += count;
-
-        sFLASH_WritePage(pBuffer, WriteAddr, temp);
-      }
-      else
-      {
-        sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
-      }
-    }
-    else /*!< NumByteToWrite > sFLASH_PAGESIZE */
-    {
-      NumByteToWrite -= count;
-      NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
-      NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
-
-      sFLASH_WritePage(pBuffer, WriteAddr, count);
-      WriteAddr +=  count;
-      pBuffer += count;
-
-      while (NumOfPage--)
-      {
-        sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
-        WriteAddr +=  sFLASH_SPI_PAGESIZE;
-        pBuffer += sFLASH_SPI_PAGESIZE;
-      }
-
-      if (NumOfSingle != 0)
-      {
-        sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
-      }
-    }
-  }
-}
-
-/**
-  * @brief  Reads a block of data from the FLASH.
-  * @param  pBuffer: pointer to the buffer that receives the data read from the FLASH.
-  * @param  ReadAddr: FLASH's internal address to read from.
-  * @param  NumByteToRead: number of bytes to read from the FLASH.
-  * @retval None
-  */
-void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
-{
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-
-  /*!< Send "Read from Memory " instruction */
-  sFLASH_SendByte(sFLASH_CMD_READ);
-
-  /*!< Send ReadAddr high nibble address byte to read from */
-  sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
-  /*!< Send ReadAddr medium nibble address byte to read from */
-  sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
-  /*!< Send ReadAddr low nibble address byte to read from */
-  sFLASH_SendByte(ReadAddr & 0xFF);
-
-  while (NumByteToRead--) /*!< while there is data to be read */
-  {
-    /*!< Read a byte from the FLASH */
-    *pBuffer = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
-    /*!< Point to the next location where the byte read will be saved */
-    pBuffer++;
-  }
-
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-}
-
-/**
-  * @brief  Reads FLASH identification.
-  * @param  None
-  * @retval FLASH identification
-  */
-uint32_t sFLASH_ReadID(void)
-{
-  uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
-
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-
-  /*!< Send "RDID " instruction */
-  sFLASH_SendByte(0x9F);
-
-  /*!< Read a byte from the FLASH */
-  Temp0 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
-
-  /*!< Read a byte from the FLASH */
-  Temp1 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
-
-  /*!< Read a byte from the FLASH */
-  Temp2 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
-
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-
-  Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
-
-  return Temp;
-}
-
-/**
-  * @brief  Initiates a read data byte (READ) sequence from the Flash.
-  *   This is done by driving the /CS line low to select the device, then the READ
-  *   instruction is transmitted followed by 3 bytes address. This function exit
-  *   and keep the /CS line low, so the Flash still being selected. With this
-  *   technique the whole content of the Flash is read with a single READ instruction.
-  * @param  ReadAddr: FLASH's internal address to read from.
-  * @retval None
-  */
-void sFLASH_StartReadSequence(uint32_t ReadAddr)
-{
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-
-  /*!< Send "Read from Memory " instruction */
-  sFLASH_SendByte(sFLASH_CMD_READ);
-
-  /*!< Send the 24-bit address of the address to read from -------------------*/
-  /*!< Send ReadAddr high nibble address byte */
-  sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
-  /*!< Send ReadAddr medium nibble address byte */
-  sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
-  /*!< Send ReadAddr low nibble address byte */
-  sFLASH_SendByte(ReadAddr & 0xFF);
-}
-
-/**
-  * @brief  Reads a byte from the SPI Flash.
-  * @note   This function must be used only if the Start_Read_Sequence function
-  *         has been previously called.
-  * @param  None
-  * @retval Byte Read from the SPI Flash.
-  */
-uint8_t sFLASH_ReadByte(void)
-{
-  return (sFLASH_SendByte(sFLASH_DUMMY_BYTE));
-}
-
-/**
-  * @brief  Sends a byte through the SPI interface and return the byte received
-  *         from the SPI bus.
-  * @param  byte: byte to send.
-  * @retval The value of the received byte.
-  */
-uint8_t sFLASH_SendByte(uint8_t byte)
-{
-  /*!< Loop while DR register in not emplty */
-  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
-
-  /*!< Send byte through the SPI1 peripheral */
-  SPI_I2S_SendData(sFLASH_SPI, byte);
-
-  /*!< Wait to receive a byte */
-  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
-
-  /*!< Return the byte read from the SPI bus */
-  return SPI_I2S_ReceiveData(sFLASH_SPI);
-}
-
-/**
-  * @brief  Sends a Half Word through the SPI interface and return the Half Word
-  *         received from the SPI bus.
-  * @param  HalfWord: Half Word to send.
-  * @retval The value of the received Half Word.
-  */
-uint16_t sFLASH_SendHalfWord(uint16_t HalfWord)
-{
-  /*!< Loop while DR register in not emplty */
-  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
-
-  /*!< Send Half Word through the sFLASH peripheral */
-  SPI_I2S_SendData(sFLASH_SPI, HalfWord);
-
-  /*!< Wait to receive a Half Word */
-  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
-
-  /*!< Return the Half Word read from the SPI bus */
-  return SPI_I2S_ReceiveData(sFLASH_SPI);
-}
-
-/**
-  * @brief  Enables the write access to the FLASH.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_WriteEnable(void)
-{
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-
-  /*!< Send "Write Enable" instruction */
-  sFLASH_SendByte(sFLASH_CMD_WREN);
-
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-}
-
-/**
-  * @brief  Polls the status of the Write In Progress (WIP) flag in the FLASH's
-  *         status register and loop until write opertaion has completed.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_WaitForWriteEnd(void)
-{
-  uint8_t flashstatus = 0;
-
-  /*!< Select the FLASH: Chip Select low */
-  sFLASH_CS_LOW();
-
-  /*!< Send "Read Status Register" instruction */
-  sFLASH_SendByte(sFLASH_CMD_RDSR);
-
-  /*!< Loop as long as the memory is busy with a write cycle */
-  do
-  {
-    /*!< Send a dummy byte to generate the clock needed by the FLASH
-    and put the value of the status register in FLASH_Status variable */
-    flashstatus = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
-
-  }
-  while ((flashstatus & sFLASH_WIP_FLAG) == SET); /* Write in progress */
-
-  /*!< Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h
deleted file mode 100644
index 74a10a3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_spi_flash.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32_eval_spi_flash
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_SPI_FLASH_H
-#define __STM32_EVAL_SPI_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SPI_FLASH
-  * @{
-  */  
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Constants
-  * @{
-  */
-/**
-  * @brief  M25P SPI Flash supported commands
-  */  
-#define sFLASH_CMD_WRITE          0x02  /*!< Write to Memory instruction */
-#define sFLASH_CMD_WRSR           0x01  /*!< Write Status Register instruction */
-#define sFLASH_CMD_WREN           0x06  /*!< Write enable instruction */
-#define sFLASH_CMD_READ           0x03  /*!< Read from Memory instruction */
-#define sFLASH_CMD_RDSR           0x05  /*!< Read Status Register instruction  */
-#define sFLASH_CMD_RDID           0x9F  /*!< Read identification */
-#define sFLASH_CMD_SE             0xD8  /*!< Sector Erase instruction */
-#define sFLASH_CMD_BE             0xC7  /*!< Bulk Erase instruction */
-
-#define sFLASH_WIP_FLAG           0x01  /*!< Write In Progress (WIP) flag */
-
-#define sFLASH_DUMMY_BYTE         0xA5
-#define sFLASH_SPI_PAGESIZE       0x100
-
-#define sFLASH_M25P128_ID         0x202018
-#define sFLASH_M25P64_ID          0x202017
-  
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Macros
-  * @{
-  */
-/**
-  * @brief  Select sFLASH: Chip Select pin low
-  */
-#define sFLASH_CS_LOW()       GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
-/**
-  * @brief  Deselect sFLASH: Chip Select pin high
-  */
-#define sFLASH_CS_HIGH()      GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)   
-/**
-  * @}
-  */ 
-  
-
-
-/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Functions
-  * @{
-  */
-/**
-  * @brief  High layer functions
-  */
-void sFLASH_DeInit(void);
-void sFLASH_Init(void);
-void sFLASH_EraseSector(uint32_t SectorAddr);
-void sFLASH_EraseBulk(void);
-void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
-void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
-void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead);
-uint32_t sFLASH_ReadID(void);
-void sFLASH_StartReadSequence(uint32_t ReadAddr);
-
-/**
-  * @brief  Low layer functions
-  */
-uint8_t sFLASH_ReadByte(void);
-uint8_t sFLASH_SendByte(uint8_t byte);
-uint16_t sFLASH_SendHalfWord(uint16_t HalfWord);
-void sFLASH_WriteEnable(void);
-void sFLASH_WaitForWriteEnd(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_EVAL_SPI_FLASH_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c
deleted file mode 100644
index f652e71..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c
+++ /dev/null
@@ -1,901 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_spi_sd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the SPI SD 
-  *          Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this memory). 
-  *          It implements a high level communication layer for read and write 
-  *          from/to this memory. The needed STM32 hardware resources (SPI and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in SD_LowLevel_Init() function declared in stm32xx_eval.c 
-  *          file.
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          SD_LowLevel_Init() function.
-  *            
-  *          +-------------------------------------------------------+
-  *          |                     Pin assignment                    |
-  *          +-------------------------+---------------+-------------+
-  *          |  STM32 SPI Pins         |     SD        |    Pin      |
-  *          +-------------------------+---------------+-------------+
-  *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |
-  *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |
-  *          |                         |   GND         |    3 (0 V)  |
-  *          |                         |   VDD         |    4 (3.3 V)|
-  *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |
-  *          |                         |   GND         |    6 (0 V)  |
-  *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |
-  *          +-------------------------+---------------+-------------+
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_spi_sd.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SPI_SD
-  * @brief      This file includes the SD card driver of STM32-EVAL boards.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Function_Prototypes
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_SPI_SD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the SD/SD communication.
-  * @param  None
-  * @retval None
-  */
-void SD_DeInit(void)
-{
-  SD_LowLevel_DeInit();
-}
-
-/**
-  * @brief  Initializes the SD/SD communication.
-  * @param  None
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_Init(void)
-{
-  uint32_t i = 0;
-
-  /*!< Initialize SD_SPI */
-  SD_LowLevel_Init(); 
-
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-
-  /*!< Send dummy byte 0xFF, 10 times with CS high */
-  /*!< Rise CS and MOSI for 80 clocks cycles */
-  for (i = 0; i <= 9; i++)
-  {
-    /*!< Send dummy byte 0xFF */
-    SD_WriteByte(SD_DUMMY_BYTE);
-  }
-  /*------------Put SD in SPI mode--------------*/
-  /*!< SD initialized and set to SPI mode properly */
-  return (SD_GoIdleState());
-}
-
-/**
- * @brief  Detect if SD card is correctly plugged in the memory slot.
- * @param  None
- * @retval Return if SD is detected or not
- */
-uint8_t SD_Detect(void)
-{
-  __IO uint8_t status = SD_PRESENT;
-
-  /*!< Check GPIO to detect SD */
-  if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN)
-  {
-    status = SD_NOT_PRESENT;
-  }
-  return status;
-}
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD 
-  *         card information.
-  * @retval The SD Response:
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
-{
-  SD_Error status = SD_RESPONSE_FAILURE;
-
-  status = SD_GetCSDRegister(&(cardinfo->SD_csd));
-  status = SD_GetCIDRegister(&(cardinfo->SD_cid));
-  cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
-  cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
-  cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
-  cardinfo->CardCapacity *= cardinfo->CardBlockSize;
-
-  /*!< Returns the reponse */
-  return status;
-}
-
-/**
-  * @brief  Reads a block of data from the SD.
-  * @param  pBuffer: pointer to the buffer that receives the data read from the 
-  *                  SD.
-  * @param  ReadAddr: SD's internal address to read from.
-  * @param  BlockSize: the SD card Data block size.
-  * @retval The SD Response:
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
-{
-  uint32_t i = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  
-  /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
-  SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
-  
-  /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
-  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
-  {
-    /*!< Now look for the data token to signify the start of the data */
-    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
-    {
-      /*!< Read the SD block data : read NumByteToRead data */
-      for (i = 0; i < BlockSize; i++)
-      {
-        /*!< Save the received data */
-        *pBuffer = SD_ReadByte();
-       
-        /*!< Point to the next location where the byte read will be saved */
-        pBuffer++;
-      }
-      /*!< Get CRC bytes (not really needed by us, but required by SD) */
-      SD_ReadByte();
-      SD_ReadByte();
-      /*!< Set response value to success */
-      rvalue = SD_RESPONSE_NO_ERROR;
-    }
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-  
-  /*!< Returns the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Reads multiple block of data from the SD.
-  * @param  pBuffer: pointer to the buffer that receives the data read from the 
-  *                  SD.
-  * @param  ReadAddr: SD's internal address to read from.
-  * @param  BlockSize: the SD card Data block size.
-  * @param  NumberOfBlocks: number of blocks to be read.
-  * @retval The SD Response:
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
-{
-  uint32_t i = 0, Offset = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-  
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  /*!< Data transfer */
-  while (NumberOfBlocks--)
-  {
-    /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
-    SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
-    /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
-    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
-    {
-      return  SD_RESPONSE_FAILURE;
-    }
-    /*!< Now look for the data token to signify the start of the data */
-    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
-    {
-      /*!< Read the SD block data : read NumByteToRead data */
-      for (i = 0; i < BlockSize; i++)
-      {
-        /*!< Read the pointed data */
-        *pBuffer = SD_ReadByte();
-        /*!< Point to the next location where the byte read will be saved */
-        pBuffer++;
-      }
-      /*!< Set next read address*/
-      Offset += 512;
-      /*!< get CRC bytes (not really needed by us, but required by SD) */
-      SD_ReadByte();
-      SD_ReadByte();
-      /*!< Set response value to success */
-      rvalue = SD_RESPONSE_NO_ERROR;
-    }
-    else
-    {
-      /*!< Set response value to failure */
-      rvalue = SD_RESPONSE_FAILURE;
-    }
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-  /*!< Returns the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Writes a block on the SD
-  * @param  pBuffer: pointer to the buffer containing the data to be written on 
-  *                  the SD.
-  * @param  WriteAddr: address to write on.
-  * @param  BlockSize: the SD card Data block size.
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
-{
-  uint32_t i = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-
-  /*!< SD chip select low */
-  SD_CS_LOW();
-
-  /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */
-  SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
-  
-  /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
-  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
-  {
-    /*!< Send a dummy byte */
-    SD_WriteByte(SD_DUMMY_BYTE);
-
-    /*!< Send the data token to signify the start of the data */
-    SD_WriteByte(0xFE);
-
-    /*!< Write the block data to SD : write count data by block */
-    for (i = 0; i < BlockSize; i++)
-    {
-      /*!< Send the pointed byte */
-      SD_WriteByte(*pBuffer);
-      /*!< Point to the next location where the byte read will be saved */
-      pBuffer++;
-    }
-    /*!< Put CRC bytes (not really needed by us, but required by SD) */
-    SD_ReadByte();
-    SD_ReadByte();
-
-    /*!< Read data response */
-    if (SD_GetDataResponse() == SD_DATA_OK)
-    {
-      rvalue = SD_RESPONSE_NO_ERROR;
-    }
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-
-  /*!< Returns the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Writes many blocks on the SD
-  * @param  pBuffer: pointer to the buffer containing the data to be written on 
-  *                  the SD.
-  * @param  WriteAddr: address to write on.
-  * @param  BlockSize: the SD card Data block size.
-  * @param  NumberOfBlocks: number of blocks to be written.
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
-{
-  uint32_t i = 0, Offset = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  /*!< Data transfer */
-  while (NumberOfBlocks--)
-  {
-    /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */
-    SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF);
-    /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
-    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
-    {
-      return SD_RESPONSE_FAILURE;
-    }
-    /*!< Send dummy byte */
-    SD_WriteByte(SD_DUMMY_BYTE);
-    /*!< Send the data token to signify the start of the data */
-    SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE);
-    /*!< Write the block data to SD : write count data by block */
-    for (i = 0; i < BlockSize; i++)
-    {
-      /*!< Send the pointed byte */
-      SD_WriteByte(*pBuffer);
-      /*!< Point to the next location where the byte read will be saved */
-      pBuffer++;
-    }
-    /*!< Set next write address */
-    Offset += 512;
-    /*!< Put CRC bytes (not really needed by us, but required by SD) */
-    SD_ReadByte();
-    SD_ReadByte();
-    /*!< Read data response */
-    if (SD_GetDataResponse() == SD_DATA_OK)
-    {
-      /*!< Set response value to success */
-      rvalue = SD_RESPONSE_NO_ERROR;
-    }
-    else
-    {
-      /*!< Set response value to failure */
-      rvalue = SD_RESPONSE_FAILURE;
-    }
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-  /*!< Returns the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Read the CSD card register.
-  *         Reading the contents of the CSD register in SPI mode is a simple 
-  *         read-block transaction.
-  * @param  SD_csd: pointer on an SCD register structure
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_GetCSDRegister(SD_CSD* SD_csd)
-{
-  uint32_t i = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-  uint8_t CSD_Tab[16];
-
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  /*!< Send CMD9 (CSD register) or CMD10(CSD register) */
-  SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF);
-  /*!< Wait for response in the R1 format (0x00 is no errors) */
-  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
-  {
-    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
-    {
-      for (i = 0; i < 16; i++)
-      {
-        /*!< Store CSD register value on CSD_Tab */
-        CSD_Tab[i] = SD_ReadByte();
-      }
-    }
-    /*!< Get CRC bytes (not really needed by us, but required by SD) */
-    SD_WriteByte(SD_DUMMY_BYTE);
-    SD_WriteByte(SD_DUMMY_BYTE);
-    /*!< Set response value to success */
-    rvalue = SD_RESPONSE_NO_ERROR;
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-
-  /*!< Byte 0 */
-  SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
-  SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
-  SD_csd->Reserved1 = CSD_Tab[0] & 0x03;
-
-  /*!< Byte 1 */
-  SD_csd->TAAC = CSD_Tab[1];
-
-  /*!< Byte 2 */
-  SD_csd->NSAC = CSD_Tab[2];
-
-  /*!< Byte 3 */
-  SD_csd->MaxBusClkFrec = CSD_Tab[3];
-
-  /*!< Byte 4 */
-  SD_csd->CardComdClasses = CSD_Tab[4] << 4;
-
-  /*!< Byte 5 */
-  SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
-  SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
-
-  /*!< Byte 6 */
-  SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
-  SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
-  SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
-  SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
-  SD_csd->Reserved2 = 0; /*!< Reserved */
-
-  SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
-
-  /*!< Byte 7 */
-  SD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
-
-  /*!< Byte 8 */
-  SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
-
-  SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
-  SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
-
-  /*!< Byte 9 */
-  SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
-  SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
-  SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
-  /*!< Byte 10 */
-  SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
-    
-  SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6;
-  SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1;
-
-  /*!< Byte 11 */
-  SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7;
-  SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F);
-
-  /*!< Byte 12 */
-  SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
-  SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
-  SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
-  SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
-
-  /*!< Byte 13 */
-  SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6;
-  SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
-  SD_csd->Reserved3 = 0;
-  SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
-
-  /*!< Byte 14 */
-  SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
-  SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
-  SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
-  SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
-  SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
-  SD_csd->ECC = (CSD_Tab[14] & 0x03);
-
-  /*!< Byte 15 */
-  SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1;
-  SD_csd->Reserved4 = 1;
-
-  /*!< Return the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Read the CID card register.
-  *         Reading the contents of the CID register in SPI mode is a simple 
-  *         read-block transaction.
-  * @param  SD_cid: pointer on an CID register structure
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_GetCIDRegister(SD_CID* SD_cid)
-{
-  uint32_t i = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-  uint8_t CID_Tab[16];
-  
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  
-  /*!< Send CMD10 (CID register) */
-  SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF);
-  
-  /*!< Wait for response in the R1 format (0x00 is no errors) */
-  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
-  {
-    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
-    {
-      /*!< Store CID register value on CID_Tab */
-      for (i = 0; i < 16; i++)
-      {
-        CID_Tab[i] = SD_ReadByte();
-      }
-    }
-    /*!< Get CRC bytes (not really needed by us, but required by SD) */
-    SD_WriteByte(SD_DUMMY_BYTE);
-    SD_WriteByte(SD_DUMMY_BYTE);
-    /*!< Set response value to success */
-    rvalue = SD_RESPONSE_NO_ERROR;
-  }
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  /*!< Send dummy byte: 8 Clock pulses of delay */
-  SD_WriteByte(SD_DUMMY_BYTE);
-
-  /*!< Byte 0 */
-  SD_cid->ManufacturerID = CID_Tab[0];
-
-  /*!< Byte 1 */
-  SD_cid->OEM_AppliID = CID_Tab[1] << 8;
-
-  /*!< Byte 2 */
-  SD_cid->OEM_AppliID |= CID_Tab[2];
-
-  /*!< Byte 3 */
-  SD_cid->ProdName1 = CID_Tab[3] << 24;
-
-  /*!< Byte 4 */
-  SD_cid->ProdName1 |= CID_Tab[4] << 16;
-
-  /*!< Byte 5 */
-  SD_cid->ProdName1 |= CID_Tab[5] << 8;
-
-  /*!< Byte 6 */
-  SD_cid->ProdName1 |= CID_Tab[6];
-
-  /*!< Byte 7 */
-  SD_cid->ProdName2 = CID_Tab[7];
-
-  /*!< Byte 8 */
-  SD_cid->ProdRev = CID_Tab[8];
-
-  /*!< Byte 9 */
-  SD_cid->ProdSN = CID_Tab[9] << 24;
-
-  /*!< Byte 10 */
-  SD_cid->ProdSN |= CID_Tab[10] << 16;
-
-  /*!< Byte 11 */
-  SD_cid->ProdSN |= CID_Tab[11] << 8;
-
-  /*!< Byte 12 */
-  SD_cid->ProdSN |= CID_Tab[12];
-
-  /*!< Byte 13 */
-  SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
-  SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
-
-  /*!< Byte 14 */
-  SD_cid->ManufactDate |= CID_Tab[14];
-
-  /*!< Byte 15 */
-  SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;
-  SD_cid->Reserved2 = 1;
-
-  /*!< Return the reponse */
-  return rvalue;
-}
-
-/**
-  * @brief  Send 5 bytes command to the SD card.
-  * @param  Cmd: The user expected command to send to SD card.
-  * @param  Arg: The command argument.
-  * @param  Crc: The CRC.
-  * @retval None
-  */
-void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
-{
-  uint32_t i = 0x00;
-  
-  uint8_t Frame[6];
-  
-  Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
-  
-  Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
-  
-  Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
-  
-  Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
-  
-  Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
-  
-  Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
-  
-  for (i = 0; i < 6; i++)
-  {
-    SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
-  }
-}
-
-/**
-  * @brief  Get SD card data response.
-  * @param  None
-  * @retval The SD status: Read data response xxx0<status>1
-  *         - status 010: Data accecpted
-  *         - status 101: Data rejected due to a crc error
-  *         - status 110: Data rejected due to a Write error.
-  *         - status 111: Data rejected due to other error.
-  */
-uint8_t SD_GetDataResponse(void)
-{
-  uint32_t i = 0;
-  uint8_t response, rvalue;
-
-  while (i <= 64)
-  {
-    /*!< Read resonse */
-    response = SD_ReadByte();
-    /*!< Mask unused bits */
-    response &= 0x1F;
-    switch (response)
-    {
-      case SD_DATA_OK:
-      {
-        rvalue = SD_DATA_OK;
-        break;
-      }
-      case SD_DATA_CRC_ERROR:
-        return SD_DATA_CRC_ERROR;
-      case SD_DATA_WRITE_ERROR:
-        return SD_DATA_WRITE_ERROR;
-      default:
-      {
-        rvalue = SD_DATA_OTHER_ERROR;
-        break;
-      }
-    }
-    /*!< Exit loop in case of data ok */
-    if (rvalue == SD_DATA_OK)
-      break;
-    /*!< Increment loop counter */
-    i++;
-  }
-
-  /*!< Wait null data */
-  while (SD_ReadByte() == 0);
-
-  /*!< Return response */
-  return response;
-}
-
-/**
-  * @brief  Returns the SD response.
-  * @param  None
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_GetResponse(uint8_t Response)
-{
-  uint32_t Count = 0xFFF;
-
-  /*!< Check if response is got or a timeout is happen */
-  while ((SD_ReadByte() != Response) && Count)
-  {
-    Count--;
-  }
-  if (Count == 0)
-  {
-    /*!< After time out */
-    return SD_RESPONSE_FAILURE;
-  }
-  else
-  {
-    /*!< Right response got */
-    return SD_RESPONSE_NO_ERROR;
-  }
-}
-
-/**
-  * @brief  Returns the SD status.
-  * @param  None
-  * @retval The SD status.
-  */
-uint16_t SD_GetStatus(void)
-{
-  uint16_t Status = 0;
-
-  /*!< SD chip select low */
-  SD_CS_LOW();
-
-  /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */
-  SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF);
-
-  Status = SD_ReadByte();
-  Status |= (uint16_t)(SD_ReadByte() << 8);
-
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-
-  /*!< Send dummy byte 0xFF */
-  SD_WriteByte(SD_DUMMY_BYTE);
-
-  return Status;
-}
-
-/**
-  * @brief  Put SD in Idle state.
-  * @param  None
-  * @retval The SD Response: 
-  *         - SD_RESPONSE_FAILURE: Sequence failed
-  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
-  */
-SD_Error SD_GoIdleState(void)
-{
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  
-  /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
-  SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
-  
-  /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
-  if (SD_GetResponse(SD_IN_IDLE_STATE))
-  {
-    /*!< No Idle State Response: return response failue */
-    return SD_RESPONSE_FAILURE;
-  }
-  /*----------Activates the card initialization process-----------*/
-  do
-  {
-    /*!< SD chip select high */
-    SD_CS_HIGH();
-    
-    /*!< Send Dummy byte 0xFF */
-    SD_WriteByte(SD_DUMMY_BYTE);
-    
-    /*!< SD chip select low */
-    SD_CS_LOW();
-    
-    /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
-    SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
-    /*!< Wait for no error Response (R1 Format) equal to 0x00 */
-  }
-  while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
-  
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  
-  /*!< Send dummy byte 0xFF */
-  SD_WriteByte(SD_DUMMY_BYTE);
-  
-  return SD_RESPONSE_NO_ERROR;
-}
-
-/**
-  * @brief  Write a byte on the SD.
-  * @param  Data: byte to send.
-  * @retval None
-  */
-uint8_t SD_WriteByte(uint8_t Data)
-{
-  /*!< Wait until the transmit buffer is empty */
-  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
-  {
-  }
-  
-  /*!< Send the byte */
-  SPI_I2S_SendData(SD_SPI, Data);
-  
-  /*!< Wait to receive a byte*/
-  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  
-  /*!< Return the byte read from the SPI bus */ 
-  return SPI_I2S_ReceiveData(SD_SPI);
-}
-
-/**
-  * @brief  Read a byte from the SD.
-  * @param  None
-  * @retval The received byte.
-  */
-uint8_t SD_ReadByte(void)
-{
-  uint8_t Data = 0;
-  
-  /*!< Wait until the transmit buffer is empty */
-  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
-  {
-  }
-  /*!< Send the byte */
-  SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE);
-
-  /*!< Wait until a data is received */
-  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  /*!< Get the received data */
-  Data = SPI_I2S_ReceiveData(SD_SPI);
-
-  /*!< Return the shifted data */
-  return Data;
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h
deleted file mode 100644
index 4a63f3a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval_spi_sd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32_eval_spi_sd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_SPI_SD_H
-#define __STM32_EVAL_SPI_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup Common
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL_SPI_SD
-  * @{
-  */  
-
-/** @defgroup STM32_EVAL_SPI_SD_Exported_Types
-  * @{
-  */ 
-
-typedef enum
-{
-/**
-  * @brief  SD reponses and error flags
-  */
-  SD_RESPONSE_NO_ERROR      = (0x00),
-  SD_IN_IDLE_STATE          = (0x01),
-  SD_ERASE_RESET            = (0x02),
-  SD_ILLEGAL_COMMAND        = (0x04),
-  SD_COM_CRC_ERROR          = (0x08),
-  SD_ERASE_SEQUENCE_ERROR   = (0x10),
-  SD_ADDRESS_ERROR          = (0x20),
-  SD_PARAMETER_ERROR        = (0x40),
-  SD_RESPONSE_FAILURE       = (0xFF),
-
-/**
-  * @brief  Data response error
-  */
-  SD_DATA_OK                = (0x05),
-  SD_DATA_CRC_ERROR         = (0x0B),
-  SD_DATA_WRITE_ERROR       = (0x0D),
-  SD_DATA_OTHER_ERROR       = (0xFF)
-} SD_Error;
-
-/** 
-  * @brief  Card Specific Data: CSD Register   
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
-  __IO uint8_t  Reserved1;            /*!< Reserved */
-  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
-  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
-  __IO uint8_t  Reserved2;            /*!< Reserved */
-  __IO uint32_t DeviceSize;           /*!< Device Size */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
-  __IO uint8_t  Reserved3;            /*!< Reserded */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
-  __IO uint8_t  FileFormat;           /*!< File Format */
-  __IO uint8_t  ECC;                  /*!< ECC code */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
-  __IO uint8_t  Reserved4;            /*!< always 1*/
-} SD_CSD;
-
-/** 
-  * @brief  Card Identification Data: CID Register   
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
-  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
-  __IO uint32_t ProdName1;            /*!< Product Name part1 */
-  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
-  __IO uint8_t  ProdRev;              /*!< Product Revision */
-  __IO uint32_t ProdSN;               /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;            /*!< Reserved1 */
-  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
-  __IO uint8_t  CID_CRC;              /*!< CID CRC */
-  __IO uint8_t  Reserved2;            /*!< always 1 */
-} SD_CID;
-
-/** 
-  * @brief SD Card information 
-  */
-typedef struct
-{
-  SD_CSD SD_csd;
-  SD_CID SD_cid;
-  uint32_t CardCapacity;  /*!< Card Capacity */
-  uint32_t CardBlockSize; /*!< Card Block Size */
-} SD_CardInfo;
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_SPI_SD_Exported_Constants
-  * @{
-  */ 
-    
-/**
-  * @brief  Block Size
-  */
-#define SD_BLOCK_SIZE    0x200
-
-/**
-  * @brief  Dummy byte
-  */
-#define SD_DUMMY_BYTE   0xFF
-
-/**
-  * @brief  Start Data tokens:
-  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is 
-  *         on the data/command line)  
-  */
-#define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
-#define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
-#define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
-#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
-#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
-
-/**
-  * @brief  SD detection on its memory slot
-  */
-#define SD_PRESENT        ((uint8_t)0x01)
-#define SD_NOT_PRESENT    ((uint8_t)0x00)
-
-
-/**
-  * @brief  Commands: CMDxx = CMD-number | 0x40
-  */
-#define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
-#define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
-#define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
-#define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
-#define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
-#define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
-#define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
-#define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
-#define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
-#define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
-#define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
-#define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
-#define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
-#define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
-#define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
-#define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
-#define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
-#define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
-#define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
-#define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
-#define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
-#define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
-#define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_SPI_SD_Exported_Macros
-  * @{
-  */
-/** 
-  * @brief  Select SD Card: ChipSelect pin low   
-  */  
-#define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
-/** 
-  * @brief  Deselect SD Card: ChipSelect pin high   
-  */ 
-#define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_SPI_SD_Exported_Functions
-  * @{
-  */ 
-void SD_DeInit(void);  
-SD_Error SD_Init(void);
-uint8_t SD_Detect(void);
-SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
-SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
-SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
-SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
-SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
-SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
-SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
-
-void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
-SD_Error SD_GetResponse(uint8_t Response);
-uint8_t SD_GetDataResponse(void);
-SD_Error SD_GoIdleState(void);
-uint16_t SD_GetStatus(void);
-
-uint8_t SD_WriteByte(uint8_t byte);
-uint8_t SD_ReadByte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_EVAL_SPI_SD_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */    
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html
deleted file mode 100644
index 430a05b..0000000
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-            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32 Standard Peripherals Library Utilities (Utilities)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-            </td>
-          </tr>
-        </tbody>
-      </table>
-      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
-      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-        <tbody>
-          <tr style="">
-            <td style="padding: 0cm;" valign="top">
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-            <ol style="margin-top: 0cm;" start="1" type="1">
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32 Standard Peripherals Library Utilities
-update History</a><o:p></o:p></span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-            </ol>
-            <span style="font-family: &quot;Times New Roman&quot;;">
-            </span>
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32
-Standard
-Peripherals Library Utilities update History</span></h2><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.5.0 / 07-March-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_sdio_sd.c\.h: driver improvement</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">SD Clock increased to 24MHz to improve the data transfer performance.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add
-new functions to check the SDIO peripheral and SD Card status at any
-time:&nbsp;SD_WaitReadOperation(), SD_WaitWriteOperation(). The
-software sequence is little bit changed&nbsp;but without any impact on
-driver API. For more details, refer to the stm32_eval_sdio_sd.c
-driver&nbsp;description.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add
-new structure containing the SD Status register parameters. This
-structure is called by the
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
-&nbsp;SD_SendSDStatus() function.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Transfers mode updated</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Read/Write Block using Polling and DMA modes</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Read/Write Multi Blocks using DMA mode only</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Interrupt mode removed</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Data transfer functions are managing only fixed Block size (512-byte)&nbsp;</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM32100B-EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100b_eval_cec.c: fix some strict ANSI-C errors</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM32100E-EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100e_eval_cec.c: fix some strict ANSI-C errors<br></span></li></ul></ul>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.4.0 / 31-December-2010<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add new directory for STM32L152-EVAL board containing the following files:</span></li>
-              <ul>
-<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32l152_eval.h/.c, </span><span style="font-size: 10pt; font-family: Verdana;">stm32l152</span><span style="font-size: 10pt; font-family: Verdana;">_eval_lcd.h/.c, stm32l152_eval_glass_lcd.h</span><span style="font-size: 10pt; font-family: Verdana;">/.c, </span><span style="font-size: 10pt; font-family: Verdana;">stm32l152_eval_i2c_ee</span><span style="font-size: 10pt; font-family: Verdana;">.h/.c</span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add support for the STM32100E-EVAL Rev B: SPI FLASH CS pin "sFLASH_CS_PIN" changed from PB.02 to PE.06.</span></li>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100e_eval_lcd.h/.c: Add support for "LCD_ILI9325" LCD controller.</span></li>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100e_eval_fsmc_onenand.h/.c driver updated to correct asynchronous and synchronous read operations procedures.<br>
-                </span></li>
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">4.3.0
-- 10/15/2010</span></h3>
-            <ol style="margin-top: 0in;" start="1" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-            
-            <ul style="margin-top: 0in;" type="disc">
-
-              
-              
-              
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C EEPROM,&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">Temperature Sensor and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">IOE Expander</span><span style="font-size: 10pt; font-family: Verdana;"> drivers&nbsp;updated to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">use the DMA for read/write transfer and add more robustness</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SD Card (SDIO) driver updated to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">add more robustness</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SPI Flash and </span><span style="font-size: 10pt; font-family: Verdana;">SD Card (SPI) drivers: SPI MISO pin configuration changed to Input Floating&nbsp;</span></li>
-            </ul>
-
-
-            
-            <ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-
-            
-            
-
-            
-            <ul style="margin-top: 0in;" type="circle">
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add new directory for STM32100E-EVAL board containing the following files:</span></li>
-              <ul>
-                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100e_eval.h/.c,
-stm32100e_eval_lcd.h/.c, stm32100e_eval_cec.h/.c,
-stm32100e_eval_fsmc_onenand.h/.c, stm32100e_eval_fsmc_sram.h/.c,
-stm32100e_eval_ioe.h/.c</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
-              </ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Common</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_sdio_sd.c:
-Update the DMA End of Transfer Check loop inside the SD_ReadBlock(),
-SD_WriteBlock(), SD_ReadMultiBlocks() and SD_Write MultiBlocks().</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_i2c_ee.c/.h</span> <br>
-                </span></li></ul>
-              <ul>
-                <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Enhanced sEE_WaitEepromStandbyState() function for more robustness.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Enhanced Read and Write operations to manage I2C limitations.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add Timeout management with user callback implementation which allows recovering from I2C bus errors.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add
-critical sections user callbacks allowing to disable then enable
-interrupts when I2C operation require to be not interrupted.</span></li></ul></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_i2c_tsensor.c/.h</span> <br>
-                </span></li></ul>
-              <ul>
-                <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Enhanced I2C communication functions by using DMA for registers Read and Write operations.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add Timeout management with user callback implementation which allows recovering from I2C bus errors.</span></li></ul></ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM32100B_EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100b_eval.h: Add LM75 DMA defines.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32100b_eval_lcd.c: </span><span style="font-size: 10pt; font-family: Verdana;">Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.</span></li></ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM3210B_EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210b_eval.h: Add LM75 DMA defines.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210b_eval_lcd.c: </span><span style="font-size: 10pt; font-family: Verdana;">Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.</span></li></ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM3210C_EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210c_eval.h: Add EEPROM driver Timeout define.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210c_eval_lcd.c: </span><span style="font-size: 10pt; font-family: Verdana;">Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.</span></li></ul><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210c_eval_i2c_ioe.c</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Enhanced I2C communication functions by using DMA for registers Read and Write operations.</span></li></ul><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add Timeout management with user callback implementation which allows recovering from I2C bus errors.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">change IOE_I2C_SPEED from "400000" to "300000".</span></li></ul></ul>
-              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">STM3210E_EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval.c: change "void SD_WaitForDMAEndOfTransfer(void)" to "uint32_t SD_DMAEndOfTransferStatus(void)".</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval.h: Add LM75 DMA defines.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nand.h: remove "NAND_CMD_AREA_TRUE1" define.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nand.c: Update FSMC timing in NAND_Init() function to be aligned with AN2784 application note.</span></li></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nor.c</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">NOR</span><span style="font-size: 10pt; font-family: Verdana;">_Init()&nbsp;function: add FSMC_AsynchronousWait&nbsp;field&nbsp;to FSMC_NORSRAMInitStructure&nbsp;</span></li></ul></ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_sram.c<br>
-                </span></li></ul>
-              <ul>
-                <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update FSMC timing in SRAM_Init() function to be aligned with AN2784 application note.</span><br>
-                  <span style="font-size: 10pt; font-family: Verdana;"></span></li></ul>
-                <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">SRAM_Init()&nbsp;function: add FSMC_AsynchronousWait&nbsp;field&nbsp;to FSMC_NORSRAMInitStructure&nbsp;</span></li></ul>
-              </ul>
-              <ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_lcd.c</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">LCD_FSMCConfig() function: add FSMC_AsynchronousWait&nbsp;field&nbsp;to FSMC_NORSRAMInitStructure&nbsp;</span></li></ul></ul></ul>
-            <ul style="margin-top: 0in;" type="disc">
-
-            
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">4.2.0
-- 04/16/2010</span></h3>
-            <ol style="margin-top: 0in;" start="1" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-            
-            <ul style="margin-top: 0in;" type="disc">
-
-              
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C EEPROM driver
-update to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">use the DMA to
-perform&nbsp;data transfer&nbsp;to/from EEPROM memory.</span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-            
-            </ul>
-
-            <ol style="margin-top: 0in;" start="2" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-            <ul style="margin-top: 0in;" type="disc">
-              <ul style="margin-top: 0in;" type="circle">
-                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_i2c_ee.c</span>:
-updated to use the DMA to perform&nbsp;data transfer&nbsp;to/from
-EEPROM memory. For more details, refer to the description provided
-within this file.</span></li>
-                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm3210c_eval.c</span>: add low level
-functions to configure the DMA (needed for I2C EEPROM driver)<br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm3210c_eval_ioe.c</span>: add a delay
-in&nbsp;IOE_TS_GetState() function to wait till the end of ADC
-conversion</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm3210e_eval_fsmc_nor.c</span>: add </span><span style="font-size: 10pt; font-family: Verdana;">PD6 pin </span><span style="font-size: 10pt; font-family: Verdana;">configuration&nbsp;in
-NOR_Init() function</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm3210b_eval_lcd.c</span>: remove the
-second ";" from "static void PutPixel(int16_t x, int16_t y);;"&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              </ul>
-            </ul>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">4.1.0
-- 03/01/2010</span></h3>
-            <ol style="margin-top: 0in;" start="1" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-            </ol>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for the
-STMicroelectronics STM32100B-EVAL evaluation board. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-            </ul>
-            <ol style="margin-top: 0in;" start="2" type="1">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">Utilities</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-            </ol>
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><i><u><span style="font-size: 10pt; font-family: Verdana;">STM32_EVAL</span></u></i><u><span style="font-size: 10pt;"><o:p></o:p></span></u></li>
-            </ul>
-            <ul style="margin-top: 0in;" type="disc">
-              <ul style="margin-top: 0in;" type="circle">
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add new directory
-"Common" containing a common drivers for all STM32 evaluation boards:
-fonts.h/.c, stm32_eval_i2c_ee.h/.c, </span><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_spi_flash.h/.c,
-                  </span><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_i2c_tsensor.h/.c,
-                  </span><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_spi_sd.h/.c
-and </span><span style="font-size: 10pt; font-family: Verdana;">stm32_eval_sdio_sd.h/.c</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new driver for the
-STM32100B-EVAL managing Leds, push button and COM ports.</span></li>
-                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New HDMI CEC High level
-driver.</span><br>
-                </li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span>For all LCD drivers new fonts has
-been added.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">New FSMC memories
-drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, </span><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nor.h/.c
-and </span><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nand.h/.c.</span></li>
-              </ul>
-            </ul>
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-
-            <b><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.</span></b>
-            
-            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-            <hr align="center" size="2" width="100%"></span></div>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-            </td>
-          </tr>
-        </tbody>
-      </table>
-      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-      </td>
-    </tr>
-  </tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
-</div>
-
-</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c
deleted file mode 100644
index 947329d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides
-  *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SPI), SPI serial
-  *              flash (sFLASH) and temperature sensor (LM75)
-  *          available on STM32100B-EVAL evaluation board from STMicroelectronics. 
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm32100b_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */
-      
-/** @defgroup STM32100B_EVAL_LOW_LEVEL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SPI, serial flash (sFLASH) and temperature 
-  *        sensor (LM75) available on STM32100B-EVAL evaluation board from 
-  *        STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Variables
-  * @{
-  */ 
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
-                                 LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
-                                 LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
-                                 LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, 
-                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
-                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
-                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
-
-const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, 
-                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
-                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
-                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
-
-const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
-                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
-                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
-                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
-                                            TAMPER_BUTTON_EXTI_LINE, 
-                                            KEY_BUTTON_EXTI_LINE,
-                                            RIGHT_BUTTON_EXTI_LINE,
-                                            LEFT_BUTTON_EXTI_LINE,
-                                            UP_BUTTON_EXTI_LINE,
-                                            DOWN_BUTTON_EXTI_LINE,
-                                            SEL_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
-                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, 
-                                              KEY_BUTTON_EXTI_PORT_SOURCE,
-                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
-                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
-                                              UP_BUTTON_EXTI_PORT_SOURCE,
-                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
-                                              SEL_BUTTON_EXTI_PORT_SOURCE};
-								 
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
-                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, 
-                                             KEY_BUTTON_EXTI_PIN_SOURCE,
-                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
-                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
-                                             UP_BUTTON_EXTI_PIN_SOURCE,
-                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
-                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
-
-const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, 
-                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
-                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
-                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
- 
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
- 
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
- 
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures LED GPIO.
-  * @param  Led: Specifies the Led to be configured. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4
-  * @retval None
-  */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* Enable the GPIO_LED Clock */
-  RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
-  /* Configure the GPIO_LED pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Turns selected LED On.
-  * @param  Led: Specifies the Led to be set on. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];   
-}
-
-/**
-  * @brief  Turns selected LED Off.
-  * @param  Led: Specifies the Led to be set off. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4 
-  * @retval None
-  */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];   
-}
-
-/**
-  * @brief  Toggles the selected LED.
-  * @param  Led: Specifies the Led to be toggled. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Configures Button GPIO and EXTI Line.
-  * @param  Button: Specifies the Button to be configured.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button
-  * @param  Button_Mode: Specifies Button mode.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
-  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
-  *                     generation capability  
-  * @retval None
-  */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the BUTTON Clock */
-  RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Configure Button pin as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
-  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
-  if (Button_Mode == BUTTON_MODE_EXTI)
-  {
-    /* Connect Button EXTI Line to Button GPIO Pin */
-    GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
-    /* Configure Button EXTI line */
-    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
-    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
-    if(Button != BUTTON_WAKEUP)
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-    }
-    else
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-    }
-    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-    EXTI_Init(&EXTI_InitStructure);
-
-    /* Enable and set Button EXTI Interrupt to the lowest priority */
-    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-    NVIC_Init(&NVIC_InitStructure); 
-  }
-}
-
-/**
-  * @brief  Returns the selected Button state.
-  * @param  Button: Specifies the Button to be checked.
-  *   This parameter can be one of following parameters:    
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button    
-  * @retval The Button GPIO pin value.
-  */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
-  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-
-/**
-  * @brief  Configures COM port.
-  * @param  COM: Specifies the COM port to be configured.
-  *   This parameter can be one of following parameters:    
-  *     @arg COM1
-  *     @arg COM2  
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
-  *   contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
-
-
-  /* Enable UART clock */
-  if (COM == COM1)
-  {
-    RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
-  }
-  else
-  {
-    /* Enable the USART2 Pins Software Remapping */
-    GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-    RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-  }
-
-  /* Configure USART Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-
-  /* Configure USART Rx as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
-  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
-  /* USART configuration */
-  USART_Init(COM_USART[COM], USART_InitStruct);
-    
-  /* Enable USART */
-  USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
-  * @brief  DeInitializes the SD/SD communication.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
-  SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
-  
-  /*!< SD_SPI Periph clock disable */
-  RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); 
-
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the SD_SPI and CS pins.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  SPI_InitTypeDef   SPI_InitStructure;
-
-  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
-       and SD_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
-                         SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
-
-  /*!< SD_SPI Periph clock enable */
-  RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE); 
-
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< SD_SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SD_SPI, &SPI_InitStructure);
-  
-  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-/**
-  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< Disable the sFLASH_SPI  */
-  SPI_Cmd(sFLASH_SPI, DISABLE);
-  
-  /*!< DeInitializes the sFLASH_SPI */
-  SPI_I2S_DeInit(sFLASH_SPI);
-  
-  /*!< sFLASH_SPI Periph clock disable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO 
-       and sFLASH_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
-                         sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
-
-  /*!< sFLASH_SPI Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  DeInitializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< Disable LM75_I2C */
-  I2C_Cmd(LM75_I2C, DISABLE);
-  /*!< DeInitializes the LM75_I2C */
-  I2C_DeInit(LM75_I2C);
-  
-  /*!< LM75_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
-    
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the LM75_I2C..
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< LM75_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
-    
-  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
-       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
-                         LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
-  
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
-}
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */ 
-     
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h
deleted file mode 100644
index b6c4ccb..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains definitions for STM32100B_EVAL's Leds, push-buttons
-  *          COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C
-  *          hardware resources.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100B_EVAL_H
-#define __STM32100B_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL
-  * @{
-  */   
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Constants
-  * @{
-  */ 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_LED
-  * @{
-  */
-#define LEDn                             4
-#define LED1_PIN                         GPIO_Pin_6
-#define LED1_GPIO_PORT                   GPIOC
-#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOC  
-  
-#define LED2_PIN                         GPIO_Pin_7
-#define LED2_GPIO_PORT                   GPIOC
-#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC
-
-#define LED3_PIN                         GPIO_Pin_8  
-#define LED3_GPIO_PORT                   GPIOC
-#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOC  
-
-#define LED4_PIN                         GPIO_Pin_9  
-#define LED4_GPIO_PORT                   GPIOC
-#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOC  
-
-/**
-  * @}
-  */ 
-  
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_BUTTON
-  * @{
-  */  
-#define BUTTONn                          8
-
-/**
- * @brief Wakeup push-button
- */
-#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
-#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
-#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
-#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
-#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
-#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
-#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
-/**
- * @brief Tamper push-button
- */
-#define TAMPER_BUTTON_PIN                GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT          GPIOC
-#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
-/**
- * @brief Key push-button
- */
-#define KEY_BUTTON_PIN                   GPIO_Pin_9
-#define KEY_BUTTON_GPIO_PORT             GPIOB
-#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
-#define KEY_BUTTON_EXTI_LINE             EXTI_Line9
-#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
-#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
-#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
-/**
- * @brief Joystick Right push-button
- */
-#define RIGHT_BUTTON_PIN                 GPIO_Pin_1
-#define RIGHT_BUTTON_GPIO_PORT           GPIOE
-#define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOE
-#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line1
-#define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOE
-#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource1
-#define RIGHT_BUTTON_EXTI_IRQn           EXTI1_IRQn
-/**
- * @brief Joystick Left push-button
- */
-#define LEFT_BUTTON_PIN                  GPIO_Pin_0
-#define LEFT_BUTTON_GPIO_PORT            GPIOE
-#define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOE
-#define LEFT_BUTTON_EXTI_LINE            EXTI_Line0
-#define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOE
-#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource0
-#define LEFT_BUTTON_EXTI_IRQn            EXTI0_IRQn  
-/**
- * @brief Joystick Up push-button
- */
-#define UP_BUTTON_PIN                    GPIO_Pin_8
-#define UP_BUTTON_GPIO_PORT              GPIOD
-#define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOD
-#define UP_BUTTON_EXTI_LINE              EXTI_Line8
-#define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOD
-#define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource8
-#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  
-/**
- * @brief Joystick Down push-button
- */  
-#define DOWN_BUTTON_PIN                  GPIO_Pin_14
-#define DOWN_BUTTON_GPIO_PORT            GPIOD
-#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
-#define DOWN_BUTTON_EXTI_LINE            EXTI_Line14
-#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
-#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
-#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
-/**
- * @brief Joystick Sel push-button
- */
-#define SEL_BUTTON_PIN                   GPIO_Pin_12
-#define SEL_BUTTON_GPIO_PORT             GPIOD
-#define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOD
-#define SEL_BUTTON_EXTI_LINE             EXTI_Line12
-#define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOD
-#define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource12
-#define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn   
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_COM
-  * @{
-  */
-#define COMn                             2
-
-/**
- * @brief Definition for COM port1, connected to USART1
- */ 
-#define EVAL_COM1                        USART1
-#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
-#define EVAL_COM1_TX_PIN                 GPIO_Pin_9
-#define EVAL_COM1_TX_GPIO_PORT           GPIOA
-#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_RX_PIN                 GPIO_Pin_10
-#define EVAL_COM1_RX_GPIO_PORT           GPIOA
-#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_IRQn                   USART1_IRQn
-
-/**
- * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
- */ 
-#define EVAL_COM2                        USART2
-#define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
-#define EVAL_COM2_TX_PIN                 GPIO_Pin_5
-#define EVAL_COM2_TX_GPIO_PORT           GPIOD
-#define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
-#define EVAL_COM2_RX_PIN                 GPIO_Pin_6
-#define EVAL_COM2_RX_GPIO_PORT           GPIOD
-#define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
-#define EVAL_COM2_IRQn                   USART2_IRQn
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_SD_SPI
-  * @{
-  */
-/**
-  * @brief  SD SPI Interface pins
-  */
-#define SD_SPI                           SPI1
-#define SD_SPI_CLK                       RCC_APB2Periph_SPI1
-#define SD_SPI_SCK_PIN                   GPIO_Pin_5                  /* PA.05 */
-#define SD_SPI_SCK_GPIO_PORT             GPIOA                       /* GPIOA */
-#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOA
-#define SD_SPI_MISO_PIN                  GPIO_Pin_6                  /* PA.06 */
-#define SD_SPI_MISO_GPIO_PORT            GPIOA                       /* GPIOA */
-#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOA
-#define SD_SPI_MOSI_PIN                  GPIO_Pin_7                  /* PA.07 */
-#define SD_SPI_MOSI_GPIO_PORT            GPIOA                       /* GPIOA */
-#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOA
-#define SD_CS_PIN                        GPIO_Pin_12                 /* PC.12 */
-#define SD_CS_GPIO_PORT                  GPIOC                       /* GPIOC */
-#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOC
-#define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */
-#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
-#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
-  * @{
-  */
-/**
-  * @brief  M25P FLASH SPI Interface pins
-  */  
-#define sFLASH_SPI                       SPI1
-#define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
-#define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
-#define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
-#define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
-#define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
-#define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_CS_PIN                    GPIO_Pin_9                  /* PD.09 */
-#define sFLASH_CS_GPIO_PORT              GPIOD                       /* GPIOD */
-#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOD
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C
-  * @{
-  */
-/**
-  * @brief  LM75 Temperature Sensor I2C Interface pins
-  */  
-#define LM75_I2C                         I2C1
-#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
-#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
-#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
-#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
-#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
-#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
-#define LM75_I2C_DR                      ((uint32_t)0x40005410)
-
-#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
-#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
-#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
-#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
-#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
-/**
-  * @}
-  */     
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Functions
-  * @{
-  */ 
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
-void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void); 
-void sFLASH_LowLevel_DeInit(void);
-void sFLASH_LowLevel_Init(void); 
-void LM75_LowLevel_DeInit(void);
-void LM75_LowLevel_Init(void); 
-/**
-  * @}
-  */ 
-    
-#ifdef __cplusplus
-}
-#endif
-  
-#endif /* __STM32100B_EVAL_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c
deleted file mode 100644
index 3172b63..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c
+++ /dev/null
@@ -1,1722 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval_cec.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides all the STM32100B-EVAL HDMI-CEC firmware functions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32100b_eval_cec.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */
-  
-/** @defgroup STM32100B_EVAL_CEC
-  * @brief This file includes the CEC Stack driver for HDMI-CEC Module
-  *        of STM32100B-EVAL board.
-  * @{
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Defines
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Variables
-  * @{
-  */
-
-__IO uint32_t ReceivedFrame = 0;
-__IO uint32_t SendFrame = 0;
-__IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
-__IO uint8_t BufferPointer[15];
-__IO uint32_t ReceiveStatus = 0;
-__IO uint32_t SendStatus = 0;
-__IO uint8_t TransErrorCode = 0;
-__IO uint8_t RecepErrorCode = 0;
-__IO uint8_t MyLogicalAddress = 0;
-__IO uint16_t MyPhysicalAddress = 0;
-__IO uint8_t DeviceType = 0;
-#ifdef HDMI_CEC_USE_DDC
-__IO uint8_t pBuffer[256];
-__IO uint16_t NumByteToRead = 255;
-#endif
-__IO uint8_t CECDevicesNumber = 0;
-
-HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
-HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
-HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
-
-__IO uint8_t FeatureOpcode = 0;
-__IO uint8_t AbortReason = 0;
-__IO uint8_t DeviceCount = 0;
-
-HDMI_CEC_Map HDMI_CEC_MapStruct;
-HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
-
-/* CEC follower addresses */
-uint8_t* HDMI_CEC_Follower_String[13][2] =
-  {
-    {(uint8_t *)"         TV         ", (uint8_t *)"0"},
-    {(uint8_t *)"Recording Device 1  ", (uint8_t *)"0"},
-    {(uint8_t *)"Recording Device 2  ", (uint8_t *)"0"},
-    {(uint8_t *)"    Tuner 1         ", (uint8_t *)"0"},
-    {(uint8_t *)" Playback Device 1  ", (uint8_t *)"0"},
-    {(uint8_t *)"   Audio System     ", (uint8_t *)"0"},
-    {(uint8_t *)"    Tuner 2         ", (uint8_t *)"0"},
-    {(uint8_t *)"    Tuner 3         ", (uint8_t *)"0"},
-    {(uint8_t *)" Playback Device 2  ", (uint8_t *)"0"},
-    {(uint8_t *)"Recording Device 3  ", (uint8_t *)"0"},
-    {(uint8_t *)"      Tuner 4       ", (uint8_t *)"0"},
-    {(uint8_t *)" Playback Device 3  ", (uint8_t *)"0"},
-    {(uint8_t *)"     Broadcast      ", (uint8_t *)"1"}
-  };
-
-/**
-  * @}
-  */
-
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Function_Prototypes
-  * @{
-  */
-static HDMI_CEC_Error PhysicalAddressDiscovery(void);
-static HDMI_CEC_Error LogicalAddressAllocation(void);
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup STM32100B_EVAL_CEC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the HDMI CEC.
-  * @param  None
-  * @retval HDMI_CEC_Error: CEC Error code
-  */
-HDMI_CEC_Error HDMI_CEC_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  CEC_InitTypeDef CEC_InitStructure;
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  uint8_t sendcount = 0;
-
-#ifdef HDMI_CEC_USE_DDC
-  I2C_InitTypeDef  I2C_InitStructure;
-  /* Enable CEC_I2C clocks */
-  RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
-
-  /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
-  RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE);
-#endif
-
-  /* Enable CEC clocks */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
-
-  /* Enable CEC_LINE_GPIO clocks */
-  RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
-
-  /* Configure CEC_LINE_GPIO as Output open drain */
-  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
-
-#ifdef HDMI_CEC_USE_DDC
-  /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
-  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN;
-  GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
-
-/* This configuration is only when the HDMI CEC is configured as source.
-   The HDMI source has to provide the +5V Power signal to the sink. 
-   On STM32100B-EVAL borad, you have to solder the SB4 Solder bridge.
-   Then, the source will wait for HPD signal to be asserted from the sink.
-   Once the HPD signal is detected the source shall read the EDID structure 
-   throuhgh the DDC channel. */
-  /* Configure CEC_HPD_GPIO as Input pull down */
-  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
-  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
-
-
-/* This configuration is only when the HDMI CEC is configured as sink.
-   The HDMI sink has to wait for the +5V Power signal from the source. 
-   On STM32100B-EVAL borad, SB4 Solder bridge should be open (default configuration).
-   Then, the sink will assert the HPD signal to inform the source that the EDID
-   is ready for read through DDC channel. In this implementation, the EDID structure
-   is not implemented. */
-/*  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
-
-  HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */
-  
-  /* Enable CEC_I2C */
-  I2C_Cmd(HDMI_CEC_I2C, ENABLE);
-
-  /* I2C configuration */
-  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
-  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
-  I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
-  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
-  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-  I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED;
-  I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
-#endif
-
-  /* Physical Address discovery */
-  errorstatus = PhysicalAddressDiscovery();
-
-  if (errorstatus != HDMI_CEC_OK)
-  {
-    /* Device not connected (Physical Address lost) */
-    return(errorstatus);
-  }
-
-
-  /* CEC DeInit */
-  CEC_DeInit();
-
-  /* Configure CEC */
-  CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
-  CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
-  CEC_Init(&CEC_InitStructure);
-
-  /* Set Prescaler value for APB1 clock = 24MHz */
-  CEC_SetPrescaler(0x4AF);
-
-  /* Enable CEC */
-  CEC_Cmd(ENABLE);
-
-  /* Logical Address Allocation */
-  sendcount = 0;
-  errorstatus = LogicalAddressAllocation();
-
-  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-  {
-    sendcount++;
-    errorstatus = LogicalAddressAllocation();
-  }
-
-  if (errorstatus != HDMI_CEC_OK)
-  {
-    /* Device Unregistred */
-    return(errorstatus);
-  }
-
-  HDMI_CEC_CheckConnectedDevices();
-  
-  /* Set the CEC initiator address */
-  CEC_OwnAddressConfig(MyLogicalAddress);
-
-  /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
-  CEC_ITConfig(ENABLE);
-
-  /* Report physical address*/
-  errorstatus = HDMI_CEC_ReportPhysicalAddress();
-  sendcount = 0;
-
-  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-  {
-    sendcount++;
-    errorstatus = HDMI_CEC_ReportPhysicalAddress();
-  }
-
-  if (errorstatus != HDMI_CEC_OK)
-  {
-    /* Device Unregistred */
-    return(errorstatus);
-  }
-
-  return errorstatus;
-}
-
-/**
-  * @brief  Transmit message by taking  data from typedef struct CEC_Meassage
-  * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
-  *         the message to be sent.
-  * @retval HDMI_CEC_Error: CEC Error code
-  */
-HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  __IO uint32_t count = 0, j = 0;
-
-  SendFrame = 0;
-  SendStatus = 0;
-  TxCounter = 0;
-  BufferCount = 0;
-
-  HDMI_CEC_TX_MessageStructPrivate =  *HDMI_CEC_TX_MessageStructure;
-
-  /* Initialize BufferPointer */
-  for (j = 0; j < 15; j++)
-  {
-    BufferPointer[j] = 0;
-  }
-
-  BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
-
-  for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
-  {
-    BufferPointer[BufferCount] =  HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1];
-  }
-
-  CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-  /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
-  CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header);
-
-  /* Initiate Message Transmission */
-  CEC_StartOfMessage();
-
-  while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  if (SendStatus == 0)
-  {
-    errorstatus = (HDMI_CEC_Error) TransErrorCode;
-  }
-
-  return errorstatus;
-}
-
-
-/**
-  * @brief  Get the ESR register status.
-  * @param  None
-  * @retval HDMI_CEC_Error: CEC Error code
-  */
-HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-
-  /* Bit timing error case*/
-  if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET)
-  {
-    errorstatus = HDMI_CEC_BIT_TIMING;
-  }
-  /* Bit period error case */
-  if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET)
-  {
-    errorstatus = HDMI_CEC_BIT_PERIOD;
-  }
-  /* Recieve error case */
-  if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET)
-  {
-    errorstatus = HDMI_CEC_RX_BLOCK_FINISHED;
-  }
-  /* Start bit error case*/
-  if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET)
-  {
-    errorstatus = HDMI_CEC_START_BIT;
-  }
-  /* Acknowledge error case*/
-  if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET)
-  {
-    errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE;
-  }
-  /* Line error case */
-  if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET)
-  {
-    errorstatus = HDMI_CEC_LINE;
-  }
-  /* Transfert error case*/
-  if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET)
-  {
-    errorstatus = HDMI_CEC_TX_BLOCK_FINISHED;
-  }
-  /* Clear All errors */
-  CEC_ClearFlag(CEC_FLAG_RERR);
-  CEC_ClearFlag(CEC_FLAG_TERR);
-  return errorstatus;
-}
-
-/**
-  * @brief  Allows to process all the interrupts that are high.
-  * @param  None
-  * @retval None
-  */
-void HDMI_CEC_ProcessIRQSrc(void)
-{
-  /********************** Reception *********************************************/
-  /* Check if a reception error occured */
-  if (CEC_GetFlagStatus(CEC_FLAG_RERR))
-  {
-    /* Set receive status bit (Error) */
-    ReceiveStatus  = 0;
-    ReceivedFrame  = 1;
-    RecepErrorCode = HDMI_CEC_GetErrorStatus();
-    CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
-  }
-  else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
-  {
-    /* Check if the byte received is the last one of the message */
-    if (CEC_GetFlagStatus(CEC_FLAG_REOM))
-    {
-      HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
-      HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter;
-      ReceiveStatus = SUCCESS;
-      ReceivedFrame = 1;
-    }
-    /* Check if the byte received is a Header */
-    else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
-    {
-      ReceiveStatus = 0;
-      HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte();
-      RxCounter = 0;
-    }
-    /* Receive each byte except header in the reception buffer */
-    else
-    {
-      if (RxCounter != 0)
-      {
-        HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
-        RxCounter++;
-      }
-      else
-      {
-        HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte();
-        RxCounter++;
-      }
-      
-    }
-    /* Clear all reception flags */
-    CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
-  }
-
-  /********************** Transmission ******************************************/
-  /* Check if a transmission error occured */
-  if (CEC_GetFlagStatus(CEC_FLAG_TERR))
-  {
-    TransErrorCode = HDMI_CEC_GetErrorStatus();
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-    SendFrame = 1;
-    SendStatus = 0;
-  }
-  /* Check if end of message bit is set in the data to be transmitted */
-  else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
-  {
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
-    CEC_EndOfMessageCmd(DISABLE);
-    SendFrame = 1;
-    SendStatus = SUCCESS;
-  }
-  /* Check if data byte has been sent */
-  else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
-  {
-    /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */
-    if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
-    {
-      CEC_SendDataByte(BufferPointer[TxCounter]);
-      TxCounter++;
-      CEC_ClearFlag(CEC_FLAG_TBTRF);
-      CEC_EndOfMessageCmd(ENABLE);
-    }
-    else
-    {
-      /* Put the byte in the TX Buffer */
-      CEC_SendDataByte(BufferPointer[TxCounter]);
-      TxCounter++;
-      CEC_ClearFlag(CEC_FLAG_TBTRF);
-    }
-  }
-}
-
-/**
-  * @brief  Report physical address to all other devices thus allowing any
-            device to create a map of the network.
-  * @param  None
-  * @retval HDMI_CEC_Error: CEC Error code.
-  */
-HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  HDMI_CEC_Message HDMI_CEC_TX_Message;
-
-  HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
-  HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
-  HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
-  HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
-  HDMI_CEC_TX_Message.Operande[2] = DeviceType;
-  HDMI_CEC_TX_Message.TxMessageLength = 0x03;
-
-  errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
-
-  return  errorstatus;
-}
-
-/**
-  * @brief  Handle CEC command receive callback.
-  *         When receiving the STANDBY Opcode commande, the system is entred in
-  *         Stop mode and when wakeup, the PLL is configured as system clock and
-  *         the HSI is selected as PLL source.      
-  * @param  None
-  * @retval None
-  */
-void HDMI_CEC_CommandCallBack(void)
-{
-  uint8_t i = 0, sendcount = 0;
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  EXTI_InitTypeDef EXTI_InitStructure;
-
-  switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
-  {
-    case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
-      HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
-      HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
-      HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
-      HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
-      HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
-      HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
-      HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
-      HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t *)"1";
-      DeviceCount++;
-      break;
-
-    case HDMI_CEC_OPCODE_STANDBY:
-      /* CEC Line */
-      GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8);
-      /* Configure the CEC Line as EXTI Line on Falling Edge */
-      EXTI_ClearITPendingBit(EXTI_Line8);
-      EXTI_InitStructure.EXTI_Line = EXTI_Line8;
-      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-      EXTI_Init(&EXTI_InitStructure);
-      /* Request to enter Stop mode */
-      PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
-
-      /* Disable the CEC EXTI Line */
-      EXTI_InitStructure.EXTI_LineCmd = DISABLE;
-      EXTI_Init(&EXTI_InitStructure);
-      /* Configure the PLL Source */
-      RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
-
-      /* Enable PLL */ 
-      RCC_PLLCmd(ENABLE);
-
-      /* Wait till PLL is ready */
-      while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
-      {
-      }
-
-      /* Select PLL as system clock source */
-      RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-      /* Wait till PLL is used as system clock source */
-      while(RCC_GetSYSCLKSource() != 0x08)
-      {
-      }
-      break;
-
-    case HDMI_CEC_OPCODE_GET_CEC_VERSION:
-      /* Send the Used CEC version */
-      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
-      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
-      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
-      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-
-      /* Retransmit message until 5 time */
-      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-      {
-        sendcount++;
-        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-      }
-      break;
-
-    case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
-      /* Send the Physical address */
-      errorstatus = HDMI_CEC_ReportPhysicalAddress();
-      sendcount = 0;
-      /* Retransmit message until 5 time */
-      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-      {
-        sendcount++;
-        errorstatus = HDMI_CEC_ReportPhysicalAddress();
-      }
-      break;
-
-    case HDMI_CEC_OPCODE_FEATURE_ABORT:
-      /* The device doesn't support the requested message type, or that it cannot
-      execute it at the present time. */
-      FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
-      AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
-      break;
-
-    case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
-      /* Send the OSD name = STM32100B CEC*/
-      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
-      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
-      /* STM32100B*/
-      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x42;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
-      /* CEC */
-      HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
-      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
-      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-      sendcount = 0;
-      /* Retransmit message until 5 time */
-      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-      {
-        sendcount++;
-        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-      }
-      break;
-
-    case HDMI_CEC_OPCODE_ROUTING_CHANGE:
-      for (i = 0;i < 0x14;i++)
-      {
-        if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) &&
-            (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) &&
-            (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) &&
-            (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F))
-        {
-          HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
-          HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
-          HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
-        }
-      }
-      break;
-
-    default:
-      /* Send Abort feature*/
-      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
-      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
-      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */
-      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
-      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
-      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-      sendcount = 0;
-      /* Retransmit message until 5 time */
-      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
-      {
-        sendcount++;
-        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
-      }
-      break;
-
-  }
-}
-
-/**
-  * @brief  Check the connected CEC devices.
-  * @param  None
-  * @retval HDMI_CEC_Error
-  */
-HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  uint32_t count = 0, i = 1;
- 
-  /*----------------------------- TV device  ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x0);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[0][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Recording device 1 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x1);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[1][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-  /*----------------------------- Recording device 2 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x2);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[2][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Tuner 1 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x3);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-  /*----------------------------- Playback device 1 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x4);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Audio system ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x5);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Tuner 2 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x6);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Tuner 3 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x7);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Playback device 2 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x8);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  /*----------------------------- Recording device 3 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0x9);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-  /*----------------------------- Tuner 4 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0xA);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-  /*----------------------------- Playback device 3 ---------------------------*/
-  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
-
-  CEC_EndOfMessageCmd(ENABLE);
-
-  CEC_SendDataByte((MyLogicalAddress << 4) | 0xB);
-
-  /* Start of message */
-  CEC_StartOfMessage();
-
-  /* Wait till the header message is sent */
-  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-  {
-    count++;
-  }
-
-  if (count >= HDMI_CEC_TIMEOUT_VALUE)
-  {
-    errorstatus = HDMI_CEC_TIMEOUT;
-    return(errorstatus);
-  }
-
-  errorstatus = HDMI_CEC_GetErrorStatus();
-
-  if (errorstatus == HDMI_CEC_OK)
-  {
-    HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
-    i++;
-    errorstatus = HDMI_CEC_OK;
-  }
-  /* Clear CEC CSR register */
-  CEC_ClearFlag(CEC_FLAG_TBTRF);
-  CEC_EndOfMessageCmd(DISABLE);
-
-  CECDevicesNumber = i - 1;
-
-  return errorstatus;
-}
-
-/**
-  * @brief  Physical address discovery.
-  * @param  None
-  * @retval HDMI_CEC_Error: CEC Error code.
-  */
-static HDMI_CEC_Error PhysicalAddressDiscovery(void)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-#ifdef HDMI_CEC_USE_DDC
-  uint32_t index = 0, i = 0;
-#endif
-
-  /*------------------------------ Physical address discovery -----------------*/
-  if (HDMI_CEC_ROOT == 0x1)
-  {
-    MyPhysicalAddress = 0x0000;
-    /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
-       of the +5V power signal and the HPD should be well configured.
-       Implement here the EDID Structure to be sent to the HDMI source.
-       For more details please refer to the HDMI specification. 
-       The EDID structure should be sent to the device source using the DDC Channel
-       and using the HPD signal. */
-  }
-  else
-  {
-  
-#ifdef HDMI_CEC_USE_DDC  
-    /* The HDMI-CEC here is configured as source or as a repeater. The configuration
-       of the +5V power signal and the HPD should be well configured.
-       The source should wait for HPD and then read the EDID structure. */
-    while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET)
-    {
-    }
-    /* Wait for 100 ms after HPD was received */
-    for(i = 0; i < 0x5FFFF; i++)
-    {
-    }
-
-    /* Return the physical address using the I2C  by reading the 2 bytes 24 and
-      25 form the EDID */
-    /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */
-    /*!< While the bus is busy */
-    while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY))
-    {
-    }
-  
-    /*!< Send START condition */
-    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
-  
-    /*!< Test on EV5 and clear it */
-    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-    {
-    }
-   
-    /*!< Send EEPROM address for write */
-    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter);
- 
-
-    /*!< Test on EV6 and clear it */
-    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-    {
-    }
-
-    /*!< Send the EEPROM's internal address to read from: Only one byte address */
-    I2C_SendData(HDMI_CEC_I2C, 0x00);  
-
-    /*!< Test on EV8 and clear it */
-    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
-    {
-    }
-  
-    /*!< Send STRAT condition a second time */  
-    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
-  
-    /*!< Test on EV5 and clear it */
-    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-    {
-    }
-  
-    /*!< Send EEPROM address for read */
-    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver);
-  
-    /*!< Test on EV6 and clear it */
-    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
-    {
-    }
-
-    /* While there is data to be read */
-    while (NumByteToRead-- > 1)
-    {
-      while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
-      {
-      }
-      for(i = 0; i < 0xFFF; i++)
-      {
-      }
-      pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C);
-    }
-
-    /* Disable Acknowledgement */
-    I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE);
-
-    /* Send STOP Condition */
-    I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE);
-
-    while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED));
-    pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C);
-
-    /* Enable Acknowledgement to be ready for another reception */
-    I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE);
-    MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]);
-#else
-    MyPhysicalAddress = 0x1000;
-#endif
-  }
-
-  return errorstatus;
-}
-/**
-  * @brief  Allocate the logical address.
-  * @param  None
-  * @retval HDMI_CEC_Error: CEC Error code.
-  */
-static HDMI_CEC_Error LogicalAddressAllocation(void)
-{
-  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
-  uint32_t count = 0;
-
-  /*------------------ Logical address allocation -----------------------------*/
-  /* Get the device type */
-  /* Device type = CEC_TV */
-  if (DeviceType == HDMI_CEC_TV)
-  {
-    if (HDMI_CEC_ROOT)
-    {
-      MyLogicalAddress = 0x00;
-    }
-    else
-    {
-      CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
-
-      CEC_EndOfMessageCmd(ENABLE);
-
-      CEC_SendDataByte(0xEE);
-
-      /* Start of message */
-      CEC_StartOfMessage();
-
-      /* Wait till the polling message is sent */
-      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-      {
-        count++;
-      }
-
-      if (count >= HDMI_CEC_TIMEOUT_VALUE)
-      {
-        errorstatus = HDMI_CEC_TIMEOUT;
-        return(errorstatus);
-      }
-
-      errorstatus = HDMI_CEC_GetErrorStatus();
-
-      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-      {
-        MyLogicalAddress = 0x0E;
-        errorstatus = HDMI_CEC_OK;
-      }
-      else if (errorstatus == HDMI_CEC_OK)
-      {
-        MyLogicalAddress = 0x0F;
-        errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
-      }
-    }
-    /* Clear CEC CSR register */
-    CEC_ClearFlag(CEC_FLAG_TBTRF);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-
-  /* Device type = CEC_RECORDING */
-  if (DeviceType == HDMI_CEC_RECORDING)
-  {
-    CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
-
-    CEC_EndOfMessageCmd(ENABLE);
-
-    CEC_SendDataByte(0x11);
-
-    /* Start of message */
-    CEC_StartOfMessage();
-
-    /* Wait till the header message is sent */
-    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-    {
-      count++;
-    }
-
-    if (count >= HDMI_CEC_TIMEOUT_VALUE)
-    {
-      errorstatus = HDMI_CEC_TIMEOUT;
-      return(errorstatus);
-    }
-
-    errorstatus = HDMI_CEC_GetErrorStatus();
-
-    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-    {
-      MyLogicalAddress = 0x01;
-      errorstatus = HDMI_CEC_OK;
-    }
-    else if (errorstatus == HDMI_CEC_OK)
-    {
-      /* Clear CEC CSR register */
-      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-      CEC_EndOfMessageCmd(DISABLE);
-
-      CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
-
-      CEC_EndOfMessageCmd(ENABLE);
-
-      CEC_SendDataByte(0x22);
-
-      /* Start of message */
-      CEC_StartOfMessage();
-
-      count = 0;
-
-      /* Wait till the header message is sent */
-      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-      {
-        count++;
-      }
-
-      if (count >= HDMI_CEC_TIMEOUT_VALUE)
-      {
-        errorstatus = HDMI_CEC_TIMEOUT;
-        return(errorstatus);
-      }
-      errorstatus = HDMI_CEC_GetErrorStatus();
-
-      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-      {
-        MyLogicalAddress = 0x02;
-        errorstatus = HDMI_CEC_OK;
-      }
-      else if (errorstatus == HDMI_CEC_OK)
-      {
-        /* Clear CEC CSR register */
-        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-        CEC_EndOfMessageCmd(DISABLE);
-
-        CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
-
-        CEC_EndOfMessageCmd(ENABLE);
-
-        CEC_SendDataByte(0x99);
-
-        /* Start of message */
-        CEC_StartOfMessage();
-
-        count = 0;
-
-        /* Wait till the header message is sent */
-        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-        {
-          count++;
-        }
-
-        if (count >= HDMI_CEC_TIMEOUT_VALUE)
-        {
-          errorstatus = HDMI_CEC_TIMEOUT;
-          return(errorstatus);
-        }
-        errorstatus = HDMI_CEC_GetErrorStatus();
-
-        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-        {
-          MyLogicalAddress = 0x09;
-          errorstatus = HDMI_CEC_OK;
-        }
-        else if (errorstatus == HDMI_CEC_OK)
-        {
-          MyLogicalAddress = 0x0F;
-          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
-        }
-      }
-    }
-    /* Clear CEC CSR register */
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-
-  /* Device type = CEC_TUNER */
-  if (DeviceType == HDMI_CEC_TUNER)
-  {
-    CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
-
-    CEC_EndOfMessageCmd(ENABLE);
-
-    CEC_SendDataByte(0x33);
-
-    /* Start of message */
-    CEC_StartOfMessage();
-
-    count = 0;
-
-    /* Wait till the header message is sent */
-    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-    {
-      count++;
-    }
-
-    if (count >= HDMI_CEC_TIMEOUT_VALUE)
-    {
-      errorstatus = HDMI_CEC_TIMEOUT;
-      return(errorstatus);
-    }
-    errorstatus = HDMI_CEC_GetErrorStatus();
-
-    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-    {
-      MyLogicalAddress = 0x03;
-      errorstatus = HDMI_CEC_OK;
-    }
-    else if (errorstatus == HDMI_CEC_OK)
-    {
-      /* Clear CEC CSR register */
-      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-      CEC_EndOfMessageCmd(DISABLE);
-
-      CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
-
-      CEC_EndOfMessageCmd(ENABLE);
-
-      CEC_SendDataByte(0x66);
-
-      /* Start of message */
-      CEC_StartOfMessage();
-
-      count = 0;
-
-      /* Wait till the header message is sent */
-      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-      {
-        count++;
-      }
-
-      if (count >= HDMI_CEC_TIMEOUT_VALUE)
-      {
-        errorstatus = HDMI_CEC_TIMEOUT;
-        return(errorstatus);
-      }
-      errorstatus = HDMI_CEC_GetErrorStatus();
-
-      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-      {
-        MyLogicalAddress = 0x06;
-        errorstatus = HDMI_CEC_OK;
-      }
-      else if (errorstatus == HDMI_CEC_OK)
-      {
-        /* Clear CEC CSR register */
-        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-        CEC_EndOfMessageCmd(DISABLE);
-
-        CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
-
-        CEC_EndOfMessageCmd(ENABLE);
-
-        CEC_SendDataByte(0x77);
-
-        /* Start of message */
-        CEC_StartOfMessage();
-
-        count = 0;
-
-        /* Wait till the header message is sent */
-        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-        {
-          count++;
-        }
-
-        if (count >= HDMI_CEC_TIMEOUT_VALUE)
-        {
-          errorstatus = HDMI_CEC_TIMEOUT;
-          return(errorstatus);
-        }
-        errorstatus = HDMI_CEC_GetErrorStatus();
-
-        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-        {
-          MyLogicalAddress = 0x07;
-          errorstatus = HDMI_CEC_OK;
-        }
-        else if (errorstatus == HDMI_CEC_OK)
-        {
-          /* Clear CEC CSR register */
-          CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-          CEC_EndOfMessageCmd(DISABLE);
-
-          CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
-
-          CEC_EndOfMessageCmd(ENABLE);
-
-          CEC_SendDataByte(0xAA);
-
-          /* Start of message */
-          CEC_StartOfMessage();
-
-          count = 0;
-
-          /* Wait till the header message is sent */
-          while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-          {
-            count++;
-          }
-
-          if (count >= HDMI_CEC_TIMEOUT_VALUE)
-          {
-            errorstatus = HDMI_CEC_TIMEOUT;
-            return(errorstatus);
-          }
-          errorstatus = HDMI_CEC_GetErrorStatus();
-
-          if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-          {
-            MyLogicalAddress = 0x0A;
-            errorstatus = HDMI_CEC_OK;
-          }
-          else if (errorstatus == HDMI_CEC_OK)
-          {
-            MyLogicalAddress = 0x0F;
-            errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
-          }
-        }
-      }
-    }
-    /* Clear CEC CSR register */
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-
-  /* Device type = CEC_PLAYBACK */
-  if (DeviceType == HDMI_CEC_PLAYBACK)
-  {
-    CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
-
-    CEC_EndOfMessageCmd(ENABLE);
-
-    CEC_SendDataByte(0x44);
-
-    /* Start of message */
-    CEC_StartOfMessage();
-
-    count = 0;
-
-    /* Wait till the header message is sent */
-    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-    {
-      count++;
-    }
-
-    if (count >= HDMI_CEC_TIMEOUT_VALUE)
-    {
-      errorstatus = HDMI_CEC_TIMEOUT;
-      return(errorstatus);
-    }
-
-    errorstatus = HDMI_CEC_GetErrorStatus();
-
-    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-    {
-      MyLogicalAddress = 0x04;
-      errorstatus = HDMI_CEC_OK;
-    }
-    else if (errorstatus == HDMI_CEC_OK)
-    {
-      /* Clear CEC CSR register */
-      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-      CEC_EndOfMessageCmd(DISABLE);
-
-      CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
-
-      CEC_EndOfMessageCmd(ENABLE);
-
-      CEC_SendDataByte(0x88);
-
-      /* Start of message */
-      CEC_StartOfMessage();
-
-      count = 0;
-
-      /* Wait till the header message is sent */
-      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-      {
-        count++;
-      }
-
-      if (count >= HDMI_CEC_TIMEOUT_VALUE)
-      {
-        errorstatus = HDMI_CEC_TIMEOUT;
-        return(errorstatus);
-      }
-      errorstatus = HDMI_CEC_GetErrorStatus();
-
-      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-      {
-        MyLogicalAddress = 0x08;
-        errorstatus = HDMI_CEC_OK;
-      }
-      else if (errorstatus == HDMI_CEC_OK)
-      {
-        /* Clear CEC CSR register */
-        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-
-        CEC_EndOfMessageCmd(DISABLE);
-
-        CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
-
-        CEC_EndOfMessageCmd(ENABLE);
-
-        CEC_SendDataByte(0xBB);
-
-        /* Start of message */
-        CEC_StartOfMessage();
-
-        count = 0;
-
-        /* Wait till the header message is sent */
-        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-        {
-          count++;
-        }
-
-        if (count >= HDMI_CEC_TIMEOUT_VALUE)
-        {
-          errorstatus = HDMI_CEC_TIMEOUT;
-          return(errorstatus);
-        }
-
-        errorstatus = HDMI_CEC_GetErrorStatus();
-
-        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-        {
-          MyLogicalAddress = 0x0B;
-          errorstatus = HDMI_CEC_OK;
-        }
-        else if (errorstatus == HDMI_CEC_OK)
-        {
-          MyLogicalAddress = 0x0F;
-          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
-        }
-      }
-    }
-
-    /* Clear CEC CSR register */
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-
-  /* Device type = CEC Audio System */
-  if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
-  {
-    CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
-
-    CEC_EndOfMessageCmd(ENABLE);
-
-    CEC_SendDataByte(0x55);
-
-    /* Start of message */
-    CEC_StartOfMessage();
-
-    count = 0;
-
-    /* Wait till the header message is sent */
-    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
-    {
-      count++;
-    }
-
-    if (count >= HDMI_CEC_TIMEOUT_VALUE)
-    {
-      errorstatus = HDMI_CEC_TIMEOUT;
-      return(errorstatus);
-    }
-
-    errorstatus = HDMI_CEC_GetErrorStatus();
-
-    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
-    {
-      MyLogicalAddress = 0x05;
-      errorstatus = HDMI_CEC_OK;
-    }
-    else if (errorstatus == HDMI_CEC_OK)
-    {
-      MyLogicalAddress = 0x0F;
-      errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
-    }
-
-    /* Clear CEC CSR register */
-    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
-    CEC_EndOfMessageCmd(DISABLE);
-  }
-
-  return errorstatus;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h
deleted file mode 100644
index 4bec71a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval_cec.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32100b_eval_cec
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100B_EVAL_CEC_H
-#define __STM32100B_EVAL_CEC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-  /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */  
-
-/** @defgroup STM32100B_EVAL_CEC
-  * @{
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Exported_Types
-  * @{
-  */
-typedef enum
-{
-  HDMI_CEC_BIT_TIMING              = (1), /*!< CEC Bit Timing Error */
-  HDMI_CEC_BIT_PERIOD              = (2), /*!< CEC Bit Period Error */
-  HDMI_CEC_RX_BLOCK_FINISHED       = (3), /*!< CEC Receive Block finished Error */
-  HDMI_CEC_START_BIT               = (4), /*!< CEC Start Bit Error */
-  HDMI_CEC_BLOCK_ACKNOWLEDGE       = (5), /*!< CEC Block Acknowledge Error */
-  HDMI_CEC_LINE                    = (6), /*!< CEC Line Error */
-  HDMI_CEC_TX_BLOCK_FINISHED       = (7), /*!< CEC Transmit Block Transfer finished Error */
-  HDMI_CEC_DEVICE_UNREGISTRED      = (8), /*!< CEC Device Unregistred */
-  HDMI_CEC_TIMEOUT                 = (9), /*!< CEC TimeOut */
-  HDMI_CEC_OK                      = (10)  /*!< CEC OK */
-}HDMI_CEC_Error;
-
-typedef struct
-{
-  __IO uint8_t PhysicalAddress_A;
-  __IO uint8_t PhysicalAddress_B;
-  __IO uint8_t PhysicalAddress_C;
-  __IO uint8_t PhysicalAddress_D;
-  __IO uint8_t LogicalAddress;
-  __IO uint8_t DeviceType;
-}HDMI_CEC_Map;
-
-
-#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
-#define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
-
-/**
-* @brief  CEC Init Structure definition
-*/
-typedef struct
-{
-  __IO uint8_t Header;
-  __IO uint8_t Opcode;
-  __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
-  __IO uint8_t TxMessageLength;
-  __IO uint8_t RxMessageLength;
-}HDMI_CEC_Message;
-
-/**
-* @}
-*/
-
-/** @defgroup STM32100B_EVAL_CEC_Exported_Constants
-  * @{
-  */
-
-/**
-  * @brief CEC device types
-  */
-#define HDMI_CEC_TV                                         0x00
-#define HDMI_CEC_RECORDING                                  0x01
-#define HDMI_CEC_TUNER                                      0x03
-#define HDMI_CEC_PLAYBACK                                   0x04
-#define HDMI_CEC_AUDIOSYSTEM                                0x05
-
-
-/**
-  * @brief  HDMI CEC I2C Interface pins
-  */
-#define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_10
-#define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_11
-#define HDMI_CEC_I2C_GPIO_PORT                              GPIOB
-#define HDMI_CEC_I2C_GPIO_CLK                               RCC_APB2Periph_GPIOB
-#define HDMI_CEC_I2C                                        I2C2
-#define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C2
-
-/**
-  * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
-  */
-#define HDMI_CEC_HPD_PIN                                    GPIO_Pin_12
-#define HDMI_CEC_HPD_GPIO_PORT                              GPIOB
-#define HDMI_CEC_HPD_GPIO_CLK                               RCC_APB2Periph_GPIOB
-
-/**
-  * @brief  HDMI CEC Interface pin
-  */
-#define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
-#define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
-#define HDMI_CEC_LINE_GPIO_CLK                              RCC_APB2Periph_GPIOB
-
-#define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
-#define HDMI_CEC_I2C_CLOCK_SPEED                            100000
-
-/**
-  * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
-  *         If you want to configure the STM32100B-EVAL board as CEC Root (Sink)
-  *         change the following define to 0x1    
-  */
-#define HDMI_CEC_ROOT                                       0x00
-
-/**
-  * @brief  To select if the DDC Channel will be used for physical address discovery
-  *         or not. To use the DDC Channel to read the EDID structure uncomment
-  *         the following line.   
-  *         If the device is configured as HMDI source it should read his own physical
-  *         address from the sink that is connected to.         
-  */
-/* #define HDMI_CEC_USE_DDC */                                    
-
-/**
-  * @brief  CEC version: V1.3a
-  */
-#define HDMI_CEC_VERSION                                    0x04
-
-/**
-  * @brief  Reason for Abort feature
-  */
-#define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
-#define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
-#define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
-#define HDMI_CEC_INVALID_OPERAND                            0x03
-#define HDMI_CEC_REFUSED                                    0x04
-
-/**
-  * @brief  HDMI CEC specific commands
-  */
-#define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
-#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
-#define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
-#define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
-#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
-#define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
-#define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
-#define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
-#define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
-#define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
-#define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
-#define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
-#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
-#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
-#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
-#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
-#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
-#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
-#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
-#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
-#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
-#define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
-#define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
-#define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
-#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
-#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
-#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
-#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
-#define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
-#define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
-#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
-#define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
-#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
-#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
-#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
-#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
-#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
-#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
-#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
-#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
-#define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
-#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
-#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
-#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
-#define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
-#define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
-#define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
-#define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
-#define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
-#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
-#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
-#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
-#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
-#define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
-#define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
-#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
-#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
-#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
-#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
-#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
-#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
-#define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Exported_Macros
-  * @{
-  */
-/* HDMI_CEC_HPD: HDMI HPD pin low  */
-#define HDMI_CEC_HPD_LOW()       GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
-/* HDMI_CEC_HPD: HDMI HPD pin high  */
-#define HDMI_CEC_HPD_HIGH()      GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
-
-/**
-  * @}
-  */
-
-/** @defgroup STM32100B_EVAL_CEC_Exported_Functions
-  * @{
-  */
-HDMI_CEC_Error HDMI_CEC_Init(void);
-HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
-HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
-void HDMI_CEC_ProcessIRQSrc(void);
-HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
-void HDMI_CEC_CommandCallBack(void);
-HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32100B_EVAL_CEC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c
deleted file mode 100644
index bbf774d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c
+++ /dev/null
@@ -1,1875 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
-  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
-  *          Liquid Crystal Display Module of STM32100B-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32100b_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */
-    
-/** @defgroup STM32100B_EVAL_LCD 
-  * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
-  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
-  *          Liquid Crystal Display Module of STM32100B-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Defines
-  * @{
-  */ 
-#define LCD_ILI9320        0x9320
-#define LCD_HX8312         0x8312
-#define LCD_SPFD5408       0x5408
-#define START_BYTE         0x70
-#define SET_INDEX          0x00
-#define READ_STATUS        0x01
-#define LCD_WRITE_REG      0x02
-#define LCD_READ_REG       0x03
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Macros
-  * @{
-  */ 
-#define ABS(X)  ((X) > 0 ? (X) : -(X))  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-static __IO uint32_t LCDType = LCD_ILI9320;
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Function_Prototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(vu32 nCount);
-#endif /* USE_Delay*/
-
-static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue);
-static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /*!< LCD_SPI disable */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  
-  /*!< LCD_SPI DeInit */
-  SPI_I2S_DeInit(LCD_SPI);
-   
-  /*!< Disable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-    
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Configure NWR(RNW), RS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
-  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
-  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);  
-   
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Setups the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_Setup(void)
-{ 
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-  
-/* Configure the LCD_SPI interface ----------------------------------------------*/
-  LCD_SPIConfig();
-  
-  if(LCDType == LCD_ILI9320)
-  {
-    _delay_(5); /* Delay 50 ms */
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
-    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0006);
-    LCD_WriteReg(LCD_REG_49, 0x0101);
-    LCD_WriteReg(LCD_REG_50, 0x0003);
-    LCD_WriteReg(LCD_REG_53, 0x0106);
-    LCD_WriteReg(LCD_REG_54, 0x0b02);
-    LCD_WriteReg(LCD_REG_55, 0x0302);
-    LCD_WriteReg(LCD_REG_56, 0x0707);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0600);
-    LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_SPFD5408)
-  {   
-    /* Start Initial Sequence --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
-    /* Power On sequence -------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */  
-    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    _delay_(5);                  /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
-    _delay_(5);                 /* Delay 50 ms */ 
-    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0007);
-    LCD_WriteReg(LCD_REG_49, 0x0302);
-    LCD_WriteReg(LCD_REG_50, 0x0105);
-    LCD_WriteReg(LCD_REG_53, 0x0206);
-    LCD_WriteReg(LCD_REG_54, 0x0808);
-    LCD_WriteReg(LCD_REG_55, 0x0206);
-    LCD_WriteReg(LCD_REG_56, 0x0504);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0105);
-    LCD_WriteReg(LCD_REG_61, 0x0808);
-    /* Set GRAM area -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
-    /* Partial Display Control -------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1
-       I/D=01 (Horizontal : increment, Vertical : decrement)
-       AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    /* Enable the LCD Oscillator ---------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x10);
-    LCD_WriteReg(LCD_REG_0, 0xA0);
-    LCD_WriteReg(LCD_REG_3, 0x01);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_3, 0x00);
-    LCD_WriteReg(LCD_REG_43, 0x04);
-  
-    LCD_WriteReg(LCD_REG_40, 0x18);
-    LCD_WriteReg(LCD_REG_26, 0x05);
-    LCD_WriteReg(LCD_REG_37, 0x05);
-    LCD_WriteReg(LCD_REG_25, 0x00);
-    
-    /* LCD Power On ----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_28, 0x73);
-    LCD_WriteReg(LCD_REG_36, 0x74);
-    LCD_WriteReg(LCD_REG_30, 0x01);
-    LCD_WriteReg(LCD_REG_24, 0xC1);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_24, 0xE1);
-    LCD_WriteReg(LCD_REG_24, 0xF1);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_24, 0xF5);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_27, 0x09);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_31, 0x11);
-    LCD_WriteReg(LCD_REG_32, 0x0E);
-    LCD_WriteReg(LCD_REG_30, 0x81);
-    _delay_(1); /* Delay 10 ms */
-    
-    /* Chip Set --------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_157, 0x00);
-    LCD_WriteReg(LCD_REG_192, 0x00);
-   
-    LCD_WriteReg(LCD_REG_14, 0x00);
-    LCD_WriteReg(LCD_REG_15, 0x00);
-    LCD_WriteReg(LCD_REG_16, 0x00);
-    LCD_WriteReg(LCD_REG_17, 0x00);
-    LCD_WriteReg(LCD_REG_18, 0x00);
-    LCD_WriteReg(LCD_REG_19, 0x00);
-    LCD_WriteReg(LCD_REG_20, 0x00);
-    LCD_WriteReg(LCD_REG_21, 0x00);
-    LCD_WriteReg(LCD_REG_22, 0x00);
-    LCD_WriteReg(LCD_REG_23, 0x00);
-   
-    LCD_WriteReg(LCD_REG_52, 0x01);
-    LCD_WriteReg(LCD_REG_53, 0x00);
-    LCD_WriteReg(LCD_REG_75, 0x00);
-    LCD_WriteReg(LCD_REG_76, 0x00);
-    LCD_WriteReg(LCD_REG_78, 0x00);
-    LCD_WriteReg(LCD_REG_79, 0x00);
-    LCD_WriteReg(LCD_REG_80, 0x00);
-  
-    LCD_WriteReg(LCD_REG_60, 0x00);
-    LCD_WriteReg(LCD_REG_61, 0x00);
-    LCD_WriteReg(LCD_REG_62, 0x01);
-    LCD_WriteReg(LCD_REG_63, 0x3F);
-    LCD_WriteReg(LCD_REG_64, 0x02);
-    LCD_WriteReg(LCD_REG_65, 0x02);
-    LCD_WriteReg(LCD_REG_66, 0x00);
-    LCD_WriteReg(LCD_REG_67, 0x00);
-    LCD_WriteReg(LCD_REG_68, 0x00);
-    LCD_WriteReg(LCD_REG_69, 0x00);
-    LCD_WriteReg(LCD_REG_70, 0xEF);
-    LCD_WriteReg(LCD_REG_71, 0x00);
-    LCD_WriteReg(LCD_REG_72, 0x00);
-    LCD_WriteReg(LCD_REG_73, 0x01);
-    LCD_WriteReg(LCD_REG_74, 0x3F);
-  
-    LCD_WriteReg(LCD_REG_29, 0x08);  /* R29:Gate scan direction setting */
-  
-    LCD_WriteReg(LCD_REG_134, 0x00);
-    LCD_WriteReg(LCD_REG_135, 0x30);
-    LCD_WriteReg(LCD_REG_136, 0x02);
-    LCD_WriteReg(LCD_REG_137, 0x05);
-  
-    LCD_WriteReg(LCD_REG_141, 0x01);  /* R141:Register set-up mode for one line clock */
-    LCD_WriteReg(LCD_REG_139, 0x20);  /* R139:One line SYSCLK number in one-line */
-    LCD_WriteReg(LCD_REG_51, 0x01);  /* R51:N line inversion setting */
-    LCD_WriteReg(LCD_REG_55, 0x01);  /* R55:Scanning method setting */
-    LCD_WriteReg(LCD_REG_118, 0x00);
-   
-    /* Gamma Set -------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_143, 0x10);
-    LCD_WriteReg(LCD_REG_144, 0x67);
-    LCD_WriteReg(LCD_REG_145, 0x07);
-    LCD_WriteReg(LCD_REG_146, 0x65);
-    LCD_WriteReg(LCD_REG_147, 0x07);
-    LCD_WriteReg(LCD_REG_148, 0x01);
-    LCD_WriteReg(LCD_REG_149, 0x76);
-    LCD_WriteReg(LCD_REG_150, 0x56);
-    LCD_WriteReg(LCD_REG_151, 0x00);
-    LCD_WriteReg(LCD_REG_152, 0x06);
-    LCD_WriteReg(LCD_REG_153, 0x03);
-    LCD_WriteReg(LCD_REG_154, 0x00);
-  
-    /* Display On ------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04);
-    LCD_WriteReg(LCD_REG_0, 0x80);
-    LCD_WriteReg(LCD_REG_59, 0x01);
-    _delay_(4);  /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_0, 0x20);
-  }  
-}
-
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM32100B_LCD_Init(void)
-{
-  /* Setups the LCD */
-  LCD_Setup();
-  /* Try to read new LCD controller ID 0x9320 */
-  if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320)
-  {
-    LCDType = LCD_ILI9320;
-  }
-  else
-  {
-    LCDType = LCD_SPFD5408;
-    /* Setups the LCD */
-    LCD_Setup();
-    /* Try to read new LCD controller ID 0x5408 */
-    if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408)
-    {
-      LCDType = LCD_HX8312;
-      /* Setups the LCD */
-      LCD_Setup();
-    }
-  }
-  LCD_SetFont(&LCD_DEFAULT_FONT);
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-  for(index = 0; index < 76800; index++)
-  {
-    LCD_WriteRAM(Color);
-  }
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-  }  
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteReg(LCD_REG_32, Xpos);
-    LCD_WriteReg(LCD_REG_33, Ypos);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteReg(LCD_REG_66, Xpos);
-    LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF));
-  }
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    }
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-    }  
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Horizontal GRAM Start Address */
-    if(Xpos >= Height)
-    {
-      LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-    }
-    else
-    {
-      LCD_WriteReg(LCD_REG_80, 0);
-    }
-    /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_81, Xpos);
-    /* Vertical GRAM Start Address */
-    if(Ypos >= Width)
-    {
-      LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-    }  
-    else
-    {
-      LCD_WriteReg(LCD_REG_82, 0);
-    }
-    /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_83, Ypos);
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    LCD_WriteReg(LCD_REG_1, 0xD0);
-    LCD_WriteReg(LCD_REG_5, 0x14);
-  
-    LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1));
-    LCD_WriteReg(LCD_REG_70, Xpos);
- 
-    LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF));
-    LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF));
-  }
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04); 
-  }
-    
-}
-
-/**
-  * @brief  Displays a line.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Length: line length.
-  * @param  Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  if(Direction == LCD_DIR_HORIZONTAL)
-  { 
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    }
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-    }
-  }
-  else
-  {
-   for(i = 0; i < Length; i++)
-    {
-      if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-      {
-        LCD_WriteRAMWord(TextColor);
-      }
-      else  if(LCDType == LCD_HX8312)
-      {
-        LCD_WriteRAM(TextColor);
-      }
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-}
-
-#ifdef USE_LCD_DrawBMP 
-/**
-  * @brief  Displays a bitmap picture loaded in the SPI Flash.
-  * @param  BmpAddress: Bmp picture address in the SPI Flash.
-  * @retval None
-  */
-void LCD_DrawBMP(uint32_t BmpAddress)
-{
-  uint32_t i = 0, size = 0;
-  /* Read bitmap size */
-  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
-  /* get bitmap data address offset */
-  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
-  
-  size = (size - i)/2;
-  sFLASH_StartReadSequence(BmpAddress + i);
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 16-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-  
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1008);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-  
-  /* Read bitmap data from SPI Flash and send them to LCD */
-  for(i = 0; i < size; i++)
-  {
-    LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
-  }
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-
-  /* Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 8-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-    /* AM = 1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-  }
-}
-#endif /* USE_LCD_DrawBMP */
- 
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Reset LCD control line(/CS) and Send Start-Byte
-  * @param  Start_Byte: the Start-Byte to be sent
-  * @retval None
-  */
-void LCD_nCS_StartByte(uint8_t Start_Byte)
-{
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-
-  SPI_I2S_SendData(LCD_SPI, Start_Byte);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Writes index to select the LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval None
-  */
-void LCD_WriteRegIndex(uint8_t LCD_Reg)
-{
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | SET_INDEX);
-
-  /* Write 16-bit Reg Index (High Byte is 0) */
-  SPI_I2S_SendData(LCD_SPI, 0x00);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_I2S_SendData(LCD_SPI, LCD_Reg);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD ILI9320 register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index (then Write Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-
-  /* Write 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-
-  SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  uint16_t tmp = 0;
-  uint8_t i = 0;
-  
-  /* LCD_SPI prescaler: 4 */
-  LCD_SPI->CR1 &= 0xFFC7;
-  LCD_SPI->CR1 |= 0x0008;
-  /* Write 16-bit Index (then Read Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Read 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
-  
-  for(i = 0; i < 5; i++)
-  {
-    SPI_I2S_SendData(LCD_SPI, 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-    /* One byte of invalid dummy data read after the start byte */
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-    {    
-    }
-    SPI_I2S_ReceiveData(LCD_SPI); 
-  }
-
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-
-  /* Read upper byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  tmp = SPI_I2S_ReceiveData(LCD_SPI);
-  
-  
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-
-  tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-
-  /* LCD_SPI prescaler: 2 */
-  LCD_SPI->CR1 &= 0xFFC7;
-
-  return tmp;
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
-
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-}
-
-
-/**
-  * @brief  Writes 1 word to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAMWord(uint16_t RGB_Code)
-{
-
-  LCD_WriteRAM_Prepare();
-
-  LCD_WriteRAM(RGB_Code);
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD HX8312 register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue)
-{
-  uint16_t tmp = 0;
-  
-  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
-  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-  
-  tmp = LCD_Reg << 8;
-  tmp |= LCD_RegValue;
-   
-  SPI_I2S_SendData(LCD_SPI, tmp);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue));
-  }
-}
-
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-    SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-  }
-
-  if(LCDType == LCD_HX8312)
-  {
-    LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
-    LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-    SPI_I2S_SendData(LCD_SPI, RGB_Code);
-
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-  
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Power On sequence ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                /* delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                /* delay 50 ms */
-    LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    /* Power On Set */
-    LCD_WriteReg(LCD_REG_28, 0x73);
-    LCD_WriteReg(LCD_REG_36, 0x74);
-    LCD_WriteReg(LCD_REG_30, 0x01);
-    LCD_WriteReg(LCD_REG_24, 0xC1);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_24, 0xE1);
-    LCD_WriteReg(LCD_REG_24, 0xF1);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_24, 0xF5);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_27, 0x09);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_31, 0x11);
-    LCD_WriteReg(LCD_REG_32, 0x0E);
-    LCD_WriteReg(LCD_REG_30, 0x81);
-    _delay_(1); /* Delay 10 ms */
-  }
-}
-
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Display On */
-    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04);
-    /* Display On */
-    LCD_WriteReg(LCD_REG_0, 0x80);
-    LCD_WriteReg(LCD_REG_59, 0x01);
-    _delay_(4); /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_0, 0x20);
-  }  
-}
-
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Display Off */
-    LCD_WriteReg(LCD_REG_7, 0x0);
-  }
-  else if(LCDType == LCD_HX8312)
-  { 
-    /* Display Off */
-    LCD_WriteReg(LCD_REG_0, 0xA0);
-    _delay_(4);  /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_59, 0x00);
-  } 
-}
-
-
-/**
-  * @brief  Configures LCD control lines in Output Push-Pull mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE);
-
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure NWR(RNW), RS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
-  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
-  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
-  
-  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET);
-  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Sets or reset LCD control lines.
-  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
-  * @param  CtrlPins: the Control line.
-  *   This parameter can be:
-  *     @arg LCD_NCS_PIN: Chip Select pin
-  *     @arg LCD_NWR_PIN: Read/Write Selection pin
-  *     @arg LCD_RS_PIN: Register/RAM Selection pin
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
-{
-  /* Set or Reset the control line */
-  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
-}
-
-
-/**
-  * @brief  Configures the LCD_SPI interface.
-  * @param  None
-  * @retval None
-  */
-void LCD_SPIConfig(void)
-{
-  SPI_InitTypeDef    SPI_InitStructure;
-  GPIO_InitTypeDef   GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
-
-  /* Enable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
-
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  SPI_I2S_DeInit(LCD_SPI);
-  
-  /* SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-    SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-    SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
-    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
-  }
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-
-  SPI_Init(LCD_SPI, &SPI_InitStructure);
-
-  /* SPI enable */
-  SPI_Cmd(LCD_SPI, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(vu32 nCount)
-{
-  vu32 index = 0; 
-  for(index = (34000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h
deleted file mode 100644
index 638c9a0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100b_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32100b_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100B_EVAL_LCD_H
-#define __STM32100B_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM32100B_EVAL_LCD
-  * @{
-  */ 
-
-
-/** @defgroup STM32100B_EVAL_LCD_Exported_Types
-  * @{
-  */ 
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
- *        display a bitmap picture on the LCD. This function assumes that the bitmap
- *        file is loaded in the SPI Flash (mounted on STM32100B-EVAL board), however
- *        user can tailor it according to his application hardware requirement.     
- */
-/*#define USE_LCD_DrawBMP*/
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h"
- 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif                                     
-
-
-/** 
-  * @brief  LCD Control pins  
-  */ 
-#define LCD_NCS_PIN             GPIO_Pin_2                  
-#define LCD_NCS_GPIO_PORT       GPIOB                       
-#define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB  
-#define LCD_NWR_PIN             GPIO_Pin_15
-#define LCD_NWR_GPIO_PORT       GPIOD
-#define LCD_NWR_GPIO_CLK        RCC_APB2Periph_GPIOD
-#define LCD_RS_PIN              GPIO_Pin_7                     
-#define LCD_RS_GPIO_PORT        GPIOD
-#define LCD_RS_GPIO_CLK         RCC_APB2Periph_GPIOD 
-
-/** 
-  * @brief  LCD SPI Interface pins 
-  */ 
-#define LCD_SPI			            SPI2
-#define LCD_SPI_CLK		          RCC_APB1Periph_SPI2
-#define LCD_SPI_SCK_PIN         GPIO_Pin_13                 
-#define LCD_SPI_SCK_GPIO_PORT   GPIOB                       
-#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOB  
-#define LCD_SPI_MISO_PIN        GPIO_Pin_14                 
-#define LCD_SPI_MISO_GPIO_PORT  GPIOB                       
-#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOB  
-#define LCD_SPI_MOSI_PIN        GPIO_Pin_15                 
-#define LCD_SPI_MOSI_GPIO_PORT  GPIOB                       
-#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOB  
-
-
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_227           0xE3
-#define LCD_REG_229           0xE5
-#define LCD_REG_231           0xE7
-#define LCD_REG_239           0xEF
-
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Exported_Macros
-  * @{
-  */ 
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100B_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-void LCD_DeInit(void);
-void LCD_Setup(void);
-void STM32100B_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); 
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_nCS_StartByte(uint8_t Start_Byte);
-void LCD_WriteRegIndex(uint8_t LCD_Reg);
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAMWord(uint16_t RGB_Code);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM(uint16_t RGB_Code);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-
-
-void LCD_CtrlLinesConfig(void);
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
-void LCD_SPIConfig(void);
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32100B_EVAL_LCD_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c
deleted file mode 100644
index d2adb8c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c
+++ /dev/null
@@ -1,762 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100e_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides
-  *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SDIO), SPI serial
-  *              flash (sFLASH) and temperature sensor (LM75)
-  *          available on STM32100E-EVAL evaluation board from STMicroelectronics.  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm32100e_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_dma.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100E_EVAL
-  * @{
-  */ 
-      
-/** @defgroup STM32100E_EVAL_LOW_LEVEL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) 
-  *        and temperature sensor (LM75) available on STM32100E-EVAL evaluation 
-  *        board from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Variables
-  * @{
-  */ 
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
-                                 LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
-                                 LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
-                                 LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, 
-                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
-                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
-                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
-
-const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, 
-                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
-                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
-                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
-
-const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
-                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
-                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
-                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
-                                            TAMPER_BUTTON_EXTI_LINE, 
-                                            KEY_BUTTON_EXTI_LINE,
-                                            RIGHT_BUTTON_EXTI_LINE,
-                                            LEFT_BUTTON_EXTI_LINE,
-                                            UP_BUTTON_EXTI_LINE,
-                                            DOWN_BUTTON_EXTI_LINE,
-                                            SEL_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
-                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, 
-                                              KEY_BUTTON_EXTI_PORT_SOURCE,
-                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
-                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
-                                              UP_BUTTON_EXTI_PORT_SOURCE,
-                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
-                                              SEL_BUTTON_EXTI_PORT_SOURCE};
-								 
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
-                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, 
-                                             KEY_BUTTON_EXTI_PIN_SOURCE,
-                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
-                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
-                                             UP_BUTTON_EXTI_PIN_SOURCE,
-                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
-                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
-
-const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, 
-                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
-                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
-                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
- 
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
- 
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
- 
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
-
-DMA_InitTypeDef   sEEDMA_InitStructure;
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures LED GPIO.
-  * @param  Led: Specifies the Led to be configured. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4
-  * @retval None
-  */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* Enable the GPIO_LED Clock */
-  RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
-  /* Configure the GPIO_LED pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Turns selected LED On.
-  * @param  Led: Specifies the Led to be set on. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];     
-}
-
-/**
-  * @brief  Turns selected LED Off.
-  * @param  Led: Specifies the Led to be set off. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4 
-  * @retval None
-  */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];    
-}
-
-/**
-  * @brief  Toggles the selected LED.
-  * @param  Led: Specifies the Led to be toggled. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Configures Button GPIO and EXTI Line.
-  * @param  Button: Specifies the Button to be configured.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button
-  * @param  Button_Mode: Specifies Button mode.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
-  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
-  *                     generation capability  
-  * @retval None
-  */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the BUTTON Clock */
-  RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Configure Button pin as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
-  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
-  if (Button_Mode == BUTTON_MODE_EXTI)
-  {
-    /* Connect Button EXTI Line to Button GPIO Pin */
-    GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
-    /* Configure Button EXTI line */
-    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
-    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
-    if(Button != BUTTON_WAKEUP)
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-    }
-    else
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-    }
-    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-    EXTI_Init(&EXTI_InitStructure);
-
-    /* Enable and set Button EXTI Interrupt to the lowest priority */
-    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-    NVIC_Init(&NVIC_InitStructure); 
-  }
-}
-
-/**
-  * @brief  Returns the selected Button state.
-  * @param  Button: Specifies the Button to be checked.
-  *   This parameter can be one of following parameters:    
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button    
-  * @retval The Button GPIO pin value.
-  */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
-  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-/**
-  * @brief  Configures COM port.
-  * @param  COM: Specifies the COM port to be configured.
-  *   This parameter can be one of following parameters:    
-  *     @arg COM1
-  *     @arg COM2  
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
-  *   contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable UART clock */
-  if (COM == COM1)
-  {
-    RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
-  }
-  else
-  {
-    RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-  }
-
-  /* Configure USART Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-
-  /* Configure USART Rx as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
-  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
-  /* USART configuration */
-  USART_Init(COM_USART[COM], USART_InitStruct);
-    
-  /* Enable USART */
-  USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
-  * @brief  DeInitializes the SD/SD communication.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
-  SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
-  
-  /*!< SD_SPI Periph clock disable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the SD_SPI and CS pins.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  SPI_InitTypeDef   SPI_InitStructure;
-
-  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
-       and SD_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
-                         SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
-
-  /*!< SD_SPI Periph clock enable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< SD_SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SD_SPI, &SPI_InitStructure);
-  
-  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-/**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure; 
-  NVIC_InitTypeDef NVIC_InitStructure;    
-   
-  /* sEE_I2C Peripheral Disable */
-  I2C_Cmd(sEE_I2C, DISABLE);
- 
-  /* sEE_I2C DeInit */
-  I2C_DeInit(sEE_I2C);
-
-  /*!< sEE_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);   
-  
-  /* Disable and Deinitialize the DMA channels */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;  
-    
-  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
-
-  /*!< sEE_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); 
-
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);  
-  
-  /*!< I2C DMA TX and RX channels configuration */
-  /* Enable the DMA clock */
-  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
-
-  /* I2C TX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
-  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  
-  /* I2C RX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
-  
-  /* Enable the DMA Channels Interrupts */
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
-}
-
-/**
-  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
-{ 
-  /* Initialize the DMA with the new parameters */
-  if (Direction == sEE_DIRECTION_TX)
-  {
-    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
-    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  }
-  else
-  { 
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
-    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
-  }
-}
-
-/**
-  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< Disable the sFLASH_SPI  */
-  SPI_Cmd(sFLASH_SPI, DISABLE);
-  
-  /*!< DeInitializes the sFLASH_SPI */
-  SPI_I2S_DeInit(sFLASH_SPI);
-  
-  /*!< sFLASH_SPI Periph clock disable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO 
-       and sFLASH_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
-                         sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
-
-  /*!< sFLASH_SPI Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  DeInitializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< Disable LM75_I2C */
-  I2C_Cmd(LM75_I2C, DISABLE);
-  /*!< DeInitializes the LM75_I2C */
-  I2C_DeInit(LM75_I2C);
-  
-  /*!< LM75_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
-    
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the LM75_I2C..
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< LM75_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
-    
-  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
-       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
-                         LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
-  
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h
deleted file mode 100644
index fc6bff2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100e_eval.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains definitions for STM32100E_EVAL's Leds, push-buttons
-  *          COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C)
-  *          hardware resources.  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_H
-#define __STM32100E_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */  
-  
-/** @addtogroup STM32100E_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL
-  * @{
-  */ 
-  
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Types
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Constants
-  * @{
-  */ 
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_LED
-  * @{
-  */
-#define LEDn                             4
-
-#define LED1_PIN                         GPIO_Pin_6
-#define LED1_GPIO_PORT                   GPIOF
-#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-  
-#define LED2_PIN                         GPIO_Pin_7
-#define LED2_GPIO_PORT                   GPIOF
-#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-
-#define LED3_PIN                         GPIO_Pin_8  
-#define LED3_GPIO_PORT                   GPIOF
-#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-
-#define LED4_PIN                         GPIO_Pin_9
-#define LED4_GPIO_PORT                   GPIOF
-#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOF
-
-/**
-  * @}
-  */
-  
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_BUTTON
-  * @{
-  */  
-#define BUTTONn                          8
-
-/**
- * @brief Wakeup push-button
- */
-#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
-#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
-#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
-#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
-#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
-#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
-#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
-/**
- * @brief Tamper push-button
- */
-#define TAMPER_BUTTON_PIN                GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT          GPIOC
-#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
-/**
- * @brief Key push-button
- */
-#define KEY_BUTTON_PIN                   GPIO_Pin_8
-#define KEY_BUTTON_GPIO_PORT             GPIOG
-#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
-#define KEY_BUTTON_EXTI_LINE             EXTI_Line8
-#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
-#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource8
-#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
-/**
- * @brief Joystick Right push-button
- */
-#define RIGHT_BUTTON_PIN                 GPIO_Pin_13
-#define RIGHT_BUTTON_GPIO_PORT           GPIOG
-#define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOG
-#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line13
-#define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOG
-#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource13
-#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
-/**
- * @brief Joystick Left push-button
- */    
-#define LEFT_BUTTON_PIN                  GPIO_Pin_14
-#define LEFT_BUTTON_GPIO_PORT            GPIOG
-#define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
-#define LEFT_BUTTON_EXTI_LINE            EXTI_Line14
-#define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
-#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
-#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
-/**
- * @brief Joystick Up push-button
- */
-#define UP_BUTTON_PIN                    GPIO_Pin_15
-#define UP_BUTTON_GPIO_PORT              GPIOG
-#define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOG
-#define UP_BUTTON_EXTI_LINE              EXTI_Line15
-#define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOG
-#define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource15
-#define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn  
-/**
- * @brief Joystick Down push-button
- */   
-#define DOWN_BUTTON_PIN                  GPIO_Pin_11
-#define DOWN_BUTTON_GPIO_PORT            GPIOG
-#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
-#define DOWN_BUTTON_EXTI_LINE            EXTI_Line11
-#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
-#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource11
-#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
-/**
- * @brief Joystick Sel push-button
- */  
-#define SEL_BUTTON_PIN                   GPIO_Pin_7
-#define SEL_BUTTON_GPIO_PORT             GPIOG
-#define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
-#define SEL_BUTTON_EXTI_LINE             EXTI_Line7
-#define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
-#define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource7
-#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn          
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_COM
-  * @{
-  */
-#define COMn                             2
-
-/**
- * @brief Definition for COM port1, connected to USART1
- */ 
-#define EVAL_COM1                        USART1
-#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
-#define EVAL_COM1_TX_PIN                 GPIO_Pin_9
-#define EVAL_COM1_TX_GPIO_PORT           GPIOA
-#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_RX_PIN                 GPIO_Pin_10
-#define EVAL_COM1_RX_GPIO_PORT           GPIOA
-#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_IRQn                   USART1_IRQn
-
-/**
- * @brief Definition for COM port2, connected to USART2
- */ 
-#define EVAL_COM2                        USART2
-#define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
-#define EVAL_COM2_TX_PIN                 GPIO_Pin_2
-#define EVAL_COM2_TX_GPIO_PORT           GPIOA
-#define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM2_RX_PIN                 GPIO_Pin_3
-#define EVAL_COM2_RX_GPIO_PORT           GPIOA
-#define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM2_IRQn                   USART2_IRQn
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_SD_FLASH
-  * @{
-  */
-/**
-  * @brief  SD SPI Interface pins
-  */
-#define SD_SPI                           SPI2
-#define SD_SPI_CLK                       RCC_APB1Periph_SPI2
-#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PC.13 */
-#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
-#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOB
-#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PC.14 */
-#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
-#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
-#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
-#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define SD_CS_PIN                        GPIO_Pin_6                  /* PG.06 */
-#define SD_CS_GPIO_PORT                  GPIOG                       /* GPIOG */
-#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOG
-#define SD_DETECT_PIN                    GPIO_Pin_11                 /* PF.11 */
-#define SD_DETECT_GPIO_PORT              GPIOF                       /* GPIOF */
-#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOF
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
-  * @{
-  */
-/**
-  * @brief  I2C EEPROM Interface pins
-  */  
-#define sEE_I2C                          I2C2
-#define sEE_I2C_CLK                      RCC_APB1Periph_I2C2
-#define sEE_I2C_SCL_PIN                  GPIO_Pin_10                 /* PB.10 */
-#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_I2C_SDA_PIN                  GPIO_Pin_11                  /* PB.11 */
-#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_M24C64_32
-
-#define sEE_I2C_DMA                      DMA1   
-#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel4
-#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel5 
-#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC4   
-#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL4 
-#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC5 
-#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL5    
-#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
-#define sEE_I2C_DR_Address               ((uint32_t)0x40005810)
-#define sEE_USE_DMA
-   
-#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel4_IRQn
-#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel5_IRQn
-#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel4_IRQHandler
-#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel5_IRQHandler  
-#define sEE_I2C_DMA_PREPRIO              0
-#define sEE_I2C_DMA_SUBPRIO              0
- 
-#define sEE_DIRECTION_TX                 0
-#define sEE_DIRECTION_RX                 1 
-
-/* Time constant for the delay caclulation allowing to have a millisecond 
-   incrementing counter. This value should be equal to (System Clock / 1000).
-   ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */
-#define sEE_TIME_CONST          24 
-
-/**
-  * @}
-  */ 
-  
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
-  * @{
-  */
-/**
-  * @brief  M25P FLASH SPI Interface pins
-  */  
-#define sFLASH_SPI                       SPI1
-#define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
-#define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
-#define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
-#define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
-#define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
-#define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_CS_PIN                    GPIO_Pin_6                  /* PE.06 */
-#define sFLASH_CS_GPIO_PORT              GPIOE                       /* GPIOE */
-#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOE
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C
-  * @{
-  */
-/**
-  * @brief  LM75 Temperature Sensor I2C Interface pins
-  */  
-#define LM75_I2C                         I2C2
-#define LM75_I2C_CLK                     RCC_APB1Periph_I2C2
-#define LM75_I2C_SCL_PIN                 GPIO_Pin_10                 /* PB.10 */
-#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SDA_PIN                 GPIO_Pin_11                 /* PB.11 */
-#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_12                 /* PB.12 */
-#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
-#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
-#define LM75_I2C_DR                      ((uint32_t)0x40005810)
-
-#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
-#define LM75_DMA_TX_CHANNEL              DMA1_Channel4
-#define LM75_DMA_RX_CHANNEL              DMA1_Channel5
-#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC4
-#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC5   
-   
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Functions
-  * @{
-  */ 
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
-void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void); 
-void sEE_LowLevel_DeInit(void);
-void sEE_LowLevel_Init(void);
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); 
-void sFLASH_LowLevel_DeInit(void);
-void sFLASH_LowLevel_Init(void); 
-void LM75_LowLevel_DeInit(void);
-void LM75_LowLevel_Init(void); 
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-  
-#endif /* __STM32100E_EVAL_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h
deleted file mode 100644
index 117afd0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100e_eval_fsmc_sram.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the 
-  *          stm32100e_eval_fsmc_sram firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_FSMC_SRAM_H
-#define __STM32100E_EVAL_FSMC_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100E_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM32100E_EVAL_FSMC_SRAM
-  * @{
-  */  
-
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Types
-  * @{
-  */
-/**
-  * @}
-  */
-  
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Constants
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Functions
-  * @{
-  */      
-
-void SRAM_Init(void);
-void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
-void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32100E_EVAL_FSMC_SRAM_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c
deleted file mode 100644
index fe2bfdf..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c
+++ /dev/null
@@ -1,1419 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100e_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H 
-  *          (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H 
-  *          (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32100e_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100E_EVAL
-  * @{
-  */
-    
-/** @defgroup STM32100E_EVAL_LCD 
-  * @brief This file includes the LCD driver for AM-240320L8TNQW00H 
-  *        (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H 
-  *        (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Private_TypesDefinitions
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint16_t LCD_REG;
-  __IO uint16_t LCD_RAM;
-} LCD_TypeDef;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LCD_Private_Defines
-  * @{
-  */
-/* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */
-#define LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
-#define LCD                ((LCD_TypeDef *) LCD_BASE)
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))                                
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Private_Macros
-  * @{
-  */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))    
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32100E_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-  
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LCD_Private_FunctionPrototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(vu32 nCount);
-#endif /* USE_Delay*/
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32100E_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_DeInit(void)
-{ 
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
-  
-  /*!< LCD_SPI DeInit */
-  FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
-   
-  /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
-     PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
-                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-  /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
-     PE.14(D11), PE.15(D12) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
-                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_Init(GPIOG, &GPIO_InitStructure); 
-}
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM32100E_LCD_Init(void)
-{ 
-  __IO uint32_t lcdid = 0;
-  
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-/* Configure the FSMC Parallel interface -------------------------------------*/
-  LCD_FSMCConfig();
-  
-  _delay_(5); /* delay 50 ms */
-  
-  /* Read the LCD ID */
-  lcdid = LCD_ReadReg(0x00);
-  
-  /* Check if the LCD is SPFD5408B Controller */
-  if(lcdid == 0x5408)
-  {
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x0100);  /* Set SS bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700);  /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1030);  /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000);  /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202);  /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000);  /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                   /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    _delay_(5);                  /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
-    _delay_(5); 
-    LCD_WriteReg(LCD_REG_19, 0x1400);  /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
-    _delay_(5);                   /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0b0d);
-    LCD_WriteReg(LCD_REG_49, 0x1923);
-    LCD_WriteReg(LCD_REG_50, 0x1c26);
-    LCD_WriteReg(LCD_REG_51, 0x261c);
-    LCD_WriteReg(LCD_REG_52, 0x2419);
-    LCD_WriteReg(LCD_REG_53, 0x0d0b);
-    LCD_WriteReg(LCD_REG_54, 0x1006);
-    LCD_WriteReg(LCD_REG_55, 0x0610);
-    LCD_WriteReg(LCD_REG_56, 0x0706);
-    LCD_WriteReg(LCD_REG_57, 0x0304);
-    LCD_WriteReg(LCD_REG_58, 0x0e05);
-    LCD_WriteReg(LCD_REG_59, 0x0e01);
-    LCD_WriteReg(LCD_REG_60, 0x010e);
-    LCD_WriteReg(LCD_REG_61, 0x050e);
-    LCD_WriteReg(LCD_REG_62, 0x0403);
-    LCD_WriteReg(LCD_REG_63, 0x0607);
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL, VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010); 
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR=1
-       I/D=01 (Horizontal : increment, Vertical : decrement)
-       AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
-    LCD_SetFont(&LCD_DEFAULT_FONT);
-    return;
-  }
-  else if(lcdid == 0x9325) /* Check if the LCD is ILI9325 Controller */
-  {
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */
-    LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-
-    /* Adjust the Gamma Curve (ILI9325)---------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0007);
-    LCD_WriteReg(LCD_REG_49, 0x0302);
-    LCD_WriteReg(LCD_REG_50, 0x0105);
-    LCD_WriteReg(LCD_REG_53, 0x0206);
-    LCD_WriteReg(LCD_REG_54, 0x0808);
-    LCD_WriteReg(LCD_REG_55, 0x0206);
-    LCD_WriteReg(LCD_REG_56, 0x0504);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0105);
-    LCD_WriteReg(LCD_REG_61, 0x0808);
-
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-
-    /* set GRAM write direction and BGR = 1 */
-    /* I/D=00 (Horizontal : increment, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-
-    LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */
-    LCD_SetFont(&LCD_DEFAULT_FONT);
-    return;  
-  }
-  /* Check if the LCD is ILI9320 Controller */
-/* Start Initial Sequence ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
-  LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-  LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-  LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-  LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-  LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-  LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-  LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-  LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-  LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-  LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-  LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-/* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-  LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-/* Adjust the Gamma Curve ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_48, 0x0006);
-  LCD_WriteReg(LCD_REG_49, 0x0101);
-  LCD_WriteReg(LCD_REG_50, 0x0003);
-  LCD_WriteReg(LCD_REG_53, 0x0106);
-  LCD_WriteReg(LCD_REG_54, 0x0b02);
-  LCD_WriteReg(LCD_REG_55, 0x0302);
-  LCD_WriteReg(LCD_REG_56, 0x0707);
-  LCD_WriteReg(LCD_REG_57, 0x0007);
-  LCD_WriteReg(LCD_REG_60, 0x0600);
-  LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-/* Set GRAM area -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-  LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-  LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-  LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-  LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-/* Partial Display Control ---------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_128, 0x0000);
-  LCD_WriteReg(LCD_REG_129, 0x0000);
-  LCD_WriteReg(LCD_REG_130, 0x0000);
-  LCD_WriteReg(LCD_REG_131, 0x0000);
-  LCD_WriteReg(LCD_REG_132, 0x0000);
-  LCD_WriteReg(LCD_REG_133, 0x0000);
-/* Panel Control -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_144, 0x0010);
-  LCD_WriteReg(LCD_REG_146, 0x0000);
-  LCD_WriteReg(LCD_REG_147, 0x0003);
-  LCD_WriteReg(LCD_REG_149, 0x0110);
-  LCD_WriteReg(LCD_REG_151, 0x0000);
-  LCD_WriteReg(LCD_REG_152, 0x0000);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  LCD_SetFont(&LCD_DEFAULT_FONT);  
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 76800; index++)
-  {
-    LCD->LCD_RAM = Color;
-  }  
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
-  LCD_WriteReg(LCD_REG_32, Xpos);
-  LCD_WriteReg(LCD_REG_33, Ypos);
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  /* Horizontal GRAM Start Address */
-  if(Xpos >= Height)
-  {
-    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-  }
-  else
-  {
-    LCD_WriteReg(LCD_REG_80, 0);
-  }
-  /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_81, Xpos);
-  /* Vertical GRAM Start Address */
-  if(Ypos >= Width)
-  {
-    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-  }  
-  else
-  {
-    LCD_WriteReg(LCD_REG_82, 0);
-  }
-  /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_83, Ypos);
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-  LCD_WriteReg(LCD_REG_3, 0x1018);    
-}
-
-
-/**
-  * @brief  Displays a line.
-  * @param Xpos: specifies the X position.
-  * @param Ypos: specifies the Y position.
-  * @param Length: line length.
-  * @param Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  if(Direction == LCD_DIR_HORIZONTAL)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-  }
-  else
-  {
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-      LCD_WriteRAM(TextColor);
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a bitmap picture loaded in the internal Flash.
-  * @param  BmpAddress: Bmp picture address in the internal Flash.
-  * @retval None
-  */
-void LCD_WriteBMP(uint32_t BmpAddress)
-{
-  uint32_t index = 0, size = 0;
-  /* Read bitmap size */
-  size = *(__IO uint16_t *) (BmpAddress + 2);
-  size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16;
-  /* Get bitmap data address offset */
-  index = *(__IO uint16_t *) (BmpAddress + 10);
-  index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16;
-  size = (size - index)/2;
-  BmpAddress += index;
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1008);
- 
-  LCD_WriteRAM_Prepare();
- 
-  for(index = 0; index < size; index++)
-  {
-    LCD_WriteRAM(*(__IO uint16_t *)BmpAddress);
-    BmpAddress += 2;
-  }
- 
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-  /* AM = 1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-}
-
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index, then Write Reg */
-  LCD->LCD_REG = LCD_Reg;
-  /* Write 16-bit Reg */
-  LCD->LCD_RAM = LCD_RegValue;
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_Reg;
-  /* Read 16-bit Reg */
-  return (LCD->LCD_RAM);
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD->LCD_REG = LCD_REG_34;
-}
-
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  /* Write 16-bit GRAM Reg */
-  LCD->LCD_RAM = RGB_Code;
-}
-
-
-/**
-  * @brief  Reads the LCD RAM.
-  * @param  None
-  * @retval LCD RAM Value.
-  */
-uint16_t LCD_ReadRAM(void)
-{
-  /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */
-  /* Read 16-bit Reg */
-  return LCD->LCD_RAM;
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{
-/* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  /* Display On */
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  /* Display Off */
-  LCD_WriteReg(LCD_REG_7, 0x0); 
-}
-
-
-/**
-  * @brief  Configures LCD Control lines (FSMC Pins) in alternate function mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
-                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
-                         RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
-     PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
-                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
-     PE.14(D11), PE.15(D12) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
-                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-  
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-  
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures the Parallel interface (FSMC) for LCD(Parallel mode)
-  * @param  None
-  * @retval None
-  */
-void LCD_FSMCConfig(void)
-{
-  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
-  FSMC_NORSRAMTimingInitTypeDef  p;
-/*-- FSMC Configuration ------------------------------------------------------*/
-/*----------------------- SRAM Bank 4 ----------------------------------------*/
-  /* FSMC_Bank1_NORSRAM4 configuration */
-  p.FSMC_AddressSetupTime = 1;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 2;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-  /* Color LCD configuration ------------------------------------
-     LCD configured as follow:
-        - Data/Address MUX = Disable
-        - Memory Type = SRAM
-        - Data Width = 16bit
-        - Write Operation = Enable
-        - Extended Mode = Enable
-        - Asynchronous Wait = Disable */
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
-  /* BANK 4 (of NOR/SRAM Bank) is enabled */
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(vu32 nCount)
-{
-  vu32 index = 0; 
-  for(index = (34000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h
deleted file mode 100644
index 66320cd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32100e_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32100e_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_LCD_H
-#define __STM32100E_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32100E_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM32100E_EVAL_LCD
-  * @{
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Exported_Types
-  * @{
-  */
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;   
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h" 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif
- 
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_58            0x3A
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_229           0xE5
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Exported_Macros
-  * @{
-  */ 
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32100E_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-/** @defgroup  
-  * @{
-  */ 
-void LCD_DeInit(void);  
-void STM32100E_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_WriteBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAM(uint16_t RGB_Code);
-uint16_t LCD_ReadRAM(void);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_CtrlLinesConfig(void);
-void LCD_FSMCConfig(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32100E_EVAL_LCD_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
deleted file mode 100644
index b9995a5..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
+++ /dev/null
@@ -1,1878 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210b_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
-  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
-  *          Liquid Crystal Display Module of STM3210B-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210b_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210B_EVAL
-  * @{
-  */
-    
-/** @defgroup STM3210B_EVAL_LCD 
-  * @briefThis file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
-  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
-  *          Liquid Crystal Display Module of STM3210B-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Defines
-  * @{
-  */ 
-#define LCD_ILI9320        0x9320
-#define LCD_HX8312         0x8312
-#define LCD_SPFD5408       0x5408
-#define START_BYTE         0x70
-#define SET_INDEX          0x00
-#define READ_STATUS        0x01
-#define LCD_WRITE_REG      0x02
-#define LCD_READ_REG       0x03
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Macros
-  * @{
-  */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))   
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-static __IO uint32_t LCDType = LCD_ILI9320;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Function_Prototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(vu32 nCount);
-#endif /* USE_Delay*/
-
-static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue);
-static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /*!< LCD_SPI disable */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  
-  /*!< LCD_SPI DeInit */
-  SPI_I2S_DeInit(LCD_SPI);
-   
-  /*!< Disable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-    
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure NWR(RNW), RS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
-  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
-  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Setups the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_Setup(void)
-{ 
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-  
-/* Configure the LCD_SPI interface ----------------------------------------------*/
-  LCD_SPIConfig();
-  if(LCDType == LCD_ILI9320)
-  {
-    _delay_(5); /* Delay 50 ms */
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
-    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0006);
-    LCD_WriteReg(LCD_REG_49, 0x0101);
-    LCD_WriteReg(LCD_REG_50, 0x0003);
-    LCD_WriteReg(LCD_REG_53, 0x0106);
-    LCD_WriteReg(LCD_REG_54, 0x0b02);
-    LCD_WriteReg(LCD_REG_55, 0x0302);
-    LCD_WriteReg(LCD_REG_56, 0x0707);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0600);
-    LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_SPFD5408)
-  {   
-    /* Start Initial Sequence --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
-    /* Power On sequence -------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */  
-    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    _delay_(5);                  /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
-    _delay_(5);                 /* Delay 50 ms */ 
-    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0007);
-    LCD_WriteReg(LCD_REG_49, 0x0302);
-    LCD_WriteReg(LCD_REG_50, 0x0105);
-    LCD_WriteReg(LCD_REG_53, 0x0206);
-    LCD_WriteReg(LCD_REG_54, 0x0808);
-    LCD_WriteReg(LCD_REG_55, 0x0206);
-    LCD_WriteReg(LCD_REG_56, 0x0504);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0105);
-    LCD_WriteReg(LCD_REG_61, 0x0808);
-    /* Set GRAM area -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
-    /* Partial Display Control -------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1
-       I/D=01 (Horizontal : increment, Vertical : decrement)
-       AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    /* Enable the LCD Oscillator ---------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x10);
-    LCD_WriteReg(LCD_REG_0, 0xA0);
-    LCD_WriteReg(LCD_REG_3, 0x01);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_3, 0x00);
-    LCD_WriteReg(LCD_REG_43, 0x04);
-  
-    LCD_WriteReg(LCD_REG_40, 0x18);
-    LCD_WriteReg(LCD_REG_26, 0x05);
-    LCD_WriteReg(LCD_REG_37, 0x05);
-    LCD_WriteReg(LCD_REG_25, 0x00);
-    
-    /* LCD Power On ----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_28, 0x73);
-    LCD_WriteReg(LCD_REG_36, 0x74);
-    LCD_WriteReg(LCD_REG_30, 0x01);
-    LCD_WriteReg(LCD_REG_24, 0xC1);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_24, 0xE1);
-    LCD_WriteReg(LCD_REG_24, 0xF1);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_24, 0xF5);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_27, 0x09);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_31, 0x11);
-    LCD_WriteReg(LCD_REG_32, 0x0E);
-    LCD_WriteReg(LCD_REG_30, 0x81);
-    _delay_(1); /* Delay 10 ms */
-    
-    /* Chip Set --------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_157, 0x00);
-    LCD_WriteReg(LCD_REG_192, 0x00);
-   
-    LCD_WriteReg(LCD_REG_14, 0x00);
-    LCD_WriteReg(LCD_REG_15, 0x00);
-    LCD_WriteReg(LCD_REG_16, 0x00);
-    LCD_WriteReg(LCD_REG_17, 0x00);
-    LCD_WriteReg(LCD_REG_18, 0x00);
-    LCD_WriteReg(LCD_REG_19, 0x00);
-    LCD_WriteReg(LCD_REG_20, 0x00);
-    LCD_WriteReg(LCD_REG_21, 0x00);
-    LCD_WriteReg(LCD_REG_22, 0x00);
-    LCD_WriteReg(LCD_REG_23, 0x00);
-   
-    LCD_WriteReg(LCD_REG_52, 0x01);
-    LCD_WriteReg(LCD_REG_53, 0x00);
-    LCD_WriteReg(LCD_REG_75, 0x00);
-    LCD_WriteReg(LCD_REG_76, 0x00);
-    LCD_WriteReg(LCD_REG_78, 0x00);
-    LCD_WriteReg(LCD_REG_79, 0x00);
-    LCD_WriteReg(LCD_REG_80, 0x00);
-  
-    LCD_WriteReg(LCD_REG_60, 0x00);
-    LCD_WriteReg(LCD_REG_61, 0x00);
-    LCD_WriteReg(LCD_REG_62, 0x01);
-    LCD_WriteReg(LCD_REG_63, 0x3F);
-    LCD_WriteReg(LCD_REG_64, 0x02);
-    LCD_WriteReg(LCD_REG_65, 0x02);
-    LCD_WriteReg(LCD_REG_66, 0x00);
-    LCD_WriteReg(LCD_REG_67, 0x00);
-    LCD_WriteReg(LCD_REG_68, 0x00);
-    LCD_WriteReg(LCD_REG_69, 0x00);
-    LCD_WriteReg(LCD_REG_70, 0xEF);
-    LCD_WriteReg(LCD_REG_71, 0x00);
-    LCD_WriteReg(LCD_REG_72, 0x00);
-    LCD_WriteReg(LCD_REG_73, 0x01);
-    LCD_WriteReg(LCD_REG_74, 0x3F);
-  
-    LCD_WriteReg(LCD_REG_29, 0x08);  /* R29:Gate scan direction setting */
-  
-    LCD_WriteReg(LCD_REG_134, 0x00);
-    LCD_WriteReg(LCD_REG_135, 0x30);
-    LCD_WriteReg(LCD_REG_136, 0x02);
-    LCD_WriteReg(LCD_REG_137, 0x05);
-  
-    LCD_WriteReg(LCD_REG_141, 0x01);  /* R141:Register set-up mode for one line clock */
-    LCD_WriteReg(LCD_REG_139, 0x20);  /* R139:One line SYSCLK number in one-line */
-    LCD_WriteReg(LCD_REG_51, 0x01);  /* R51:N line inversion setting */
-    LCD_WriteReg(LCD_REG_55, 0x01);  /* R55:Scanning method setting */
-    LCD_WriteReg(LCD_REG_118, 0x00);
-   
-    /* Gamma Set -------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_143, 0x10);
-    LCD_WriteReg(LCD_REG_144, 0x67);
-    LCD_WriteReg(LCD_REG_145, 0x07);
-    LCD_WriteReg(LCD_REG_146, 0x65);
-    LCD_WriteReg(LCD_REG_147, 0x07);
-    LCD_WriteReg(LCD_REG_148, 0x01);
-    LCD_WriteReg(LCD_REG_149, 0x76);
-    LCD_WriteReg(LCD_REG_150, 0x56);
-    LCD_WriteReg(LCD_REG_151, 0x00);
-    LCD_WriteReg(LCD_REG_152, 0x06);
-    LCD_WriteReg(LCD_REG_153, 0x03);
-    LCD_WriteReg(LCD_REG_154, 0x00);
-  
-    /* Display On ------------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04);
-    LCD_WriteReg(LCD_REG_0, 0x80);
-    LCD_WriteReg(LCD_REG_59, 0x01);
-    _delay_(4);  /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_0, 0x20);
-  }  
-}
-
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM3210B_LCD_Init(void)
-{
-  /* Setups the LCD */
-  LCD_Setup();
-  /* Try to read new LCD controller ID 0x9320 */
-  if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320)
-  {
-    LCDType = LCD_ILI9320;
-  }
-  else
-  {
-    LCDType = LCD_SPFD5408;
-    /* Setups the LCD */
-    LCD_Setup();
-    /* Try to read new LCD controller ID 0x5408 */
-    if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408)
-    {
-      LCDType = LCD_HX8312;
-      /* Setups the LCD */
-      LCD_Setup();
-    }
-  }
-  LCD_SetFont(&LCD_DEFAULT_FONT);
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-  for(index = 0; index < 76800; index++)
-  {
-    LCD_WriteRAM(Color);
-  }
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-  }  
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteReg(LCD_REG_32, Xpos);
-    LCD_WriteReg(LCD_REG_33, Ypos);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteReg(LCD_REG_66, Xpos);
-    LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF));
-  }
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    }
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-    }  
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Horizontal GRAM Start Address */
-    if(Xpos >= Height)
-    {
-      LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-    }
-    else
-    {
-      LCD_WriteReg(LCD_REG_80, 0);
-    }
-    /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_81, Xpos);
-    /* Vertical GRAM Start Address */
-    if(Ypos >= Width)
-    {
-      LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-    }  
-    else
-    {
-      LCD_WriteReg(LCD_REG_82, 0);
-    }
-    /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_83, Ypos);
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    LCD_WriteReg(LCD_REG_1, 0xD0);
-    LCD_WriteReg(LCD_REG_5, 0x14);
-  
-    LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1));
-    LCD_WriteReg(LCD_REG_70, Xpos);
- 
-    LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF));
-    LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8));
-    LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF));
-  }
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04); 
-  }
-    
-}
-
-
-/**
-  * @brief  Displays a line.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Length: line length.
-  * @param  Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  if(Direction == LCD_DIR_HORIZONTAL)
-  { 
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    }
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-    }
-  }
-  else
-  {
-   for(i = 0; i < Length; i++)
-    {
-      if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-      {
-        LCD_WriteRAMWord(TextColor);
-      }
-      else  if(LCDType == LCD_HX8312)
-      {
-        LCD_WriteRAM(TextColor);
-      }
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-
-    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-    {
-      LCD_WriteRAMWord(TextColor);
-    }
-    else if(LCDType == LCD_HX8312)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-}
-
-#ifdef USE_LCD_DrawBMP 
-/**
-  * @brief  Displays a bitmap picture loaded in the SPI Flash.
-  * @param  BmpAddress: Bmp picture address in the SPI Flash.
-  * @retval None
-  */
-void LCD_DrawBMP(uint32_t BmpAddress)
-{
-  uint32_t i = 0, size = 0;
-  /* Read bitmap size */
-  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
-  /* get bitmap data address offset */
-  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
-  
-  size = (size - i)/2;
-  sFLASH_StartReadSequence(BmpAddress + i);
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 16-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-  
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1008);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-  
-  /* Read bitmap data from SPI Flash and send them to LCD */
-  for(i = 0; i < size; i++)
-  {
-    LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
-  }
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-
-  /* Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 8-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-    /* AM = 1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-  }
-}
-#endif /* USE_LCD_DrawBMP */
- 
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Reset LCD control line(/CS) and Send Start-Byte
-  * @param  Start_Byte: the Start-Byte to be sent
-  * @retval None
-  */
-void LCD_nCS_StartByte(uint8_t Start_Byte)
-{
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-
-  SPI_I2S_SendData(LCD_SPI, Start_Byte);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Writes index to select the LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval None
-  */
-void LCD_WriteRegIndex(uint8_t LCD_Reg)
-{
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | SET_INDEX);
-
-  /* Write 16-bit Reg Index (High Byte is 0) */
-  SPI_I2S_SendData(LCD_SPI, 0x00);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_I2S_SendData(LCD_SPI, LCD_Reg);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD ILI9320 register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index (then Write Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-
-  /* Write 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-
-  SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  uint16_t tmp = 0;
-  uint8_t i = 0;
-  
-  /* LCD_SPI prescaler: 4 */
-  LCD_SPI->CR1 &= 0xFFC7;
-  LCD_SPI->CR1 |= 0x0008;
-  /* Write 16-bit Index (then Read Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Read 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
-  
-  for(i = 0; i < 5; i++)
-  {
-    SPI_I2S_SendData(LCD_SPI, 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-    /* One byte of invalid dummy data read after the start byte */
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-    {    
-    }
-    SPI_I2S_ReceiveData(LCD_SPI); 
-  }
-
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-
-  /* Read upper byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  tmp = SPI_I2S_ReceiveData(LCD_SPI);
-  
-  
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-
-  tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-
-  /* LCD_SPI prescaler: 2 */
-  LCD_SPI->CR1 &= 0xFFC7;
-
-  return tmp;
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
-
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-}
-
-
-/**
-  * @brief  Writes 1 word to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAMWord(uint16_t RGB_Code)
-{
-
-  LCD_WriteRAM_Prepare();
-
-  LCD_WriteRAM(RGB_Code);
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD HX8312 register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue)
-{
-  uint16_t tmp = 0;
-  
-  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
-  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-  
-  tmp = LCD_Reg << 8;
-  tmp |= LCD_RegValue;
-   
-  SPI_I2S_SendData(LCD_SPI, tmp);
-
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue);
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue));
-  }
-}
-
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-    SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-  }
-
-  if(LCDType == LCD_HX8312)
-  {
-    LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
-    LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-    SPI_I2S_SendData(LCD_SPI, RGB_Code);
-
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-  
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Power On sequence ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                /* delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                /* delay 50 ms */
-    LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    /* Power On Set */
-    LCD_WriteReg(LCD_REG_28, 0x73);
-    LCD_WriteReg(LCD_REG_36, 0x74);
-    LCD_WriteReg(LCD_REG_30, 0x01);
-    LCD_WriteReg(LCD_REG_24, 0xC1);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_24, 0xE1);
-    LCD_WriteReg(LCD_REG_24, 0xF1);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_24, 0xF5);
-    _delay_(6); /* Delay 60 ms */
-    LCD_WriteReg(LCD_REG_27, 0x09);
-    _delay_(1); /* Delay 10 ms */
-    LCD_WriteReg(LCD_REG_31, 0x11);
-    LCD_WriteReg(LCD_REG_32, 0x0E);
-    LCD_WriteReg(LCD_REG_30, 0x81);
-    _delay_(1); /* Delay 10 ms */
-  }
-}
-
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Display On */
-    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  }
-  else if(LCDType == LCD_HX8312)
-  {  
-    LCD_WriteReg(LCD_REG_1, 0x50);
-    LCD_WriteReg(LCD_REG_5, 0x04);
-    /* Display On */
-    LCD_WriteReg(LCD_REG_0, 0x80);
-    LCD_WriteReg(LCD_REG_59, 0x01);
-    _delay_(4); /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_0, 0x20);
-  }  
-}
-
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Display Off */
-    LCD_WriteReg(LCD_REG_7, 0x0);
-  }
-  else if(LCDType == LCD_HX8312)
-  { 
-    /* Display Off */
-    LCD_WriteReg(LCD_REG_0, 0xA0);
-    _delay_(4);  /* Delay 40 ms */
-    LCD_WriteReg(LCD_REG_59, 0x00);
-  } 
-}
-
-
-/**
-  * @brief  Configures LCD control lines in Output Push-Pull mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE);
-
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure NWR(RNW), RS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
-  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
-  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
-  
-  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET);
-  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Sets or reset LCD control lines.
-  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
-  * @param  CtrlPins: the Control line.
-  *   This parameter can be:
-  *     @arg LCD_NCS_PIN: Chip Select pin
-  *     @arg LCD_NWR_PIN: Read/Write Selection pin
-  *     @arg LCD_RS_PIN: Register/RAM Selection pin
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
-{
-  /* Set or Reset the control line */
-  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
-}
-
-/**
-  * @brief  Configures the LCD_SPI interface.
-  * @param  None
-  * @retval None
-  */
-void LCD_SPIConfig(void)
-{
-  SPI_InitTypeDef    SPI_InitStructure;
-  GPIO_InitTypeDef   GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
-
-  /* Enable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
-
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  SPI_I2S_DeInit(LCD_SPI);
-  
-  /* SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-    SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-    SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  }
-  else if(LCDType == LCD_HX8312)
-  {
-    SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
-    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
-  }
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-
-  SPI_Init(LCD_SPI, &SPI_InitStructure);
-
-  /* SPI enable */
-  SPI_Cmd(LCD_SPI, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(vu32 nCount)
-{
-  vu32 index = 0; 
-  for(index = (100000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
deleted file mode 100644
index 0b7577c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210b_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm3210b_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210B_EVAL_LCD_H
-#define __STM3210B_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210B_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM3210B_EVAL_LCD
-  * @{
-  */ 
-
-
-/** @defgroup STM3210B_EVAL_LCD_Exported_Types
-  * @{
-  */
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;   
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup STM3210B_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
- *        display a bitmap picture on the LCD. This function assumes that the bitmap
- *        file is loaded in the SPI Flash (mounted on STM3210B-EVAL board), however
- *        user can tailor it according to his application hardware requirement.     
- */
-/*#define USE_LCD_DrawBMP*/
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h"
- 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif                                     
-
-
-/** 
-  * @brief  LCD Control pins  
-  */ 
-#define LCD_NCS_PIN             GPIO_Pin_2                  
-#define LCD_NCS_GPIO_PORT       GPIOB                       
-#define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB  
-#define LCD_NWR_PIN             GPIO_Pin_15
-#define LCD_NWR_GPIO_PORT       GPIOD
-#define LCD_NWR_GPIO_CLK        RCC_APB2Periph_GPIOD
-#define LCD_RS_PIN              GPIO_Pin_7                     
-#define LCD_RS_GPIO_PORT        GPIOD
-#define LCD_RS_GPIO_CLK         RCC_APB2Periph_GPIOD 
-
-/** 
-  * @brief  LCD SPI Interface pins 
-  */ 
-#define LCD_SPI			            SPI2
-#define LCD_SPI_CLK		          RCC_APB1Periph_SPI2
-#define LCD_SPI_SCK_PIN         GPIO_Pin_13                 
-#define LCD_SPI_SCK_GPIO_PORT   GPIOB                       
-#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOB  
-#define LCD_SPI_MISO_PIN        GPIO_Pin_14                 
-#define LCD_SPI_MISO_GPIO_PORT  GPIOB                       
-#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOB  
-#define LCD_SPI_MOSI_PIN        GPIO_Pin_15                 
-#define LCD_SPI_MOSI_GPIO_PORT  GPIOB                       
-#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOB 
-
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_227           0xE3
-#define LCD_REG_229           0xE5
-#define LCD_REG_231           0xE7
-#define LCD_REG_239           0xEF
-
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210B_EVAL_LCD_Exported_Macros
-  * @{
-  */
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))   
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup STM3210B_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-void LCD_DeInit(void);
-void LCD_Setup(void);
-void STM3210B_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); 
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-
-void LCD_nCS_StartByte(uint8_t Start_Byte);
-void LCD_WriteRegIndex(uint8_t LCD_Reg);
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAMWord(uint16_t RGB_Code);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM(uint16_t RGB_Code);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-
-void LCD_CtrlLinesConfig(void);
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
-void LCD_SPIConfig(void);
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210B_EVAL_LCD_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c
deleted file mode 100644
index b256930..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c
+++ /dev/null
@@ -1,604 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210c_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides
-  *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SPI) and I2C
-  *              serial EEPROM (sEE)
-  *          available on STM3210C-EVAL evaluation board from STMicroelectronics.   
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210c_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_dma.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210C_EVAL
-  * @{
-  */ 
-      
-/** @defgroup STM3210C_EVAL_LOW_LEVEL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL 
-  *        evaluation board from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Variables
-  * @{
-  */ 
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
-                                 LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
-                                 LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
-                                 LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
-                                      KEY_BUTTON_GPIO_PORT}; 
-
-const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
-                                      KEY_BUTTON_PIN}; 
-
-const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
-                                      KEY_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
-                                            TAMPER_BUTTON_EXTI_LINE, 
-                                            KEY_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
-                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, 
-                                              KEY_BUTTON_EXTI_PORT_SOURCE};
-								 
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
-                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, 
-                                             KEY_BUTTON_EXTI_PIN_SOURCE}; 
-
-const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
-                                       KEY_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; 
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
-
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
-
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
- 
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
- 
-DMA_InitTypeDef   sEEDMA_InitStructure; 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures LED GPIO.
-  * @param  Led: Specifies the Led to be configured. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4
-  * @retval None
-  */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* Enable the GPIO_LED Clock */
-  RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
-  /* Configure the GPIO_LED pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Turns selected LED On.
-  * @param  Led: Specifies the Led to be set on. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];     
-}
-
-/**
-  * @brief  Turns selected LED Off.
-  * @param  Led: Specifies the Led to be set off. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4 
-  * @retval None
-  */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];  
-}
-
-/**
-  * @brief  Toggles the selected LED.
-  * @param  Led: Specifies the Led to be toggled. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Configures Button GPIO and EXTI Line.
-  * @param  Button: Specifies the Button to be configured.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button
-  * @param  Button_Mode: Specifies Button mode.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
-  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
-  *                     generation capability  
-  * @retval None
-  */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the BUTTON Clock */
-  RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Configure Button pin as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
-  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
-  if (Button_Mode == BUTTON_MODE_EXTI)
-  {
-    /* Connect Button EXTI Line to Button GPIO Pin */
-    GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
-    /* Configure Button EXTI line */
-    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
-    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
-    if(Button != BUTTON_WAKEUP)
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-    }
-    else
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-    }
-    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-    EXTI_Init(&EXTI_InitStructure);
-
-    /* Enable and set Button EXTI Interrupt to the lowest priority */
-    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-    NVIC_Init(&NVIC_InitStructure); 
-  }
-}
-
-/**
-  * @brief  Returns the selected Button state.
-  * @param  Button: Specifies the Button to be checked.
-  *   This parameter can be one of following parameters:    
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button    
-  * @retval The Button GPIO pin value.
-  */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
-  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-
-/**
-  * @brief  Configures COM port.
-  * @param  COM: Specifies the COM port to be configured.
-  *   This parameter can be one of following parameters:    
-  *     @arg COM1
-  *     @arg COM2  
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
-  *   contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
-
-  if (COM == COM1)
-  {
-    /* Enable the USART2 Pins Software Remapping */
-    GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
-    RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-  }
-
-  /* Configure USART Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-
-  /* Configure USART Rx as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
-  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
-  /* USART configuration */
-  USART_Init(COM_USART[COM], USART_InitStruct);
-    
-  /* Enable USART */
-  USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
-  * @brief  DeInitializes the SD/SD communication.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
-  SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
-  
-  /*!< SD_SPI Periph clock disable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
-  /*!< DeRemap SPI3 Pins */
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE);  
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the SD_SPI and CS pins.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  SPI_InitTypeDef   SPI_InitStructure;
-
-  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
-       and SD_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
-                         SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
-
-  /*!< SD_SPI Periph clock enable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
-  /*!< AFIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-  /*!< Remap SPI3 Pins */
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3,ENABLE);  
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< SD_SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SD_SPI, &SPI_InitStructure);
-  
-  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-/**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure; 
-  NVIC_InitTypeDef NVIC_InitStructure;    
-   
-  /* sEE_I2C Peripheral Disable */
-  I2C_Cmd(sEE_I2C, DISABLE);
- 
-  /* sEE_I2C DeInit */
-  I2C_DeInit(sEE_I2C);
-
-  /*!< sEE_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);   
-  
-  /* Disable and Deinitialize the DMA channels */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;  
-    
-  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
-
-  /*!< sEE_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); 
-
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);  
-  
-  /*!< I2C DMA TX and RX channels configuration */
-  /* Enable the DMA clock */
-  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
-
-  /* I2C TX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
-  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  
-  /* I2C RX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
-  
-  /* Enable the DMA Channels Interrupts */
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
-}
-
-
-/**
-  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
-{ 
-  /* Initialize the DMA with the new parameters */
-  if (Direction == sEE_DIRECTION_TX)
-  {
-    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
-    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  }
-  else
-  { 
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
-    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
-  }
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
deleted file mode 100644
index 469693f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210c_eval.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains definitions for STM3210C_EVAL's Leds, push-buttons
-  *          COM ports, SD Card on SPI and sEE on I2C hardware resources.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 210 STMicroelectronics</center></h2>
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210C_EVAL_H
-#define __STM3210C_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM3210C_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL
-  * @{
-  */ 
-  
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Types
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Constants
-  * @{
-  */ 
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_LED
-  * @{
-  */
-#define LEDn                             4
-
-#define LED1_PIN                         GPIO_Pin_7
-#define LED1_GPIO_PORT                   GPIOD
-#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOD  
-  
-#define LED2_PIN                         GPIO_Pin_13
-#define LED2_GPIO_PORT                   GPIOD
-#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOD  
-
-#define LED3_PIN                         GPIO_Pin_3  
-#define LED3_GPIO_PORT                   GPIOD
-#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOD  
-
-#define LED4_PIN                         GPIO_Pin_4  
-#define LED4_GPIO_PORT                   GPIOD
-#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOD  
-
-
-/**
-  * @}
-  */ 
-  
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_BUTTON
-  * @{
-  */  
-#define BUTTONn                          3 /*!< Joystick pins are connected to 
-                                                an IO Expander (accessible through 
-                                                I2C1 interface) */
-
-/**
- * @brief Wakeup push-button
- */
-#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
-#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
-#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
-#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
-#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
-#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
-#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
-
-/**
- * @brief Tamper push-button
- */
-#define TAMPER_BUTTON_PIN                GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT          GPIOC
-#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
-
-/**
- * @brief Key push-button
- */
-#define KEY_BUTTON_PIN                   GPIO_Pin_9
-#define KEY_BUTTON_GPIO_PORT             GPIOB
-#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
-#define KEY_BUTTON_EXTI_LINE             EXTI_Line9
-#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
-#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
-#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_COM
-  * @{
-  */
-#define COMn                             1
-
-/**
- * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
- */ 
-#define EVAL_COM1                        USART2
-#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
-#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
-#define EVAL_COM1_TX_GPIO_PORT           GPIOD
-#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
-#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
-#define EVAL_COM1_RX_GPIO_PORT           GPIOD
-#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
-#define EVAL_COM1_IRQn                   USART2_IRQn
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM3210B_EVAL_SD_SPI
-  * @{
-  */
-/**
-  * @brief  SD SPI Interface pins
-  */
-#define SD_SPI                           SPI3
-#define SD_SPI_CLK                       RCC_APB1Periph_SPI3
-#define SD_SPI_SCK_PIN                   GPIO_Pin_10                 /* PC.10 */
-#define SD_SPI_SCK_GPIO_PORT             GPIOC                       /* GPIOC */
-#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOC
-#define SD_SPI_MISO_PIN                  GPIO_Pin_11                 /* PC.11 */
-#define SD_SPI_MISO_GPIO_PORT            GPIOC                       /* GPIOC */
-#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOC
-#define SD_SPI_MOSI_PIN                  GPIO_Pin_12                 /* PC.12 */
-#define SD_SPI_MOSI_GPIO_PORT            GPIOC                       /* GPIOC */
-#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOC
-#define SD_CS_PIN                        GPIO_Pin_4                  /* PA.04 */
-#define SD_CS_GPIO_PORT                  GPIOA                       /* GPIOA */
-#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOA
-#define SD_DETECT_PIN                    GPIO_Pin_0                  /* PE.00 */
-#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
-#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
-  * @{
-  */
-/**
-  * @brief  I2C EEPROM Interface pins
-  */  
-#define sEE_I2C                          I2C1
-#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
-#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
-#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
-#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_M24C64_32
-
-#define sEE_I2C_DMA                      DMA1   
-#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
-#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
-#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
-#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
-#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
-#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
-#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
-#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
-#define sEE_USE_DMA
-   
-#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
-#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
-#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
-#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler   
-#define sEE_I2C_DMA_PREPRIO              0
-#define sEE_I2C_DMA_SUBPRIO              0   
-   
-#define sEE_DIRECTION_TX                 0
-#define sEE_DIRECTION_RX                 1   
-
-/* Time constant for the delay caclulation allowing to have a millisecond 
-   incrementing counter. This value should be equal to (System Clock / 1000).
-   ie. if system clock = 72MHz then sEE_TIME_CONST should be 72. */
-#define sEE_TIME_CONST                   72 
-   
-/**
-  * @}
-  */
-   
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Functions
-  * @{
-  */ 
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); 
-void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void); 
-void sEE_LowLevel_DeInit(void);
-void sEE_LowLevel_Init(void); 
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210C_EVAL_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c
deleted file mode 100644
index 3f547e3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c
+++ /dev/null
@@ -1,1407 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210c_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
-  *          Liquid Crystal Display Module of STM3210C-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210c_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210C_EVAL
-  * @{
-  */
-    
-/** @defgroup STM3210C_EVAL_LCD 
-  * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
-  *        Liquid Crystal Display Module of STM3210C-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Defines
-  * @{
-  */ 
-#define START_BYTE         0x70
-#define SET_INDEX          0x00
-#define READ_STATUS        0x01
-#define LCD_WRITE_REG      0x02
-#define LCD_READ_REG       0x03
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Macros
-  * @{
-  */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))    
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Private_FunctionPrototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(__IO uint32_t nCount);
-#endif /* USE_Delay*/
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /*!< LCD_SPI disable */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  
-  /*!< LCD_SPI DeInit */
-  SPI_I2S_DeInit(LCD_SPI);
-   
-  /*!< Disable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE);
-    
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-   
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Setups the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_Setup(void)
-{ 
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-  
-/* Configure the LCD_SPI interface ----------------------------------------------*/
-  LCD_SPIConfig();
-  _delay_(5); /* Delay 50 ms */
-  /* Start Initial Sequence ------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
-  LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-  LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-  LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-  LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-  LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-  LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-  LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-  LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-  LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-  LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-  LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-  /* Power On sequence -----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-  LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-  /* Adjust the Gamma Curve ------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_48, 0x0006);
-  LCD_WriteReg(LCD_REG_49, 0x0101);
-  LCD_WriteReg(LCD_REG_50, 0x0003);
-  LCD_WriteReg(LCD_REG_53, 0x0106);
-  LCD_WriteReg(LCD_REG_54, 0x0b02);
-  LCD_WriteReg(LCD_REG_55, 0x0302);
-  LCD_WriteReg(LCD_REG_56, 0x0707);
-  LCD_WriteReg(LCD_REG_57, 0x0007);
-  LCD_WriteReg(LCD_REG_60, 0x0600);
-  LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-  /* Set GRAM area ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-  LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-  LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-  LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-  LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-  /* Partial Display Control -----------------------------------------------*/
-  LCD_WriteReg(LCD_REG_128, 0x0000);
-  LCD_WriteReg(LCD_REG_129, 0x0000);
-  LCD_WriteReg(LCD_REG_130, 0x0000);
-  LCD_WriteReg(LCD_REG_131, 0x0000);
-  LCD_WriteReg(LCD_REG_132, 0x0000);
-  LCD_WriteReg(LCD_REG_133, 0x0000);
-  /* Panel Control ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_144, 0x0010);
-  LCD_WriteReg(LCD_REG_146, 0x0000);
-  LCD_WriteReg(LCD_REG_147, 0x0003);
-  LCD_WriteReg(LCD_REG_149, 0x0110);
-  LCD_WriteReg(LCD_REG_151, 0x0000);
-  LCD_WriteReg(LCD_REG_152, 0x0000);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM3210C_LCD_Init(void)
-{
-  /* Setups the LCD */
-  LCD_Setup();
-  LCD_SetFont(&LCD_DEFAULT_FONT);
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1)& 0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 76800; index++)
-  {
-    LCD_WriteRAM(Color);
-  }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-  
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
- LCD_WriteReg(LCD_REG_32, Xpos);
- LCD_WriteReg(LCD_REG_33, Ypos);
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }   
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{ 
-  /* Horizontal GRAM Start Address */
-  if(Xpos >= Height)
-  {
-    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-  }
-  else
-  {
-    LCD_WriteReg(LCD_REG_80, 0);
-  }
-  /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_81, Xpos);
-  /* Vertical GRAM Start Address */
-  if(Ypos >= Width)
-  {
-    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-  }  
-  else
-  {
-    LCD_WriteReg(LCD_REG_82, 0);
-  }
-  /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_83, Ypos);
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-  LCD_WriteReg(LCD_REG_3, 0x1018);    
-}
-
-
-/**
-  * @brief  Displays a line.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Length: line length.
-  * @param  Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  if(Direction == LCD_DIR_HORIZONTAL)
-  { 
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-  else
-  {
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAMWord(TextColor);
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  s32  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-    LCD_WriteRAMWord(TextColor);
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-#ifdef USE_LCD_DrawBMP
-/**
-  * @brief  Displays a bitmap picture loaded in the SPI Flash.
-  * @param  BmpAddress: Bmp picture address in the SPI Flash.
-  * @retval None
-  */
-//void LCD_DrawBMP(uint32_t BmpAddress)
-//{
-//  uint32_t i = 0, size = 0;
-//
-//  /* Read bitmap size */
-//  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
-//
-//  /* get bitmap data address offset */
-//  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
-//  
-//  size = (size - i)/2;
-//
-//  sFLASH_StartReadSequence(BmpAddress + i);
-//
-//  /* Disable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, DISABLE);
-//  /* SPI in 16-bit mode */
-//  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
-//
-//  /* Enable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, ENABLE);
-//  
-//  /* Set GRAM write direction and BGR = 1 */
-//  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-//  /* AM=1 (address is updated in vertical writing direction) */
-//  LCD_WriteReg(LCD_REG_3, 0x1008);
-//
-//  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-//
-//  /* Read bitmap data from SPI Flash and send them to LCD */
-//  for(i = 0; i < size; i++)
-//  {
-//    LCD_WriteRAM(__REV_HalfWord(sFLASH_SendHalfWord(0xA5A5)));
-//  }
-//
-//  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-//
-//  /* Deselect the FLASH: Chip Select high */
-//  sFLASH_CS_HIGH();
-//
-//  /* Disable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, DISABLE);
-//  /* SPI in 8-bit mode */
-//  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
-//
-//  /* Enable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, ENABLE);
-//
-//  /* Set GRAM write direction and BGR = 1 */
-//  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-//  /* AM = 1 (address is updated in vertical writing direction) */
-//  LCD_WriteReg(LCD_REG_3, 0x1018);
-//}
-
-
-/**
-  * @brief  Displays a bitmap picture loaded in the Internal FLASH.
-  * @param  BmpAddress: Bmp picture address in the Internal FLASH.
-  * @retval None
-  */
-void LCD_DrawBMP(const uint16_t *BmpAddress)
-{
-  uint32_t i = 0, size = 0;
-  /* Read bitmap size */
-  size = BmpAddress[1] | (BmpAddress[2] << 16);
-  /* get bitmap data address offset */
-  i = BmpAddress[5] | (BmpAddress[6] << 16);
-  size = (size - i)/2;
-  BmpAddress += i/2;
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1008);
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  /* Read bitmap data from SPI Flash and send them to LCD */
-  for(i = 0; i < size; i++)
-  {
-    LCD_WriteRAM(BmpAddress[i]);
-  }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-  /* AM = 1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-}
-#endif
-
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Reset LCD control line(/CS) and Send Start-Byte
-  * @param  Start_Byte: the Start-Byte to be sent
-  * @retval None
-  */
-void LCD_nCS_StartByte(uint8_t Start_Byte)
-{
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-  SPI_I2S_SendData(LCD_SPI, Start_Byte);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-/**
-  * @brief  Writes index to select the LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval None
-  */
-void LCD_WriteRegIndex(uint8_t LCD_Reg)
-{
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | SET_INDEX);
-  /* Write 16-bit Reg Index (High Byte is 0) */
-  SPI_I2S_SendData(LCD_SPI, 0x00);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  SPI_I2S_SendData(LCD_SPI, LCD_Reg);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  None
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  uint16_t tmp = 0;
-  uint8_t i = 0;
-  
-  /* LCD_SPI prescaler: 4 */
-  LCD_SPI->CR1 &= 0xFFC7;
-  LCD_SPI->CR1 |= 0x0008;
-  /* Write 16-bit Index (then Read Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Read 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
-  
-  for(i = 0; i < 5; i++)
-  {
-    SPI_I2S_SendData(LCD_SPI, 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-    {
-    }
-    /* One byte of invalid dummy data read after the start byte */
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-    {    
-    }
-    SPI_I2S_ReceiveData(LCD_SPI); 
-  }
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-  /* Read upper byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  tmp = SPI_I2S_ReceiveData(LCD_SPI);
-  
-  
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  /* LCD_SPI prescaler: 2 */
-  LCD_SPI->CR1 &= 0xFFC7;
-  return tmp;
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-}
-
-
-/**
-  * @brief  Writes 1 word to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAMWord(uint16_t RGB_Code)
-{
-  LCD_WriteRAM_Prepare();
-  LCD_WriteRAM(RGB_Code);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index (then Write Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Write 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-  SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{ 
-  /* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* delay 50 ms */
-  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-}
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  /* Display On */
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
- 
-}
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  /* Display Off */
-  LCD_WriteReg(LCD_REG_7, 0x0);
-}
-
-/**
-  * @brief  Configures LCD control lines in Output Push-Pull mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
-
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);  
-}
-
-/**
-  * @brief  Sets or reset LCD control lines.
-  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
-  * @param  CtrlPins: the Control line. This parameter can be:
-  *     @arg LCD_NCS_PIN: Chip Select pin
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
-{
-  /* Set or Reset the control line */
-  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
-}
-
-
-/**
-  * @brief  Configures the LCD_SPI interface.
-  * @param  None
-  * @retval None
-  */
-void LCD_SPIConfig(void)
-{
-  SPI_InitTypeDef    SPI_InitStructure;
-  GPIO_InitTypeDef   GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK
-                         | RCC_APB2Periph_AFIO, ENABLE);
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
-
-  /* Enable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
-  
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-  
-  SPI_I2S_DeInit(LCD_SPI);
-  
-  /* SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_Init(LCD_SPI, &SPI_InitStructure);
-
-  /* SPI enable */
-  SPI_Cmd(LCD_SPI, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(__IO uint32_t nCount)
-{
-  __IO uint32_t index = 0; 
-  for(index = (100000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */  
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h
deleted file mode 100644
index 0584c8a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210c_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the lcd firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210C_EVAL_LCD_H
-#define __STM3210C_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210C_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM3210C_EVAL_LCD
-  * @{
-  */ 
-
-
-/** @defgroup STM3210C_EVAL_LCD_Exported_Types
-  * @{
-  */
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;   
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210C_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
- *        display a bitmap picture on the LCD. This function assumes that the bitmap
- *        file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however
- *        user can tailor it according to his application hardware requirement.     
- */
-/*#define USE_LCD_DrawBMP*/
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h"
- 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif 
-
-/** 
-  * @brief  LCD Control pins  
-  */ 
-#define LCD_NCS_PIN             GPIO_Pin_2                  
-#define LCD_NCS_GPIO_PORT       GPIOB                       
-#define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB  
-
-/** 
-  * @brief  LCD SPI Interface pins 
-  */ 
-#define LCD_SPI			            SPI3
-#define LCD_SPI_CLK		          RCC_APB1Periph_SPI3
-#define LCD_SPI_SCK_PIN         GPIO_Pin_10                 
-#define LCD_SPI_SCK_GPIO_PORT   GPIOC                       
-#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOC  
-#define LCD_SPI_MISO_PIN        GPIO_Pin_11                 
-#define LCD_SPI_MISO_GPIO_PORT  GPIOC                       
-#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOC  
-#define LCD_SPI_MOSI_PIN        GPIO_Pin_12                 
-#define LCD_SPI_MOSI_GPIO_PORT  GPIOC                       
-#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOC       
-
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_229           0xE5
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */ 
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210C_EVAL_LCD_Exported_Macros
-  * @{
-  */
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))   
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210C_EVAL_LCD_Exported_Functions
-  * @{
-  */
-void LCD_DeInit(void);   
-void LCD_Setup(void);
-void STM3210C_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-#ifdef USE_LCD_DrawBMP
-//void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawBMP(const uint16_t *BmpAddress);
-#endif 
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-
-void LCD_nCS_StartByte(uint8_t Start_Byte);
-void LCD_WriteRegIndex(uint8_t LCD_Reg);
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAMWord(uint16_t RGB_Code);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM(uint16_t RGB_Code);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-
-void LCD_CtrlLinesConfig(void);
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
-void LCD_SPIConfig(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210C_EVAL_LCD_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-     
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
deleted file mode 100644
index 0e345e4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
+++ /dev/null
@@ -1,667 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides
-  *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SDIO), SPI serial
-  *              flash (sFLASH) and temperature sensor (LM75)
-  *          available on STM3210E-EVAL evaluation board from STMicroelectronics.  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210e_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_dma.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */ 
-      
-/** @defgroup STM3210E_EVAL_LOW_LEVEL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) 
-  *        and temperature sensor (LM75) available on STM3210E-EVAL evaluation 
-  *        board from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Variables
-  * @{
-  */ 
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
-                                 LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
-                                 LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
-                                 LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, 
-                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
-                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
-                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
-
-const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, 
-                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
-                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
-                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
-
-const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
-                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
-                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
-                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
-                                            TAMPER_BUTTON_EXTI_LINE, 
-                                            KEY_BUTTON_EXTI_LINE,
-                                            RIGHT_BUTTON_EXTI_LINE,
-                                            LEFT_BUTTON_EXTI_LINE,
-                                            UP_BUTTON_EXTI_LINE,
-                                            DOWN_BUTTON_EXTI_LINE,
-                                            SEL_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
-                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, 
-                                              KEY_BUTTON_EXTI_PORT_SOURCE,
-                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
-                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
-                                              UP_BUTTON_EXTI_PORT_SOURCE,
-                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
-                                              SEL_BUTTON_EXTI_PORT_SOURCE};
-								 
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
-                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, 
-                                             KEY_BUTTON_EXTI_PIN_SOURCE,
-                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
-                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
-                                             UP_BUTTON_EXTI_PIN_SOURCE,
-                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
-                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
-
-const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, 
-                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
-                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
-                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
- 
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
- 
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
- 
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures LED GPIO.
-  * @param  Led: Specifies the Led to be configured. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4
-  * @retval None
-  */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* Enable the GPIO_LED Clock */
-  RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
-  /* Configure the GPIO_LED pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Turns selected LED On.
-  * @param  Led: Specifies the Led to be set on. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];     
-}
-
-/**
-  * @brief  Turns selected LED Off.
-  * @param  Led: Specifies the Led to be set off. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4 
-  * @retval None
-  */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];    
-}
-
-/**
-  * @brief  Toggles the selected LED.
-  * @param  Led: Specifies the Led to be toggled. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Configures Button GPIO and EXTI Line.
-  * @param  Button: Specifies the Button to be configured.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button
-  * @param  Button_Mode: Specifies Button mode.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
-  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
-  *                     generation capability  
-  * @retval None
-  */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable the BUTTON Clock */
-  RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Configure Button pin as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
-  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
-  if (Button_Mode == BUTTON_MODE_EXTI)
-  {
-    /* Connect Button EXTI Line to Button GPIO Pin */
-    GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
-    /* Configure Button EXTI line */
-    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
-    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-
-    if(Button != BUTTON_WAKEUP)
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-    }
-    else
-    {
-      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-    }
-    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-    EXTI_Init(&EXTI_InitStructure);
-
-    /* Enable and set Button EXTI Interrupt to the lowest priority */
-    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-    NVIC_Init(&NVIC_InitStructure); 
-  }
-}
-
-/**
-  * @brief  Returns the selected Button state.
-  * @param  Button: Specifies the Button to be checked.
-  *   This parameter can be one of following parameters:    
-  *     @arg BUTTON_WAKEUP: Wakeup Push Button
-  *     @arg BUTTON_TAMPER: Tamper Push Button  
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button    
-  * @retval The Button GPIO pin value.
-  */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
-  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-}
-
-/**
-  * @brief  Configures COM port.
-  * @param  COM: Specifies the COM port to be configured.
-  *   This parameter can be one of following parameters:    
-  *     @arg COM1
-  *     @arg COM2  
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
-  *   contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable UART clock */
-  if (COM == COM1)
-  {
-    RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
-  }
-  else
-  {
-    RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-  }
-
-  /* Configure USART Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-
-  /* Configure USART Rx as input floating */
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
-  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
-  /* USART configuration */
-  USART_Init(COM_USART[COM], USART_InitStruct);
-    
-  /* Enable USART */
-  USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
-  * @brief  DeInitializes the SDIO interface.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /*!< Disable SDIO Clock */
-  SDIO_ClockCmd(DISABLE);
-  
-  /*!< Set Power State to OFF */
-  SDIO_SetPowerState(SDIO_PowerState_OFF);
-
-  /*!< DeInitializes the SDIO peripheral */
-  SDIO_DeInit();
-  
-  /*!< Disable the SDIO AHB Clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, DISABLE);
-
-  /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  /*!< Configure PD.02 CMD line */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
-  *         data transfer).
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< GPIOC and GPIOD Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);
-
-  /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  /*!< Configure PD.02 CMD line */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Enable the SDIO AHB Clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE);
-
-  /*!< Enable the DMA2 Clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
-}
-
-/**
-  * @brief  Configures the DMA2 Channel4 for SDIO Tx request.
-  * @param  BufferSRC: pointer to the source buffer
-  * @param  BufferSize: buffer size
-  * @retval None
-  */
-void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
-{
-
-  DMA_InitTypeDef DMA_InitStructure;
-
-  DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
-
-  /*!< DMA2 Channel4 disable */
-  DMA_Cmd(DMA2_Channel4, DISABLE);
-
-  /*!< DMA2 Channel4 Config */
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA2_Channel4, &DMA_InitStructure);
-
-  /*!< DMA2 Channel4 enable */
-  DMA_Cmd(DMA2_Channel4, ENABLE);  
-}
-
-/**
-  * @brief  Configures the DMA2 Channel4 for SDIO Rx request.
-  * @param  BufferDST: pointer to the destination buffer
-  * @param  BufferSize: buffer size
-  * @retval None
-  */
-void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
-{
-  DMA_InitTypeDef DMA_InitStructure;
-
-  DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
-
-  /*!< DMA2 Channel4 disable */
-  DMA_Cmd(DMA2_Channel4, DISABLE);
-
-  /*!< DMA2 Channel4 Config */
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
-  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST;
-  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
-  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
-  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
-  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(DMA2_Channel4, &DMA_InitStructure);
-
-  /*!< DMA2 Channel4 enable */
-  DMA_Cmd(DMA2_Channel4, ENABLE); 
-}
-
-/**
-  * @brief  Returns the DMA End Of Transfer Status.
-  * @param  None
-  * @retval DMA SDIO Channel Status.
-  */
-uint32_t SD_DMAEndOfTransferStatus(void)
-{
-  return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4);
-}
-
-/**
-  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< Disable the sFLASH_SPI  */
-  SPI_Cmd(sFLASH_SPI, DISABLE);
-  
-  /*!< DeInitializes the sFLASH_SPI */
-  SPI_I2S_DeInit(sFLASH_SPI);
-  
-  /*!< sFLASH_SPI Periph clock disable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the peripherals used by the SPI FLASH driver.
-  * @param  None
-  * @retval None
-  */
-void sFLASH_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO 
-       and sFLASH_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
-                         sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
-
-  /*!< sFLASH_SPI Periph clock enable */
-  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
-  
-  /*!< Configure sFLASH_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
-  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sFLASH_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
-  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  DeInitializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< Disable LM75_I2C */
-  I2C_Cmd(LM75_I2C, DISABLE);
-  /*!< DeInitializes the LM75_I2C */
-  I2C_DeInit(LM75_I2C);
-  
-  /*!< LM75_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
-    
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the LM75_I2C..
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< LM75_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
-    
-  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
-       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
-                         LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
-  
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
deleted file mode 100644
index 69dcff1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains definitions for STM3210E_EVAL's Leds, push-buttons
-  *          COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C)
-  *          hardware resources.  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210E_EVAL_H
-#define __STM3210E_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */  
-  
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL
-  * @{
-  */ 
-  
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Types
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Constants
-  * @{
-  */ 
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_LED
-  * @{
-  */
-#define LEDn                             4
-
-#define LED1_PIN                         GPIO_Pin_6
-#define LED1_GPIO_PORT                   GPIOF
-#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-  
-#define LED2_PIN                         GPIO_Pin_7
-#define LED2_GPIO_PORT                   GPIOF
-#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-
-#define LED3_PIN                         GPIO_Pin_8  
-#define LED3_GPIO_PORT                   GPIOF
-#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOF  
-
-#define LED4_PIN                         GPIO_Pin_9
-#define LED4_GPIO_PORT                   GPIOF
-#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOF
-
-/**
-  * @}
-  */
-  
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_BUTTON
-  * @{
-  */  
-#define BUTTONn                          8
-
-/**
- * @brief Wakeup push-button
- */
-#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
-#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
-#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
-#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
-#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
-#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
-#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
-/**
- * @brief Tamper push-button
- */
-#define TAMPER_BUTTON_PIN                GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT          GPIOC
-#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
-/**
- * @brief Key push-button
- */
-#define KEY_BUTTON_PIN                   GPIO_Pin_8
-#define KEY_BUTTON_GPIO_PORT             GPIOG
-#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
-#define KEY_BUTTON_EXTI_LINE             EXTI_Line8
-#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
-#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource8
-#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
-/**
- * @brief Joystick Right push-button
- */
-#define RIGHT_BUTTON_PIN                 GPIO_Pin_13
-#define RIGHT_BUTTON_GPIO_PORT           GPIOG
-#define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOG
-#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line13
-#define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOG
-#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource13
-#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
-/**
- * @brief Joystick Left push-button
- */    
-#define LEFT_BUTTON_PIN                  GPIO_Pin_14
-#define LEFT_BUTTON_GPIO_PORT            GPIOG
-#define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
-#define LEFT_BUTTON_EXTI_LINE            EXTI_Line14
-#define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
-#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
-#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
-/**
- * @brief Joystick Up push-button
- */
-#define UP_BUTTON_PIN                    GPIO_Pin_15
-#define UP_BUTTON_GPIO_PORT              GPIOG
-#define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOG
-#define UP_BUTTON_EXTI_LINE              EXTI_Line15
-#define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOG
-#define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource15
-#define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn  
-/**
- * @brief Joystick Down push-button
- */   
-#define DOWN_BUTTON_PIN                  GPIO_Pin_3
-#define DOWN_BUTTON_GPIO_PORT            GPIOD
-#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
-#define DOWN_BUTTON_EXTI_LINE            EXTI_Line3
-#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
-#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource3
-#define DOWN_BUTTON_EXTI_IRQn            EXTI3_IRQn  
-/**
- * @brief Joystick Sel push-button
- */  
-#define SEL_BUTTON_PIN                   GPIO_Pin_7
-#define SEL_BUTTON_GPIO_PORT             GPIOG
-#define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
-#define SEL_BUTTON_EXTI_LINE             EXTI_Line7
-#define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
-#define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource7
-#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn          
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_COM
-  * @{
-  */
-#define COMn                             2
-
-/**
- * @brief Definition for COM port1, connected to USART1
- */ 
-#define EVAL_COM1                        USART1
-#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
-#define EVAL_COM1_TX_PIN                 GPIO_Pin_9
-#define EVAL_COM1_TX_GPIO_PORT           GPIOA
-#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_RX_PIN                 GPIO_Pin_10
-#define EVAL_COM1_RX_GPIO_PORT           GPIOA
-#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM1_IRQn                   USART1_IRQn
-
-/**
- * @brief Definition for COM port2, connected to USART2
- */ 
-#define EVAL_COM2                        USART2
-#define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
-#define EVAL_COM2_TX_PIN                 GPIO_Pin_2
-#define EVAL_COM2_TX_GPIO_PORT           GPIOA
-#define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM2_RX_PIN                 GPIO_Pin_3
-#define EVAL_COM2_RX_GPIO_PORT           GPIOA
-#define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
-#define EVAL_COM2_IRQn                   USART2_IRQn
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_SD_FLASH
-  * @{
-  */
-/**
-  * @brief  SD FLASH SDIO Interface
-  */ 
-
-#define SD_DETECT_PIN                    GPIO_Pin_11                 /* PF.11 */
-#define SD_DETECT_GPIO_PORT              GPIOF                       /* GPIOF */
-#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOF
-
-#define SDIO_FIFO_ADDRESS                ((uint32_t)0x40018080)
-/** 
-  * @brief  SDIO Intialization Frequency (400KHz max)
-  */
-#define SDIO_INIT_CLK_DIV                ((uint8_t)0xB2)
-/** 
-  * @brief  SDIO Data Transfer Frequency (25MHz max) 
-  */
-#define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x00) 
-
-/**
-  * @}
-  */ 
-  
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
-  * @{
-  */
-/**
-  * @brief  M25P FLASH SPI Interface pins
-  */  
-#define sFLASH_SPI                       SPI1
-#define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
-#define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
-#define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
-#define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
-#define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
-#define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
-#define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_CS_PIN                    GPIO_Pin_2                  /* PB.02 */
-#define sFLASH_CS_GPIO_PORT              GPIOB                       /* GPIOB */
-#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOB
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C
-  * @{
-  */
-/**
-  * @brief  LM75 Temperature Sensor I2C Interface pins
-  */  
-#define LM75_I2C                         I2C1
-#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
-#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
-#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
-#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
-#define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
-#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
-#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
-#define LM75_I2C_DR                      ((uint32_t)0x40005410)
-
-#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
-#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
-#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
-#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
-#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Functions
-  * @{
-  */ 
-void STM_EVAL_LEDInit(Led_TypeDef Led);
-void STM_EVAL_LEDOn(Led_TypeDef Led);
-void STM_EVAL_LEDOff(Led_TypeDef Led);
-void STM_EVAL_LEDToggle(Led_TypeDef Led);
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
-void SD_LowLevel_DeInit(void);
-void SD_LowLevel_Init(void); 
-void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
-void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
-uint32_t SD_DMAEndOfTransferStatus(void);
-void sFLASH_LowLevel_DeInit(void);
-void sFLASH_LowLevel_Init(void); 
-void LM75_LowLevel_DeInit(void);
-void LM75_LowLevel_Init(void); 
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-  
-#endif /* __STM3210E_EVAL_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
deleted file mode 100644
index 97f1022..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_fsmc_nand.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to drive the
-  *          NAND512W3A2 memory mounted on STM3210E-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210e_eval_fsmc_nand.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM3210E_EVAL_FSMC_NAND
-  * @brief      This file provides a set of functions needed to drive the
-  *             NAND512W3A2 memory mounted on STM3210E-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
-  * @{
-  */ 
-/** 
-  * @brief  FSMC Bank 2 
-  */
-#define FSMC_Bank_NAND     FSMC_Bank2_NAND
-#define Bank_NAND_ADDR     Bank2_NAND_ADDR 
-#define Bank2_NAND_ADDR    ((uint32_t)0x70000000)     
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
-  * @{
-  */
-#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)  
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures the FSMC and GPIOs to interface with the NAND memory.
-  *         This function must be called before any write/read operation on the 
-  *         NAND.
-  * @param  None
-  * @retval None
-  */
-void NAND_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure; 
-  FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
-  FSMC_NAND_PCCARDTimingInitTypeDef  p;
-  
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
-                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
-  
-/*-- GPIO Configuration ------------------------------------------------------*/
-/*!< CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |  
-                                 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | 
-                                 GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-
-  GPIO_Init(GPIOD, &GPIO_InitStructure); 
-
-/*!< D4->D7 NAND pin configuration  */  
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
-
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-
-/*!< NWAIT NAND pin configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-
-  GPIO_Init(GPIOD, &GPIO_InitStructure); 
-
-/*!< INT2 NAND pin configuration */  
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-  /*-- FSMC Configuration ------------------------------------------------------*/
-  p.FSMC_SetupTime = 0x0;
-  p.FSMC_WaitSetupTime = 0x2;
-  p.FSMC_HoldSetupTime = 0x1;
-  p.FSMC_HiZSetupTime = 0x0;
-
-  FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
-  FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
-  FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
-  FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
-  FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
-  FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
-  FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
-  FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
-  FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
-
-  FSMC_NANDInit(&FSMC_NANDInitStructure);
-
-  /*!< FSMC NAND Bank Cmd Test */
-  FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
-}
-
-/**
-  * @brief  Reads NAND memory's ID.
-  * @param  NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
-  *         the Manufacturer and Device ID.  
-  * @retval None
-  */
-void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
-{
-  uint32_t data = 0;
-
-  /*!< Send Command to the command area */
-  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
-  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
-
-   /*!< Sequence to read ID from NAND flash */
-   data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
-
-   NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
-   NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
-   NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
-   NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);
-}
-
-/**
-  * @brief  This routine is for writing one or several 512 Bytes Page size.
-  * @param  pBuffer: pointer on the Buffer containing data to be written 
-  * @param  Address: First page address
-  * @param  NumPageToWrite: Number of page to write  
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation 
-  *                And the new status of the increment address operation. It can be:
-  *              - NAND_VALID_ADDRESS: When the new address is valid address
-  *              - NAND_INVALID_ADDRESS: When the new address is invalid address  
-  */
-uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
-{
-  uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
-  uint32_t status = NAND_READY, size = 0x00;
-
-  while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
-  {
-    /*!< Page write command and address */
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
-
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
-
-    /*!< Calculate the size */
-    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
-
-    /*!< Write data */
-    for(; index < size; index++)
-    {
-      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
-    }
-    
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
-
-    /*!< Check status for successful operation */
-    status = NAND_GetStatus();
-    
-    if(status == NAND_READY)
-    {
-      numpagewritten++;
-
-      NumPageToWrite--;
-
-      /*!< Calculate Next small page Address */
-      addressstatus = NAND_AddressIncrement(&Address);
-    }
-  }
-  
-  return (status | addressstatus);
-}
-
-/**
-  * @brief  This routine is for sequential read from one or several 512 Bytes Page size.
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  Address: First page address
-  * @param  NumPageToRead: Number of page to read  
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation 
-  *                And the new status of the increment address operation. It can be:
-  *              - NAND_VALID_ADDRESS: When the new address is valid address
-  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
-  */
-uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
-{
-  uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
-  uint32_t status = NAND_READY, size = 0x00;
-
-  while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
-  {
-    /*!< Page Read command and page address */
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
-   
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
-    
-    /*!< Calculate the size */
-    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
-    
-    /*!< Get Data into Buffer */    
-    for(; index < size; index++)
-    {
-      pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
-    }
-
-    numpageread++;
-    
-    NumPageToRead--;
-
-    /*!< Calculate page address */
-    addressstatus = NAND_AddressIncrement(&Address);
-  }
-
-  status = NAND_GetStatus();
-  
-  return (status | addressstatus);
-}
-
-/**
-  * @brief  This routine write the spare area information for the specified
-  *         pages addresses.  
-  * @param  pBuffer: pointer on the Buffer containing data to be written 
-  * @param  Address: First page address
-  * @param  NumSpareAreaTowrite: Number of Spare Area to write
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation 
-  *                And the new status of the increment address operation. It can be:
-  *              - NAND_VALID_ADDRESS: When the new address is valid address
-  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
-  */
-uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
-{
-  uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
-  uint32_t status = NAND_READY, size = 0x00; 
-
-  while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
-  {
-    /*!< Page write Spare area command and address */
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
-
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
-
-    /*!< Calculate the size */ 
-    size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
-
-    /*!< Write the data */ 
-    for(; index < size; index++)
-    {
-      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
-    }
-    
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
-
-    /*!< Check status for successful operation */
-    status = NAND_GetStatus();
-
-    if(status == NAND_READY)
-    {
-      numsparesreawritten++;
-
-      NumSpareAreaTowrite--;
-    
-      /*!< Calculate Next page Address */
-      addressstatus = NAND_AddressIncrement(&Address);
-    }
-  }
-  
-  return (status | addressstatus);
-}
-
-/**
-  * @brief  This routine read the spare area information from the specified
-  *         pages addresses.  
-  * @param  pBuffer: pointer on the Buffer to fill 
-  * @param  Address: First page address
-  * @param  NumSpareAreaToRead: Number of Spare Area to read
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation 
-  *                And the new status of the increment address operation. It can be:
-  *              - NAND_VALID_ADDRESS: When the new address is valid address
-  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
-  */
-uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
-{
-  uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
-  uint32_t status = NAND_READY, size = 0x00;
-
-  while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
-  {     
-    /*!< Page Read command and page address */
-    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
-
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
-    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
-
-    /*!< Data Read */
-    size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
-
-    /*!< Get Data into Buffer */
-    for ( ;index < size; index++)
-    {
-      pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
-    }
-    
-    numsparearearead++;
-    
-    NumSpareAreaToRead--;
-
-    /*!< Calculate page address */
-    addressstatus = NAND_AddressIncrement(&Address);
-  }
-
-  status = NAND_GetStatus();
-
-  return (status | addressstatus);
-}
-
-/**
-  * @brief  This routine erase complete block from NAND FLASH
-  * @param  Address: Any address into block to be erased
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation 
-  */
-uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
-{
-  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
-
-  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
-  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
-  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
-
-  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; 
-
-  return (NAND_GetStatus());
-}
-
-/**
-  * @brief  This routine reset the NAND FLASH.
-  * @param  None
-  * @retval NAND_READY
-  */
-uint32_t NAND_Reset(void)
-{
-  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
-
-  return (NAND_READY);
-}
-
-/**
-  * @brief  Get the NAND operation status.
-  * @param  None
-  * @retval New status of the NAND operation. This parameter can be:
-  *              - NAND_TIMEOUT_ERROR: when the previous operation generate
-  *                a Timeout error
-  *              - NAND_READY: when memory is ready for the next operation
-  */
-uint32_t NAND_GetStatus(void)
-{
-  uint32_t timeout = 0x1000000, status = NAND_READY;
-
-  status = NAND_ReadStatus();
-
-  /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
-  while ((status != NAND_READY) &&( timeout != 0x00))
-  {
-     status = NAND_ReadStatus();
-     timeout --;
-  }
-
-  if(timeout == 0x00)
-  {
-    status =  NAND_TIMEOUT_ERROR;
-  }
-
-  /*!< Return the operation status */
-  return (status);
-}
-  
-/**
-  * @brief  Reads the NAND memory status using the Read status command. 
-  * @param  None
-  * @retval The status of the NAND memory. This parameter can be:
-  *              - NAND_BUSY: when memory is busy
-  *              - NAND_READY: when memory is ready for the next operation
-  *              - NAND_ERROR: when the previous operation gererates error
-  */
-uint32_t NAND_ReadStatus(void)
-{
-  uint32_t data = 0x00, status = NAND_BUSY;
-
-  /*!< Read status operation ------------------------------------ */
-  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
-  data = *(__IO uint8_t *)(Bank_NAND_ADDR);
-
-  if((data & NAND_ERROR) == NAND_ERROR)
-  {
-    status = NAND_ERROR;
-  } 
-  else if((data & NAND_READY) == NAND_READY)
-  {
-    status = NAND_READY;
-  }
-  else
-  {
-    status = NAND_BUSY; 
-  }
-  
-  return (status);
-}
-
-/**
-  * @brief  Increment the NAND memory address. 
-  * @param  Address: address to be incremented.
-  * @retval The new status of the increment address operation. It can be:
-  *              - NAND_VALID_ADDRESS: When the new address is valid address
-  *              - NAND_INVALID_ADDRESS: When the new address is invalid address   
-  */
-uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
-{
-  uint32_t status = NAND_VALID_ADDRESS;
- 
-  Address->Page++;
-
-  if(Address->Page == NAND_BLOCK_SIZE)
-  {
-    Address->Page = 0;
-    Address->Block++;
-    
-    if(Address->Block == NAND_ZONE_SIZE)
-    {
-      Address->Block = 0;
-      Address->Zone++;
-
-      if(Address->Zone == NAND_MAX_ZONE)
-      {
-        status = NAND_INVALID_ADDRESS;
-      }
-    }
-  } 
-  
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
deleted file mode 100644
index e3a03d8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_fsmc_nor.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to drive the M29W128FL, 
-  *          M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210e_eval_fsmc_nor.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM3210E_EVAL_FSMC_NOR
-  * @brief      This file provides a set of functions needed to drive the M29W128FL, 
-  *             M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines
-  * @{
-  */ 
-/** 
-  * @brief  FSMC Bank 1 NOR/SRAM2  
-  */
-#define Bank1_NOR2_ADDR       ((uint32_t)0x64000000)
-
-/* Delay definition */   
-#define BlockErase_Timeout    ((uint32_t)0x00A00000)
-#define ChipErase_Timeout     ((uint32_t)0x30000000) 
-#define Program_Timeout       ((uint32_t)0x00001400)     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros
-  * @{
-  */
-#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
-#define NOR_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))  
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Configures the FSMC and GPIOs to interface with the NOR memory.
-  *         This function must be called before any write/read operation
-  *         on the NOR.
-  * @param  None
-  * @retval None
-  */
-void NOR_Init(void)
-{
-  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
-  FSMC_NORSRAMTimingInitTypeDef  p;
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
-                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
-
-  /*-- GPIO Configuration ------------------------------------------------------*/
-  /*!< NOR Data lines configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
-                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
-                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
-                                GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /*!< NOR Address lines configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
-                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
-                                GPIO_Pin_14 | GPIO_Pin_15;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
-                                GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-
-  /*!< NOE and NWE configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-
-  /*!< NE2 configuration */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-  /*!< Configure PD6 for NOR memory Ready/Busy signal */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-  
-  /*-- FSMC Configuration ----------------------------------------------------*/
-  p.FSMC_AddressSetupTime = 0x02;
-  p.FSMC_AddressHoldTime = 0x00;
-  p.FSMC_DataSetupTime = 0x05;
-  p.FSMC_BusTurnAroundDuration = 0x00;
-  p.FSMC_CLKDivision = 0x00;
-  p.FSMC_DataLatency = 0x00;
-  p.FSMC_AccessMode = FSMC_AccessMode_B;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
-
-  /*!< Enable FSMC Bank1_NOR Bank */
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
-}
-
-/**
-  * @brief  Reads NOR memory's Manufacturer and Device Code.
-  * @param  NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the 
-  *         Manufacturer and Device Code.  
-  * @retval None
-  */
-void NOR_ReadID(NOR_IDTypeDef* NOR_ID)
-{
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
-
-  NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
-  NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
-  NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
-  NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
-}
-
-/**
-  * @brief  Erases the specified Nor memory block.
-  * @param  BlockAddr: address of the block to erase.
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_EraseBlock(uint32_t BlockAddr)
-{
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
-
-  return (NOR_GetStatus(BlockErase_Timeout));
-}
-
-/**
-  * @brief  Erases the entire chip.
-  * @param  None                      
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_EraseChip(void)
-{
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
-
-  return (NOR_GetStatus(ChipErase_Timeout));
-}
-
-/**
-  * @brief  Writes a half-word to the NOR memory.
-  * @param  WriteAddr: NOR memory internal address to write to.
-  * @param  Data: Data to write. 
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
-{
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
-  NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
-
-  return (NOR_GetStatus(Program_Timeout));
-}
-
-/**
-  * @brief  Writes a half-word buffer to the FSMC NOR memory. 
-  * @param  pBuffer: pointer to buffer. 
-  * @param  WriteAddr: NOR memory internal address from which the data will be 
-  *         written.
-  * @param  NumHalfwordToWrite: number of Half words to write. 
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
-{
-  NOR_Status status = NOR_ONGOING; 
-
-  do
-  {
-    /*!< Transfer data to the memory */
-    status = NOR_WriteHalfWord(WriteAddr, *pBuffer++);
-    WriteAddr = WriteAddr + 2;
-    NumHalfwordToWrite--;
-  }
-  while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
-  
-  return (status); 
-}
-
-/**
-  * @brief  Writes a half-word buffer to the FSMC NOR memory. This function 
-  *         must be used only with S29GL128P NOR memory.
-  * @param  pBuffer: pointer to buffer. 
-  * @param  WriteAddr: NOR memory internal address from which the data will be 
-  *         written.
-  * @param  NumHalfwordToWrite: number of Half words to write.
-  *         The maximum allowed value is 32 Half words (64 bytes).
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
-{
-  uint32_t lastloadedaddress = 0x00;
-  uint32_t currentaddress = 0x00;
-  uint32_t endaddress = 0x00;
-
-  /*!< Initialize variables */
-  currentaddress = WriteAddr;
-  endaddress = WriteAddr + NumHalfwordToWrite - 1;
-  lastloadedaddress = WriteAddr;
-
-  /*!< Issue unlock command sequence */
-  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
-
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);  
-
-  /*!< Write Write Buffer Load Command */
-  NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
-  NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
-
-  /*!< Load Data into NOR Buffer */
-  while(currentaddress <= endaddress)
-  {
-    /*!< Store last loaded address & data value (for polling) */
-    lastloadedaddress = currentaddress;
- 
-    NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
-    currentaddress += 1; 
-  }
-
-  NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
-  
-  return(NOR_GetStatus(Program_Timeout));
-}
-
-/**
-  * @brief  Reads a half-word from the NOR memory. 
-  * @param  ReadAddr: NOR memory internal address to read from.
-  * @retval Half-word read from the NOR memory
-  */
-uint16_t NOR_ReadHalfWord(uint32_t ReadAddr)
-{
-  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
-  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);  
-  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
-
-  return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
-}
-
-/**
-  * @brief  Reads a block of data from the FSMC NOR memory.
-  * @param  pBuffer: pointer to the buffer that receives the data read from the 
-  *         NOR memory.
-  * @param  ReadAddr: NOR memory internal address to read from.
-  * @param  NumHalfwordToRead : number of Half word to read.
-  * @retval None
-  */
-void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
-{
-  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
-  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
-  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
-
-  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */
-  {
-    /*!< Read a Halfword from the NOR */
-    *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
-    ReadAddr = ReadAddr + 2; 
-  }  
-}
-
-/**
-  * @brief  Returns the NOR memory to Read mode.
-  * @param  None
-  * @retval NOR_SUCCESS
-  */
-NOR_Status NOR_ReturnToReadMode(void)
-{
-  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
-
-  return (NOR_SUCCESS);
-}
-
-/**
-  * @brief  Returns the NOR memory to Read mode and resets the errors in the NOR 
-  *         memory Status Register.  
-  * @param  None
-  * @retval NOR_SUCCESS
-  */
-NOR_Status NOR_Reset(void)
-{
-  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
-  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); 
-  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); 
-
-  return (NOR_SUCCESS);
-}
-
-/**
-  * @brief  Returns the NOR operation status.
-  * @param  Timeout: NOR progamming Timeout
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_Status NOR_GetStatus(uint32_t Timeout)
-{ 
-  uint16_t val1 = 0x00, val2 = 0x00;
-  NOR_Status status = NOR_ONGOING; 
-  uint32_t timeout = Timeout;
-
-  /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/
-  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) 
-  {
-    timeout--;
-  }
-
-  timeout = Timeout;
-  
-  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))   
-  {
-    timeout--;
-  }
-  
-  /*!< Get the NOR memory operation status -----------------------------------*/
-  while((Timeout != 0x00) && (status != NOR_SUCCESS))
-  {
-    Timeout--;
-
-    /*!< Read DQ6 and DQ5 */
-    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
-    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
-
-    /*!< If DQ6 did not toggle between the two reads then return NOR_Success */
-    if((val1 & 0x0040) == (val2 & 0x0040)) 
-    {
-      return NOR_SUCCESS;
-    }
-
-    if((val1 & 0x0020) != 0x0020)
-    {
-      status = NOR_ONGOING;
-    }
-
-    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
-    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
-    
-    if((val1 & 0x0040) == (val2 & 0x0040)) 
-    {
-      return NOR_SUCCESS;
-    }
-    else if((val1 & 0x0020) == 0x0020)
-    {
-      return NOR_ERROR;
-    }
-  }
-
-  if(Timeout == 0x00)
-  {
-    status = NOR_TIMEOUT;
-  } 
-
-  /*!< Return the operation status */
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
deleted file mode 100644
index 7423f49..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_fsmc_nor.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the 
-  *          stm3210e_eval_fsmc_nor firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210E_EVAL_FSMC_NOR_H
-#define __STM3210E_EVAL_FSMC_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM3210E_EVAL_FSMC_NOR
-  * @{
-  */  
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Types
-  * @{
-  */
-typedef struct
-{
-  uint16_t Manufacturer_Code;
-  uint16_t Device_Code1;
-  uint16_t Device_Code2;
-  uint16_t Device_Code3;
-}NOR_IDTypeDef;
-
-/* NOR Status */
-typedef enum
-{
-  NOR_SUCCESS = 0,
-  NOR_ONGOING,
-  NOR_ERROR,
-  NOR_TIMEOUT
-}NOR_Status;  
-/**
-  * @}
-  */
-  
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Constants
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Functions
-  * @{
-  */ 
-void NOR_Init(void);
-void NOR_ReadID(NOR_IDTypeDef* NOR_ID);
-NOR_Status NOR_EraseBlock(uint32_t BlockAddr);
-NOR_Status NOR_EraseChip(void);
-NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data);
-NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
-NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
-uint16_t NOR_ReadHalfWord(uint32_t ReadAddr);
-void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
-NOR_Status NOR_ReturnToReadMode(void);
-NOR_Status NOR_Reset(void);
-NOR_Status NOR_GetStatus(uint32_t Timeout);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210E_EVAL_FSMC_NOR_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c
deleted file mode 100644
index f9277af..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c
+++ /dev/null
@@ -1,1329 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H 
-  *          (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal
-  *          Display Module of STM3210E-EVAL board.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm3210e_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-    
-/** @defgroup STM3210E_EVAL_LCD 
-  * @brief This file includes the LCD driver for AM-240320L8TNQW00H 
-  *        (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal
-  *        Display Module of STM3210E-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Private_TypesDefinitions
-  * @{
-  */ 
-typedef struct
-{
-  __IO uint16_t LCD_REG;
-  __IO uint16_t LCD_RAM;
-} LCD_TypeDef;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LCD_Private_Defines
-  * @{
-  */
-/* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */
-#define LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
-#define LCD                ((LCD_TypeDef *) LCD_BASE)
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))                                
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Private_Macros
-  * @{
-  */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))    
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM3210E_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-  
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LCD_Private_FunctionPrototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(vu32 nCount);
-#endif /* USE_Delay*/
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM3210E_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_DeInit(void)
-{ 
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
-  
-  /*!< LCD_SPI DeInit */
-  FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
-   
-  /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
-     PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
-                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-  /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
-     PE.14(D11), PE.15(D12) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
-                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_Init(GPIOG, &GPIO_InitStructure); 
-}
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM3210E_LCD_Init(void)
-{ 
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-/* Configure the FSMC Parallel interface -------------------------------------*/
-  LCD_FSMCConfig();
-  
-  _delay_(5); /* delay 50 ms */
-  /* Check if the LCD is SPFD5408B Controller */
-  if(LCD_ReadReg(0x00) == 0x5408)
-  {
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_1, 0x0100);  /* Set SS bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700);  /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1030);  /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000);  /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202);  /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000);  /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                   /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    _delay_(5);                  /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
-    _delay_(5); 
-    LCD_WriteReg(LCD_REG_19, 0x1400);  /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
-    _delay_(5);                   /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0b0d);
-    LCD_WriteReg(LCD_REG_49, 0x1923);
-    LCD_WriteReg(LCD_REG_50, 0x1c26);
-    LCD_WriteReg(LCD_REG_51, 0x261c);
-    LCD_WriteReg(LCD_REG_52, 0x2419);
-    LCD_WriteReg(LCD_REG_53, 0x0d0b);
-    LCD_WriteReg(LCD_REG_54, 0x1006);
-    LCD_WriteReg(LCD_REG_55, 0x0610);
-    LCD_WriteReg(LCD_REG_56, 0x0706);
-    LCD_WriteReg(LCD_REG_57, 0x0304);
-    LCD_WriteReg(LCD_REG_58, 0x0e05);
-    LCD_WriteReg(LCD_REG_59, 0x0e01);
-    LCD_WriteReg(LCD_REG_60, 0x010e);
-    LCD_WriteReg(LCD_REG_61, 0x050e);
-    LCD_WriteReg(LCD_REG_62, 0x0403);
-    LCD_WriteReg(LCD_REG_63, 0x0607);
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL, VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010); 
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR=1
-       I/D=01 (Horizontal : increment, Vertical : decrement)
-       AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
-    LCD_SetFont(&LCD_DEFAULT_FONT);
-    return;
-  }
-/* Start Initial Sequence ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
-  LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-  LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-  LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-  LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-  LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-  LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-  LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-  LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-  LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-  LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-  LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-/* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-  LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-/* Adjust the Gamma Curve ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_48, 0x0006);
-  LCD_WriteReg(LCD_REG_49, 0x0101);
-  LCD_WriteReg(LCD_REG_50, 0x0003);
-  LCD_WriteReg(LCD_REG_53, 0x0106);
-  LCD_WriteReg(LCD_REG_54, 0x0b02);
-  LCD_WriteReg(LCD_REG_55, 0x0302);
-  LCD_WriteReg(LCD_REG_56, 0x0707);
-  LCD_WriteReg(LCD_REG_57, 0x0007);
-  LCD_WriteReg(LCD_REG_60, 0x0600);
-  LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-/* Set GRAM area -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-  LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-  LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-  LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-  LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-/* Partial Display Control ---------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_128, 0x0000);
-  LCD_WriteReg(LCD_REG_129, 0x0000);
-  LCD_WriteReg(LCD_REG_130, 0x0000);
-  LCD_WriteReg(LCD_REG_131, 0x0000);
-  LCD_WriteReg(LCD_REG_132, 0x0000);
-  LCD_WriteReg(LCD_REG_133, 0x0000);
-/* Panel Control -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_144, 0x0010);
-  LCD_WriteReg(LCD_REG_146, 0x0000);
-  LCD_WriteReg(LCD_REG_147, 0x0003);
-  LCD_WriteReg(LCD_REG_149, 0x0110);
-  LCD_WriteReg(LCD_REG_151, 0x0000);
-  LCD_WriteReg(LCD_REG_152, 0x0000);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */  
-  LCD_SetFont(&LCD_DEFAULT_FONT);  
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 76800; index++)
-  {
-    LCD->LCD_RAM = Color;
-  }  
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
-  LCD_WriteReg(LCD_REG_32, Xpos);
-  LCD_WriteReg(LCD_REG_33, Ypos);
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  /* Horizontal GRAM Start Address */
-  if(Xpos >= Height)
-  {
-    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-  }
-  else
-  {
-    LCD_WriteReg(LCD_REG_80, 0);
-  }
-  /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_81, Xpos);
-  /* Vertical GRAM Start Address */
-  if(Ypos >= Width)
-  {
-    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-  }  
-  else
-  {
-    LCD_WriteReg(LCD_REG_82, 0);
-  }
-  /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_83, Ypos);
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-  LCD_WriteReg(LCD_REG_3, 0x1018);    
-}
-
-
-/**
-  * @brief  Displays a line.
-  * @param Xpos: specifies the X position.
-  * @param Ypos: specifies the Y position.
-  * @param Length: line length.
-  * @param Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  if(Direction == LCD_DIR_HORIZONTAL)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-  }
-  else
-  {
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-      LCD_WriteRAM(TextColor);
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    LCD_WriteRAM(TextColor);
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a bitmap picture loaded in the internal Flash.
-  * @param  BmpAddress: Bmp picture address in the internal Flash.
-  * @retval None
-  */
-void LCD_WriteBMP(uint32_t BmpAddress)
-{
-  uint32_t index = 0, size = 0;
-  /* Read bitmap size */
-  size = *(__IO uint16_t *) (BmpAddress + 2);
-  size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16;
-  /* Get bitmap data address offset */
-  index = *(__IO uint16_t *) (BmpAddress + 10);
-  index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16;
-  size = (size - index)/2;
-  BmpAddress += index;
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1008);
- 
-  LCD_WriteRAM_Prepare();
- 
-  for(index = 0; index < size; index++)
-  {
-    LCD_WriteRAM(*(__IO uint16_t *)BmpAddress);
-    BmpAddress += 2;
-  }
- 
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-  /* AM = 1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-}
-
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index, then Write Reg */
-  LCD->LCD_REG = LCD_Reg;
-  /* Write 16-bit Reg */
-  LCD->LCD_RAM = LCD_RegValue;
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_Reg;
-  /* Read 16-bit Reg */
-  return (LCD->LCD_RAM);
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD->LCD_REG = LCD_REG_34;
-}
-
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  /* Write 16-bit GRAM Reg */
-  LCD->LCD_RAM = RGB_Code;
-}
-
-
-/**
-  * @brief  Reads the LCD RAM.
-  * @param  None
-  * @retval LCD RAM Value.
-  */
-uint16_t LCD_ReadRAM(void)
-{
-  /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */
-  /* Read 16-bit Reg */
-  return LCD->LCD_RAM;
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{
-/* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  /* Display On */
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  /* Display Off */
-  LCD_WriteReg(LCD_REG_7, 0x0); 
-}
-
-
-/**
-  * @brief  Configures LCD Control lines (FSMC Pins) in alternate function mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
-                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
-                         RCC_APB2Periph_AFIO, ENABLE);
-  /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
-     PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
-                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOD, &GPIO_InitStructure);
-  /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
-     PE.14(D11), PE.15(D12) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
-                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
-                                GPIO_Pin_15;
-  GPIO_Init(GPIOE, &GPIO_InitStructure);
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_Init(GPIOG, &GPIO_InitStructure);
-}
-
-
-/**
-  * @brief  Configures the Parallel interface (FSMC) for LCD(Parallel mode)
-  * @param  None
-  * @retval None
-  */
-void LCD_FSMCConfig(void)
-{
-  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
-  FSMC_NORSRAMTimingInitTypeDef  p;
-/*-- FSMC Configuration ------------------------------------------------------*/
-/*----------------------- SRAM Bank 4 ----------------------------------------*/
-  /* FSMC_Bank1_NORSRAM4 configuration */
-  p.FSMC_AddressSetupTime = 1;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 2;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-  /* Color LCD configuration ------------------------------------
-     LCD configured as follow:
-        - Data/Address MUX = Disable
-        - Memory Type = SRAM
-        - Data Width = 16bit
-        - Write Operation = Enable
-        - Extended Mode = Enable
-        - Asynchronous Wait = Disable */
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
-  /* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(vu32 nCount)
-{
-  vu32 index = 0; 
-  for(index = (100000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h
deleted file mode 100644
index 3e86c94..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm3210e_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210E_EVAL_LCD_H
-#define __STM3210E_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM3210E_EVAL_LCD
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Types
-  * @{
-  */
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;   
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h" 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif
- 
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_58            0x3A
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_229           0xE5
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Macros
-  * @{
-  */ 
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-/** @defgroup  
-  * @{
-  */ 
-void LCD_DeInit(void);  
-void STM3210E_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_WriteBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAM(uint16_t RGB_Code);
-uint16_t LCD_ReadRAM(void);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_CtrlLinesConfig(void);
-void LCD_FSMCConfig(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210E_EVAL_LCD_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
deleted file mode 100644
index 0209e69..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
+++ /dev/null
@@ -1,750 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides:
-  *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SPI) and
-  *              temperature sensor (LM75) available on STM32L152-EVAL 
-  *              evaluation board RevB from STMicroelectronics.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l152_eval.h"
-#include "stm32l1xx_spi.h"
-#include "stm32l1xx_i2c.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32L152_EVAL
-  * @{
-  */   
-    
-/** @defgroup STM32L152_EVAL_LOW_LEVEL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SPI and temperature sensor (LM75) available on 
-  *        STM32L152-EVAL evaluation board from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables
-  * @{
-  */ 
-GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
-                                 LED4_GPIO_PORT};
-const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
-                                 LED4_PIN};
-const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
-                                 LED4_GPIO_CLK};
-
-GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
-                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
-                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
-
-const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
-                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
-                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
-
-const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
-                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
-                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
-
-const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE,
-                                            RIGHT_BUTTON_EXTI_LINE,
-                                            LEFT_BUTTON_EXTI_LINE,
-                                            UP_BUTTON_EXTI_LINE,
-                                            DOWN_BUTTON_EXTI_LINE,
-                                            SEL_BUTTON_EXTI_LINE};
-
-const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE,
-                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
-                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
-                                              UP_BUTTON_EXTI_PORT_SOURCE,
-                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
-                                              SEL_BUTTON_EXTI_PORT_SOURCE};
-								 
-const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE,
-                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
-                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
-                                             UP_BUTTON_EXTI_PIN_SOURCE,
-                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
-                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
-                                             
-const uint16_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
-                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
-                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
-
-USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
-
-GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
- 
-GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
-
-const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
-
-const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
- 
-const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
-
-const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
-
-const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
- 
-const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};
-
-const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};
- 
-const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};
- 
-const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};
-
-DMA_InitTypeDef   sEEDMA_InitStructure;
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Configures LED GPIO.
-  * @param  Led: Specifies the Led to be configured. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4
-  * @retval None
-  */
-void STM_EVAL_LEDInit(Led_TypeDef Led)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* Enable the GPIO_LED Clock */
-  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
-
-  /* Configure the GPIO_LED pin */
-  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
-  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Turns selected LED On.
-  * @param  Led: Specifies the Led to be set on. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDOn(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Turns selected LED Off.
-  * @param  Led: Specifies the Led to be set off. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4 
-  * @retval None
-  */
-void STM_EVAL_LEDOff(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];  
-}
-
-/**
-  * @brief  Toggles the selected LED.
-  * @param  Led: Specifies the Led to be toggled. 
-  *   This parameter can be one of following parameters:
-  *     @arg LED1
-  *     @arg LED2
-  *     @arg LED3
-  *     @arg LED4  
-  * @retval None
-  */
-void STM_EVAL_LEDToggle(Led_TypeDef Led)
-{
-  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
-}
-
-/**
-  * @brief  Configures Button GPIO and EXTI Line.
-  * @param  Button: Specifies the Button to be configured.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button
-  * @param  Button_Mode: Specifies Button mode.
-  *   This parameter can be one of following parameters:   
-  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
-  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
-  *                     generation capability  
-  * @retval None
-  */
-void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  EXTI_InitTypeDef EXTI_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* There is no Wakeup and Tamper buttons on STM32L152-EVAL, the Button value should
-     be greater than 1. */
-  if(Button > 1)
-  {
-    Button = (Button_TypeDef) (Button - 2);
-    
-    /* Enable the BUTTON Clock */
-    RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
-    /* Configure Button pin as input */
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
-    GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
-
-
-    if (Button_Mode == BUTTON_MODE_EXTI)
-    {
-      /* Connect Button EXTI Line to Button GPIO Pin */
-      SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
-
-      /* Configure Button EXTI line */
-      EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
-      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
-    
-      if(Button != BUTTON_KEY) 
-      {
-        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
-      }
-      else
-      {
-        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
-      }
-      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-      EXTI_Init(&EXTI_InitStructure);
-
-      /* Enable and set Button EXTI Interrupt to the lowest priority */
-      NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
-      NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
-      NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
-      NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-
-      NVIC_Init(&NVIC_InitStructure); 
-    }
-  }
-}
-
-/**
-  * @brief  Returns the selected Button state.
-  * @param  Button: Specifies the Button to be checked.
-  *   This parameter can be one of following parameters:    
-  *     @arg BUTTON_KEY: Key Push Button 
-  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
-  *     @arg BUTTON_LEFT: Joystick Left Push Button 
-  *     @arg BUTTON_UP: Joystick Up Push Button 
-  *     @arg BUTTON_DOWN: Joystick Down Push Button
-  *     @arg BUTTON_SEL: Joystick Sel Push Button    
-  * @retval - When Button > 1, the Button GPIO pin value is returned.
-  *         - When Button = 0 or 1, error code (0xFF) is returned.   
-  */
-uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
-{
-  /* There is no Wakeup and Tamper pins on STM32L152-EVAL, the Button value should
-     be greater than 1. */
-  if(Button > 1)
-  {
-    Button = (Button_TypeDef) (Button - 2);
-    return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
-  }
-  else
-  {
-    return 0xFF; /* Error Code */
-  }
-}
-
-/**
-  * @brief  Configures COM port.
-  * @param  COM: Specifies the COM port to be configured.
-  *   This parameter can be one of following parameters:    
-  *     @arg COM1
-  *     @arg COM2  
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
-  *   contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Enable GPIO clock */
-  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
-
-  /* Enable UART clock */
-  RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
-
-  /* Connect PXx to USARTx_Tx */
-  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
-
-  /* Connect PXx to USARTx_Rx */
-  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
-  
-  /* Configure USART Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
-  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
-    
-  /* Configure USART Rx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
-  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
-
-  /* USART configuration */
-  USART_Init(COM_USART[COM], USART_InitStruct);
-    
-  /* Enable USART */
-  USART_Cmd(COM_USART[COM], ENABLE);
-}
-
-/**
-  * @brief  DeInitializes the SPI interface.
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
-  SPI_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
-  
-  /*!< SD_SPI Periph clock disable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); 
-
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
-  *         data transfer).
-  * @param  None
-  * @retval None
-  */
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  SPI_InitTypeDef   SPI_InitStructure;
-
-  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
-       and SD_SPI_SCK_GPIO Periph clock enable */
-  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
-                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
-
-  /*!< SD_SPI Periph clock enable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); 
-
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MISO */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
-  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI pins: MOSI */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
-  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
-  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
-  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Connect PXx to SD_SPI_SCK */
-  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
-
-  /* Connect PXx to SD_SPI_MISO */
-  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); 
-
-  /* Connect PXx to SD_SPI_MOSI */
-  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  
-  
-  /*!< SD_SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SD_SPI, &SPI_InitStructure);
-  
-  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-/**
-  * @brief  DeInitializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_DeInit(void)
-{ 
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< Disable LM75_I2C */
-  I2C_Cmd(LM75_I2C, DISABLE);
-  
-  /*!< DeInitializes the LM75_I2C */
-  I2C_DeInit(LM75_I2C);
-  
-  /*!< LM75_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
-    
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Initializes the LM75_I2C.
-  * @param  None
-  * @retval None
-  */
-void LM75_LowLevel_Init(void)
-{ 
-  GPIO_InitTypeDef  GPIO_InitStructure;
-
-  /*!< LM75_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
-    
-  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
-       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
-  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
-                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
-  
-  /*!< Configure LM75_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
-  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
-  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
-  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure LM75_I2C pin: SMBUS ALERT */
-  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
-  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
-
-
-  /* Connect PXx to I2C_SCL */
-  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
-
-  /* Connect PXx to I2C_SDA */
-  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); 
-
-  /* Connect PXx to I2C_SMBUSALER */
-  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);     
-}
-
-/**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure; 
-  NVIC_InitTypeDef NVIC_InitStructure;    
-     
-  /* sEE_I2C Peripheral Disable */
-  I2C_Cmd(sEE_I2C, DISABLE);
- 
-  /* sEE_I2C DeInit */
-  I2C_DeInit(sEE_I2C);
-
-  /*!< sEE_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);   
-  
-  /* Disable and Deinitialize the DMA channels */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;  
-   
-  /*!< sEE_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
-  
-  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
-  RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
-
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-  
-  /* Reset sEE_I2C peripheral */
-  RCC_APB1PeriphResetCmd(sEE_I2C_CLK, ENABLE);
-  
-  /* Release reset signal of sEE_I2C IP */
-  RCC_APB1PeriphResetCmd(sEE_I2C_CLK, DISABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */   
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
-  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Connect PXx to I2C_SCL*/
-  GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
-
-  /* Connect PXx to I2C_SDA*/
-  GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);  
-
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);  
-  
-  /*!< I2C DMA TX and RX channels configuration */
-  /* Enable the DMA clock */
-  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
-
-  /* I2C TX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
-  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  
-  /* I2C RX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
-  
-  /* Enable the DMA Channels Interrupts */
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
-}
-
-/**
-  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
-{ 
-  /* Initialize the DMA with the new parameters */
-  if (Direction == sEE_DIRECTION_TX)
-  {
-    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
-    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  }
-  else
-  { 
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
-    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
-  }
-}
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
deleted file mode 100644
index 27c1638..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
+++ /dev/null
@@ -1,810 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152_eval_i2c_ee.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage an I2C M24CXX 
-  *          EEPROM memory.
-  *          
-  *          ===================================================================      
-  *          Notes: 
-  *           - This driver is intended for STM32L1xx families devices only.
-  *           - There is no I2C EEPROM memory available in STM32L152-EVAL board,
-  *             to use this driver you have to build your own hardware.     
-  *          ===================================================================
-  *              
-  *          It implements a high level communication layer for read and write 
-  *          from/to this memory. The needed STM32 hardware resources (I2C and 
-  *          GPIO) are defined in stm32l152_eval.h file, and the initialization is 
-  *          performed in sEE_LowLevel_Init() function declared in stm32l152_eval.c 
-  *          file.
-  *          You can easily tailor this driver to any other development board, 
-  *          by just adapting the defines for hardware resources and 
-  *          sEE_LowLevel_Init() function. 
-  *        
-  *          @note In this driver, basic read and write functions (sEE_ReadBuffer() 
-  *                and sEE_WritePage()) use the DMA to perform the data transfer 
-  *                to/from EEPROM memory (except when number of requested data is
-  *                equal to 1). Thus, after calling these two functions, user 
-  *                application may perform other tasks while DMA is transferring
-  *                data. The application should then monitor the variable holding 
-  *                the number of data in order to determine when the transfer is
-  *                completed (variable decremented to 0). Stopping transfer tasks
-  *                are performed into DMA interrupt handlers (which are integrated
-  *                into this driver).
-  *            
-  *     +-----------------------------------------------------------------+
-  *     |                        Pin assignment                           |                 
-  *     +---------------------------------------+-----------+-------------+
-  *     |  STM32 I2C Pins                       |   sEE     |   Pin       |
-  *     +---------------------------------------+-----------+-------------+
-  *     | .                                     |   E0(GND) |    1  (0V)  |
-  *     | .                                     |   E1(GND) |    2  (0V)  |
-  *     | .                                     |   E2(GND) |    3  (0V)  |
-  *     | .                                     |   E0(VSS) |    4  (0V)  |
-  *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
-  *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
-  *     | .                                     |   /WC(VDD)|    7 (3.3V) |
-  *     | .                                     |   VDD     |    8 (3.3V) |
-  *     +---------------------------------------+-----------+-------------+  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l152_eval_i2c_ee.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32L152_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM32L152_EVAL_I2C_EE
-  * @brief      This file includes the I2C EEPROM driver of STM32L152-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Defines
-  * @{
-  */  
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Macros
-  * @{
-  */
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Variables
-  * @{
-  */
-__IO uint16_t  sEEAddress = 0;   
-__IO uint32_t  sEETimeout = sEE_LONG_TIMEOUT;   
-__IO uint16_t* sEEDataReadPointer;   
-__IO uint8_t*  sEEDataWritePointer;  
-__IO uint8_t   sEEDataNum;
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Function_Prototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_DeInit(void)
-{
-  sEE_LowLevel_DeInit(); 
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_Init(void)
-{ 
-  I2C_InitTypeDef  I2C_InitStructure;
-  
-  sEE_LowLevel_Init();
-  
-  /*!< I2C configuration */
-  /* sEE_I2C configuration */
-  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
-  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
-  I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7;
-  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
-  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-  I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
-  
-  /* sEE_I2C Peripheral Enable */
-  I2C_Cmd(sEE_I2C, ENABLE);
-  /* Apply sEE_I2C configuration after enabling it */
-  I2C_Init(sEE_I2C, &I2C_InitStructure);
-
-  /* Enable the sEE_I2C peripheral DMA requests */
-  I2C_DMACmd(sEE_I2C, ENABLE);
-  
-#if defined (sEE_M24C64_32)
-  /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */
-  sEEAddress = sEE_HW_ADDRESS;  
-#elif defined (sEE_M24C08)
-  /*!< depending on the sEE Address selected in the i2c_ee.h file */
- #ifdef sEE_Block0_ADDRESS
-  /*!< Select the sEE Block0 to write on */
-  sEEAddress = sEE_Block0_ADDRESS;
- #endif
-  
- #ifdef sEE_Block1_ADDRESS
-  /*!< Select the sEE Block1 to write on */
-  sEEAddress = sEE_Block1_ADDRESS;
- #endif
-
- #ifdef sEE_Block2_ADDRESS
-  /*!< Select the sEE Block2 to write on */
-  sEEAddress = sEE_Block2_ADDRESS;
- #endif
-  
- #ifdef sEE_Block3_ADDRESS
-  /*!< Select the sEE Block3 to write on */
-  sEEAddress = sEE_Block3_ADDRESS;
- #endif 
-#endif /*!< sEE_M24C64_32 */    
-}
-
-/**
-  * @brief  Reads a block of data from the EEPROM.
-  * @param  pBuffer : pointer to the buffer that receives the data read from 
-  *         the EEPROM.
-  * @param  ReadAddr : EEPROM's internal address to start reading from.
-  * @param  NumByteToRead : pointer to the variable holding number of bytes to 
-  *         be read from the EEPROM.
-  * 
-  *        @note The variable pointed by NumByteToRead is reset to 0 when all the 
-  *              data are read from the EEPROM. Application should monitor this 
-  *              variable in order know when the transfer is complete.
-  * 
-  * @note When number of data to be read is higher than 1, this function just 
-  *       configures the communication and enable the DMA channel to transfer data.
-  *       Meanwhile, the user application may perform other tasks.
-  *       When number of data to be read is 1, then the DMA is not used. The byte
-  *       is read in polling mode.
-  * 
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
-{  
-  /* Set the pointer to the Number of data to be read. This pointer will be used 
-      by the DMA Transfer Completer interrupt Handler in order to reset the 
-      variable to 0. User should check on this variable in order to know if the 
-      DMA transfer has been complete or not. */
-  sEEDataReadPointer = NumByteToRead;
-  
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send START condition */
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send EEPROM address for write */
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-
-  /*!< Test on EV6 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  } 
-
-#ifdef sEE_M24C08  
-  
-  /*!< Send the EEPROM's internal address to read from: Only one byte address */
-  I2C_SendData(sEE_I2C, ReadAddr);  
-
-#elif defined (sEE_M24C64_32)
-
-  /*!< Send the EEPROM's internal address to read from: MSB of the address first */
-  I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8));    
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-  /*!< Send the EEPROM's internal address to read from: LSB of the address */
-  I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF));    
-  
-#endif /*!< sEE_M24C08 */
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET)
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send STRAT condition a second time */  
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  } 
-  
-  /*!< Send EEPROM address for read */
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver);  
-  
-  /* If number of data to be read is 1, then DMA couldn't be used */
-  /* One Byte Master Reception procedure (POLLING) ---------------------------*/
-  if ((uint16_t)(*NumByteToRead) < 2)
-  {
-    /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }     
-    
-    /*!< Disable Acknowledgement */
-    I2C_AcknowledgeConfig(sEE_I2C, DISABLE);   
-    
-    /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
-    (void)sEE_I2C->SR2;
-    
-    /*!< Send STOP Condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);
-    
-    /* Wait for the byte to be received */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }
-    
-    /*!< Read the byte received from the EEPROM */
-    *pBuffer = I2C_ReceiveData(sEE_I2C);
-    
-    /*!< Decrement the read bytes counter */
-    (uint16_t)(*NumByteToRead)--;        
-    
-    /* Wait to make sure that STOP control bit has been cleared */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(sEE_I2C->CR1 & I2C_CR1_STOP)
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }  
-    
-    /*!< Re-Enable Acknowledgement to be ready for another reception */
-    I2C_AcknowledgeConfig(sEE_I2C, ENABLE);    
-  }
-  else/* More than one Byte Master Reception procedure (DMA) -----------------*/
-  {
-    /*!< Test on EV6 and clear it */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }  
-    
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX);
-    
-    /* Inform the DMA that the next End Of Transfer Signal will be the last one */
-    I2C_DMALastTransferCmd(sEE_I2C, ENABLE); 
-    
-    /* Enable the DMA Rx Channel */
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);    
-  }
-  
-  /* If all operations OK, return sEE_OK (0) */
-  return sEE_OK;
-}
-
-/**
-  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
-  *
-  * @note   The number of bytes (combined to write start address) must not 
-  *         cross the EEPROM page boundary. This function can only write into
-  *         the boundaries of an EEPROM page.
-  *         This function doesn't check on boundaries condition (in this driver 
-  *         the function sEE_WriteBuffer() which calls sEE_WritePage() is 
-  *         responsible of checking on Page boundaries).
-  * 
-  * @param  pBuffer : pointer to the buffer containing the data to be written to 
-  *         the EEPROM.
-  * @param  WriteAddr : EEPROM's internal address to write to.
-  * @param  NumByteToWrite : pointer to the variable holding number of bytes to 
-  *         be written into the EEPROM. 
-  * 
-  *        @note The variable pointed by NumByteToWrite is reset to 0 when all the 
-  *              data are written to the EEPROM. Application should monitor this 
-  *              variable in order know when the transfer is complete.
-  * 
-  * @note This function just configure the communication and enable the DMA 
-  *       channel to transfer data. Meanwhile, the user application may perform 
-  *       other tasks in parallel.
-  * 
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
-{ 
-  /* Set the pointer to the Number of data to be written. This pointer will be used 
-      by the DMA Transfer Completer interrupt Handler in order to reset the 
-      variable to 0. User should check on this variable in order to know if the 
-      DMA transfer has been complete or not. */
-  sEEDataWritePointer = NumByteToWrite;  
-  
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send START condition */
-  I2C_GenerateSTART(sEE_I2C, ENABLE);
-  
-  /*!< Test on EV5 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-  
-  /*!< Send EEPROM address for write */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-
-  /*!< Test on EV6 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-#ifdef sEE_M24C08
-  
-  /*!< Send the EEPROM's internal address to write to : only one byte Address */
-  I2C_SendData(sEE_I2C, WriteAddr);
-  
-#elif defined(sEE_M24C64_32)
-  
-  /*!< Send the EEPROM's internal address to write to : MSB of the address first */
-  I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8));
-
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT;  
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }  
-  
-  /*!< Send the EEPROM's internal address to write to : LSB of the address */
-  I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF));
-  
-#endif /*!< sEE_M24C08 */  
-  
-  /*!< Test on EV8 and clear it */
-  sEETimeout = sEE_FLAG_TIMEOUT; 
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }  
-  
-  /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-  sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX);
-  
-  /* Enable the DMA Tx Channel */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE);
-  
-  /* If all operations OK, return sEE_OK (0) */
-  return sEE_OK;
-}
-
-/**
-  * @brief  Writes buffer of data to the I2C EEPROM.
-  * @param  pBuffer : pointer to the buffer  containing the data to be written 
-  *         to the EEPROM.
-  * @param  WriteAddr : EEPROM's internal address to write to.
-  * @param  NumByteToWrite : number of bytes to write to the EEPROM.
-  * @retval None
-  */
-void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
-{
-  uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0;
-  uint16_t Addr = 0;
-
-  Addr = WriteAddr % sEE_PAGESIZE;
-  count = sEE_PAGESIZE - Addr;
-  NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
-  NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
- 
-  /*!< If WriteAddr is sEE_PAGESIZE aligned  */
-  if(Addr == 0) 
-  {
-    /*!< If NumByteToWrite < sEE_PAGESIZE */
-    if(NumOfPage == 0) 
-    {
-      /* Store the number of data to be written */
-      sEEDataNum = NumOfSingle;
-      /* Start writing data */
-      sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-      /* Wait transfer through DMA to be complete */
-      sEETimeout = sEE_LONG_TIMEOUT;
-      while (sEEDataNum > 0)
-      {
-        if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-      }
-      sEE_WaitEepromStandbyState();
-    }
-    /*!< If NumByteToWrite > sEE_PAGESIZE */
-    else  
-    {
-      while(NumOfPage--)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = sEE_PAGESIZE;        
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }      
-        sEE_WaitEepromStandbyState();
-        WriteAddr +=  sEE_PAGESIZE;
-        pBuffer += sEE_PAGESIZE;
-      }
-
-      if(NumOfSingle!=0)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;          
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }    
-        sEE_WaitEepromStandbyState();
-      }
-    }
-  }
-  /*!< If WriteAddr is not sEE_PAGESIZE aligned  */
-  else 
-  {
-    /*!< If NumByteToWrite < sEE_PAGESIZE */
-    if(NumOfPage== 0) 
-    {
-      /*!< If the number of data to be written is more than the remaining space 
-      in the current page: */
-      if (NumByteToWrite > count)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = count;        
-        /*!< Write the data conained in same page */
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }          
-        sEE_WaitEepromStandbyState();      
-        
-        /* Store the number of data to be written */
-        sEEDataNum = (NumByteToWrite - count);          
-        /*!< Write the remaining data in the following page */
-        sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }     
-        sEE_WaitEepromStandbyState();        
-      }      
-      else      
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;         
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }          
-        sEE_WaitEepromStandbyState();        
-      }     
-    }
-    /*!< If NumByteToWrite > sEE_PAGESIZE */
-    else
-    {
-      NumByteToWrite -= count;
-      NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
-      NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
-      
-      if(count != 0)
-      {  
-        /* Store the number of data to be written */
-        sEEDataNum = count;         
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }     
-        sEE_WaitEepromStandbyState();
-        WriteAddr += count;
-        pBuffer += count;
-      } 
-      
-      while(NumOfPage--)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = sEE_PAGESIZE;          
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }        
-        sEE_WaitEepromStandbyState();
-        WriteAddr +=  sEE_PAGESIZE;
-        pBuffer += sEE_PAGESIZE;  
-      }
-      if(NumOfSingle != 0)
-      {
-        /* Store the number of data to be written */
-        sEEDataNum = NumOfSingle;           
-        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
-        /* Wait transfer through DMA to be complete */
-        sEETimeout = sEE_LONG_TIMEOUT;
-        while (sEEDataNum > 0)
-        {
-          if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
-        }         
-        sEE_WaitEepromStandbyState();
-      }
-    }
-  }  
-}
-
-/**
-  * @brief  Wait for EEPROM Standby state.
-  * 
-  * @note  This function allows to wait and check that EEPROM has finished the 
-  *        last operation. It is mostly used after Write operation: after receiving
-  *        the buffer to be written, the EEPROM may need additional time to actually
-  *        perform the write operation. During this time, it doesn't answer to
-  *        I2C packets addressed to it. Once the write operation is complete
-  *        the EEPROM responds to its address.
-  * 
-  * @param  None
-  * @retval sEE_OK (0) if operation is correctly performed, else return value 
-  *         different from sEE_OK (0) or the timeout user callback.
-  */
-uint32_t sEE_WaitEepromStandbyState(void)      
-{
-  __IO uint16_t tmpSR1 = 0;
-  __IO uint32_t sEETrials = 0;
-
-  /*!< While the bus is busy */
-  sEETimeout = sEE_LONG_TIMEOUT;
-  while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
-  {
-    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-  }
-
-  /* Keep looping till the slave acknowledge his address or maximum number 
-     of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
-     in stm32_eval_i2c_ee.h file) */
-  while (1)
-  {
-    /*!< Send START condition */
-    I2C_GenerateSTART(sEE_I2C, ENABLE);
-
-    /*!< Test on EV5 and clear it */
-    sEETimeout = sEE_FLAG_TIMEOUT;
-    while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
-    {
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }    
-
-    /*!< Send EEPROM address for write */
-    I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
-    
-    /* Wait for ADDR flag to be set (Slave acknowledged his address) */
-    sEETimeout = sEE_LONG_TIMEOUT;
-    do
-    {     
-      /* Get the current value of the SR1 register */
-      tmpSR1 = sEE_I2C->SR1;
-      
-      /* Update the timeout value and exit if it reach 0 */
-      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
-    }
-    /* Keep looping till the Address is acknowledged or the AF flag is 
-       set (address not acknowledged at time) */
-    while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0);
-     
-    /* Check if the ADDR flag has been set */
-    if (tmpSR1 & I2C_SR1_ADDR)
-    {
-      /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already 
-         been read) */
-      (void)sEE_I2C->SR2;
-      
-      /*!< STOP condition */    
-      I2C_GenerateSTOP(sEE_I2C, ENABLE);
-        
-      /* Exit the function */
-      return sEE_OK;
-    }
-    else
-    {
-      /*!< Clear AF flag */
-      I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF);                  
-    }
-    
-    /* Check if the maximum allowed numbe of trials has bee reached */
-    if (sEETrials++ == sEE_MAX_TRIALS_NUMBER)
-    {
-      /* If the maximum number of trials has been reached, exit the function */
-      return sEE_TIMEOUT_UserCallback();
-    }
-  }
-}
-
-/**
-  * @brief  This function handles the DMA Tx Channel interrupt Handler.
-  * @param  None
-  * @retval None
-  */
-void sEE_I2C_DMA_TX_IRQHandler(void)
-{
-  /* Check if the DMA transfer is complete */
-  if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET)
-  {  
-    /* Disable the DMA Tx Channel and Clear all its Flags */  
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-    DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL);
-
-    /*!< Wait till all data have been physically transferred on the bus */
-    sEETimeout = sEE_LONG_TIMEOUT;
-    while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF))
-    {
-      if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback();
-    }
-    
-    /*!< Send STOP condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);
-    
-    /* Reset the variable holding the number of data to be written */
-    *sEEDataWritePointer = 0;  
-  }
-}
-
-/**
-  * @brief  This function handles the DMA Rx Channel interrupt Handler.
-  * @param  None
-  * @retval None
-  */
-void sEE_I2C_DMA_RX_IRQHandler(void)
-{
-  /* Check if the DMA transfer is complete */
-  if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET)
-  {      
-    /*!< Send STOP Condition */
-    I2C_GenerateSTOP(sEE_I2C, ENABLE);    
-    
-    /* Disable the DMA Rx Channel and Clear all its Flags */  
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-    DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL);
-    
-    /* Reset the variable holding the number of data to be read */
-    *sEEDataReadPointer = 0;
-  }
-}
-
-#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
-  * @brief  Basic management of the timeout situation.
-  * @param  None.
-  * @retval None.
-  */
-uint32_t sEE_TIMEOUT_UserCallback(void)
-{
-  /* Block communication and all processes */
-  while (1)
-  {   
-  }
-}
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
deleted file mode 100644
index f0ad428..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152_eval_i2c_ee.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32l152_eval_i2c_ee
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L152_EVAL_I2C_EE_H
-#define __STM32L152_EVAL_I2C_EE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32L152_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM32L152_EVAL_I2C_EE
-  * @{
-  */  
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Types
-  * @{
-  */ 
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Constants
-  * @{
-  */
-
-/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() 
-   function implemented in stm32_evel_i2c_ee.c file.
-   sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
-   occure during communication (waiting on an event that doesn't occur, bus 
-   errors, busy devices ...). */   
-/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
-   
-#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32)
-/* Use the defines below the choose the EEPROM type */
-/* #define sEE_M24C08*/  /* Support the device: M24C08. */
-/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and 
-   HW address are correctly defined*/
-#define sEE_M24C64_32  /* Support the devices: M24C32 and M24C64 */
-#endif
-
-#ifdef sEE_M24C64_32
-/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device 
-  address selection (ne need for additional address lines). According to the 
-  Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */
-
- #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */ 
-
-#elif defined (sEE_M24C08)
-/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 
-   EEPROM Addresses defines */
- #define sEE_Block0_ADDRESS     0xA0   /* E2 = 0 */ 
- /*#define sEE_Block1_ADDRESS     0xA2*/ /* E2 = 0 */  
- /*#define sEE_Block2_ADDRESS     0xA4*/ /* E2 = 0 */
- /*#define sEE_Block3_ADDRESS     0xA6*/ /* E2 = 0 */
-
-#endif /* sEE_M24C64_32 */
-
-#define I2C_SPEED               200000
-#define I2C_SLAVE_ADDRESS7      0xA0
-
-#if defined (sEE_M24C08)
- #define sEE_PAGESIZE           16
-#elif defined (sEE_M24C64_32)
- #define sEE_PAGESIZE           32
-#endif
-   
-/* Maximum Timeout values for flags and events waiting loops. These timeouts are
-   not based on accurate values, they just guarantee that the application will 
-   not remain stuck if the I2C communication is corrupted.
-   You may modify these timeout values depending on CPU frequency and application
-   conditions (interrupts routines ...). */   
-#define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
-#define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
-
-/* Maximum number of trials for sEE_WaitEepromStandbyState() function */
-#define sEE_MAX_TRIALS_NUMBER     300
-   
-/* Defintions for the state of the DMA transfer */   
-#define sEE_STATE_READY           0
-#define sEE_STATE_BUSY            1
-#define sEE_STATE_ERROR           2
-   
-#define sEE_OK                    0
-#define sEE_FAIL                  1   
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Macros
-  * @{
-  */    
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Functions
-  * @{
-  */ 
-void     sEE_DeInit(void);
-void     sEE_Init(void);
-uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
-uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
-void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
-uint32_t sEE_WaitEepromStandbyState(void);
-
-/* USER Callbacks: These are functions for which prototypes only are declared in
-   EEPROM driver and that should be implemented into user applicaiton. */  
-/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
-   occure during communication (waiting on an event that doesn't occur, bus 
-   errors, busy devices ...).
-   You can use the default timeout callback implementation by uncommenting the 
-   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file.
-   Typically the user implementation of this callback should reset I2C peripheral
-   and re-initialize communication or in worst case reset all the application. */
-uint32_t sEE_TIMEOUT_UserCallback(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L152_EVAL_I2C_EE_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
deleted file mode 100644
index 8170595..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
+++ /dev/null
@@ -1,1529 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152_eval_lcd.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
-  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module 
-  *          of STM32L152-EVAL board RevB.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l152_eval_lcd.h"
-#include "../Common/fonts.c"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32L152_EVAL
-  * @{
-  */
-    
-/** @defgroup STM32L152_EVAL_LCD 
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), 
-  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module 
-  *          of STM32L152-EVAL board.
-  * @{
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Defines
-  * @{
-  */ 
-#define LCD_ILI9320        0x9320
-#define LCD_SPFD5408       0x5408
-#define START_BYTE         0x70
-#define SET_INDEX          0x00
-#define READ_STATUS        0x01
-#define LCD_WRITE_REG      0x02
-#define LCD_READ_REG       0x03
-#define MAX_POLY_CORNERS   200
-#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Macros
-  * @{
-  */ 
-#define ABS(X)  ((X) > 0 ? (X) : -(X))  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Variables
-  * @{
-  */ 
-static sFONT *LCD_Currentfonts;
-/* Global variables to set the written text color */
-static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-static __IO uint32_t LCDType = LCD_SPFD5408;
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
-  * @{
-  */ 
-#ifndef USE_Delay
-static void delay(__IO uint32_t nCount);
-#endif /* USE_Delay*/
-
-static void PutPixel(int16_t x, int16_t y);
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  DeInitializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM32L152_LCD_DeInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /*!< LCD Display Off */
-  LCD_DisplayOff();
-
-  /*!< LCD_SPI disable */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  
-  /*!< LCD_SPI DeInit */
-  SPI_DeInit(LCD_SPI);
-   
-  /*!< Disable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-    
-  /* Configure NCS in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-   
-  /* Configure SPI pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Setups the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_Setup(void)
-{ 
-/* Configure the LCD Control pins --------------------------------------------*/
-  LCD_CtrlLinesConfig();
-  
-/* Configure the LCD_SPI interface ----------------------------------------------*/
-  LCD_SPIConfig(); 
-    
-  if(LCDType == LCD_SPFD5408)
-  {   
-    /* Start Initial Sequence --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
-    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
-    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
-    /* Power On sequence -------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */  
-    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    _delay_(5);                  /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
-    _delay_(5);                 /* Delay 50 ms */ 
-    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
-    _delay_(5);                 /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve --------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0007);
-    LCD_WriteReg(LCD_REG_49, 0x0302);
-    LCD_WriteReg(LCD_REG_50, 0x0105);
-    LCD_WriteReg(LCD_REG_53, 0x0206);
-    LCD_WriteReg(LCD_REG_54, 0x0808);
-    LCD_WriteReg(LCD_REG_55, 0x0206);
-    LCD_WriteReg(LCD_REG_56, 0x0504);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0105);
-    LCD_WriteReg(LCD_REG_61, 0x0808);
-    /* Set GRAM area -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
-    /* Partial Display Control -------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control -----------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1
-       I/D=01 (Horizontal : increment, Vertical : decrement)
-       AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
-  } 
-  else if(LCDType == LCD_ILI9320)
-  {
-    _delay_(5); /* Delay 50 ms */
-    /* Start Initial Sequence ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
-    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-    /* Power On sequence -----------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
-    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-    _delay_(5);                       /* Delay 50 ms */
-    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-    /* Adjust the Gamma Curve ------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_48, 0x0006);
-    LCD_WriteReg(LCD_REG_49, 0x0101);
-    LCD_WriteReg(LCD_REG_50, 0x0003);
-    LCD_WriteReg(LCD_REG_53, 0x0106);
-    LCD_WriteReg(LCD_REG_54, 0x0b02);
-    LCD_WriteReg(LCD_REG_55, 0x0302);
-    LCD_WriteReg(LCD_REG_56, 0x0707);
-    LCD_WriteReg(LCD_REG_57, 0x0007);
-    LCD_WriteReg(LCD_REG_60, 0x0600);
-    LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-    /* Set GRAM area ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-    /* Partial Display Control -----------------------------------------------*/
-    LCD_WriteReg(LCD_REG_128, 0x0000);
-    LCD_WriteReg(LCD_REG_129, 0x0000);
-    LCD_WriteReg(LCD_REG_130, 0x0000);
-    LCD_WriteReg(LCD_REG_131, 0x0000);
-    LCD_WriteReg(LCD_REG_132, 0x0000);
-    LCD_WriteReg(LCD_REG_133, 0x0000);
-    /* Panel Control ---------------------------------------------------------*/
-    LCD_WriteReg(LCD_REG_144, 0x0010);
-    LCD_WriteReg(LCD_REG_146, 0x0000);
-    LCD_WriteReg(LCD_REG_147, 0x0003);
-    LCD_WriteReg(LCD_REG_149, 0x0110);
-    LCD_WriteReg(LCD_REG_151, 0x0000);
-    LCD_WriteReg(LCD_REG_152, 0x0000);
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  }
-}
-
-
-/**
-  * @brief  Initializes the LCD.
-  * @param  None
-  * @retval None
-  */
-void STM32L152_LCD_Init(void)
-{ 
-  /* Setups the LCD */
-  LCD_Setup();
-
-  /* Try to read new LCD controller ID 0x5408 */
-  if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408)
-  {
-    LCDType = LCD_SPFD5408;
-  }
-  else
-  {
-    LCDType = LCD_ILI9320;
-    /* Setups the LCD */
-    LCD_Setup();
-  } 
-    
-  LCD_SetFont(&LCD_DEFAULT_FONT);
-}
-
-/**
-  * @brief  Sets the LCD Text and Background colors.
-  * @param  _TextColor: specifies the Text Color.
-  * @param  _BackColor: specifies the Background Color.
-  * @retval None
-  */
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
-{
-  TextColor = _TextColor; 
-  BackColor = _BackColor;
-}
-
-/**
-  * @brief  Gets the LCD Text and Background colors.
-  * @param  _TextColor: pointer to the variable that will contain the Text 
-            Color.
-  * @param  _BackColor: pointer to the variable that will contain the Background 
-            Color.
-  * @retval None
-  */
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
-{
-  *_TextColor = TextColor; *_BackColor = BackColor;
-}
-
-/**
-  * @brief  Sets the Text color.
-  * @param  Color: specifies the Text color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetTextColor(__IO uint16_t Color)
-{
-  TextColor = Color;
-}
-
-
-/**
-  * @brief  Sets the Background color.
-  * @param  Color: specifies the Background color code RGB(5-6-5).
-  * @retval None
-  */
-void LCD_SetBackColor(__IO uint16_t Color)
-{
-  BackColor = Color;
-}
-
-/**
-  * @brief  Sets the Text Font.
-  * @param  fonts: specifies the font to be used.
-  * @retval None
-  */
-void LCD_SetFont(sFONT *fonts)
-{
-  LCD_Currentfonts = fonts;
-}
-
-/**
-  * @brief  Gets the Text Font.
-  * @param  None.
-  * @retval the used font.
-  */
-sFONT *LCD_GetFont(void)
-{
-  return LCD_Currentfonts;
-}
-
-/**
-  * @brief  Clears the selected line.
-  * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
-  * @retval None
-  */
-void LCD_ClearLine(uint8_t Line)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-  }
-}
-
-
-/**
-  * @brief  Clears the hole LCD.
-  * @param  Color: the color of the background.
-  * @retval None
-  */
-void LCD_Clear(uint16_t Color)
-{
-  uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
-
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  
-  for(index = 0; index < 76800; index++)
-  {
-    LCD_WriteRAM(Color);
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
- 
-}
-
-
-/**
-  * @brief  Sets the cursor position.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
-  * @retval None
-  */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
-{
-  LCD_WriteReg(LCD_REG_32, Xpos);
-  LCD_WriteReg(LCD_REG_33, Ypos);
-}
-
-
-/**
-  * @brief  Draws a character on LCD.
-  * @param  Xpos: the Line where to display the character shape.
-  * @param  Ypos: start column address.
-  * @param  c: pointer to the character data.
-  * @retval None
-  */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
-{
-  uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
-   
-  Xaddress = Xpos;
-  
-  LCD_SetCursor(Xaddress, Ypos);
-  
-  for(index = 0; index < LCD_Currentfonts->Height; index++)
-  {
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
-    for(i = 0; i < LCD_Currentfonts->Width; i++)
-    {
-      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
-        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
-
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-    Xaddress++;
-    LCD_SetCursor(Xaddress, Ypos);
-  }
-}
-
-
-/**
-  * @brief  Displays one character (16dots width, 24dots height).
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  Column: start column address.
-  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
-  * @retval None
-  */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
-{
-  Ascii -= 32;
-  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
-}
-
-
-/**
-  * @brief  Displays a maximum of 20 char on the LCD.
-  * @param  Line: the Line where to display the character shape .
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..9
-  * @param  *ptr: pointer to string to display on LCD.
-  * @retval None
-  */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
-{
-  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
-  {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
-  }
-}
-
-
-/**
-  * @brief  Sets a display window
-  * @param  Xpos: specifies the X buttom left position.
-  * @param  Ypos: specifies the Y buttom left position.
-  * @param  Height: display window height.
-  * @param  Width: display window width.
-  * @retval None
-  */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  /* Horizontal GRAM Start Address */
-  if(Xpos >= Height)
-  {
-    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-  }
-  else
-  {
-    LCD_WriteReg(LCD_REG_80, 0);
-  }
-  /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_81, Xpos);
-  /* Vertical GRAM Start Address */
-  if(Ypos >= Width)
-  {
-    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-  }  
-  else
-  {
-    LCD_WriteReg(LCD_REG_82, 0);
-  }
-  /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_83, Ypos);
-
-  LCD_SetCursor(Xpos, Ypos);
-}
-
-
-/**
-  * @brief  Disables LCD Window mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_WindowModeDisable(void)
-{
-  LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-  LCD_WriteReg(LCD_REG_3, 0x1018);    
-}
-
-/**
-  * @brief  Displays a line.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Length: line length.
-  * @param  Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
-  * @retval None
-  */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
-{
-  uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
-  
-  if(Direction == LCD_DIR_HORIZONTAL)
-  { 
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-    
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAM(TextColor);
-    }
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-  else
-  {
-    for(i = 0; i < Length; i++)
-    {
-      LCD_WriteRAMWord(TextColor);
-      Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
-    }
-  }
-}
-
-
-/**
-  * @brief  Displays a rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: display rectangle height.
-  * @param  Width: display rectangle width.
-  * @retval None
-  */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-}
-
-
-/**
-  * @brief  Displays a circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;/* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-  CurX = 0;
-  CurY = Radius;
-  
-  while (CurX <= CurY)
-  {
-    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
-    LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY); 
-    LCD_WriteRAMWord(TextColor);
-    
-    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
-    LCD_WriteRAMWord(TextColor);
-
-    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
-    LCD_WriteRAMWord(TextColor);
- 
-    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
-    LCD_WriteRAMWord(TextColor);
-
-    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
-    LCD_WriteRAMWord(TextColor);
-
-    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
-    LCD_WriteRAMWord(TextColor);
-
-    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
-    LCD_WriteRAMWord(TextColor);
-
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-}
-
-
-/**
-  * @brief  Displays a monocolor picture.
-  * @param  Pict: pointer to the picture array.
-  * @retval None
-  */
-void LCD_DrawMonoPict(const uint32_t *Pict)
-{
-  uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
-
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-
-  for(index = 0; index < 2400; index++)
-  {
-    for(i = 0; i < 32; i++)
-    {
-      if((Pict[index] & (1 << i)) == 0x00)
-      {
-        LCD_WriteRAM(BackColor);
-      }
-      else
-      {
-        LCD_WriteRAM(TextColor);
-      }
-    }
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-#ifdef USE_LCD_DrawBMP 
-/**
-  * @brief  Displays a bitmap picture loaded in the SPI Flash.
-  * @param  BmpAddress: Bmp picture address in the SPI Flash.
-  * @retval None
-  */
-void LCD_DrawBMP(uint32_t BmpAddress)
-{
-  uint32_t i = 0, size = 0;
-  /* Read bitmap size */
-  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
-  /* get bitmap data address offset */
-  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
-  
-  size = (size - i)/2;
-  sFLASH_StartReadSequence(BmpAddress + i);
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 16-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-  
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-    /* AM=1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1008);
-    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-  }
-  
-  /* Read bitmap data from SPI Flash and send them to LCD */
-  for(i = 0; i < size; i++)
-  {
-    LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
-  }
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  }
-
-  /* Deselect the FLASH: Chip Select high */
-  sFLASH_CS_HIGH();
-  /* Disable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, DISABLE);
-  /* SPI in 8-bit mode */
-  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
-  /* Enable LCD_SPI  */
-  SPI_Cmd(LCD_SPI, ENABLE);
-
-  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
-  {
-    /* Set GRAM write direction and BGR = 1 */
-    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-    /* AM = 1 (address is updated in vertical writing direction) */
-    LCD_WriteReg(LCD_REG_3, 0x1018);
-  }
-}
-#endif /* USE_LCD_DrawBMP */
- 
-/**
-  * @brief  Displays a full rectangle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Height: rectangle height.
-  * @param  Width: rectangle width.
-  * @retval None
-  */
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
-{
-  LCD_SetTextColor(TextColor);
-
-  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
-  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
-  
-  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
-  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
-
-  Width -= 2;
-  Height--;
-  Ypos--;
-
-  LCD_SetTextColor(BackColor);
-
-  while(Height--)
-  {
-    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
-  }
-
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Displays a full circle.
-  * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position.
-  * @param  Radius
-  * @retval None
-  */
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
-{
-  int32_t  D;    /* Decision Variable */ 
-  uint32_t  CurX;/* Current X Value */
-  uint32_t  CurY;/* Current Y Value */ 
-  
-  D = 3 - (Radius << 1);
-
-  CurX = 0;
-  CurY = Radius;
-  
-  LCD_SetTextColor(BackColor);
-
-  while (CurX <= CurY)
-  {
-    if(CurY > 0) 
-    {
-      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
-    }
-
-    if(CurX > 0) 
-    {
-      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
-    }
-    if (D < 0)
-    { 
-      D += (CurX << 2) + 6;
-    }
-    else
-    {
-      D += ((CurX - CurY) << 2) + 10;
-      CurY--;
-    }
-    CurX++;
-  }
-
-  LCD_SetTextColor(TextColor);
-  LCD_DrawCircle(Xpos, Ypos, Radius);
-}
-
-/**
-  * @brief  Displays an uni line (between two points).
-  * @param  x1: specifies the point 1 x position.
-  * @param  y1: specifies the point 1 y position.
-  * @param  x2: specifies the point 2 x position.
-  * @param  y2: specifies the point 2 y position.
-  * @retval None
-  */
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
-{
-  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
-  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
-  curpixel = 0;
-  
-  deltax = ABS(x2 - x1);        /* The difference between the x's */
-  deltay = ABS(y2 - y1);        /* The difference between the y's */
-  x = x1;                       /* Start x off at the first pixel */
-  y = y1;                       /* Start y off at the first pixel */
-  
-  if (x2 >= x1)                 /* The x-values are increasing */
-  {
-    xinc1 = 1;
-    xinc2 = 1;
-  }
-  else                          /* The x-values are decreasing */
-  {
-    xinc1 = -1;
-    xinc2 = -1;
-  }
-  
-  if (y2 >= y1)                 /* The y-values are increasing */
-  {
-    yinc1 = 1;
-    yinc2 = 1;
-  }
-  else                          /* The y-values are decreasing */
-  {
-    yinc1 = -1;
-    yinc2 = -1;
-  }
-  
-  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
-  {
-    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
-    yinc2 = 0;                  /* Don't change the y for every iteration */
-    den = deltax;
-    num = deltax / 2;
-    numadd = deltay;
-    numpixels = deltax;         /* There are more x-values than y-values */
-  }
-  else                          /* There is at least one y-value for every x-value */
-  {
-    xinc2 = 0;                  /* Don't change the x for every iteration */
-    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
-    den = deltay;
-    num = deltay / 2;
-    numadd = deltax;
-    numpixels = deltay;         /* There are more y-values than x-values */
-  }
-  
-  for (curpixel = 0; curpixel <= numpixels; curpixel++)
-  {
-    PutPixel(x, y);             /* Draw the current pixel */
-    num += numadd;              /* Increase the numerator by the top of the fraction */
-    if (num >= den)             /* Check if numerator >= denominator */
-    {
-      num -= den;               /* Calculate the new numerator value */
-      x += xinc1;               /* Change the x as appropriate */
-      y += yinc1;               /* Change the y as appropriate */
-    }
-    x += xinc2;                 /* Change the x as appropriate */
-    y += yinc2;                 /* Change the y as appropriate */
-  }
-}
-
-/**
-  * @brief  Displays an polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLine(pPoint Points, uint16_t PointCount)
-{
-  int16_t X = 0, Y = 0;
-
-  if(PointCount < 2)
-  {
-    return;
-  }
-
-  while(--PointCount)
-  {
-    X = Points->X;
-    Y = Points->Y;
-    Points++;
-    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
-  }
-}
-
-/**
-  * @brief  Displays an relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @param  Closed: specifies if the draw is closed or not.
-  *           1: closed, 0 : not closed.
-  * @retval None
-  */
-static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
-{
-  int16_t X = 0, Y = 0;
-  pPoint First = Points;
-
-  if(PointCount < 2)
-  {
-    return;
-  }  
-  X = Points->X;
-  Y = Points->Y;
-  while(--PointCount)
-  {
-    Points++;
-    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
-    X = X + Points->X;
-    Y = Y + Points->Y;
-  }
-  if(Closed)
-  {
-    LCD_DrawUniLine(First->X, First->Y, X, Y);
-  }  
-}
-
-/**
-  * @brief  Displays a closed polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLine(Points, PointCount);
-  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
-}
-
-/**
-  * @brief  Displays a relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
-}
-
-/**
-  * @brief  Displays a closed relative polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
-{
-  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
-}
-
-
-/**
-  * @brief  Displays a  full polyline (between many points).
-  * @param  Points: pointer to the points array.
-  * @param  PointCount: Number of points.
-  * @retval None
-  */
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
-{
-  /*  public-domain code by Darel Rex Finley, 2007 */
-  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
-  j = 0, swap = 0;
-  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
-
-  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
-  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
-
-  for(i = 1; i < PointCount; i++)
-  {
-    pixelX = POLY_X(i);
-    if(pixelX < IMAGE_LEFT)
-    {
-      IMAGE_LEFT = pixelX;
-    }
-    if(pixelX > IMAGE_RIGHT)
-    {
-      IMAGE_RIGHT = pixelX;
-    }
-    
-    pixelY = POLY_Y(i);
-    if(pixelY < IMAGE_TOP)
-    { 
-      IMAGE_TOP = pixelY;
-    }
-    if(pixelY > IMAGE_BOTTOM)
-    {
-      IMAGE_BOTTOM = pixelY;
-    }
-  }
-  
-  LCD_SetTextColor(BackColor);  
-
-  /*  Loop through the rows of the image. */
-  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
-  {  
-    /* Build a list of nodes. */
-    nodes = 0; j = PointCount-1;
-
-    for (i = 0; i < PointCount; i++) 
-    {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
-      {
-        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
-      }
-      j = i; 
-    }
-  
-    /* Sort the nodes, via a simple "Bubble" sort. */
-    i = 0;
-    while (i < nodes-1) 
-    {
-      if (nodeX[i]>nodeX[i+1]) 
-      {
-        swap = nodeX[i]; 
-        nodeX[i] = nodeX[i+1]; 
-        nodeX[i+1] = swap; 
-        if(i)
-        {
-          i--; 
-        }
-      }
-      else 
-      {
-        i++;
-      }
-    }
-  
-    /*  Fill the pixels between node pairs. */
-    for (i = 0; i < nodes; i+=2) 
-    {
-      if(nodeX[i] >= IMAGE_RIGHT) 
-      {
-        break;
-      }
-      if(nodeX[i+1] > IMAGE_LEFT) 
-      {
-        if (nodeX[i] < IMAGE_LEFT)
-        {
-          nodeX[i]=IMAGE_LEFT;
-        }
-        if(nodeX[i+1] > IMAGE_RIGHT)
-        {
-          nodeX[i+1] = IMAGE_RIGHT;
-        }
-        LCD_SetTextColor(BackColor);
-        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
-        LCD_SetTextColor(TextColor);
-        PutPixel(pixelY, nodeX[i+1]);
-        PutPixel(pixelY, nodeX[i]);
-        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
-      }
-    }
-  } 
-
-  /* draw the edges */
-  LCD_SetTextColor(TextColor);
-}
-
-/**
-  * @brief  Reset LCD control line(/CS) and Send Start-Byte
-  * @param  Start_Byte: the Start-Byte to be sent
-  * @retval None
-  */
-void LCD_nCS_StartByte(uint8_t Start_Byte)
-{
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-
-  SPI_SendData(LCD_SPI, Start_Byte);
-
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Writes index to select the LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval None
-  */
-void LCD_WriteRegIndex(uint8_t LCD_Reg)
-{
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | SET_INDEX);
-
-  /* Write 16-bit Reg Index (High Byte is 0) */
-  SPI_SendData(LCD_SPI, 0x00);
-
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_SendData(LCD_SPI, LCD_Reg);
-
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Writes to the selected LCD ILI9320 register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index (then Write Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-
-  /* Write 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-
-  SPI_SendData(LCD_SPI, LCD_RegValue >> 8);
-
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Reads the selected LCD Register.
-  * @param  LCD_Reg: address of the selected register.
-  * @retval LCD Register Value.
-  */
-uint16_t LCD_ReadReg(uint8_t LCD_Reg)
-{
-  uint16_t tmp = 0;
-  uint8_t i = 0;
-  
-  /* LCD_SPI prescaler: 4 */
-  LCD_SPI->CR1 &= 0xFFC7;
-  LCD_SPI->CR1 |= 0x0008;
-  /* Write 16-bit Index (then Read Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Read 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
-  
-  for(i = 0; i < 5; i++)
-  {
-    SPI_SendData(LCD_SPI, 0xFF);
-    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-    {
-    }
-    /* One byte of invalid dummy data read after the start byte */
-    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
-    {    
-    }
-    SPI_ReceiveData(LCD_SPI); 
-  }
-
-  SPI_SendData(LCD_SPI, 0xFF);
-
-  /* Read upper byte */
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
-  {
-  }
-  tmp = SPI_ReceiveData(LCD_SPI);
-  
-  
-  SPI_SendData(LCD_SPI, 0xFF);
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-
-  /* Read lower byte */
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
-  {
-  }
-
-  tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-
-  /* LCD_SPI prescaler: 2 */
-  LCD_SPI->CR1 &= 0xFFC7;
-
-  return tmp;
-}
-
-
-/**
-  * @brief  Prepare to write to the LCD RAM.
-  * @param  None
-  * @retval None
-  */
-void LCD_WriteRAM_Prepare(void)
-{
-  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
-
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-}
-
-
-/**
-  * @brief  Writes 1 word to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAMWord(uint16_t RGB_Code)
-{
-  LCD_WriteRAM_Prepare();
-
-  LCD_WriteRAM(RGB_Code);
-
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-/**
-  * @brief  Writes to the LCD RAM.
-  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
-  * @retval None
-  */
-void LCD_WriteRAM(uint16_t RGB_Code)
-{
-  SPI_SendData(LCD_SPI, RGB_Code >> 8);
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-  SPI_SendData(LCD_SPI, RGB_Code & 0xFF);
-  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Power on the LCD.
-  * @param  None
-  * @retval None
-  */
-void LCD_PowerOn(void)
-{
-  /* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                /* delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                /* delay 50 ms */
-  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Enables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOn(void)
-{
-  /* Display On */
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-}
-
-
-/**
-  * @brief  Disables the Display.
-  * @param  None
-  * @retval None
-  */
-void LCD_DisplayOff(void)
-{
-  /* Display Off */
-  LCD_WriteReg(LCD_REG_7, 0x0);
-}
-
-
-/**
-  * @brief  Configures LCD control lines in Output Push-Pull mode.
-  * @param  None
-  * @retval None
-  */
-void LCD_CtrlLinesConfig(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
-  
-  /* Configure NCS (PF.02) in Output Push-Pull mode */
-  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-    
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
-
-
-/**
-  * @brief  Sets or reset LCD control lines.
-  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
-  * @param  CtrlPins: the Control line.
-  *   This parameter can be:
-  *     @arg LCD_NCS_PIN: Chip Select pin
-  *     @arg LCD_NWR_PIN: Read/Write Selection pin
-  *     @arg LCD_RS_PIN: Register/RAM Selection pin
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @retval None
-  */
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
-{
-  /* Set or Reset the control line */
-  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
-}
-
-
-/**
-  * @brief  Configures the LCD_SPI interface.
-  * @param  None
-  * @retval None
-  */
-void LCD_SPIConfig(void)
-{
-  SPI_InitTypeDef    SPI_InitStructure;
-  GPIO_InitTypeDef   GPIO_InitStructure;
-
-  /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */
-  RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
-
-  /* Enable LCD_SPI and SYSCFG clock  */
-  RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);
-  
-  /* Configure LCD_SPI SCK pin */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Configure LCD_SPI MISO pin */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
-  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Configure LCD_SPI MOSI pin */
-  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
-  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
-
-  /* Connect PE.13 to SPI SCK */
-  GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);
-
-  /* Connect PE.14 to SPI MISO */
-  GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);
-
-  /* Connect PE.15 to SPI MOSI */
-  GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);
-  
-  SPI_DeInit(LCD_SPI);
-  
-  /* SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(LCD_SPI, &SPI_InitStructure);
-
-  /* SPI enable */
-  SPI_Cmd(LCD_SPI, ENABLE);
-}
-
-/**
-  * @brief  Displays a pixel.
-  * @param  x: pixel x.
-  * @param  y: pixel y.  
-  * @retval None
-  */
-static void PutPixel(int16_t x, int16_t y)
-{ 
-  if(x < 0 || x > 239 || y < 0 || y > 319)
-  {
-    return;  
-  }
-  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
-}
-
-#ifndef USE_Delay
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-static void delay(__IO uint32_t nCount)
-{
-  __IO uint32_t index = 0; 
-  for(index = (34000 * nCount); index != 0; index--)
-  {
-  }
-}
-#endif /* USE_Delay*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h
deleted file mode 100644
index 6c7f982..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32l152_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L152_EVAL_LCD_H
-#define __STM32L152_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM32L152_EVAL
-  * @{
-  */
-  
-/** @addtogroup STM32L152_EVAL_LCD
-  * @{
-  */ 
-
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Types
-  * @{
-  */ 
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
- *        display a bitmap picture on the LCD. This function assumes that the bitmap
- *        file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however
- *        user can tailor it according to his application hardware requirement.     
- */
-/*#define USE_LCD_DrawBMP*/
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h"
- 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif                                     
-
-
-/** 
-  * @brief  LCD Control pins  
-  */ 
-#define LCD_NCS_PIN             GPIO_Pin_2                  
-#define LCD_NCS_GPIO_PORT       GPIOH                      
-#define LCD_NCS_GPIO_CLK        RCC_AHBPeriph_GPIOH 
-
-/** 
-  * @brief  LCD SPI Interface pins 
-  */ 
-#define LCD_SPI_SCK_PIN               GPIO_Pin_13                    /* PE.13 */
-#define LCD_SPI_SCK_GPIO_PORT         GPIOE                          /* GPIOE */
-#define LCD_SPI_SCK_GPIO_CLK          RCC_AHBPeriph_GPIOE  
-#define LCD_SPI_SCK_SOURCE            GPIO_PinSource13
-#define LCD_SPI_SCK_AF                GPIO_AF_SPI1
-#define LCD_SPI_MISO_PIN              GPIO_Pin_14                    /* PE.14 */
-#define LCD_SPI_MISO_GPIO_PORT        GPIOE                          /* GPIOE */
-#define LCD_SPI_MISO_GPIO_CLK         RCC_AHBPeriph_GPIOE  
-#define LCD_SPI_MISO_SOURCE           GPIO_PinSource14
-#define LCD_SPI_MISO_AF               GPIO_AF_SPI1
-#define LCD_SPI_MOSI_PIN              GPIO_Pin_15                    /* PE.15 */
-#define LCD_SPI_MOSI_GPIO_PORT        GPIOE                          /* GPIOE */
-#define LCD_SPI_MOSI_GPIO_CLK         RCC_AHBPeriph_GPIOE  
-#define LCD_SPI_MOSI_SOURCE           GPIO_PinSource15
-#define LCD_SPI_MOSI_AF               GPIO_AF_SPI1
-#define LCD_SPI                       SPI1
-#define LCD_SPI_CLK                   RCC_APB2Periph_SPI1
-
-
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_227           0xE3
-#define LCD_REG_229           0xE5
-#define LCD_REG_231           0xE7
-#define LCD_REG_239           0xEF
-
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Macros
-  * @{
-  */ 
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32L152_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-void STM32L152_LCD_DeInit(void);
-void LCD_Setup(void);
-void STM32L152_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); 
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_nCS_StartByte(uint8_t Start_Byte);
-void LCD_WriteRegIndex(uint8_t LCD_Reg);
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAMWord(uint16_t RGB_Code);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM(uint16_t RGB_Code);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-
-void LCD_CtrlLinesConfig(void);
-void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
-void LCD_SPIConfig(void);
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L152_EVAL_LCD_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c
deleted file mode 100644
index 9b6984b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   STM32xx-EVAL abstraction layer. 
-  *          This file should be added to the main application to use the provided
-  *          functions that manage Leds, push-buttons, COM ports and low level 
-  *          HW resources initialization of the different modules available on
-  *          STM32 evaluation boards from STMicroelectronics.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-  
-/** @defgroup STM32_EVAL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports and low level HW resources initialization of the different 
-  *        modules available on STM32 Evaluation Boards from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_Abstraction_Layer
-  * @{
-  */ 
-  
-#ifdef USE_STM32100B_EVAL
- #include "stm32100b_eval/stm32100b_eval.c"
-#elif defined USE_STM3210B_EVAL
- #include "stm3210b_eval/stm3210b_eval.c" 
-#elif defined USE_STM3210E_EVAL
- #include "stm3210e_eval/stm3210e_eval.c"
-#elif defined USE_STM3210C_EVAL
- #include "stm3210c_eval/stm3210c_eval.c"
-#elif defined USE_STM32L152_EVAL
- #include "stm32l152_eval/stm32l152_eval.c"
-#elif defined USE_STM32100E_EVAL
- #include "stm32100e_eval/stm32100e_eval.c"
-#else 
- #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
-#endif
-
-/** @defgroup STM32_EVAL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_FunctionPrototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Functions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h
deleted file mode 100644
index d30caff..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   Header file for stm32_eval.c module.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_H
-#define __STM32_EVAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_Abstraction_Layer
-  * @{
-  */
-  
-/** @defgroup STM32_EVAL_HARDWARE_RESOURCES
-  * @{
-  */
-
-/**
-@code  
- The table below gives an overview of the hardware resources supported by each 
- STM32 EVAL board.
-     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
-     - IOE: IO Expander on I2C
-     - sFLASH: serial SPI FLASH (M25Pxxx)
-     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
-     - TSENSOR: Temperature Sensor (LM75)
-     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) 
-  =================================================================================================================+
-    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |
-  =================================================================================================================+
-   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32100E-EVAL  |  4  |    8     |     2     | YES (FSMC)| YES  |  YES   | YES |   YES   |    YES   |    NO     |
-  =================================================================================================================+
-@endcode
-*/
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_Exported_Types
-  * @{
-  */
-typedef enum 
-{
-  LED1 = 0,
-  LED2 = 1,
-  LED3 = 2,
-  LED4 = 3
-} Led_TypeDef;
-
-typedef enum 
-{  
-  BUTTON_WAKEUP = 0,
-  BUTTON_TAMPER = 1,
-  BUTTON_KEY = 2,
-  BUTTON_RIGHT = 3,
-  BUTTON_LEFT = 4,
-  BUTTON_UP = 5,
-  BUTTON_DOWN = 6,
-  BUTTON_SEL = 7
-} Button_TypeDef;
-
-typedef enum 
-{  
-  BUTTON_MODE_GPIO = 0,
-  BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-
-typedef enum 
-{ 
-  JOY_NONE = 0,
-  JOY_SEL = 1,
-  JOY_DOWN = 2,
-  JOY_LEFT = 3,
-  JOY_RIGHT = 4,
-  JOY_UP = 5
-} JOYState_TypeDef
-;
-
-typedef enum 
-{
-  COM1 = 0,
-  COM2 = 1
-} COM_TypeDef;   
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_Exported_Constants
-  * @{
-  */
-
-/** 
-  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation
-  *   board used in your application.
-  *   
-  *  Tip: To avoid modifying this file each time you need to switch between these
-  *       boards, you can define the board in your toolchain compiler preprocessor.    
-  */ 
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\
-   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- //#define USE_STM32L152_EVAL
- //#define USE_STM32100E_EVAL
-#endif
-
-#ifdef USE_STM32100B_EVAL
- #include "stm32f10x.h"
- #include "stm32100b_eval/stm32100b_eval.h"
-#elif defined USE_STM3210B_EVAL
- #include "stm32f10x.h"
- #include "stm3210b_eval/stm3210b_eval.h" 
-#elif defined USE_STM3210E_EVAL
- #include "stm32f10x.h"
- #include "stm3210e_eval/stm3210e_eval.h"
-#elif defined USE_STM3210C_EVAL
- #include "stm32f10x.h"
- #include "stm3210c_eval/stm3210c_eval.h"
-#elif defined USE_STM32L152_EVAL
- #include "stm32l1xx.h"
- #include "stm32l152_eval/stm32l152_eval.h" 
-#elif defined USE_STM32100E_EVAL
- #include "stm32f10x.h"
- #include "stm32100e_eval/stm32100e_eval.h"
-#else 
- #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
-#endif                      
-
-
-/** 
-  * @brief  STM32 Button Defines Legacy  
-  */ 
-#define Button_WAKEUP        BUTTON_WAKEUP
-#define Button_TAMPER        BUTTON_TAMPER
-#define Button_KEY           BUTTON_KEY
-#define Button_RIGHT         BUTTON_RIGHT
-#define Button_LEFT          BUTTON_LEFT
-#define Button_UP            BUTTON_UP
-#define Button_DOWN          BUTTON_DOWN
-#define Button_SEL           BUTTON_SEL
-#define Mode_GPIO            BUTTON_MODE_GPIO
-#define Mode_EXTI            BUTTON_MODE_EXTI
-#define Button_Mode_TypeDef  ButtonMode_TypeDef
-#define JOY_CENTER           JOY_SEL
-#define JOY_State_TypeDef    JOYState_TypeDef 
-
-/** 
-  * @brief  LCD Defines Legacy  
-  */ 
-#define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK
-#define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT
-#define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK
-#define R0                  LCD_REG_0
-#define R1                  LCD_REG_1
-#define R2                  LCD_REG_2
-#define R3                  LCD_REG_3
-#define R4                  LCD_REG_4
-#define R5                  LCD_REG_5
-#define R6                  LCD_REG_6
-#define R7                  LCD_REG_7
-#define R8                  LCD_REG_8
-#define R9                  LCD_REG_9
-#define R10                 LCD_REG_10
-#define R12                 LCD_REG_12
-#define R13                 LCD_REG_13
-#define R14                 LCD_REG_14
-#define R15                 LCD_REG_15
-#define R16                 LCD_REG_16
-#define R17                 LCD_REG_17
-#define R18                 LCD_REG_18
-#define R19                 LCD_REG_19
-#define R20                 LCD_REG_20
-#define R21                 LCD_REG_21
-#define R22                 LCD_REG_22
-#define R23                 LCD_REG_23
-#define R24                 LCD_REG_24
-#define R25                 LCD_REG_25
-#define R26                 LCD_REG_26
-#define R27                 LCD_REG_27
-#define R28                 LCD_REG_28
-#define R29                 LCD_REG_29
-#define R30                 LCD_REG_30
-#define R31                 LCD_REG_31
-#define R32                 LCD_REG_32
-#define R33                 LCD_REG_33
-#define R34                 LCD_REG_34
-#define R36                 LCD_REG_36
-#define R37                 LCD_REG_37
-#define R40                 LCD_REG_40
-#define R41                 LCD_REG_41
-#define R43                 LCD_REG_43
-#define R45                 LCD_REG_45
-#define R48                 LCD_REG_48
-#define R49                 LCD_REG_49
-#define R50                 LCD_REG_50
-#define R51                 LCD_REG_51
-#define R52                 LCD_REG_52
-#define R53                 LCD_REG_53
-#define R54                 LCD_REG_54
-#define R55                 LCD_REG_55
-#define R56                 LCD_REG_56
-#define R57                 LCD_REG_57
-#define R59                 LCD_REG_59
-#define R60                 LCD_REG_60
-#define R61                 LCD_REG_61
-#define R62                 LCD_REG_62
-#define R63                 LCD_REG_63
-#define R64                 LCD_REG_64
-#define R65                 LCD_REG_65
-#define R66                 LCD_REG_66
-#define R67                 LCD_REG_67
-#define R68                 LCD_REG_68
-#define R69                 LCD_REG_69
-#define R70                 LCD_REG_70
-#define R71                 LCD_REG_71
-#define R72                 LCD_REG_72
-#define R73                 LCD_REG_73
-#define R74                 LCD_REG_74
-#define R75                 LCD_REG_75
-#define R76                 LCD_REG_76
-#define R77                 LCD_REG_77
-#define R78                 LCD_REG_78
-#define R79                 LCD_REG_79
-#define R80                 LCD_REG_80
-#define R81                 LCD_REG_81
-#define R82                 LCD_REG_82
-#define R83                 LCD_REG_83
-#define R96                 LCD_REG_96
-#define R97                 LCD_REG_97
-#define R106                LCD_REG_106
-#define R118                LCD_REG_118
-#define R128                LCD_REG_128
-#define R129                LCD_REG_129
-#define R130                LCD_REG_130
-#define R131                LCD_REG_131
-#define R132                LCD_REG_132
-#define R133                LCD_REG_133
-#define R134                LCD_REG_134
-#define R135                LCD_REG_135
-#define R136                LCD_REG_136
-#define R137                LCD_REG_137
-#define R139                LCD_REG_139
-#define R140                LCD_REG_140
-#define R141                LCD_REG_141
-#define R143                LCD_REG_143
-#define R144                LCD_REG_144
-#define R145                LCD_REG_145
-#define R146                LCD_REG_146
-#define R147                LCD_REG_147
-#define R148                LCD_REG_148
-#define R149                LCD_REG_149
-#define R150                LCD_REG_150
-#define R151                LCD_REG_151
-#define R152                LCD_REG_152
-#define R153                LCD_REG_153
-#define R154                LCD_REG_154
-#define R157                LCD_REG_157
-#define R192                LCD_REG_192
-#define R193                LCD_REG_193
-#define R227                LCD_REG_227
-#define R229                LCD_REG_229
-#define R231                LCD_REG_231
-#define R239                LCD_REG_239
-#define White               LCD_COLOR_WHITE
-#define Black               LCD_COLOR_BLACK
-#define Grey                LCD_COLOR_GREY
-#define Blue                LCD_COLOR_BLUE
-#define Blue2               LCD_COLOR_BLUE2
-#define Red                 LCD_COLOR_RED
-#define Magenta             LCD_COLOR_MAGENTA
-#define Green               LCD_COLOR_GREEN
-#define Cyan                LCD_COLOR_CYAN
-#define Yellow              LCD_COLOR_YELLOW
-#define Line0               LCD_LINE_0
-#define Line1               LCD_LINE_1
-#define Line2               LCD_LINE_2
-#define Line3               LCD_LINE_3
-#define Line4               LCD_LINE_4
-#define Line5               LCD_LINE_5
-#define Line6               LCD_LINE_6
-#define Line7               LCD_LINE_7
-#define Line8               LCD_LINE_8
-#define Line9               LCD_LINE_9
-#define Horizontal          LCD_DIR_HORIZONTAL
-#define Vertical            LCD_DIR_VERTICAL
-
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_Exported_Functions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32_EVAL_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/CMSIS_Logo_Final.jpg b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/CMSIS_Logo_Final.jpg
deleted file mode 100644
index e045601..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/CMSIS_Logo_Final.jpg
+++ /dev/null